1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: true if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns true if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr))
299 if (ixgbe_get_phy_id(hw))
302 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304 if (hw->phy.type == ixgbe_phy_unknown) {
305 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
306 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
310 hw->phy.type = ixgbe_phy_cu_unknown;
312 hw->phy.type = ixgbe_phy_generic;
319 * ixgbe_identify_phy_generic - Get physical layer module
320 * @hw: pointer to hardware structure
322 * Determines the physical layer module found on the current adapter.
324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
329 DEBUGFUNC("ixgbe_identify_phy_generic");
331 if (!hw->phy.phy_semaphore_mask) {
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
338 if (hw->phy.type != ixgbe_phy_unknown)
339 return IXGBE_SUCCESS;
341 if (hw->phy.nw_mng_if_sel) {
342 phy_addr = (hw->phy.nw_mng_if_sel &
343 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
345 if (ixgbe_probe_phy(hw, phy_addr))
346 return IXGBE_SUCCESS;
348 return IXGBE_ERR_PHY_ADDR_INVALID;
351 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
352 if (ixgbe_probe_phy(hw, phy_addr)) {
353 status = IXGBE_SUCCESS;
358 /* Certain media types do not have a phy so an address will not
359 * be found and the code will take this path. Caller has to
360 * decide if it is an error or not.
362 if (status != IXGBE_SUCCESS)
369 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
370 * @hw: pointer to the hardware structure
372 * This function checks the MMNGC.MNG_VETO bit to see if there are
373 * any constraints on link from manageability. For MAC's that don't
374 * have this bit just return faluse since the link can not be blocked
377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 DEBUGFUNC("ixgbe_check_reset_blocked");
383 /* If we don't have this bit, it can't be blocking */
384 if (hw->mac.type == ixgbe_mac_82598EB)
387 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
388 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
389 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
390 "MNG_VETO bit detected.\n");
398 * ixgbe_validate_phy_addr - Determines phy address is valid
399 * @hw: pointer to hardware structure
402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 DEBUGFUNC("ixgbe_validate_phy_addr");
409 hw->phy.addr = phy_addr;
410 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
411 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
413 if (phy_id != 0xFFFF && phy_id != 0x0)
420 * ixgbe_get_phy_id - Get the phy type
421 * @hw: pointer to hardware structure
424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
430 DEBUGFUNC("ixgbe_get_phy_id");
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
436 if (status == IXGBE_SUCCESS) {
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
448 * ixgbe_get_phy_type_from_id - Get the phy type
449 * @phy_id: PHY ID information
452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
454 enum ixgbe_phy_type phy_type;
456 DEBUGFUNC("ixgbe_get_phy_type_from_id");
460 phy_type = ixgbe_phy_tn;
466 phy_type = ixgbe_phy_aq;
469 phy_type = ixgbe_phy_qt;
472 phy_type = ixgbe_phy_nl;
476 phy_type = ixgbe_phy_x550em_ext_t;
478 case IXGBE_M88E1500_E_PHY_ID:
479 case IXGBE_M88E1543_E_PHY_ID:
480 phy_type = ixgbe_phy_m88;
483 phy_type = ixgbe_phy_unknown;
490 * ixgbe_reset_phy_generic - Performs a PHY reset
491 * @hw: pointer to hardware structure
493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
497 s32 status = IXGBE_SUCCESS;
499 DEBUGFUNC("ixgbe_reset_phy_generic");
501 if (hw->phy.type == ixgbe_phy_unknown)
502 status = ixgbe_identify_phy_generic(hw);
504 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
507 /* Don't reset PHY if it's shut down due to overtemp. */
508 if (!hw->phy.reset_if_overtemp &&
509 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
512 /* Blocked by MNG FW so bail */
513 if (ixgbe_check_reset_blocked(hw))
517 * Perform soft PHY reset to the PHY_XS.
518 * This will cause a soft reset to the PHY
520 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
521 IXGBE_MDIO_PHY_XS_DEV_TYPE,
522 IXGBE_MDIO_PHY_XS_RESET);
525 * Poll for reset bit to self-clear indicating reset is complete.
526 * Some PHYs could take up to 3 seconds to complete and need about
527 * 1.7 usec delay after the reset is complete.
529 for (i = 0; i < 30; i++) {
531 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
532 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
533 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
539 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
540 status = IXGBE_ERR_RESET_FAILED;
541 ERROR_REPORT1(IXGBE_ERROR_POLLING,
542 "PHY reset polling failed to complete.\n");
550 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
552 * @hw: pointer to hardware structure
553 * @reg_addr: 32 bit address of PHY register to read
554 * @phy_data: Pointer to read data from PHY register
556 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
559 u32 i, data, command;
561 /* Setup and write the address cycle command */
562 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
563 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
564 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
565 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
567 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
570 * Check every 10 usec to see if the address cycle completed.
571 * The MDI Command bit will clear when the operation is
574 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
577 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
578 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
583 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
584 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
585 return IXGBE_ERR_PHY;
589 * Address cycle complete, setup and write the read
592 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
593 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
594 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
595 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
597 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
600 * Check every 10 usec to see if the address cycle
601 * completed. The MDI Command bit will clear when the
602 * operation is complete
604 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
607 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
608 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
612 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
613 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
614 return IXGBE_ERR_PHY;
618 * Read operation is complete. Get the data
621 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
622 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
623 *phy_data = (u16)(data);
625 return IXGBE_SUCCESS;
629 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
630 * using the SWFW lock - this function is needed in most cases
631 * @hw: pointer to hardware structure
632 * @reg_addr: 32 bit address of PHY register to read
633 * @phy_data: Pointer to read data from PHY register
635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
636 u32 device_type, u16 *phy_data)
639 u32 gssr = hw->phy.phy_semaphore_mask;
641 DEBUGFUNC("ixgbe_read_phy_reg_generic");
643 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
644 return IXGBE_ERR_SWFW_SYNC;
646 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
648 hw->mac.ops.release_swfw_sync(hw, gssr);
654 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
656 * @hw: pointer to hardware structure
657 * @reg_addr: 32 bit PHY register to write
658 * @device_type: 5 bit device type
659 * @phy_data: Data to write to the PHY register
661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
662 u32 device_type, u16 phy_data)
666 /* Put the data in the MDI single read and write data register*/
667 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
669 /* Setup and write the address cycle command */
670 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
671 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
672 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
673 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
675 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
678 * Check every 10 usec to see if the address cycle completed.
679 * The MDI Command bit will clear when the operation is
682 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
685 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
686 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
690 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
691 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
692 return IXGBE_ERR_PHY;
696 * Address cycle complete, setup and write the write
699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
707 * Check every 10 usec to see if the address cycle
708 * completed. The MDI Command bit will clear when the
709 * operation is complete
711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
714 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
721 return IXGBE_ERR_PHY;
724 return IXGBE_SUCCESS;
728 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
729 * using SWFW lock- this function is needed in most cases
730 * @hw: pointer to hardware structure
731 * @reg_addr: 32 bit PHY register to write
732 * @device_type: 5 bit device type
733 * @phy_data: Data to write to the PHY register
735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
736 u32 device_type, u16 phy_data)
739 u32 gssr = hw->phy.phy_semaphore_mask;
741 DEBUGFUNC("ixgbe_write_phy_reg_generic");
743 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
744 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
746 hw->mac.ops.release_swfw_sync(hw, gssr);
748 status = IXGBE_ERR_SWFW_SYNC;
755 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
756 * @hw: pointer to hardware structure
758 * Restart auto-negotiation and PHY and waits for completion.
760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
762 s32 status = IXGBE_SUCCESS;
763 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
764 bool autoneg = false;
765 ixgbe_link_speed speed;
767 DEBUGFUNC("ixgbe_setup_phy_link_generic");
769 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
771 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
772 /* Set or unset auto-negotiation 10G advertisement */
773 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
777 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
778 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
779 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
781 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
782 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
786 if (hw->mac.type == ixgbe_mac_X550) {
787 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
788 /* Set or unset auto-negotiation 5G advertisement */
789 hw->phy.ops.read_reg(hw,
790 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
791 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
794 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
795 if (hw->phy.autoneg_advertised &
796 IXGBE_LINK_SPEED_5GB_FULL)
797 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
799 hw->phy.ops.write_reg(hw,
800 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
806 /* Set or unset auto-negotiation 2.5G advertisement */
807 hw->phy.ops.read_reg(hw,
808 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
809 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
812 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
813 if (hw->phy.autoneg_advertised &
814 IXGBE_LINK_SPEED_2_5GB_FULL)
815 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
817 hw->phy.ops.write_reg(hw,
818 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
824 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
825 /* Set or unset auto-negotiation 1G advertisement */
826 hw->phy.ops.read_reg(hw,
827 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
832 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
833 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
835 hw->phy.ops.write_reg(hw,
836 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
841 if (speed & IXGBE_LINK_SPEED_100_FULL) {
842 /* Set or unset auto-negotiation 100M advertisement */
843 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
844 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
847 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
848 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
849 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
850 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
852 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
853 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
857 /* Blocked by MNG FW so don't reset PHY */
858 if (ixgbe_check_reset_blocked(hw))
861 /* Restart PHY auto-negotiation. */
862 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
865 autoneg_reg |= IXGBE_MII_RESTART;
867 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
868 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
874 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
875 * @hw: pointer to hardware structure
876 * @speed: new link speed
878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
879 ixgbe_link_speed speed,
880 bool autoneg_wait_to_complete)
882 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
884 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
887 * Clear autoneg_advertised and set new values based on input link
890 hw->phy.autoneg_advertised = 0;
892 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
893 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
895 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
896 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
898 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
901 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
902 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
904 if (speed & IXGBE_LINK_SPEED_100_FULL)
905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
907 if (speed & IXGBE_LINK_SPEED_10_FULL)
908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
910 /* Setup link based on the new speed settings */
911 ixgbe_setup_phy_link(hw);
913 return IXGBE_SUCCESS;
917 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
918 * @hw: pointer to hardware structure
920 * Determines the supported link capabilities by reading the PHY auto
921 * negotiation register.
923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
928 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
929 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
934 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
941 switch (hw->mac.type) {
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
946 case ixgbe_mac_X550EM_x:
947 case ixgbe_mac_X550EM_a:
948 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
958 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
959 * @hw: pointer to hardware structure
960 * @speed: pointer to link speed
961 * @autoneg: boolean auto-negotiation value
963 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
964 ixgbe_link_speed *speed,
967 s32 status = IXGBE_SUCCESS;
969 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
972 if (!hw->phy.speeds_supported)
973 status = ixgbe_get_copper_speeds_supported(hw);
975 *speed = hw->phy.speeds_supported;
980 * ixgbe_check_phy_link_tnx - Determine link and speed status
981 * @hw: pointer to hardware structure
983 * Reads the VS1 register to determine if link is up and the current speed for
986 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
989 s32 status = IXGBE_SUCCESS;
991 u32 max_time_out = 10;
996 DEBUGFUNC("ixgbe_check_phy_link_tnx");
998 /* Initialize speed and link to default case */
1000 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1003 * Check current speed and link status of the PHY register.
1004 * This is a vendor specific register and may have to
1005 * be changed for other copper PHYs.
1007 for (time_out = 0; time_out < max_time_out; time_out++) {
1009 status = hw->phy.ops.read_reg(hw,
1010 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1011 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1013 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1014 phy_speed = phy_data &
1015 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1016 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1020 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1029 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1030 * @hw: pointer to hardware structure
1032 * Restart auto-negotiation and PHY and waits for completion.
1034 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1036 s32 status = IXGBE_SUCCESS;
1037 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1038 bool autoneg = false;
1039 ixgbe_link_speed speed;
1041 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1043 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1045 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1046 /* Set or unset auto-negotiation 10G advertisement */
1047 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1048 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1051 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1052 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1053 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1055 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1056 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1060 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1061 /* Set or unset auto-negotiation 1G advertisement */
1062 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1068 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1070 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1075 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1076 /* Set or unset auto-negotiation 100M advertisement */
1077 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1082 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1083 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1085 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1086 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1090 /* Blocked by MNG FW so don't reset PHY */
1091 if (ixgbe_check_reset_blocked(hw))
1094 /* Restart PHY auto-negotiation. */
1095 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1098 autoneg_reg |= IXGBE_MII_RESTART;
1100 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1101 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1107 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1108 * @hw: pointer to hardware structure
1109 * @firmware_version: pointer to the PHY Firmware Version
1111 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1112 u16 *firmware_version)
1116 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1118 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1119 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1126 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1127 * @hw: pointer to hardware structure
1128 * @firmware_version: pointer to the PHY Firmware Version
1130 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1131 u16 *firmware_version)
1135 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1137 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1145 * ixgbe_reset_phy_nl - Performs a PHY reset
1146 * @hw: pointer to hardware structure
1148 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1150 u16 phy_offset, control, eword, edata, block_crc;
1151 bool end_data = false;
1152 u16 list_offset, data_offset;
1154 s32 ret_val = IXGBE_SUCCESS;
1157 DEBUGFUNC("ixgbe_reset_phy_nl");
1159 /* Blocked by MNG FW so bail */
1160 if (ixgbe_check_reset_blocked(hw))
1163 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1166 /* reset the PHY and poll for completion */
1167 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1169 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1171 for (i = 0; i < 100; i++) {
1172 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1174 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1179 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1180 DEBUGOUT("PHY reset did not complete.\n");
1181 ret_val = IXGBE_ERR_PHY;
1185 /* Get init offsets */
1186 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1188 if (ret_val != IXGBE_SUCCESS)
1191 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1195 * Read control word from PHY init contents offset
1197 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1200 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1201 IXGBE_CONTROL_SHIFT_NL;
1202 edata = eword & IXGBE_DATA_MASK_NL;
1204 case IXGBE_DELAY_NL:
1206 DEBUGOUT1("DELAY: %d MS\n", edata);
1210 DEBUGOUT("DATA:\n");
1212 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 for (i = 0; i < edata; i++) {
1218 ret_val = hw->eeprom.ops.read(hw, data_offset,
1222 hw->phy.ops.write_reg(hw, phy_offset,
1223 IXGBE_TWINAX_DEV, eword);
1224 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1230 case IXGBE_CONTROL_NL:
1232 DEBUGOUT("CONTROL:\n");
1233 if (edata == IXGBE_CONTROL_EOL_NL) {
1236 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1239 DEBUGOUT("Bad control value\n");
1240 ret_val = IXGBE_ERR_PHY;
1245 DEBUGOUT("Bad control type\n");
1246 ret_val = IXGBE_ERR_PHY;
1255 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1256 "eeprom read at offset %d failed", data_offset);
1257 return IXGBE_ERR_PHY;
1261 * ixgbe_identify_module_generic - Identifies module type
1262 * @hw: pointer to hardware structure
1264 * Determines HW type and calls appropriate function.
1266 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1268 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1270 DEBUGFUNC("ixgbe_identify_module_generic");
1272 switch (hw->mac.ops.get_media_type(hw)) {
1273 case ixgbe_media_type_fiber:
1274 status = ixgbe_identify_sfp_module_generic(hw);
1277 case ixgbe_media_type_fiber_qsfp:
1278 status = ixgbe_identify_qsfp_module_generic(hw);
1282 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1283 status = IXGBE_ERR_SFP_NOT_PRESENT;
1291 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1292 * @hw: pointer to hardware structure
1294 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1296 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1298 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1300 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1302 u8 comp_codes_1g = 0;
1303 u8 comp_codes_10g = 0;
1304 u8 oui_bytes[3] = {0, 0, 0};
1307 u16 enforce_sfp = 0;
1309 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1311 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1312 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1313 status = IXGBE_ERR_SFP_NOT_PRESENT;
1317 /* LAN ID is needed for I2C access */
1318 hw->mac.ops.set_lan_id(hw);
1320 status = hw->phy.ops.read_i2c_eeprom(hw,
1321 IXGBE_SFF_IDENTIFIER,
1324 if (status != IXGBE_SUCCESS)
1325 goto err_read_i2c_eeprom;
1327 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1328 hw->phy.type = ixgbe_phy_sfp_unsupported;
1329 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1331 status = hw->phy.ops.read_i2c_eeprom(hw,
1332 IXGBE_SFF_1GBE_COMP_CODES,
1335 if (status != IXGBE_SUCCESS)
1336 goto err_read_i2c_eeprom;
1338 status = hw->phy.ops.read_i2c_eeprom(hw,
1339 IXGBE_SFF_10GBE_COMP_CODES,
1342 if (status != IXGBE_SUCCESS)
1343 goto err_read_i2c_eeprom;
1344 status = hw->phy.ops.read_i2c_eeprom(hw,
1345 IXGBE_SFF_CABLE_TECHNOLOGY,
1348 if (status != IXGBE_SUCCESS)
1349 goto err_read_i2c_eeprom;
1356 * 3 SFP_DA_CORE0 - 82599-specific
1357 * 4 SFP_DA_CORE1 - 82599-specific
1358 * 5 SFP_SR/LR_CORE0 - 82599-specific
1359 * 6 SFP_SR/LR_CORE1 - 82599-specific
1360 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1361 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1362 * 9 SFP_1g_cu_CORE0 - 82599-specific
1363 * 10 SFP_1g_cu_CORE1 - 82599-specific
1364 * 11 SFP_1g_sx_CORE0 - 82599-specific
1365 * 12 SFP_1g_sx_CORE1 - 82599-specific
1367 if (hw->mac.type == ixgbe_mac_82598EB) {
1368 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1369 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1371 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1373 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1375 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1377 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1378 if (hw->bus.lan_id == 0)
1380 ixgbe_sfp_type_da_cu_core0;
1383 ixgbe_sfp_type_da_cu_core1;
1384 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1385 hw->phy.ops.read_i2c_eeprom(
1386 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1389 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1390 if (hw->bus.lan_id == 0)
1392 ixgbe_sfp_type_da_act_lmt_core0;
1395 ixgbe_sfp_type_da_act_lmt_core1;
1398 ixgbe_sfp_type_unknown;
1400 } else if (comp_codes_10g &
1401 (IXGBE_SFF_10GBASESR_CAPABLE |
1402 IXGBE_SFF_10GBASELR_CAPABLE)) {
1403 if (hw->bus.lan_id == 0)
1405 ixgbe_sfp_type_srlr_core0;
1408 ixgbe_sfp_type_srlr_core1;
1409 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1410 if (hw->bus.lan_id == 0)
1412 ixgbe_sfp_type_1g_cu_core0;
1415 ixgbe_sfp_type_1g_cu_core1;
1416 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1417 if (hw->bus.lan_id == 0)
1419 ixgbe_sfp_type_1g_sx_core0;
1422 ixgbe_sfp_type_1g_sx_core1;
1423 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1424 if (hw->bus.lan_id == 0)
1426 ixgbe_sfp_type_1g_lx_core0;
1429 ixgbe_sfp_type_1g_lx_core1;
1431 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1435 if (hw->phy.sfp_type != stored_sfp_type)
1436 hw->phy.sfp_setup_needed = true;
1438 /* Determine if the SFP+ PHY is dual speed or not. */
1439 hw->phy.multispeed_fiber = false;
1440 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1441 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1442 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1443 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1444 hw->phy.multispeed_fiber = true;
1446 /* Determine PHY vendor */
1447 if (hw->phy.type != ixgbe_phy_nl) {
1448 hw->phy.id = identifier;
1449 status = hw->phy.ops.read_i2c_eeprom(hw,
1450 IXGBE_SFF_VENDOR_OUI_BYTE0,
1453 if (status != IXGBE_SUCCESS)
1454 goto err_read_i2c_eeprom;
1456 status = hw->phy.ops.read_i2c_eeprom(hw,
1457 IXGBE_SFF_VENDOR_OUI_BYTE1,
1460 if (status != IXGBE_SUCCESS)
1461 goto err_read_i2c_eeprom;
1463 status = hw->phy.ops.read_i2c_eeprom(hw,
1464 IXGBE_SFF_VENDOR_OUI_BYTE2,
1467 if (status != IXGBE_SUCCESS)
1468 goto err_read_i2c_eeprom;
1471 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1472 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1473 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1475 switch (vendor_oui) {
1476 case IXGBE_SFF_VENDOR_OUI_TYCO:
1477 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1479 ixgbe_phy_sfp_passive_tyco;
1481 case IXGBE_SFF_VENDOR_OUI_FTL:
1482 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1485 hw->phy.type = ixgbe_phy_sfp_ftl;
1487 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1488 hw->phy.type = ixgbe_phy_sfp_avago;
1490 case IXGBE_SFF_VENDOR_OUI_INTEL:
1491 hw->phy.type = ixgbe_phy_sfp_intel;
1494 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1496 ixgbe_phy_sfp_passive_unknown;
1497 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1499 ixgbe_phy_sfp_active_unknown;
1501 hw->phy.type = ixgbe_phy_sfp_unknown;
1506 /* Allow any DA cable vendor */
1507 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1508 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1509 status = IXGBE_SUCCESS;
1513 /* Verify supported 1G SFP modules */
1514 if (comp_codes_10g == 0 &&
1515 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1521 hw->phy.type = ixgbe_phy_sfp_unsupported;
1522 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1526 /* Anything else 82598-based is supported */
1527 if (hw->mac.type == ixgbe_mac_82598EB) {
1528 status = IXGBE_SUCCESS;
1532 ixgbe_get_device_caps(hw, &enforce_sfp);
1533 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1534 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540 /* Make sure we're a supported PHY type */
1541 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1542 status = IXGBE_SUCCESS;
1544 if (hw->allow_unsupported_sfp == true) {
1545 EWARN(hw, "WARNING: Intel (R) Network "
1546 "Connections are quality tested "
1547 "using Intel (R) Ethernet Optics."
1548 " Using untested modules is not "
1549 "supported and may cause unstable"
1550 " operation or damage to the "
1551 "module or the adapter. Intel "
1552 "Corporation is not responsible "
1553 "for any harm caused by using "
1554 "untested modules.\n", status);
1555 status = IXGBE_SUCCESS;
1557 DEBUGOUT("SFP+ module not supported\n");
1559 ixgbe_phy_sfp_unsupported;
1560 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1564 status = IXGBE_SUCCESS;
1571 err_read_i2c_eeprom:
1572 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1573 if (hw->phy.type != ixgbe_phy_nl) {
1575 hw->phy.type = ixgbe_phy_unknown;
1577 return IXGBE_ERR_SFP_NOT_PRESENT;
1581 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1582 * @hw: pointer to hardware structure
1584 * Determines physical layer capabilities of the current SFP.
1586 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1588 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1589 u8 comp_codes_10g = 0;
1590 u8 comp_codes_1g = 0;
1592 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1594 hw->phy.ops.identify_sfp(hw);
1595 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1596 return physical_layer;
1598 switch (hw->phy.type) {
1599 case ixgbe_phy_sfp_passive_tyco:
1600 case ixgbe_phy_sfp_passive_unknown:
1601 case ixgbe_phy_qsfp_passive_unknown:
1602 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1604 case ixgbe_phy_sfp_ftl_active:
1605 case ixgbe_phy_sfp_active_unknown:
1606 case ixgbe_phy_qsfp_active_unknown:
1607 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1609 case ixgbe_phy_sfp_avago:
1610 case ixgbe_phy_sfp_ftl:
1611 case ixgbe_phy_sfp_intel:
1612 case ixgbe_phy_sfp_unknown:
1613 hw->phy.ops.read_i2c_eeprom(hw,
1614 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1615 hw->phy.ops.read_i2c_eeprom(hw,
1616 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1617 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1619 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1620 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1621 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1623 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1624 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1626 case ixgbe_phy_qsfp_intel:
1627 case ixgbe_phy_qsfp_unknown:
1628 hw->phy.ops.read_i2c_eeprom(hw,
1629 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1630 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1631 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1632 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1633 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1639 return physical_layer;
1643 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1644 * @hw: pointer to hardware structure
1646 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1648 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1650 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1652 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1654 u8 comp_codes_1g = 0;
1655 u8 comp_codes_10g = 0;
1656 u8 oui_bytes[3] = {0, 0, 0};
1657 u16 enforce_sfp = 0;
1659 u8 cable_length = 0;
1661 bool active_cable = false;
1663 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1665 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1666 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1667 status = IXGBE_ERR_SFP_NOT_PRESENT;
1671 /* LAN ID is needed for I2C access */
1672 hw->mac.ops.set_lan_id(hw);
1674 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1677 if (status != IXGBE_SUCCESS)
1678 goto err_read_i2c_eeprom;
1680 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1681 hw->phy.type = ixgbe_phy_sfp_unsupported;
1682 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1686 hw->phy.id = identifier;
1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1691 if (status != IXGBE_SUCCESS)
1692 goto err_read_i2c_eeprom;
1694 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1697 if (status != IXGBE_SUCCESS)
1698 goto err_read_i2c_eeprom;
1700 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1701 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1702 if (hw->bus.lan_id == 0)
1703 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1705 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1706 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1707 IXGBE_SFF_10GBASELR_CAPABLE)) {
1708 if (hw->bus.lan_id == 0)
1709 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1711 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1713 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1714 active_cable = true;
1716 if (!active_cable) {
1717 /* check for active DA cables that pre-date
1719 hw->phy.ops.read_i2c_eeprom(hw,
1720 IXGBE_SFF_QSFP_CONNECTOR,
1723 hw->phy.ops.read_i2c_eeprom(hw,
1724 IXGBE_SFF_QSFP_CABLE_LENGTH,
1727 hw->phy.ops.read_i2c_eeprom(hw,
1728 IXGBE_SFF_QSFP_DEVICE_TECH,
1732 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1733 (cable_length > 0) &&
1734 ((device_tech >> 4) ==
1735 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1736 active_cable = true;
1740 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1741 if (hw->bus.lan_id == 0)
1743 ixgbe_sfp_type_da_act_lmt_core0;
1746 ixgbe_sfp_type_da_act_lmt_core1;
1748 /* unsupported module type */
1749 hw->phy.type = ixgbe_phy_sfp_unsupported;
1750 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1755 if (hw->phy.sfp_type != stored_sfp_type)
1756 hw->phy.sfp_setup_needed = true;
1758 /* Determine if the QSFP+ PHY is dual speed or not. */
1759 hw->phy.multispeed_fiber = false;
1760 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1761 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1762 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1763 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1764 hw->phy.multispeed_fiber = true;
1766 /* Determine PHY vendor for optical modules */
1767 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1768 IXGBE_SFF_10GBASELR_CAPABLE)) {
1769 status = hw->phy.ops.read_i2c_eeprom(hw,
1770 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1773 if (status != IXGBE_SUCCESS)
1774 goto err_read_i2c_eeprom;
1776 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1780 if (status != IXGBE_SUCCESS)
1781 goto err_read_i2c_eeprom;
1783 status = hw->phy.ops.read_i2c_eeprom(hw,
1784 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1787 if (status != IXGBE_SUCCESS)
1788 goto err_read_i2c_eeprom;
1791 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1792 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1793 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1795 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1796 hw->phy.type = ixgbe_phy_qsfp_intel;
1798 hw->phy.type = ixgbe_phy_qsfp_unknown;
1800 ixgbe_get_device_caps(hw, &enforce_sfp);
1801 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1802 /* Make sure we're a supported PHY type */
1803 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1804 status = IXGBE_SUCCESS;
1806 if (hw->allow_unsupported_sfp == true) {
1807 EWARN(hw, "WARNING: Intel (R) Network "
1808 "Connections are quality tested "
1809 "using Intel (R) Ethernet Optics."
1810 " Using untested modules is not "
1811 "supported and may cause unstable"
1812 " operation or damage to the "
1813 "module or the adapter. Intel "
1814 "Corporation is not responsible "
1815 "for any harm caused by using "
1816 "untested modules.\n", status);
1817 status = IXGBE_SUCCESS;
1819 DEBUGOUT("QSFP module not supported\n");
1821 ixgbe_phy_sfp_unsupported;
1822 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1826 status = IXGBE_SUCCESS;
1833 err_read_i2c_eeprom:
1834 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1836 hw->phy.type = ixgbe_phy_unknown;
1838 return IXGBE_ERR_SFP_NOT_PRESENT;
1843 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1844 * @hw: pointer to hardware structure
1845 * @list_offset: offset to the SFP ID list
1846 * @data_offset: offset to the SFP data block
1848 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1849 * so it returns the offsets to the phy init sequence block.
1851 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1856 u16 sfp_type = hw->phy.sfp_type;
1858 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1860 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1861 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1863 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1864 return IXGBE_ERR_SFP_NOT_PRESENT;
1866 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1867 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1868 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1871 * Limiting active cables and 1G Phys must be initialized as
1874 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1875 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1876 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1877 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1878 sfp_type = ixgbe_sfp_type_srlr_core0;
1879 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1880 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1881 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1882 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1883 sfp_type = ixgbe_sfp_type_srlr_core1;
1885 /* Read offset to PHY init contents */
1886 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1887 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1888 "eeprom read at offset %d failed",
1889 IXGBE_PHY_INIT_OFFSET_NL);
1890 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1893 if ((!*list_offset) || (*list_offset == 0xFFFF))
1894 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1896 /* Shift offset to first ID word */
1900 * Find the matching SFP ID in the EEPROM
1901 * and program the init sequence
1903 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1906 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1907 if (sfp_id == sfp_type) {
1909 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1911 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1912 DEBUGOUT("SFP+ module not supported\n");
1913 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1918 (*list_offset) += 2;
1919 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1924 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1925 DEBUGOUT("No matching SFP+ module found\n");
1926 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1929 return IXGBE_SUCCESS;
1932 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1933 "eeprom read at offset %d failed", *list_offset);
1934 return IXGBE_ERR_PHY;
1938 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1939 * @hw: pointer to hardware structure
1940 * @byte_offset: EEPROM byte offset to read
1941 * @eeprom_data: value read
1943 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1945 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1948 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1950 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1951 IXGBE_I2C_EEPROM_DEV_ADDR,
1956 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1957 * @hw: pointer to hardware structure
1958 * @byte_offset: byte offset at address 0xA2
1959 * @eeprom_data: value read
1961 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1963 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1966 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1967 IXGBE_I2C_EEPROM_DEV_ADDR2,
1972 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1973 * @hw: pointer to hardware structure
1974 * @byte_offset: EEPROM byte offset to write
1975 * @eeprom_data: value to write
1977 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1979 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1982 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1984 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1985 IXGBE_I2C_EEPROM_DEV_ADDR,
1990 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1991 * @hw: pointer to hardware structure
1992 * @offset: eeprom offset to be read
1993 * @addr: I2C address to be read
1995 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1997 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1998 offset == IXGBE_SFF_IDENTIFIER &&
1999 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2005 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2006 * @hw: pointer to hardware structure
2007 * @byte_offset: byte offset to read
2009 * @lock: true if to take and release semaphore
2011 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2012 * a specified device address.
2014 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2015 u8 dev_addr, u8 *data, bool lock)
2020 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2024 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2026 if (hw->mac.type >= ixgbe_mac_X550)
2028 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2029 max_retry = IXGBE_SFP_DETECT_RETRIES;
2032 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2033 return IXGBE_ERR_SWFW_SYNC;
2035 ixgbe_i2c_start(hw);
2037 /* Device Address and write indication */
2038 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2039 if (status != IXGBE_SUCCESS)
2042 status = ixgbe_get_i2c_ack(hw);
2043 if (status != IXGBE_SUCCESS)
2046 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2047 if (status != IXGBE_SUCCESS)
2050 status = ixgbe_get_i2c_ack(hw);
2051 if (status != IXGBE_SUCCESS)
2054 ixgbe_i2c_start(hw);
2056 /* Device Address and read indication */
2057 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2058 if (status != IXGBE_SUCCESS)
2061 status = ixgbe_get_i2c_ack(hw);
2062 if (status != IXGBE_SUCCESS)
2065 status = ixgbe_clock_in_i2c_byte(hw, data);
2066 if (status != IXGBE_SUCCESS)
2069 status = ixgbe_clock_out_i2c_bit(hw, nack);
2070 if (status != IXGBE_SUCCESS)
2075 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2076 return IXGBE_SUCCESS;
2079 ixgbe_i2c_bus_clear(hw);
2081 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2085 if (retry < max_retry)
2086 DEBUGOUT("I2C byte read error - Retrying.\n");
2088 DEBUGOUT("I2C byte read error.\n");
2090 } while (retry < max_retry);
2096 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2097 * @hw: pointer to hardware structure
2098 * @byte_offset: byte offset to read
2101 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2102 * a specified device address.
2104 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2105 u8 dev_addr, u8 *data)
2107 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2112 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2113 * @hw: pointer to hardware structure
2114 * @byte_offset: byte offset to read
2117 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2118 * a specified device address.
2120 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2121 u8 dev_addr, u8 *data)
2123 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2128 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2129 * @hw: pointer to hardware structure
2130 * @byte_offset: byte offset to write
2131 * @data: value to write
2132 * @lock: true if to take and release semaphore
2134 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2135 * a specified device address.
2137 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2138 u8 dev_addr, u8 data, bool lock)
2143 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2145 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2147 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2149 return IXGBE_ERR_SWFW_SYNC;
2152 ixgbe_i2c_start(hw);
2154 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2155 if (status != IXGBE_SUCCESS)
2158 status = ixgbe_get_i2c_ack(hw);
2159 if (status != IXGBE_SUCCESS)
2162 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2163 if (status != IXGBE_SUCCESS)
2166 status = ixgbe_get_i2c_ack(hw);
2167 if (status != IXGBE_SUCCESS)
2170 status = ixgbe_clock_out_i2c_byte(hw, data);
2171 if (status != IXGBE_SUCCESS)
2174 status = ixgbe_get_i2c_ack(hw);
2175 if (status != IXGBE_SUCCESS)
2180 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2181 return IXGBE_SUCCESS;
2184 ixgbe_i2c_bus_clear(hw);
2186 if (retry < max_retry)
2187 DEBUGOUT("I2C byte write error - Retrying.\n");
2189 DEBUGOUT("I2C byte write error.\n");
2190 } while (retry < max_retry);
2193 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2199 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2200 * @hw: pointer to hardware structure
2201 * @byte_offset: byte offset to write
2202 * @data: value to write
2204 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2205 * a specified device address.
2207 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2208 u8 dev_addr, u8 data)
2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2215 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2216 * @hw: pointer to hardware structure
2217 * @byte_offset: byte offset to write
2218 * @data: value to write
2220 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2221 * a specified device address.
2223 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2224 u8 dev_addr, u8 data)
2226 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2231 * ixgbe_i2c_start - Sets I2C start condition
2232 * @hw: pointer to hardware structure
2234 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2235 * Set bit-bang mode on X550 hardware.
2237 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2239 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2241 DEBUGFUNC("ixgbe_i2c_start");
2243 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2245 /* Start condition must begin with data and clock high */
2246 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2247 ixgbe_raise_i2c_clk(hw, &i2cctl);
2249 /* Setup time for start condition (4.7us) */
2250 usec_delay(IXGBE_I2C_T_SU_STA);
2252 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2254 /* Hold time for start condition (4us) */
2255 usec_delay(IXGBE_I2C_T_HD_STA);
2257 ixgbe_lower_i2c_clk(hw, &i2cctl);
2259 /* Minimum low period of clock is 4.7 us */
2260 usec_delay(IXGBE_I2C_T_LOW);
2265 * ixgbe_i2c_stop - Sets I2C stop condition
2266 * @hw: pointer to hardware structure
2268 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2269 * Disables bit-bang mode and negates data output enable on X550
2272 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2274 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2275 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2276 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2277 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2279 DEBUGFUNC("ixgbe_i2c_stop");
2281 /* Stop condition must begin with data low and clock high */
2282 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2283 ixgbe_raise_i2c_clk(hw, &i2cctl);
2285 /* Setup time for stop condition (4us) */
2286 usec_delay(IXGBE_I2C_T_SU_STO);
2288 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2290 /* bus free time between stop and start (4.7us)*/
2291 usec_delay(IXGBE_I2C_T_BUF);
2293 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2294 i2cctl &= ~bb_en_bit;
2295 i2cctl |= data_oe_bit | clk_oe_bit;
2296 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2297 IXGBE_WRITE_FLUSH(hw);
2302 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2303 * @hw: pointer to hardware structure
2304 * @data: data byte to clock in
2306 * Clocks in one byte data via I2C data/clock
2308 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2313 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2316 for (i = 7; i >= 0; i--) {
2317 ixgbe_clock_in_i2c_bit(hw, &bit);
2321 return IXGBE_SUCCESS;
2325 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2326 * @hw: pointer to hardware structure
2327 * @data: data byte clocked out
2329 * Clocks out one byte data via I2C data/clock
2331 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2333 s32 status = IXGBE_SUCCESS;
2338 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2340 for (i = 7; i >= 0; i--) {
2341 bit = (data >> i) & 0x1;
2342 status = ixgbe_clock_out_i2c_bit(hw, bit);
2344 if (status != IXGBE_SUCCESS)
2348 /* Release SDA line (set high) */
2349 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2350 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2351 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2352 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2353 IXGBE_WRITE_FLUSH(hw);
2359 * ixgbe_get_i2c_ack - Polls for I2C ACK
2360 * @hw: pointer to hardware structure
2362 * Clocks in/out one bit via I2C data/clock
2364 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2366 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2367 s32 status = IXGBE_SUCCESS;
2369 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2373 DEBUGFUNC("ixgbe_get_i2c_ack");
2376 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2377 i2cctl |= data_oe_bit;
2378 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2379 IXGBE_WRITE_FLUSH(hw);
2381 ixgbe_raise_i2c_clk(hw, &i2cctl);
2383 /* Minimum high period of clock is 4us */
2384 usec_delay(IXGBE_I2C_T_HIGH);
2386 /* Poll for ACK. Note that ACK in I2C spec is
2387 * transition from 1 to 0 */
2388 for (i = 0; i < timeout; i++) {
2389 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2390 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2398 DEBUGOUT("I2C ack was not received.\n");
2399 status = IXGBE_ERR_I2C;
2402 ixgbe_lower_i2c_clk(hw, &i2cctl);
2404 /* Minimum low period of clock is 4.7 us */
2405 usec_delay(IXGBE_I2C_T_LOW);
2411 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2412 * @hw: pointer to hardware structure
2413 * @data: read data value
2415 * Clocks in one bit via I2C data/clock
2417 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2419 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2420 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2422 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2425 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2426 i2cctl |= data_oe_bit;
2427 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2428 IXGBE_WRITE_FLUSH(hw);
2430 ixgbe_raise_i2c_clk(hw, &i2cctl);
2432 /* Minimum high period of clock is 4us */
2433 usec_delay(IXGBE_I2C_T_HIGH);
2435 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2436 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2438 ixgbe_lower_i2c_clk(hw, &i2cctl);
2440 /* Minimum low period of clock is 4.7 us */
2441 usec_delay(IXGBE_I2C_T_LOW);
2443 return IXGBE_SUCCESS;
2447 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2448 * @hw: pointer to hardware structure
2449 * @data: data value to write
2451 * Clocks out one bit via I2C data/clock
2453 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2456 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2458 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2460 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2461 if (status == IXGBE_SUCCESS) {
2462 ixgbe_raise_i2c_clk(hw, &i2cctl);
2464 /* Minimum high period of clock is 4us */
2465 usec_delay(IXGBE_I2C_T_HIGH);
2467 ixgbe_lower_i2c_clk(hw, &i2cctl);
2469 /* Minimum low period of clock is 4.7 us.
2470 * This also takes care of the data hold time.
2472 usec_delay(IXGBE_I2C_T_LOW);
2474 status = IXGBE_ERR_I2C;
2475 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2476 "I2C data was not set to %X\n", data);
2483 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2484 * @hw: pointer to hardware structure
2485 * @i2cctl: Current value of I2CCTL register
2487 * Raises the I2C clock line '0'->'1'
2488 * Negates the I2C clock output enable on X550 hardware.
2490 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2492 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2494 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2497 DEBUGFUNC("ixgbe_raise_i2c_clk");
2500 *i2cctl |= clk_oe_bit;
2501 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2504 for (i = 0; i < timeout; i++) {
2505 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2507 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2508 IXGBE_WRITE_FLUSH(hw);
2509 /* SCL rise time (1000ns) */
2510 usec_delay(IXGBE_I2C_T_RISE);
2512 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2513 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2519 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2520 * @hw: pointer to hardware structure
2521 * @i2cctl: Current value of I2CCTL register
2523 * Lowers the I2C clock line '1'->'0'
2524 * Asserts the I2C clock output enable on X550 hardware.
2526 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2528 DEBUGFUNC("ixgbe_lower_i2c_clk");
2530 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2531 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2533 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2534 IXGBE_WRITE_FLUSH(hw);
2536 /* SCL fall time (300ns) */
2537 usec_delay(IXGBE_I2C_T_FALL);
2541 * ixgbe_set_i2c_data - Sets the I2C data bit
2542 * @hw: pointer to hardware structure
2543 * @i2cctl: Current value of I2CCTL register
2544 * @data: I2C data value (0 or 1) to set
2546 * Sets the I2C data bit
2547 * Asserts the I2C data output enable on X550 hardware.
2549 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2551 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2552 s32 status = IXGBE_SUCCESS;
2554 DEBUGFUNC("ixgbe_set_i2c_data");
2557 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2559 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2560 *i2cctl &= ~data_oe_bit;
2562 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2563 IXGBE_WRITE_FLUSH(hw);
2565 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2566 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2568 if (!data) /* Can't verify data in this case */
2569 return IXGBE_SUCCESS;
2571 *i2cctl |= data_oe_bit;
2572 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2573 IXGBE_WRITE_FLUSH(hw);
2576 /* Verify data was set correctly */
2577 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2578 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2579 status = IXGBE_ERR_I2C;
2580 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2581 "Error - I2C data was not set to %X.\n",
2589 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2590 * @hw: pointer to hardware structure
2591 * @i2cctl: Current value of I2CCTL register
2593 * Returns the I2C data bit value
2594 * Negates the I2C data output enable on X550 hardware.
2596 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2598 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2601 DEBUGFUNC("ixgbe_get_i2c_data");
2604 *i2cctl |= data_oe_bit;
2605 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2606 IXGBE_WRITE_FLUSH(hw);
2607 usec_delay(IXGBE_I2C_T_FALL);
2610 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2619 * ixgbe_i2c_bus_clear - Clears the I2C bus
2620 * @hw: pointer to hardware structure
2622 * Clears the I2C bus by sending nine clock pulses.
2623 * Used when data line is stuck low.
2625 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2630 DEBUGFUNC("ixgbe_i2c_bus_clear");
2632 ixgbe_i2c_start(hw);
2633 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2635 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2637 for (i = 0; i < 9; i++) {
2638 ixgbe_raise_i2c_clk(hw, &i2cctl);
2640 /* Min high period of clock is 4us */
2641 usec_delay(IXGBE_I2C_T_HIGH);
2643 ixgbe_lower_i2c_clk(hw, &i2cctl);
2645 /* Min low period of clock is 4.7us*/
2646 usec_delay(IXGBE_I2C_T_LOW);
2649 ixgbe_i2c_start(hw);
2651 /* Put the i2c bus back to default state */
2656 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2657 * @hw: pointer to hardware structure
2659 * Checks if the LASI temp alarm status was triggered due to overtemp
2661 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2663 s32 status = IXGBE_SUCCESS;
2666 DEBUGFUNC("ixgbe_tn_check_overtemp");
2668 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2671 /* Check that the LASI temp alarm status was triggered */
2672 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2673 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2675 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2678 status = IXGBE_ERR_OVERTEMP;
2679 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2685 * ixgbe_set_copper_phy_power - Control power for copper phy
2686 * @hw: pointer to hardware structure
2687 * @on: true for on, false for off
2689 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2694 if (!on && ixgbe_mng_present(hw))
2697 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2698 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2704 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2706 if (ixgbe_check_reset_blocked(hw))
2708 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2711 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2712 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,