1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
53 * @hw: pointer to hardware structure
55 * Initialize the function pointers and assign the MAC type for X540.
56 * Does not touch the hardware.
58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
61 struct ixgbe_phy_info *phy = &hw->phy;
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 DEBUGFUNC("ixgbe_init_ops_X540");
67 ret_val = ixgbe_init_phy_ops_generic(hw);
68 ret_val = ixgbe_init_ops_generic(hw);
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
73 eeprom->ops.read = ixgbe_read_eerd_X540;
74 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
75 eeprom->ops.write = ixgbe_write_eewr_X540;
76 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
79 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
82 phy->ops.init = ixgbe_init_phy_ops_generic;
83 phy->ops.reset = NULL;
84 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
87 mac->ops.reset_hw = ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
102 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
103 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
104 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
106 /* RAR, Multicast, VLAN */
107 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
108 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
109 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
110 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
111 mac->rar_highwater = 1;
112 mac->ops.set_vfta = ixgbe_set_vfta_generic;
113 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
114 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
115 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
116 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
117 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
120 mac->ops.get_link_capabilities =
121 ixgbe_get_copper_link_capabilities_generic;
122 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
123 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
124 mac->ops.check_link = ixgbe_check_mac_link_generic;
127 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
128 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
129 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
130 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
131 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
132 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
137 * ARC supported; valid only if manageability features are
140 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
141 & IXGBE_FWSM_MODE_MASK);
143 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
146 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
147 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
149 /* Manageability interface */
150 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
152 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
158 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
159 * @hw: pointer to hardware structure
160 * @speed: pointer to link speed
161 * @autoneg: true when autoneg or autotry is enabled
163 * Determines the link capabilities by reading the AUTOC register.
165 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
166 ixgbe_link_speed *speed,
169 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
171 return IXGBE_SUCCESS;
175 * ixgbe_get_media_type_X540 - Get media type
176 * @hw: pointer to hardware structure
178 * Returns the media type (fiber, copper, backplane)
180 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
182 UNREFERENCED_1PARAMETER(hw);
183 return ixgbe_media_type_copper;
187 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
188 * @hw: pointer to hardware structure
189 * @speed: new link speed
190 * @autoneg_wait_to_complete: true when waiting for completion is needed
192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
193 ixgbe_link_speed speed,
194 bool autoneg_wait_to_complete)
196 DEBUGFUNC("ixgbe_setup_mac_link_X540");
197 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
201 * ixgbe_reset_hw_X540 - Perform hardware reset
202 * @hw: pointer to hardware structure
204 * Resets the hardware by resetting the transmit and receive units, masks
205 * and clears all interrupts, and perform a reset.
207 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
212 DEBUGFUNC("ixgbe_reset_hw_X540");
214 /* Call adapter stop to disable tx/rx and clear interrupts */
215 status = hw->mac.ops.stop_adapter(hw);
216 if (status != IXGBE_SUCCESS)
219 /* flush pending Tx transactions */
220 ixgbe_clear_tx_pending(hw);
223 ctrl = IXGBE_CTRL_RST;
224 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
226 IXGBE_WRITE_FLUSH(hw);
228 /* Poll for reset bit to self-clear indicating reset is complete */
229 for (i = 0; i < 10; i++) {
231 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
232 if (!(ctrl & IXGBE_CTRL_RST_MASK))
236 if (ctrl & IXGBE_CTRL_RST_MASK) {
237 status = IXGBE_ERR_RESET_FAILED;
238 ERROR_REPORT1(IXGBE_ERROR_POLLING,
239 "Reset polling failed to complete.\n");
244 * Double resets are required for recovery from certain error
245 * conditions. Between resets, it is necessary to stall to allow time
246 * for any pending HW events to complete.
248 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
249 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
253 /* Set the Rx packet buffer size. */
254 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
256 /* Store the permanent mac address */
257 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
260 * Store MAC address from RAR0, clear receive address registers, and
261 * clear the multicast table. Also reset num_rar_entries to 128,
262 * since we modify this value when programming the SAN MAC address.
264 hw->mac.num_rar_entries = 128;
265 hw->mac.ops.init_rx_addrs(hw);
267 /* Store the permanent SAN mac address */
268 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
270 /* Add the SAN MAC address to the RAR only if it's a valid address */
271 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
272 /* Save the SAN MAC RAR index */
273 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
275 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
276 hw->mac.san_addr, 0, IXGBE_RAH_AV);
278 /* clear VMDq pool/queue selection for this RAR */
279 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
280 IXGBE_CLEAR_VMDQ_ALL);
282 /* Reserve the last RAR for the SAN MAC address */
283 hw->mac.num_rar_entries--;
286 /* Store the alternative WWNN/WWPN prefix */
287 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
288 &hw->mac.wwpn_prefix);
295 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
296 * @hw: pointer to hardware structure
298 * Starts the hardware using the generic start_hw function
299 * and the generation start_hw function.
300 * Then performs revision-specific operations, if any.
302 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
304 s32 ret_val = IXGBE_SUCCESS;
306 DEBUGFUNC("ixgbe_start_hw_X540");
308 ret_val = ixgbe_start_hw_generic(hw);
309 if (ret_val != IXGBE_SUCCESS)
312 ret_val = ixgbe_start_hw_gen2(hw);
319 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
320 * @hw: pointer to hardware structure
322 * Determines physical layer capabilities of the current configuration.
324 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
326 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
329 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
331 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
332 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
333 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
334 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
335 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
336 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
337 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
338 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
340 return physical_layer;
344 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
345 * @hw: pointer to hardware structure
347 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
348 * ixgbe_hw struct in order to set up EEPROM access.
350 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
352 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
356 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
358 if (eeprom->type == ixgbe_eeprom_uninitialized) {
359 eeprom->semaphore_delay = 10;
360 eeprom->type = ixgbe_flash;
362 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
363 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
364 IXGBE_EEC_SIZE_SHIFT);
365 eeprom->word_size = 1 << (eeprom_size +
366 IXGBE_EEPROM_WORD_SIZE_SHIFT);
368 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
369 eeprom->type, eeprom->word_size);
372 return IXGBE_SUCCESS;
376 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
377 * @hw: pointer to hardware structure
378 * @offset: offset of word in the EEPROM to read
379 * @data: word read from the EEPROM
381 * Reads a 16 bit word from the EEPROM using the EERD register.
383 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
385 s32 status = IXGBE_SUCCESS;
387 DEBUGFUNC("ixgbe_read_eerd_X540");
388 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
390 status = ixgbe_read_eerd_generic(hw, offset, data);
391 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
393 status = IXGBE_ERR_SWFW_SYNC;
400 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
401 * @hw: pointer to hardware structure
402 * @offset: offset of word in the EEPROM to read
403 * @words: number of words
404 * @data: word(s) read from the EEPROM
406 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
408 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
409 u16 offset, u16 words, u16 *data)
411 s32 status = IXGBE_SUCCESS;
413 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
414 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
416 status = ixgbe_read_eerd_buffer_generic(hw, offset,
418 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
420 status = IXGBE_ERR_SWFW_SYNC;
427 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
428 * @hw: pointer to hardware structure
429 * @offset: offset of word in the EEPROM to write
430 * @data: word write to the EEPROM
432 * Write a 16 bit word to the EEPROM using the EEWR register.
434 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
436 s32 status = IXGBE_SUCCESS;
438 DEBUGFUNC("ixgbe_write_eewr_X540");
439 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
441 status = ixgbe_write_eewr_generic(hw, offset, data);
442 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
444 status = IXGBE_ERR_SWFW_SYNC;
451 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
452 * @hw: pointer to hardware structure
453 * @offset: offset of word in the EEPROM to write
454 * @words: number of words
455 * @data: word(s) write to the EEPROM
457 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
459 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
460 u16 offset, u16 words, u16 *data)
462 s32 status = IXGBE_SUCCESS;
464 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
465 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
467 status = ixgbe_write_eewr_buffer_generic(hw, offset,
469 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
471 status = IXGBE_ERR_SWFW_SYNC;
478 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
480 * This function does not use synchronization for EERD and EEWR. It can
481 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
483 * @hw: pointer to hardware structure
485 * Returns a negative error code on error, or the 16-bit checksum
487 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
494 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
496 /* Do not use hw->eeprom.ops.read because we do not want to take
497 * the synchronization semaphores here. Instead use
498 * ixgbe_read_eerd_generic
501 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
503 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
506 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
507 if (ixgbe_read_eerd_generic(hw, i, &word)) {
508 DEBUGOUT("EEPROM read failed\n");
509 return IXGBE_ERR_EEPROM;
514 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
515 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
517 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
518 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
521 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
522 DEBUGOUT("EEPROM read failed\n");
523 return IXGBE_ERR_EEPROM;
526 /* Skip pointer section if the pointer is invalid. */
527 if (pointer == 0xFFFF || pointer == 0 ||
528 pointer >= hw->eeprom.word_size)
531 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
532 DEBUGOUT("EEPROM read failed\n");
533 return IXGBE_ERR_EEPROM;
536 /* Skip pointer section if length is invalid. */
537 if (length == 0xFFFF || length == 0 ||
538 (pointer + length) >= hw->eeprom.word_size)
541 for (j = pointer + 1; j <= pointer + length; j++) {
542 if (ixgbe_read_eerd_generic(hw, j, &word)) {
543 DEBUGOUT("EEPROM read failed\n");
544 return IXGBE_ERR_EEPROM;
550 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
552 return (s32)checksum;
556 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
557 * @hw: pointer to hardware structure
558 * @checksum_val: calculated checksum
560 * Performs checksum calculation and validates the EEPROM checksum. If the
561 * caller does not need checksum_val, the value can be NULL.
563 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
568 u16 read_checksum = 0;
570 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
572 /* Read the first word from the EEPROM. If this times out or fails, do
573 * not continue or we could be in for a very long wait while every
576 status = hw->eeprom.ops.read(hw, 0, &checksum);
578 DEBUGOUT("EEPROM read failed\n");
582 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
583 return IXGBE_ERR_SWFW_SYNC;
585 status = hw->eeprom.ops.calc_checksum(hw);
589 checksum = (u16)(status & 0xffff);
591 /* Do not use hw->eeprom.ops.read because we do not want to take
592 * the synchronization semaphores twice here.
594 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
599 /* Verify read checksum from EEPROM is the same as
600 * calculated checksum
602 if (read_checksum != checksum) {
603 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
604 "Invalid EEPROM checksum");
605 status = IXGBE_ERR_EEPROM_CHECKSUM;
608 /* If the user cares, return the calculated checksum */
610 *checksum_val = checksum;
613 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
619 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
620 * @hw: pointer to hardware structure
622 * After writing EEPROM to shadow RAM using EEWR register, software calculates
623 * checksum and updates the EEPROM and instructs the hardware to update
626 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
631 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
633 /* Read the first word from the EEPROM. If this times out or fails, do
634 * not continue or we could be in for a very long wait while every
637 status = hw->eeprom.ops.read(hw, 0, &checksum);
639 DEBUGOUT("EEPROM read failed\n");
643 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
644 return IXGBE_ERR_SWFW_SYNC;
646 status = hw->eeprom.ops.calc_checksum(hw);
650 checksum = (u16)(status & 0xffff);
652 /* Do not use hw->eeprom.ops.write because we do not want to
653 * take the synchronization semaphores twice here.
655 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
659 status = ixgbe_update_flash_X540(hw);
662 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
668 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
669 * @hw: pointer to hardware structure
671 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
672 * EEPROM from shadow RAM to the flash device.
674 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
679 DEBUGFUNC("ixgbe_update_flash_X540");
681 status = ixgbe_poll_flash_update_done_X540(hw);
682 if (status == IXGBE_ERR_EEPROM) {
683 DEBUGOUT("Flash update time out\n");
687 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
688 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
690 status = ixgbe_poll_flash_update_done_X540(hw);
691 if (status == IXGBE_SUCCESS)
692 DEBUGOUT("Flash update complete\n");
694 DEBUGOUT("Flash update time out\n");
696 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
697 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
699 if (flup & IXGBE_EEC_SEC1VAL) {
700 flup |= IXGBE_EEC_FLUP;
701 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
704 status = ixgbe_poll_flash_update_done_X540(hw);
705 if (status == IXGBE_SUCCESS)
706 DEBUGOUT("Flash update complete\n");
708 DEBUGOUT("Flash update time out\n");
715 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
716 * @hw: pointer to hardware structure
718 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
719 * flash update is done.
721 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
725 s32 status = IXGBE_ERR_EEPROM;
727 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
729 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
730 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
731 if (reg & IXGBE_EEC_FLUDONE) {
732 status = IXGBE_SUCCESS;
738 if (i == IXGBE_FLUDONE_ATTEMPTS)
739 ERROR_REPORT1(IXGBE_ERROR_POLLING,
740 "Flash update status polling timed out");
746 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
747 * @hw: pointer to hardware structure
748 * @mask: Mask to specify which semaphore to acquire
750 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
751 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
753 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
755 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
756 u32 fwmask = swmask << 5;
757 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
763 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
765 if (swmask & IXGBE_GSSR_EEP_SM)
766 hwmask |= IXGBE_GSSR_FLASH_SM;
768 /* SW only mask doesn't have FW bit pair */
769 if (mask & IXGBE_GSSR_SW_MNG_SM)
770 swmask |= IXGBE_GSSR_SW_MNG_SM;
772 swmask |= swi2c_mask;
773 fwmask |= swi2c_mask << 2;
774 for (i = 0; i < timeout; i++) {
775 /* SW NVM semaphore bit is used for access to all
776 * SW_FW_SYNC bits (not just NVM)
778 if (ixgbe_get_swfw_sync_semaphore(hw))
779 return IXGBE_ERR_SWFW_SYNC;
781 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
782 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
784 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
786 ixgbe_release_swfw_sync_semaphore(hw);
787 return IXGBE_SUCCESS;
789 /* Firmware currently using resource (fwmask), hardware
790 * currently using resource (hwmask), or other software
791 * thread currently using resource (swmask)
793 ixgbe_release_swfw_sync_semaphore(hw);
797 /* Failed to get SW only semaphore */
798 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
799 ERROR_REPORT1(IXGBE_ERROR_POLLING,
800 "Failed to get SW only semaphore");
801 return IXGBE_ERR_SWFW_SYNC;
804 /* If the resource is not released by the FW/HW the SW can assume that
805 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
806 * of the requested resource(s) while ignoring the corresponding FW/HW
807 * bits in the SW_FW_SYNC register.
809 if (ixgbe_get_swfw_sync_semaphore(hw))
810 return IXGBE_ERR_SWFW_SYNC;
811 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
812 if (swfw_sync & (fwmask | hwmask)) {
814 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
815 ixgbe_release_swfw_sync_semaphore(hw);
817 return IXGBE_SUCCESS;
819 /* If the resource is not released by other SW the SW can assume that
820 * the other SW malfunctions. In that case the SW should clear all SW
821 * flags that it does not own and then repeat the whole process once
824 if (swfw_sync & swmask) {
825 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
826 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
829 rmask |= IXGBE_GSSR_I2C_MASK;
830 ixgbe_release_swfw_sync_X540(hw, rmask);
831 ixgbe_release_swfw_sync_semaphore(hw);
832 return IXGBE_ERR_SWFW_SYNC;
834 ixgbe_release_swfw_sync_semaphore(hw);
836 return IXGBE_ERR_SWFW_SYNC;
840 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
841 * @hw: pointer to hardware structure
842 * @mask: Mask to specify which semaphore to release
844 * Releases the SWFW semaphore through the SW_FW_SYNC register
845 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
847 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
849 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
852 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
854 if (mask & IXGBE_GSSR_I2C_MASK)
855 swmask |= mask & IXGBE_GSSR_I2C_MASK;
856 ixgbe_get_swfw_sync_semaphore(hw);
858 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
859 swfw_sync &= ~swmask;
860 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
862 ixgbe_release_swfw_sync_semaphore(hw);
867 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
868 * @hw: pointer to hardware structure
870 * Sets the hardware semaphores so SW/FW can gain control of shared resources
872 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
874 s32 status = IXGBE_ERR_EEPROM;
879 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
881 /* Get SMBI software semaphore between device drivers first */
882 for (i = 0; i < timeout; i++) {
884 * If the SMBI bit is 0 when we read it, then the bit will be
885 * set and we have the semaphore
887 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
888 if (!(swsm & IXGBE_SWSM_SMBI)) {
889 status = IXGBE_SUCCESS;
895 /* Now get the semaphore between SW/FW through the REGSMP bit */
896 if (status == IXGBE_SUCCESS) {
897 for (i = 0; i < timeout; i++) {
898 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
899 if (!(swsm & IXGBE_SWFW_REGSMP))
906 * Release semaphores and return error if SW NVM semaphore
907 * was not granted because we don't have access to the EEPROM
910 ERROR_REPORT1(IXGBE_ERROR_POLLING,
911 "REGSMP Software NVM semaphore not granted.\n");
912 ixgbe_release_swfw_sync_semaphore(hw);
913 status = IXGBE_ERR_EEPROM;
916 ERROR_REPORT1(IXGBE_ERROR_POLLING,
917 "Software semaphore SMBI between device drivers "
925 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
926 * @hw: pointer to hardware structure
928 * This function clears hardware semaphore bits.
930 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
934 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
936 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
938 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
939 swsm &= ~IXGBE_SWFW_REGSMP;
940 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
942 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
943 swsm &= ~IXGBE_SWSM_SMBI;
944 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
946 IXGBE_WRITE_FLUSH(hw);
950 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
951 * @hw: pointer to hardware structure
953 * This function reset hardware semaphore bits for a semaphore that may
954 * have be left locked due to a catastrophic failure.
956 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
958 /* First try to grab the semaphore but we don't need to bother
959 * looking to see whether we got the lock or not since we do
960 * the same thing regardless of whether we got the lock or not.
961 * We got the lock - we release it.
962 * We timeout trying to get the lock - we force its release.
964 ixgbe_get_swfw_sync_semaphore(hw);
965 ixgbe_release_swfw_sync_semaphore(hw);
969 * ixgbe_blink_led_start_X540 - Blink LED based on index.
970 * @hw: pointer to hardware structure
971 * @index: led number to blink
973 * Devices that implement the version 2 interface:
976 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
980 ixgbe_link_speed speed;
983 DEBUGFUNC("ixgbe_blink_led_start_X540");
986 return IXGBE_ERR_PARAM;
989 * Link should be up in order for the blink bit in the LED control
990 * register to work. Force link and speed in the MAC if link is down.
991 * This will be reversed when we stop the blinking.
993 hw->mac.ops.check_link(hw, &speed, &link_up, false);
994 if (link_up == false) {
995 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
996 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
997 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
999 /* Set the LED to LINK_UP + BLINK. */
1000 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1001 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1002 ledctl_reg |= IXGBE_LED_BLINK(index);
1003 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1004 IXGBE_WRITE_FLUSH(hw);
1006 return IXGBE_SUCCESS;
1010 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1011 * @hw: pointer to hardware structure
1012 * @index: led number to stop blinking
1014 * Devices that implement the version 2 interface:
1017 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1023 return IXGBE_ERR_PARAM;
1025 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1027 /* Restore the LED to its default value. */
1028 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1029 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1030 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1031 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1032 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1034 /* Unforce link and speed in the MAC. */
1035 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1036 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1037 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1038 IXGBE_WRITE_FLUSH(hw);
1040 return IXGBE_SUCCESS;