1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
44 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
45 * @hw: pointer to hardware structure
47 * Initialize the function pointers and assign the MAC type for X550.
48 * Does not touch the hardware.
50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
52 struct ixgbe_mac_info *mac = &hw->mac;
53 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
56 DEBUGFUNC("ixgbe_init_ops_X550");
58 ret_val = ixgbe_init_ops_X540(hw);
59 mac->ops.dmac_config = ixgbe_dmac_config_X550;
60 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
61 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
62 mac->ops.setup_eee = ixgbe_setup_eee_X550;
63 mac->ops.set_source_address_pruning =
64 ixgbe_set_source_address_pruning_X550;
65 mac->ops.set_ethertype_anti_spoofing =
66 ixgbe_set_ethertype_anti_spoofing_X550;
68 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
69 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
70 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
71 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
72 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
73 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
74 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
75 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
76 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
79 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
80 mac->ops.mdd_event = ixgbe_mdd_event_X550;
81 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
82 mac->ops.disable_rx = ixgbe_disable_rx_x550;
83 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
84 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
85 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
91 * ixgbe_read_cs4227 - Read CS4227 register
92 * @hw: pointer to hardware structure
93 * @reg: register number to write
94 * @value: pointer to receive value read
98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
104 * ixgbe_write_cs4227 - Write CS4227 register
105 * @hw: pointer to hardware structure
106 * @reg: register number to write
107 * @value: value to write to register
109 * Returns status code
111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
117 * ixgbe_read_pe - Read register from port expander
118 * @hw: pointer to hardware structure
119 * @reg: register number to read
120 * @value: pointer to receive read value
122 * Returns status code
124 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
128 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
129 if (status != IXGBE_SUCCESS)
130 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
131 "port expander access failed with %d\n", status);
136 * ixgbe_write_pe - Write register to port expander
137 * @hw: pointer to hardware structure
138 * @reg: register number to write
139 * @value: value to write
141 * Returns status code
143 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
147 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
148 if (status != IXGBE_SUCCESS)
149 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
150 "port expander access failed with %d\n", status);
155 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
156 * @hw: pointer to hardware structure
158 * This function assumes that the caller has acquired the proper semaphore.
161 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
168 /* Trigger hard reset. */
169 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
170 if (status != IXGBE_SUCCESS)
172 reg |= IXGBE_PE_BIT1;
173 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
174 if (status != IXGBE_SUCCESS)
177 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
178 if (status != IXGBE_SUCCESS)
180 reg &= ~IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
190 if (status != IXGBE_SUCCESS)
193 usec_delay(IXGBE_CS4227_RESET_HOLD);
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg |= IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 /* Wait for the reset to complete. */
204 msec_delay(IXGBE_CS4227_RESET_DELAY);
205 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
206 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
208 if (status == IXGBE_SUCCESS &&
209 value == IXGBE_CS4227_EEPROM_LOAD_OK)
211 msec_delay(IXGBE_CS4227_CHECK_DELAY);
213 if (retry == IXGBE_CS4227_RETRIES) {
214 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
215 "CS4227 reset did not complete.");
216 return IXGBE_ERR_PHY;
219 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
220 if (status != IXGBE_SUCCESS ||
221 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 EEPROM did not load successfully.");
224 return IXGBE_ERR_PHY;
227 return IXGBE_SUCCESS;
231 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
232 * @hw: pointer to hardware structure
234 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
236 s32 status = IXGBE_SUCCESS;
237 u32 swfw_mask = hw->phy.phy_semaphore_mask;
241 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
242 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
243 if (status != IXGBE_SUCCESS) {
244 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
245 "semaphore failed with %d", status);
246 msec_delay(IXGBE_CS4227_CHECK_DELAY);
250 /* Get status of reset flow. */
251 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
253 if (status == IXGBE_SUCCESS &&
254 value == IXGBE_CS4227_RESET_COMPLETE)
257 if (status != IXGBE_SUCCESS ||
258 value != IXGBE_CS4227_RESET_PENDING)
261 /* Reset is pending. Wait and check again. */
262 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
263 msec_delay(IXGBE_CS4227_CHECK_DELAY);
266 /* If still pending, assume other instance failed. */
267 if (retry == IXGBE_CS4227_RETRIES) {
268 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
269 if (status != IXGBE_SUCCESS) {
270 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
271 "semaphore failed with %d", status);
276 /* Reset the CS4227. */
277 status = ixgbe_reset_cs4227(hw);
278 if (status != IXGBE_SUCCESS) {
279 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
280 "CS4227 reset failed: %d", status);
284 /* Reset takes so long, temporarily release semaphore in case the
285 * other driver instance is waiting for the reset indication.
287 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
288 IXGBE_CS4227_RESET_PENDING);
289 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
291 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
292 if (status != IXGBE_SUCCESS) {
293 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
294 "semaphore failed with %d", status);
298 /* Record completion for next time. */
299 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
300 IXGBE_CS4227_RESET_COMPLETE);
303 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
304 msec_delay(hw->eeprom.semaphore_delay);
308 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
309 * @hw: pointer to hardware structure
311 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
313 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
315 if (hw->bus.lan_id) {
316 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
317 esdp |= IXGBE_ESDP_SDP1_DIR;
319 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
320 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
321 IXGBE_WRITE_FLUSH(hw);
325 * ixgbe_identify_phy_x550em - Get PHY type based on device id
326 * @hw: pointer to hardware structure
330 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
332 switch (hw->device_id) {
333 case IXGBE_DEV_ID_X550EM_X_SFP:
334 /* set up for CS4227 usage */
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
336 ixgbe_setup_mux_ctl(hw);
337 ixgbe_check_cs4227(hw);
339 return ixgbe_identify_module_generic(hw);
341 case IXGBE_DEV_ID_X550EM_X_KX4:
342 hw->phy.type = ixgbe_phy_x550em_kx4;
344 case IXGBE_DEV_ID_X550EM_X_KR:
345 hw->phy.type = ixgbe_phy_x550em_kr;
347 case IXGBE_DEV_ID_X550EM_X_1G_T:
348 case IXGBE_DEV_ID_X550EM_X_10G_T:
349 return ixgbe_identify_phy_generic(hw);
353 return IXGBE_SUCCESS;
356 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
357 u32 device_type, u16 *phy_data)
359 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
360 return IXGBE_NOT_IMPLEMENTED;
363 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
364 u32 device_type, u16 phy_data)
366 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
367 return IXGBE_NOT_IMPLEMENTED;
371 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
372 * @hw: pointer to hardware structure
374 * Initialize the function pointers and for MAC type X550EM.
375 * Does not touch the hardware.
377 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
379 struct ixgbe_mac_info *mac = &hw->mac;
380 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
381 struct ixgbe_phy_info *phy = &hw->phy;
384 DEBUGFUNC("ixgbe_init_ops_X550EM");
386 /* Similar to X550 so start there. */
387 ret_val = ixgbe_init_ops_X550(hw);
389 /* Since this function eventually calls
390 * ixgbe_init_ops_540 by design, we are setting
391 * the pointers to NULL explicitly here to overwrite
392 * the values being set in the x540 function.
394 /* Thermal sensor not supported in x550EM */
395 mac->ops.get_thermal_sensor_data = NULL;
396 mac->ops.init_thermal_sensor_thresh = NULL;
397 mac->thermal_sensor_enabled = false;
399 /* FCOE not supported in x550EM */
400 mac->ops.get_san_mac_addr = NULL;
401 mac->ops.set_san_mac_addr = NULL;
402 mac->ops.get_wwn_prefix = NULL;
403 mac->ops.get_fcoe_boot_status = NULL;
405 /* IPsec not supported in x550EM */
406 mac->ops.disable_sec_rx_path = NULL;
407 mac->ops.enable_sec_rx_path = NULL;
409 /* AUTOC register is not present in x550EM. */
410 mac->ops.prot_autoc_read = NULL;
411 mac->ops.prot_autoc_write = NULL;
413 /* X550EM bus type is internal*/
414 hw->bus.type = ixgbe_bus_type_internal;
415 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
417 if (hw->mac.type == ixgbe_mac_X550EM_x) {
418 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
419 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
420 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
421 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
424 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
425 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
426 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
427 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
428 mac->ops.get_supported_physical_layer =
429 ixgbe_get_supported_physical_layer_X550em;
431 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
432 mac->ops.setup_fc = ixgbe_setup_fc_generic;
434 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
437 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
438 mac->ops.setup_eee = NULL;
441 phy->ops.init = ixgbe_init_phy_ops_X550em;
442 phy->ops.identify = ixgbe_identify_phy_x550em;
443 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
444 phy->ops.set_phy_power = NULL;
448 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
449 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
450 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
451 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
452 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
453 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
454 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
455 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
461 * ixgbe_dmac_config_X550
462 * @hw: pointer to hardware structure
464 * Configure DMA coalescing. If enabling dmac, dmac is activated.
465 * When disabling dmac, dmac enable dmac bit is cleared.
467 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
469 u32 reg, high_pri_tc;
471 DEBUGFUNC("ixgbe_dmac_config_X550");
473 /* Disable DMA coalescing before configuring */
474 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
475 reg &= ~IXGBE_DMACR_DMAC_EN;
476 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
478 /* Disable DMA Coalescing if the watchdog timer is 0 */
479 if (!hw->mac.dmac_config.watchdog_timer)
482 ixgbe_dmac_config_tcs_X550(hw);
484 /* Configure DMA Coalescing Control Register */
485 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
487 /* Set the watchdog timer in units of 40.96 usec */
488 reg &= ~IXGBE_DMACR_DMACWT_MASK;
489 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
491 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
492 /* If fcoe is enabled, set high priority traffic class */
493 if (hw->mac.dmac_config.fcoe_en) {
494 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
495 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
496 IXGBE_DMACR_HIGH_PRI_TC_MASK);
498 reg |= IXGBE_DMACR_EN_MNG_IND;
500 /* Enable DMA coalescing after configuration */
501 reg |= IXGBE_DMACR_DMAC_EN;
502 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
505 return IXGBE_SUCCESS;
509 * ixgbe_dmac_config_tcs_X550
510 * @hw: pointer to hardware structure
512 * Configure DMA coalescing threshold per TC. The dmac enable bit must
513 * be cleared before configuring.
515 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
517 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
519 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
521 /* Configure DMA coalescing enabled */
522 switch (hw->mac.dmac_config.link_speed) {
523 case IXGBE_LINK_SPEED_100_FULL:
524 pb_headroom = IXGBE_DMACRXT_100M;
526 case IXGBE_LINK_SPEED_1GB_FULL:
527 pb_headroom = IXGBE_DMACRXT_1G;
530 pb_headroom = IXGBE_DMACRXT_10G;
534 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
535 IXGBE_MHADD_MFS_SHIFT) / 1024);
537 /* Set the per Rx packet buffer receive threshold */
538 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
539 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
540 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
542 if (tc < hw->mac.dmac_config.num_tcs) {
544 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
545 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
546 IXGBE_RXPBSIZE_SHIFT;
548 /* Calculate receive buffer threshold in kilobytes */
549 if (rx_pb_size > pb_headroom)
550 rx_pb_size = rx_pb_size - pb_headroom;
554 /* Minimum of MFS shall be set for DMCTH */
555 reg |= (rx_pb_size > maxframe_size_kb) ?
556 rx_pb_size : maxframe_size_kb;
558 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
560 return IXGBE_SUCCESS;
564 * ixgbe_dmac_update_tcs_X550
565 * @hw: pointer to hardware structure
567 * Disables dmac, updates per TC settings, and then enables dmac.
569 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
573 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
575 /* Disable DMA coalescing before configuring */
576 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
577 reg &= ~IXGBE_DMACR_DMAC_EN;
578 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
580 ixgbe_dmac_config_tcs_X550(hw);
582 /* Enable DMA coalescing after configuration */
583 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
584 reg |= IXGBE_DMACR_DMAC_EN;
585 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
587 return IXGBE_SUCCESS;
591 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
592 * @hw: pointer to hardware structure
594 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
595 * ixgbe_hw struct in order to set up EEPROM access.
597 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
599 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
603 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
605 if (eeprom->type == ixgbe_eeprom_uninitialized) {
606 eeprom->semaphore_delay = 10;
607 eeprom->type = ixgbe_flash;
609 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
610 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
611 IXGBE_EEC_SIZE_SHIFT);
612 eeprom->word_size = 1 << (eeprom_size +
613 IXGBE_EEPROM_WORD_SIZE_SHIFT);
615 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
616 eeprom->type, eeprom->word_size);
619 return IXGBE_SUCCESS;
623 * ixgbe_setup_eee_X550 - Enable/disable EEE support
624 * @hw: pointer to the HW structure
625 * @enable_eee: boolean flag to enable EEE
627 * Enable/disable EEE based on enable_eee flag.
628 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
632 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
640 DEBUGFUNC("ixgbe_setup_eee_X550");
642 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
643 /* Enable or disable EEE per flag */
645 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
647 if (hw->device_id == IXGBE_DEV_ID_X550T) {
648 /* Advertise EEE capability */
649 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
650 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
652 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
653 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
654 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
656 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
657 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
658 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
659 /* Not supported on first revision. */
660 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
661 if (!(fuse & IXGBE_FUSES0_REV1))
662 return IXGBE_SUCCESS;
664 status = ixgbe_read_iosf_sb_reg_x550(hw,
665 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
666 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
667 if (status != IXGBE_SUCCESS)
670 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
671 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
673 /* Don't advertise FEC capability when EEE enabled. */
674 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
676 status = ixgbe_write_iosf_sb_reg_x550(hw,
677 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
678 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
679 if (status != IXGBE_SUCCESS)
683 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
685 if (hw->device_id == IXGBE_DEV_ID_X550T) {
686 /* Disable advertised EEE capability */
687 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
688 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
690 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
691 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
692 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
694 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
695 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
696 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
697 status = ixgbe_read_iosf_sb_reg_x550(hw,
698 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
699 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
700 if (status != IXGBE_SUCCESS)
703 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
704 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
706 /* Advertise FEC capability when EEE is disabled. */
707 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
709 status = ixgbe_write_iosf_sb_reg_x550(hw,
710 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
711 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
712 if (status != IXGBE_SUCCESS)
716 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
718 return IXGBE_SUCCESS;
722 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
723 * @hw: pointer to hardware structure
724 * @enable: enable or disable source address pruning
725 * @pool: Rx pool to set source address pruning for
727 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
732 /* max rx pool is 63 */
736 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
737 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
740 pfflp |= (1ULL << pool);
742 pfflp &= ~(1ULL << pool);
744 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
745 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
749 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
750 * @hw: pointer to hardware structure
751 * @enable: enable or disable switch for Ethertype anti-spoofing
752 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
755 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
758 int vf_target_reg = vf >> 3;
759 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
762 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
764 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
766 pfvfspoof |= (1 << vf_target_shift);
768 pfvfspoof &= ~(1 << vf_target_shift);
770 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
774 * ixgbe_iosf_wait - Wait for IOSF command completion
775 * @hw: pointer to hardware structure
776 * @ctrl: pointer to location to receive final IOSF control value
778 * Returns failing status on timeout
780 * Note: ctrl can be NULL if the IOSF control register value is not needed
782 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
786 /* Check every 10 usec to see if the address cycle completed.
787 * The SB IOSF BUSY bit will clear when the operation is
790 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
791 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
792 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
798 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
799 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
800 return IXGBE_ERR_PHY;
803 return IXGBE_SUCCESS;
807 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
809 * @hw: pointer to hardware structure
810 * @reg_addr: 32 bit PHY register to write
811 * @device_type: 3 bit device type
812 * @data: Data to write to the register
814 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
815 u32 device_type, u32 data)
817 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
821 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
822 if (ret != IXGBE_SUCCESS)
825 ret = ixgbe_iosf_wait(hw, NULL);
826 if (ret != IXGBE_SUCCESS)
829 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
830 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
832 /* Write IOSF control register */
833 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
835 /* Write IOSF data register */
836 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
838 ret = ixgbe_iosf_wait(hw, &command);
840 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
841 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
842 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
843 ERROR_REPORT2(IXGBE_ERROR_POLLING,
844 "Failed to write, error %x\n", error);
849 ixgbe_release_swfw_semaphore(hw, gssr);
854 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
856 * @hw: pointer to hardware structure
857 * @reg_addr: 32 bit PHY register to write
858 * @device_type: 3 bit device type
859 * @phy_data: Pointer to read data from the register
861 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
862 u32 device_type, u32 *data)
864 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
868 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
869 if (ret != IXGBE_SUCCESS)
872 ret = ixgbe_iosf_wait(hw, NULL);
873 if (ret != IXGBE_SUCCESS)
876 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
877 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
879 /* Write IOSF control register */
880 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
882 ret = ixgbe_iosf_wait(hw, &command);
884 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
885 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
886 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
887 ERROR_REPORT2(IXGBE_ERROR_POLLING,
888 "Failed to read, error %x\n", error);
892 if (ret == IXGBE_SUCCESS)
893 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
896 ixgbe_release_swfw_semaphore(hw, gssr);
901 * ixgbe_disable_mdd_X550
902 * @hw: pointer to hardware structure
904 * Disable malicious driver detection
906 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
910 DEBUGFUNC("ixgbe_disable_mdd_X550");
912 /* Disable MDD for TX DMA and interrupt */
913 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
914 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
915 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
917 /* Disable MDD for RX and interrupt */
918 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
919 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
920 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
924 * ixgbe_enable_mdd_X550
925 * @hw: pointer to hardware structure
927 * Enable malicious driver detection
929 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
933 DEBUGFUNC("ixgbe_enable_mdd_X550");
935 /* Enable MDD for TX DMA and interrupt */
936 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
937 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
938 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
940 /* Enable MDD for RX and interrupt */
941 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
942 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
943 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
947 * ixgbe_restore_mdd_vf_X550
948 * @hw: pointer to hardware structure
951 * Restore VF that was disabled during malicious driver detection event
953 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
955 u32 idx, reg, num_qs, start_q, bitmask;
957 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
959 /* Map VF to queues */
960 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
961 switch (reg & IXGBE_MRQC_MRQE_MASK) {
962 case IXGBE_MRQC_VMDQRT8TCEN:
963 num_qs = 8; /* 16 VFs / pools */
964 bitmask = 0x000000FF;
966 case IXGBE_MRQC_VMDQRSS32EN:
967 case IXGBE_MRQC_VMDQRT4TCEN:
968 num_qs = 4; /* 32 VFs / pools */
969 bitmask = 0x0000000F;
971 default: /* 64 VFs / pools */
973 bitmask = 0x00000003;
976 start_q = vf * num_qs;
978 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
981 reg |= (bitmask << (start_q % 32));
982 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
983 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
987 * ixgbe_mdd_event_X550
988 * @hw: pointer to hardware structure
989 * @vf_bitmap: vf bitmap of malicious vfs
991 * Handle malicious driver detection event.
993 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
996 u32 i, j, reg, q, shift, vf, idx;
998 DEBUGFUNC("ixgbe_mdd_event_X550");
1000 /* figure out pool size for mapping to vf's */
1001 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1002 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1003 case IXGBE_MRQC_VMDQRT8TCEN:
1004 shift = 3; /* 16 VFs / pools */
1006 case IXGBE_MRQC_VMDQRSS32EN:
1007 case IXGBE_MRQC_VMDQRT4TCEN:
1008 shift = 2; /* 32 VFs / pools */
1011 shift = 1; /* 64 VFs / pools */
1015 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1016 for (i = 0; i < 4; i++) {
1017 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1018 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1023 /* Get malicious queue */
1024 for (j = 0; j < 32 && wqbr; j++) {
1026 if (!(wqbr & (1 << j)))
1029 /* Get queue from bitmask */
1032 /* Map queue to vf */
1035 /* Set vf bit in vf_bitmap */
1037 vf_bitmap[idx] |= (1 << (vf % 32));
1044 * ixgbe_get_media_type_X550em - Get media type
1045 * @hw: pointer to hardware structure
1047 * Returns the media type (fiber, copper, backplane)
1049 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1051 enum ixgbe_media_type media_type;
1053 DEBUGFUNC("ixgbe_get_media_type_X550em");
1055 /* Detect if there is a copper PHY attached. */
1056 switch (hw->device_id) {
1057 case IXGBE_DEV_ID_X550EM_X_KR:
1058 case IXGBE_DEV_ID_X550EM_X_KX4:
1059 media_type = ixgbe_media_type_backplane;
1061 case IXGBE_DEV_ID_X550EM_X_SFP:
1062 media_type = ixgbe_media_type_fiber;
1064 case IXGBE_DEV_ID_X550EM_X_1G_T:
1065 case IXGBE_DEV_ID_X550EM_X_10G_T:
1066 media_type = ixgbe_media_type_copper;
1069 media_type = ixgbe_media_type_unknown;
1076 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1077 * @hw: pointer to hardware structure
1078 * @linear: true if SFP module is linear
1080 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1082 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1084 switch (hw->phy.sfp_type) {
1085 case ixgbe_sfp_type_not_present:
1086 return IXGBE_ERR_SFP_NOT_PRESENT;
1087 case ixgbe_sfp_type_da_cu_core0:
1088 case ixgbe_sfp_type_da_cu_core1:
1091 case ixgbe_sfp_type_srlr_core0:
1092 case ixgbe_sfp_type_srlr_core1:
1093 case ixgbe_sfp_type_da_act_lmt_core0:
1094 case ixgbe_sfp_type_da_act_lmt_core1:
1095 case ixgbe_sfp_type_1g_sx_core0:
1096 case ixgbe_sfp_type_1g_sx_core1:
1097 case ixgbe_sfp_type_1g_lx_core0:
1098 case ixgbe_sfp_type_1g_lx_core1:
1101 case ixgbe_sfp_type_unknown:
1102 case ixgbe_sfp_type_1g_cu_core0:
1103 case ixgbe_sfp_type_1g_cu_core1:
1105 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1108 return IXGBE_SUCCESS;
1112 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1113 * @hw: pointer to hardware structure
1115 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1117 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1122 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1124 status = ixgbe_identify_module_generic(hw);
1126 if (status != IXGBE_SUCCESS)
1129 /* Check if SFP module is supported */
1130 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1136 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1137 * @hw: pointer to hardware structure
1139 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1144 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1146 /* Check if SFP module is supported */
1147 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1149 if (status != IXGBE_SUCCESS)
1152 ixgbe_init_mac_link_ops_X550em(hw);
1153 hw->phy.ops.reset = NULL;
1155 return IXGBE_SUCCESS;
1159 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1160 * @hw: pointer to hardware structure
1162 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1164 struct ixgbe_mac_info *mac = &hw->mac;
1166 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1168 switch (hw->mac.ops.get_media_type(hw)) {
1169 case ixgbe_media_type_fiber:
1170 /* CS4227 does not support autoneg, so disable the laser control
1171 * functions for SFP+ fiber
1173 mac->ops.disable_tx_laser = NULL;
1174 mac->ops.enable_tx_laser = NULL;
1175 mac->ops.flap_tx_laser = NULL;
1176 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1177 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1178 mac->ops.set_rate_select_speed =
1179 ixgbe_set_soft_rate_select_speed;
1181 case ixgbe_media_type_copper:
1182 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1183 mac->ops.check_link = ixgbe_check_link_t_X550em;
1191 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1192 * @hw: pointer to hardware structure
1193 * @speed: pointer to link speed
1194 * @autoneg: true when autoneg or autotry is enabled
1196 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1197 ixgbe_link_speed *speed,
1200 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1203 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1205 /* CS4227 SFP must not enable auto-negotiation */
1208 /* Check if 1G SFP module. */
1209 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1211 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1212 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1213 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1214 return IXGBE_SUCCESS;
1217 /* Link capabilities are based on SFP */
1218 if (hw->phy.multispeed_fiber)
1219 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1220 IXGBE_LINK_SPEED_1GB_FULL;
1222 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1224 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1225 IXGBE_LINK_SPEED_1GB_FULL;
1229 return IXGBE_SUCCESS;
1233 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1234 * @hw: pointer to hardware structure
1235 * @lsc: pointer to boolean flag which indicates whether external Base T
1236 * PHY interrupt is lsc
1238 * Determime if external Base T PHY interrupt cause is high temperature
1239 * failure alarm or link status change.
1241 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1242 * failure alarm, else return PHY access status.
1244 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1251 /* Vendor alarm triggered */
1252 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1253 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1256 if (status != IXGBE_SUCCESS ||
1257 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1260 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1261 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1262 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1265 if (status != IXGBE_SUCCESS ||
1266 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1267 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1270 /* High temperature failure alarm triggered */
1271 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1272 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1275 if (status != IXGBE_SUCCESS)
1278 /* If high temperature failure, then return over temp error and exit */
1279 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1280 /* power down the PHY in case the PHY FW didn't already */
1281 ixgbe_set_copper_phy_power(hw, false);
1282 return IXGBE_ERR_OVERTEMP;
1285 /* Vendor alarm 2 triggered */
1286 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1287 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1289 if (status != IXGBE_SUCCESS ||
1290 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1293 /* link connect/disconnect event occurred */
1294 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1295 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1297 if (status != IXGBE_SUCCESS)
1301 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1304 return IXGBE_SUCCESS;
1308 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1309 * @hw: pointer to hardware structure
1311 * Enable link status change and temperature failure alarm for the external
1314 * Returns PHY access status
1316 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1322 /* Clear interrupt flags */
1323 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1325 /* Enable link status change alarm */
1326 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1327 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1329 if (status != IXGBE_SUCCESS)
1332 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1334 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1335 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1337 if (status != IXGBE_SUCCESS)
1340 /* Enables high temperature failure alarm */
1341 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1342 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1345 if (status != IXGBE_SUCCESS)
1348 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1350 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1351 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1354 if (status != IXGBE_SUCCESS)
1357 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1358 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1359 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1362 if (status != IXGBE_SUCCESS)
1365 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1366 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1368 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1369 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1372 if (status != IXGBE_SUCCESS)
1375 /* Enable chip-wide vendor alarm */
1376 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1377 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1380 if (status != IXGBE_SUCCESS)
1383 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1385 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1386 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1393 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1394 * @hw: pointer to hardware structure
1395 * @speed: link speed
1397 * Configures the integrated KR PHY.
1399 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1400 ixgbe_link_speed speed)
1405 status = ixgbe_read_iosf_sb_reg_x550(hw,
1406 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1407 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1411 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1412 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1413 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1415 /* Advertise 10G support. */
1416 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1417 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1419 /* Advertise 1G support. */
1420 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1421 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1423 /* Restart auto-negotiation. */
1424 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1425 status = ixgbe_write_iosf_sb_reg_x550(hw,
1426 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1427 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1433 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1434 * @hw: pointer to hardware structure
1436 * Initialize any function pointers that were not able to be
1437 * set during init_shared_code because the PHY/SFP type was
1438 * not known. Perform the SFP init if necessary.
1440 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1442 struct ixgbe_phy_info *phy = &hw->phy;
1445 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1447 hw->mac.ops.set_lan_id(hw);
1449 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1450 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1451 ixgbe_setup_mux_ctl(hw);
1453 /* Save NW management interface connected on board. This is used
1454 * to determine internal PHY mode.
1456 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1457 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1460 /* Identify the PHY or SFP module */
1461 ret_val = phy->ops.identify(hw);
1462 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1465 /* Setup function pointers based on detected hardware */
1466 ixgbe_init_mac_link_ops_X550em(hw);
1467 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1468 phy->ops.reset = NULL;
1470 /* Set functions pointers based on phy type */
1471 switch (hw->phy.type) {
1472 case ixgbe_phy_x550em_kx4:
1473 phy->ops.setup_link = NULL;
1474 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1475 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1477 case ixgbe_phy_x550em_kr:
1478 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1479 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1480 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1482 case ixgbe_phy_x550em_ext_t:
1483 /* Save NW management interface connected on board. This is used
1484 * to determine internal PHY mode
1486 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1488 /* If internal link mode is XFI, then setup iXFI internal link,
1489 * else setup KR now.
1491 phy->ops.setup_internal_link =
1492 ixgbe_setup_internal_phy_t_x550em;
1494 /* setup SW LPLU only for first revision */
1495 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1496 IXGBE_FUSES0_GROUP(0))))
1497 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1499 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1500 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1509 * ixgbe_reset_hw_X550em - Perform hardware reset
1510 * @hw: pointer to hardware structure
1512 * Resets the hardware by resetting the transmit and receive units, masks
1513 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1516 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1518 ixgbe_link_speed link_speed;
1523 bool link_up = false;
1525 DEBUGFUNC("ixgbe_reset_hw_X550em");
1527 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1528 status = hw->mac.ops.stop_adapter(hw);
1529 if (status != IXGBE_SUCCESS)
1532 /* flush pending Tx transactions */
1533 ixgbe_clear_tx_pending(hw);
1535 /* PHY ops must be identified and initialized prior to reset */
1537 /* Identify PHY and related function pointers */
1538 status = hw->phy.ops.init(hw);
1540 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1543 /* start the external PHY */
1544 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1545 status = ixgbe_init_ext_t_x550em(hw);
1550 /* Setup SFP module if there is one present. */
1551 if (hw->phy.sfp_setup_needed) {
1552 status = hw->mac.ops.setup_sfp(hw);
1553 hw->phy.sfp_setup_needed = false;
1556 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1560 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1561 hw->phy.ops.reset(hw);
1564 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1565 * If link reset is used when link is up, it might reset the PHY when
1566 * mng is using it. If link is down or the flag to force full link
1567 * reset is set, then perform link reset.
1569 ctrl = IXGBE_CTRL_LNK_RST;
1570 if (!hw->force_full_reset) {
1571 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1573 ctrl = IXGBE_CTRL_RST;
1576 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1577 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1578 IXGBE_WRITE_FLUSH(hw);
1580 /* Poll for reset bit to self-clear meaning reset is complete */
1581 for (i = 0; i < 10; i++) {
1583 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1584 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1588 if (ctrl & IXGBE_CTRL_RST_MASK) {
1589 status = IXGBE_ERR_RESET_FAILED;
1590 DEBUGOUT("Reset polling failed to complete.\n");
1595 /* Double resets are required for recovery from certain error
1596 * conditions. Between resets, it is necessary to stall to
1597 * allow time for any pending HW events to complete.
1599 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1600 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1604 /* Store the permanent mac address */
1605 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1607 /* Store MAC address from RAR0, clear receive address registers, and
1608 * clear the multicast table. Also reset num_rar_entries to 128,
1609 * since we modify this value when programming the SAN MAC address.
1611 hw->mac.num_rar_entries = 128;
1612 hw->mac.ops.init_rx_addrs(hw);
1614 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1615 /* Config MDIO clock speed. */
1616 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1617 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1618 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1621 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1622 ixgbe_setup_mux_ctl(hw);
1628 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1629 * @hw: pointer to hardware structure
1631 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1636 status = hw->phy.ops.read_reg(hw,
1637 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1638 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1641 if (status != IXGBE_SUCCESS)
1644 /* If PHY FW reset completed bit is set then this is the first
1645 * SW instance after a power on so the PHY FW must be un-stalled.
1647 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1648 status = hw->phy.ops.read_reg(hw,
1649 IXGBE_MDIO_GLOBAL_RES_PR_10,
1650 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1653 if (status != IXGBE_SUCCESS)
1656 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1658 status = hw->phy.ops.write_reg(hw,
1659 IXGBE_MDIO_GLOBAL_RES_PR_10,
1660 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1663 if (status != IXGBE_SUCCESS)
1671 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1672 * @hw: pointer to hardware structure
1674 * Configures the integrated KR PHY.
1676 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1678 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1682 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1683 * @hw: pointer to hardware structure
1685 * Configure the external PHY and the integrated KR PHY for SFP support.
1687 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1688 ixgbe_link_speed speed,
1689 bool autoneg_wait_to_complete)
1692 u16 reg_slice, reg_val;
1693 bool setup_linear = false;
1694 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1696 /* Check if SFP module is supported and linear */
1697 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1699 /* If no SFP module present, then return success. Return success since
1700 * there is no reason to configure CS4227 and SFP not present error is
1701 * not excepted in the setup MAC link flow.
1703 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1704 return IXGBE_SUCCESS;
1706 if (ret_val != IXGBE_SUCCESS)
1709 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1710 /* Configure CS4227 LINE side to 10G SR. */
1711 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1712 (hw->bus.lan_id << 12);
1713 reg_val = IXGBE_CS4227_SPEED_10G;
1714 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1717 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1718 (hw->bus.lan_id << 12);
1719 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1720 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1723 /* Configure CS4227 for HOST connection rate then type. */
1724 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1725 (hw->bus.lan_id << 12);
1726 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1727 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1728 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1731 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1732 (hw->bus.lan_id << 12);
1734 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1736 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1737 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1740 /* Setup XFI internal link. */
1741 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1743 /* Configure internal PHY for KR/KX. */
1744 ixgbe_setup_kr_speed_x550em(hw, speed);
1746 /* Configure CS4227 LINE side to proper mode. */
1747 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1748 (hw->bus.lan_id << 12);
1750 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1752 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1753 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1760 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1761 * @hw: pointer to hardware structure
1762 * @speed: the link speed to force
1764 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1765 * internal and external PHY at a specific speed, without autonegotiation.
1767 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1772 /* Disable AN and force speed to 10G Serial. */
1773 status = ixgbe_read_iosf_sb_reg_x550(hw,
1774 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1775 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1776 if (status != IXGBE_SUCCESS)
1779 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1780 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1782 /* Select forced link speed for internal PHY. */
1784 case IXGBE_LINK_SPEED_10GB_FULL:
1785 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1787 case IXGBE_LINK_SPEED_1GB_FULL:
1788 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1791 /* Other link speeds are not supported by internal KR PHY. */
1792 return IXGBE_ERR_LINK_SETUP;
1795 status = ixgbe_write_iosf_sb_reg_x550(hw,
1796 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1797 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1798 if (status != IXGBE_SUCCESS)
1801 /* Disable training protocol FSM. */
1802 status = ixgbe_read_iosf_sb_reg_x550(hw,
1803 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1804 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1805 if (status != IXGBE_SUCCESS)
1807 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1808 status = ixgbe_write_iosf_sb_reg_x550(hw,
1809 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1810 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1811 if (status != IXGBE_SUCCESS)
1814 /* Disable Flex from training TXFFE. */
1815 status = ixgbe_read_iosf_sb_reg_x550(hw,
1816 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1817 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1818 if (status != IXGBE_SUCCESS)
1820 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1821 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1822 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1823 status = ixgbe_write_iosf_sb_reg_x550(hw,
1824 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1825 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1826 if (status != IXGBE_SUCCESS)
1828 status = ixgbe_read_iosf_sb_reg_x550(hw,
1829 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1830 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1831 if (status != IXGBE_SUCCESS)
1833 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1834 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1835 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1836 status = ixgbe_write_iosf_sb_reg_x550(hw,
1837 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1838 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1839 if (status != IXGBE_SUCCESS)
1842 /* Enable override for coefficients. */
1843 status = ixgbe_read_iosf_sb_reg_x550(hw,
1844 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1845 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1846 if (status != IXGBE_SUCCESS)
1848 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1849 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1850 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1851 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1852 status = ixgbe_write_iosf_sb_reg_x550(hw,
1853 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1854 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1855 if (status != IXGBE_SUCCESS)
1858 /* Toggle port SW reset by AN reset. */
1859 status = ixgbe_read_iosf_sb_reg_x550(hw,
1860 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1861 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1862 if (status != IXGBE_SUCCESS)
1864 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1865 status = ixgbe_write_iosf_sb_reg_x550(hw,
1866 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1867 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1873 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1874 * @hw: address of hardware structure
1875 * @link_up: address of boolean to indicate link status
1877 * Returns error code if unable to get link status.
1879 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1886 /* read this twice back to back to indicate current status */
1887 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1888 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1890 if (ret != IXGBE_SUCCESS)
1893 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1894 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1896 if (ret != IXGBE_SUCCESS)
1899 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1901 return IXGBE_SUCCESS;
1905 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1906 * @hw: point to hardware structure
1908 * Configures the link between the integrated KR PHY and the external X557 PHY
1909 * The driver will call this function when it gets a link status change
1910 * interrupt from the X557 PHY. This function configures the link speed
1911 * between the PHYs to match the link speed of the BASE-T link.
1913 * A return of a non-zero value indicates an error, and the base driver should
1914 * not report link up.
1916 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1918 ixgbe_link_speed force_speed;
1923 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1924 return IXGBE_ERR_CONFIG;
1926 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1927 /* If link is down, there is no setup necessary so return */
1928 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1929 if (status != IXGBE_SUCCESS)
1933 return IXGBE_SUCCESS;
1935 status = hw->phy.ops.read_reg(hw,
1936 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1937 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1939 if (status != IXGBE_SUCCESS)
1942 /* If link is still down - no setup is required so return */
1943 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1944 if (status != IXGBE_SUCCESS)
1947 return IXGBE_SUCCESS;
1949 /* clear everything but the speed and duplex bits */
1950 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1953 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1954 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1956 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1957 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1960 /* Internal PHY does not support anything else */
1961 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1964 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1966 speed = IXGBE_LINK_SPEED_10GB_FULL |
1967 IXGBE_LINK_SPEED_1GB_FULL;
1968 return ixgbe_setup_kr_speed_x550em(hw, speed);
1973 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1974 * @hw: pointer to hardware structure
1976 * Configures the integrated KR PHY to use internal loopback mode.
1978 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1983 /* Disable AN and force speed to 10G Serial. */
1984 status = ixgbe_read_iosf_sb_reg_x550(hw,
1985 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1986 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1987 if (status != IXGBE_SUCCESS)
1989 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1990 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1991 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1992 status = ixgbe_write_iosf_sb_reg_x550(hw,
1993 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1994 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1995 if (status != IXGBE_SUCCESS)
1998 /* Set near-end loopback clocks. */
1999 status = ixgbe_read_iosf_sb_reg_x550(hw,
2000 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2001 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2002 if (status != IXGBE_SUCCESS)
2004 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2005 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2006 status = ixgbe_write_iosf_sb_reg_x550(hw,
2007 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2008 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2009 if (status != IXGBE_SUCCESS)
2012 /* Set loopback enable. */
2013 status = ixgbe_read_iosf_sb_reg_x550(hw,
2014 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2015 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2016 if (status != IXGBE_SUCCESS)
2018 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2019 status = ixgbe_write_iosf_sb_reg_x550(hw,
2020 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2021 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2022 if (status != IXGBE_SUCCESS)
2025 /* Training bypass. */
2026 status = ixgbe_read_iosf_sb_reg_x550(hw,
2027 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2028 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2029 if (status != IXGBE_SUCCESS)
2031 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2032 status = ixgbe_write_iosf_sb_reg_x550(hw,
2033 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2034 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2040 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2041 * assuming that the semaphore is already obtained.
2042 * @hw: pointer to hardware structure
2043 * @offset: offset of word in the EEPROM to read
2044 * @data: word read from the EEPROM
2046 * Reads a 16 bit word from the EEPROM using the hostif.
2048 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2052 struct ixgbe_hic_read_shadow_ram buffer;
2054 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2055 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2056 buffer.hdr.req.buf_lenh = 0;
2057 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2058 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2060 /* convert offset from words to bytes */
2061 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2063 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2065 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2067 IXGBE_HI_COMMAND_TIMEOUT, false);
2072 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2073 FW_NVM_DATA_OFFSET);
2079 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2080 * @hw: pointer to hardware structure
2081 * @offset: offset of word in the EEPROM to read
2082 * @data: word read from the EEPROM
2084 * Reads a 16 bit word from the EEPROM using the hostif.
2086 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2089 s32 status = IXGBE_SUCCESS;
2091 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2093 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2095 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2096 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2098 status = IXGBE_ERR_SWFW_SYNC;
2105 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2106 * @hw: pointer to hardware structure
2107 * @offset: offset of word in the EEPROM to read
2108 * @words: number of words
2109 * @data: word(s) read from the EEPROM
2111 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2113 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2114 u16 offset, u16 words, u16 *data)
2116 struct ixgbe_hic_read_shadow_ram buffer;
2117 u32 current_word = 0;
2122 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2124 /* Take semaphore for the entire operation. */
2125 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2127 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2131 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2132 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2134 words_to_read = words;
2136 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2137 buffer.hdr.req.buf_lenh = 0;
2138 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2139 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2141 /* convert offset from words to bytes */
2142 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2143 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2145 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2147 IXGBE_HI_COMMAND_TIMEOUT,
2151 DEBUGOUT("Host interface command failed\n");
2155 for (i = 0; i < words_to_read; i++) {
2156 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2158 u32 value = IXGBE_READ_REG(hw, reg);
2160 data[current_word] = (u16)(value & 0xffff);
2163 if (i < words_to_read) {
2165 data[current_word] = (u16)(value & 0xffff);
2169 words -= words_to_read;
2173 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2178 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2179 * @hw: pointer to hardware structure
2180 * @offset: offset of word in the EEPROM to write
2181 * @data: word write to the EEPROM
2183 * Write a 16 bit word to the EEPROM using the hostif.
2185 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2189 struct ixgbe_hic_write_shadow_ram buffer;
2191 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2193 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2194 buffer.hdr.req.buf_lenh = 0;
2195 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2196 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2199 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2201 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2203 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2205 IXGBE_HI_COMMAND_TIMEOUT, false);
2211 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2212 * @hw: pointer to hardware structure
2213 * @offset: offset of word in the EEPROM to write
2214 * @data: word write to the EEPROM
2216 * Write a 16 bit word to the EEPROM using the hostif.
2218 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2221 s32 status = IXGBE_SUCCESS;
2223 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2225 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2227 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2228 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2230 DEBUGOUT("write ee hostif failed to get semaphore");
2231 status = IXGBE_ERR_SWFW_SYNC;
2238 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2239 * @hw: pointer to hardware structure
2240 * @offset: offset of word in the EEPROM to write
2241 * @words: number of words
2242 * @data: word(s) write to the EEPROM
2244 * Write a 16 bit word(s) to the EEPROM using the hostif.
2246 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2247 u16 offset, u16 words, u16 *data)
2249 s32 status = IXGBE_SUCCESS;
2252 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2254 /* Take semaphore for the entire operation. */
2255 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2256 if (status != IXGBE_SUCCESS) {
2257 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2261 for (i = 0; i < words; i++) {
2262 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2265 if (status != IXGBE_SUCCESS) {
2266 DEBUGOUT("Eeprom buffered write failed\n");
2271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2278 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2279 * @hw: pointer to hardware structure
2280 * @ptr: pointer offset in eeprom
2281 * @size: size of section pointed by ptr, if 0 first word will be used as size
2282 * @csum: address of checksum to update
2284 * Returns error status for any failure
2286 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2287 u16 size, u16 *csum, u16 *buffer,
2292 u16 length, bufsz, i, start;
2295 bufsz = sizeof(buf) / sizeof(buf[0]);
2297 /* Read a chunk at the pointer location */
2299 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2301 DEBUGOUT("Failed to read EEPROM image\n");
2306 if (buffer_size < ptr)
2307 return IXGBE_ERR_PARAM;
2308 local_buffer = &buffer[ptr];
2316 length = local_buffer[0];
2318 /* Skip pointer section if length is invalid. */
2319 if (length == 0xFFFF || length == 0 ||
2320 (ptr + length) >= hw->eeprom.word_size)
2321 return IXGBE_SUCCESS;
2324 if (buffer && ((u32)start + (u32)length > buffer_size))
2325 return IXGBE_ERR_PARAM;
2327 for (i = start; length; i++, length--) {
2328 if (i == bufsz && !buffer) {
2334 /* Read a chunk at the pointer location */
2335 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2338 DEBUGOUT("Failed to read EEPROM image\n");
2342 *csum += local_buffer[i];
2344 return IXGBE_SUCCESS;
2348 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2349 * @hw: pointer to hardware structure
2350 * @buffer: pointer to buffer containing calculated checksum
2351 * @buffer_size: size of buffer
2353 * Returns a negative error code on error, or the 16-bit checksum
2355 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2357 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2361 u16 pointer, i, size;
2363 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2365 hw->eeprom.ops.init_params(hw);
2368 /* Read pointer area */
2369 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2370 IXGBE_EEPROM_LAST_WORD + 1,
2373 DEBUGOUT("Failed to read EEPROM image\n");
2376 local_buffer = eeprom_ptrs;
2378 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2379 return IXGBE_ERR_PARAM;
2380 local_buffer = buffer;
2384 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2385 * checksum word itself
2387 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2388 if (i != IXGBE_EEPROM_CHECKSUM)
2389 checksum += local_buffer[i];
2392 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2393 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2395 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2396 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2399 pointer = local_buffer[i];
2401 /* Skip pointer section if the pointer is invalid. */
2402 if (pointer == 0xFFFF || pointer == 0 ||
2403 pointer >= hw->eeprom.word_size)
2407 case IXGBE_PCIE_GENERAL_PTR:
2408 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2410 case IXGBE_PCIE_CONFIG0_PTR:
2411 case IXGBE_PCIE_CONFIG1_PTR:
2412 size = IXGBE_PCIE_CONFIG_SIZE;
2419 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2420 buffer, buffer_size);
2425 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2427 return (s32)checksum;
2431 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2432 * @hw: pointer to hardware structure
2434 * Returns a negative error code on error, or the 16-bit checksum
2436 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2438 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2442 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2443 * @hw: pointer to hardware structure
2444 * @checksum_val: calculated checksum
2446 * Performs checksum calculation and validates the EEPROM checksum. If the
2447 * caller does not need checksum_val, the value can be NULL.
2449 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2453 u16 read_checksum = 0;
2455 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2457 /* Read the first word from the EEPROM. If this times out or fails, do
2458 * not continue or we could be in for a very long wait while every
2461 status = hw->eeprom.ops.read(hw, 0, &checksum);
2463 DEBUGOUT("EEPROM read failed\n");
2467 status = hw->eeprom.ops.calc_checksum(hw);
2471 checksum = (u16)(status & 0xffff);
2473 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2478 /* Verify read checksum from EEPROM is the same as
2479 * calculated checksum
2481 if (read_checksum != checksum) {
2482 status = IXGBE_ERR_EEPROM_CHECKSUM;
2483 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2484 "Invalid EEPROM checksum");
2487 /* If the user cares, return the calculated checksum */
2489 *checksum_val = checksum;
2495 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2496 * @hw: pointer to hardware structure
2498 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2499 * checksum and updates the EEPROM and instructs the hardware to update
2502 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2507 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2509 /* Read the first word from the EEPROM. If this times out or fails, do
2510 * not continue or we could be in for a very long wait while every
2513 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2515 DEBUGOUT("EEPROM read failed\n");
2519 status = ixgbe_calc_eeprom_checksum_X550(hw);
2523 checksum = (u16)(status & 0xffff);
2525 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2530 status = ixgbe_update_flash_X550(hw);
2536 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2537 * @hw: pointer to hardware structure
2539 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2541 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2543 s32 status = IXGBE_SUCCESS;
2544 union ixgbe_hic_hdr2 buffer;
2546 DEBUGFUNC("ixgbe_update_flash_X550");
2548 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2549 buffer.req.buf_lenh = 0;
2550 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2551 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2553 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2555 IXGBE_HI_COMMAND_TIMEOUT, false);
2561 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2562 * @hw: pointer to hardware structure
2564 * Determines physical layer capabilities of the current configuration.
2566 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2568 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2569 u16 ext_ability = 0;
2571 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2573 hw->phy.ops.identify(hw);
2575 switch (hw->phy.type) {
2576 case ixgbe_phy_x550em_kr:
2577 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2578 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2580 case ixgbe_phy_x550em_kx4:
2581 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2582 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2584 case ixgbe_phy_x550em_ext_t:
2585 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2586 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2588 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2589 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2590 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2591 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2597 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2598 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2600 return physical_layer;
2604 * ixgbe_get_bus_info_x550em - Set PCI bus info
2605 * @hw: pointer to hardware structure
2607 * Sets bus link width and speed to unknown because X550em is
2610 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2613 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2615 hw->bus.width = ixgbe_bus_width_unknown;
2616 hw->bus.speed = ixgbe_bus_speed_unknown;
2618 hw->mac.ops.set_lan_id(hw);
2620 return IXGBE_SUCCESS;
2624 * ixgbe_disable_rx_x550 - Disable RX unit
2626 * Enables the Rx DMA unit for x550
2628 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2630 u32 rxctrl, pfdtxgswc;
2632 struct ixgbe_hic_disable_rxen fw_cmd;
2634 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2636 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2637 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2638 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2639 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2640 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2641 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2642 hw->mac.set_lben = true;
2644 hw->mac.set_lben = false;
2647 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2648 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2649 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2650 fw_cmd.port_number = (u8)hw->bus.lan_id;
2652 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2653 sizeof(struct ixgbe_hic_disable_rxen),
2654 IXGBE_HI_COMMAND_TIMEOUT, true);
2656 /* If we fail - disable RX using register write */
2658 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2659 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2660 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2661 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2668 * ixgbe_enter_lplu_x550em - Transition to low power states
2669 * @hw: pointer to hardware structure
2671 * Configures Low Power Link Up on transition to low power states
2672 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2673 * X557 PHY immediately prior to entering LPLU.
2675 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2677 u16 an_10g_cntl_reg, autoneg_reg, speed;
2679 ixgbe_link_speed lcd_speed;
2683 /* SW LPLU not required on later HW revisions. */
2684 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2685 return IXGBE_SUCCESS;
2687 /* If blocked by MNG FW, then don't restart AN */
2688 if (ixgbe_check_reset_blocked(hw))
2689 return IXGBE_SUCCESS;
2691 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2692 if (status != IXGBE_SUCCESS)
2695 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2697 if (status != IXGBE_SUCCESS)
2700 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2701 * disabled, then force link down by entering low power mode.
2703 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2704 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2705 return ixgbe_set_copper_phy_power(hw, FALSE);
2708 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2710 if (status != IXGBE_SUCCESS)
2713 /* If no valid LCD link speed, then force link down and exit. */
2714 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2715 return ixgbe_set_copper_phy_power(hw, FALSE);
2717 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2718 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2721 if (status != IXGBE_SUCCESS)
2724 /* If no link now, speed is invalid so take link down */
2725 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2726 if (status != IXGBE_SUCCESS)
2727 return ixgbe_set_copper_phy_power(hw, false);
2729 /* clear everything but the speed bits */
2730 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2732 /* If current speed is already LCD, then exit. */
2733 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2734 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2735 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2736 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2739 /* Clear AN completed indication */
2740 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2741 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2744 if (status != IXGBE_SUCCESS)
2747 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2748 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2751 if (status != IXGBE_SUCCESS)
2754 status = hw->phy.ops.read_reg(hw,
2755 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2759 if (status != IXGBE_SUCCESS)
2762 save_autoneg = hw->phy.autoneg_advertised;
2764 /* Setup link at least common link speed */
2765 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2767 /* restore autoneg from before setting lplu speed */
2768 hw->phy.autoneg_advertised = save_autoneg;
2774 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2775 * @hw: pointer to hardware structure
2776 * @lcd_speed: pointer to lowest common link speed
2778 * Determine lowest common link speed with link partner.
2780 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2784 u16 word = hw->eeprom.ctrl_word_3;
2786 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2788 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2789 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2792 if (status != IXGBE_SUCCESS)
2795 /* If link partner advertised 1G, return 1G */
2796 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2797 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2801 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2802 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2803 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2806 /* Link partner not capable of lower speeds, return 10G */
2807 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2812 * ixgbe_setup_fc_X550em - Set up flow control
2813 * @hw: pointer to hardware structure
2815 * Called at init time to set up flow control.
2817 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2819 s32 ret_val = IXGBE_SUCCESS;
2820 u32 pause, asm_dir, reg_val;
2822 DEBUGFUNC("ixgbe_setup_fc_X550em");
2824 /* Validate the requested mode */
2825 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2826 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2827 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2828 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2832 /* 10gig parts do not have a word in the EEPROM to determine the
2833 * default flow control setting, so we explicitly set it to full.
2835 if (hw->fc.requested_mode == ixgbe_fc_default)
2836 hw->fc.requested_mode = ixgbe_fc_full;
2838 /* Determine PAUSE and ASM_DIR bits. */
2839 switch (hw->fc.requested_mode) {
2844 case ixgbe_fc_tx_pause:
2848 case ixgbe_fc_rx_pause:
2849 /* Rx Flow control is enabled and Tx Flow control is
2850 * disabled by software override. Since there really
2851 * isn't a way to advertise that we are capable of RX
2852 * Pause ONLY, we will advertise that we support both
2853 * symmetric and asymmetric Rx PAUSE, as such we fall
2854 * through to the fc_full statement. Later, we will
2855 * disable the adapter's ability to send PAUSE frames.
2862 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2863 "Flow control param set incorrectly\n");
2864 ret_val = IXGBE_ERR_CONFIG;
2868 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2869 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2870 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2871 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2872 if (ret_val != IXGBE_SUCCESS)
2874 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2875 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2877 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2879 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2880 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2881 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2882 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2884 /* This device does not fully support AN. */
2885 hw->fc.disable_fc_autoneg = true;
2893 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2894 * @hw: pointer to hardware structure
2895 * @state: set mux if 1, clear if 0
2897 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2901 if (!hw->bus.lan_id)
2903 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2905 esdp |= IXGBE_ESDP_SDP1;
2907 esdp &= ~IXGBE_ESDP_SDP1;
2908 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2909 IXGBE_WRITE_FLUSH(hw);
2913 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2914 * @hw: pointer to hardware structure
2915 * @mask: Mask to specify which semaphore to acquire
2917 * Acquires the SWFW semaphore and sets the I2C MUX
2919 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2923 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2925 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2929 if (mask & IXGBE_GSSR_I2C_MASK)
2930 ixgbe_set_mux(hw, 1);
2932 return IXGBE_SUCCESS;
2936 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2937 * @hw: pointer to hardware structure
2938 * @mask: Mask to specify which semaphore to release
2940 * Releases the SWFW semaphore and sets the I2C MUX
2942 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2944 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2946 if (mask & IXGBE_GSSR_I2C_MASK)
2947 ixgbe_set_mux(hw, 0);
2949 ixgbe_release_swfw_sync_X540(hw, mask);
2953 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2954 * @hw: pointer to hardware structure
2956 * Handle external Base T PHY interrupt. If high temperature
2957 * failure alarm then return error, else if link status change
2958 * then setup internal/external PHY link
2960 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2961 * failure alarm, else return PHY access status.
2963 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2968 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2970 if (status != IXGBE_SUCCESS)
2974 return ixgbe_setup_internal_phy(hw);
2976 return IXGBE_SUCCESS;
2980 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2981 * @hw: pointer to hardware structure
2982 * @speed: new link speed
2983 * @autoneg_wait_to_complete: true when waiting for completion is needed
2985 * Setup internal/external PHY link speed based on link speed, then set
2986 * external PHY auto advertised link speed.
2988 * Returns error status for any failure
2990 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2991 ixgbe_link_speed speed,
2992 bool autoneg_wait_to_complete)
2995 ixgbe_link_speed force_speed;
2997 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2999 /* Setup internal/external PHY link speed to iXFI (10G), unless
3000 * only 1G is auto advertised then setup KX link.
3002 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3003 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3005 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3007 /* If internal link mode is XFI, then setup XFI internal link. */
3008 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3009 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3011 if (status != IXGBE_SUCCESS)
3015 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3019 * ixgbe_check_link_t_X550em - Determine link and speed status
3020 * @hw: pointer to hardware structure
3021 * @speed: pointer to link speed
3022 * @link_up: true when link is up
3023 * @link_up_wait_to_complete: bool used to wait for link up or not
3025 * Check that both the MAC and X557 external PHY have link.
3027 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3028 bool *link_up, bool link_up_wait_to_complete)
3033 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3034 return IXGBE_ERR_CONFIG;
3036 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3037 link_up_wait_to_complete);
3039 /* If check link fails or MAC link is not up, then return */
3040 if (status != IXGBE_SUCCESS || !(*link_up))
3043 /* MAC link is up, so check external PHY link.
3044 * Read this twice back to back to indicate current status.
3046 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3047 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3050 if (status != IXGBE_SUCCESS)
3053 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3057 if (status != IXGBE_SUCCESS)
3060 /* If external PHY link is not up, then indicate link not up */
3061 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3064 return IXGBE_SUCCESS;
3068 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3069 * @hw: pointer to hardware structure
3071 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3075 status = ixgbe_reset_phy_generic(hw);
3077 if (status != IXGBE_SUCCESS)
3080 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3081 return ixgbe_enable_lasi_ext_t_x550em(hw);
3085 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3086 * @hw: pointer to hardware structure
3087 * @led_idx: led number to turn on
3089 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3093 DEBUGFUNC("ixgbe_led_on_t_X550em");
3095 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3096 return IXGBE_ERR_PARAM;
3098 /* To turn on the LED, set mode to ON. */
3099 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3100 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3101 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3102 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3103 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3105 return IXGBE_SUCCESS;
3109 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3110 * @hw: pointer to hardware structure
3111 * @led_idx: led number to turn off
3113 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3117 DEBUGFUNC("ixgbe_led_off_t_X550em");
3119 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3120 return IXGBE_ERR_PARAM;
3122 /* To turn on the LED, set mode to ON. */
3123 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3124 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3125 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3126 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3127 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3129 return IXGBE_SUCCESS;