1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
386 mac->ops.setup_fc = ixgbe_setup_fc_generic;
388 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
390 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
391 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
393 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
394 mac->ops.setup_eee = NULL;
397 phy->ops.init = ixgbe_init_phy_ops_X550em;
398 phy->ops.identify = ixgbe_identify_phy_x550em;
399 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
400 phy->ops.set_phy_power = NULL;
404 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
405 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
406 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
407 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
408 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
409 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
410 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
411 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
417 * ixgbe_dmac_config_X550
418 * @hw: pointer to hardware structure
420 * Configure DMA coalescing. If enabling dmac, dmac is activated.
421 * When disabling dmac, dmac enable dmac bit is cleared.
423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
425 u32 reg, high_pri_tc;
427 DEBUGFUNC("ixgbe_dmac_config_X550");
429 /* Disable DMA coalescing before configuring */
430 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
431 reg &= ~IXGBE_DMACR_DMAC_EN;
432 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
434 /* Disable DMA Coalescing if the watchdog timer is 0 */
435 if (!hw->mac.dmac_config.watchdog_timer)
438 ixgbe_dmac_config_tcs_X550(hw);
440 /* Configure DMA Coalescing Control Register */
441 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
443 /* Set the watchdog timer in units of 40.96 usec */
444 reg &= ~IXGBE_DMACR_DMACWT_MASK;
445 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
447 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
448 /* If fcoe is enabled, set high priority traffic class */
449 if (hw->mac.dmac_config.fcoe_en) {
450 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
451 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
452 IXGBE_DMACR_HIGH_PRI_TC_MASK);
454 reg |= IXGBE_DMACR_EN_MNG_IND;
456 /* Enable DMA coalescing after configuration */
457 reg |= IXGBE_DMACR_DMAC_EN;
458 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
461 return IXGBE_SUCCESS;
465 * ixgbe_dmac_config_tcs_X550
466 * @hw: pointer to hardware structure
468 * Configure DMA coalescing threshold per TC. The dmac enable bit must
469 * be cleared before configuring.
471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
473 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
475 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
477 /* Configure DMA coalescing enabled */
478 switch (hw->mac.dmac_config.link_speed) {
479 case IXGBE_LINK_SPEED_100_FULL:
480 pb_headroom = IXGBE_DMACRXT_100M;
482 case IXGBE_LINK_SPEED_1GB_FULL:
483 pb_headroom = IXGBE_DMACRXT_1G;
486 pb_headroom = IXGBE_DMACRXT_10G;
490 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
491 IXGBE_MHADD_MFS_SHIFT) / 1024);
493 /* Set the per Rx packet buffer receive threshold */
494 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
495 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
496 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
498 if (tc < hw->mac.dmac_config.num_tcs) {
500 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
501 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
502 IXGBE_RXPBSIZE_SHIFT;
504 /* Calculate receive buffer threshold in kilobytes */
505 if (rx_pb_size > pb_headroom)
506 rx_pb_size = rx_pb_size - pb_headroom;
510 /* Minimum of MFS shall be set for DMCTH */
511 reg |= (rx_pb_size > maxframe_size_kb) ?
512 rx_pb_size : maxframe_size_kb;
514 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
516 return IXGBE_SUCCESS;
520 * ixgbe_dmac_update_tcs_X550
521 * @hw: pointer to hardware structure
523 * Disables dmac, updates per TC settings, and then enables dmac.
525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
529 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
531 /* Disable DMA coalescing before configuring */
532 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
533 reg &= ~IXGBE_DMACR_DMAC_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
536 ixgbe_dmac_config_tcs_X550(hw);
538 /* Enable DMA coalescing after configuration */
539 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
540 reg |= IXGBE_DMACR_DMAC_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
543 return IXGBE_SUCCESS;
547 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
548 * @hw: pointer to hardware structure
550 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
551 * ixgbe_hw struct in order to set up EEPROM access.
553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
555 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
559 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
561 if (eeprom->type == ixgbe_eeprom_uninitialized) {
562 eeprom->semaphore_delay = 10;
563 eeprom->type = ixgbe_flash;
565 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
566 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
567 IXGBE_EEC_SIZE_SHIFT);
568 eeprom->word_size = 1 << (eeprom_size +
569 IXGBE_EEPROM_WORD_SIZE_SHIFT);
571 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
572 eeprom->type, eeprom->word_size);
575 return IXGBE_SUCCESS;
579 * ixgbe_setup_eee_X550 - Enable/disable EEE support
580 * @hw: pointer to the HW structure
581 * @enable_eee: boolean flag to enable EEE
583 * Enable/disable EEE based on enable_eee flag.
584 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
595 DEBUGFUNC("ixgbe_setup_eee_X550");
597 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
598 /* Enable or disable EEE per flag */
600 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
602 if (hw->device_id == IXGBE_DEV_ID_X550T) {
603 /* Advertise EEE capability */
604 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
607 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
608 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
609 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
611 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
613 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
614 status = ixgbe_read_iosf_sb_reg_x550(hw,
615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
616 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
617 if (status != IXGBE_SUCCESS)
620 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
621 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
623 status = ixgbe_write_iosf_sb_reg_x550(hw,
624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
625 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
626 if (status != IXGBE_SUCCESS)
630 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
632 if (hw->device_id == IXGBE_DEV_ID_X550T) {
633 /* Disable advertised EEE capability */
634 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
635 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
637 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
638 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
639 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
641 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
642 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
643 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
644 status = ixgbe_read_iosf_sb_reg_x550(hw,
645 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
646 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
647 if (status != IXGBE_SUCCESS)
650 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
651 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
653 status = ixgbe_write_iosf_sb_reg_x550(hw,
654 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
655 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
656 if (status != IXGBE_SUCCESS)
660 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
662 return IXGBE_SUCCESS;
666 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
667 * @hw: pointer to hardware structure
668 * @enable: enable or disable source address pruning
669 * @pool: Rx pool to set source address pruning for
671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
676 /* max rx pool is 63 */
680 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
681 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
684 pfflp |= (1ULL << pool);
686 pfflp &= ~(1ULL << pool);
688 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
689 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
693 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
694 * @hw: pointer to hardware structure
695 * @enable: enable or disable switch for Ethertype anti-spoofing
696 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
702 int vf_target_reg = vf >> 3;
703 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
706 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
708 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
710 pfvfspoof |= (1 << vf_target_shift);
712 pfvfspoof &= ~(1 << vf_target_shift);
714 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
718 * ixgbe_iosf_wait - Wait for IOSF command completion
719 * @hw: pointer to hardware structure
720 * @ctrl: pointer to location to receive final IOSF control value
722 * Returns failing status on timeout
724 * Note: ctrl can be NULL if the IOSF control register value is not needed
726 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
730 /* Check every 10 usec to see if the address cycle completed.
731 * The SB IOSF BUSY bit will clear when the operation is
734 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
735 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
736 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
742 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
743 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
744 return IXGBE_ERR_PHY;
747 return IXGBE_SUCCESS;
751 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
753 * @hw: pointer to hardware structure
754 * @reg_addr: 32 bit PHY register to write
755 * @device_type: 3 bit device type
756 * @data: Data to write to the register
758 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
759 u32 device_type, u32 data)
764 ret = ixgbe_iosf_wait(hw, NULL);
765 if (ret != IXGBE_SUCCESS)
768 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
769 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
771 /* Write IOSF control register */
772 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
774 /* Write IOSF data register */
775 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
777 ret = ixgbe_iosf_wait(hw, &command);
779 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
780 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
781 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
782 ERROR_REPORT2(IXGBE_ERROR_POLLING,
783 "Failed to write, error %x\n", error);
784 return IXGBE_ERR_PHY;
791 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
793 * @hw: pointer to hardware structure
794 * @reg_addr: 32 bit PHY register to write
795 * @device_type: 3 bit device type
796 * @phy_data: Pointer to read data from the register
798 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
799 u32 device_type, u32 *data)
804 ret = ixgbe_iosf_wait(hw, NULL);
805 if (ret != IXGBE_SUCCESS)
808 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
809 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
811 /* Write IOSF control register */
812 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
814 ret = ixgbe_iosf_wait(hw, &command);
816 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
817 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
818 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
819 ERROR_REPORT2(IXGBE_ERROR_POLLING,
820 "Failed to read, error %x\n", error);
821 return IXGBE_ERR_PHY;
824 if (ret != IXGBE_SUCCESS)
827 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
829 return IXGBE_SUCCESS;
833 * ixgbe_disable_mdd_X550
834 * @hw: pointer to hardware structure
836 * Disable malicious driver detection
838 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
842 DEBUGFUNC("ixgbe_disable_mdd_X550");
844 /* Disable MDD for TX DMA and interrupt */
845 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
846 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
847 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
849 /* Disable MDD for RX and interrupt */
850 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
851 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
852 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
856 * ixgbe_enable_mdd_X550
857 * @hw: pointer to hardware structure
859 * Enable malicious driver detection
861 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
865 DEBUGFUNC("ixgbe_enable_mdd_X550");
867 /* Enable MDD for TX DMA and interrupt */
868 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
869 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
870 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
872 /* Enable MDD for RX and interrupt */
873 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
874 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
875 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
879 * ixgbe_restore_mdd_vf_X550
880 * @hw: pointer to hardware structure
883 * Restore VF that was disabled during malicious driver detection event
885 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
887 u32 idx, reg, num_qs, start_q, bitmask;
889 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
891 /* Map VF to queues */
892 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
893 switch (reg & IXGBE_MRQC_MRQE_MASK) {
894 case IXGBE_MRQC_VMDQRT8TCEN:
895 num_qs = 8; /* 16 VFs / pools */
896 bitmask = 0x000000FF;
898 case IXGBE_MRQC_VMDQRSS32EN:
899 case IXGBE_MRQC_VMDQRT4TCEN:
900 num_qs = 4; /* 32 VFs / pools */
901 bitmask = 0x0000000F;
903 default: /* 64 VFs / pools */
905 bitmask = 0x00000003;
908 start_q = vf * num_qs;
910 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
913 reg |= (bitmask << (start_q % 32));
914 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
915 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
919 * ixgbe_mdd_event_X550
920 * @hw: pointer to hardware structure
921 * @vf_bitmap: vf bitmap of malicious vfs
923 * Handle malicious driver detection event.
925 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
928 u32 i, j, reg, q, shift, vf, idx;
930 DEBUGFUNC("ixgbe_mdd_event_X550");
932 /* figure out pool size for mapping to vf's */
933 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
934 switch (reg & IXGBE_MRQC_MRQE_MASK) {
935 case IXGBE_MRQC_VMDQRT8TCEN:
936 shift = 3; /* 16 VFs / pools */
938 case IXGBE_MRQC_VMDQRSS32EN:
939 case IXGBE_MRQC_VMDQRT4TCEN:
940 shift = 2; /* 32 VFs / pools */
943 shift = 1; /* 64 VFs / pools */
947 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
948 for (i = 0; i < 4; i++) {
949 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
950 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
955 /* Get malicious queue */
956 for (j = 0; j < 32 && wqbr; j++) {
958 if (!(wqbr & (1 << j)))
961 /* Get queue from bitmask */
964 /* Map queue to vf */
967 /* Set vf bit in vf_bitmap */
969 vf_bitmap[idx] |= (1 << (vf % 32));
976 * ixgbe_get_media_type_X550em - Get media type
977 * @hw: pointer to hardware structure
979 * Returns the media type (fiber, copper, backplane)
981 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
983 enum ixgbe_media_type media_type;
985 DEBUGFUNC("ixgbe_get_media_type_X550em");
987 /* Detect if there is a copper PHY attached. */
988 switch (hw->device_id) {
989 case IXGBE_DEV_ID_X550EM_X_KR:
990 case IXGBE_DEV_ID_X550EM_X_KX4:
991 media_type = ixgbe_media_type_backplane;
993 case IXGBE_DEV_ID_X550EM_X_SFP:
994 media_type = ixgbe_media_type_fiber;
996 case IXGBE_DEV_ID_X550EM_X_1G_T:
997 case IXGBE_DEV_ID_X550EM_X_10G_T:
998 media_type = ixgbe_media_type_copper;
1001 media_type = ixgbe_media_type_unknown;
1008 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1009 * @hw: pointer to hardware structure
1010 * @linear: true if SFP module is linear
1012 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1014 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1016 switch (hw->phy.sfp_type) {
1017 case ixgbe_sfp_type_not_present:
1018 return IXGBE_ERR_SFP_NOT_PRESENT;
1019 case ixgbe_sfp_type_da_cu_core0:
1020 case ixgbe_sfp_type_da_cu_core1:
1023 case ixgbe_sfp_type_srlr_core0:
1024 case ixgbe_sfp_type_srlr_core1:
1025 case ixgbe_sfp_type_da_act_lmt_core0:
1026 case ixgbe_sfp_type_da_act_lmt_core1:
1027 case ixgbe_sfp_type_1g_sx_core0:
1028 case ixgbe_sfp_type_1g_sx_core1:
1029 case ixgbe_sfp_type_1g_lx_core0:
1030 case ixgbe_sfp_type_1g_lx_core1:
1033 case ixgbe_sfp_type_unknown:
1034 case ixgbe_sfp_type_1g_cu_core0:
1035 case ixgbe_sfp_type_1g_cu_core1:
1037 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1040 return IXGBE_SUCCESS;
1044 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1045 * @hw: pointer to hardware structure
1047 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1049 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1056 status = ixgbe_identify_module_generic(hw);
1058 if (status != IXGBE_SUCCESS)
1061 /* Check if SFP module is supported */
1062 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1068 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1069 * @hw: pointer to hardware structure
1071 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1076 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1078 /* Check if SFP module is supported */
1079 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1081 if (status != IXGBE_SUCCESS)
1084 ixgbe_init_mac_link_ops_X550em(hw);
1085 hw->phy.ops.reset = NULL;
1087 return IXGBE_SUCCESS;
1091 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1092 * @hw: pointer to hardware structure
1094 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1096 struct ixgbe_mac_info *mac = &hw->mac;
1098 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1100 switch (hw->mac.ops.get_media_type(hw)) {
1101 case ixgbe_media_type_fiber:
1102 /* CS4227 does not support autoneg, so disable the laser control
1103 * functions for SFP+ fiber
1105 mac->ops.disable_tx_laser = NULL;
1106 mac->ops.enable_tx_laser = NULL;
1107 mac->ops.flap_tx_laser = NULL;
1108 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1109 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1110 mac->ops.set_rate_select_speed =
1111 ixgbe_set_soft_rate_select_speed;
1113 case ixgbe_media_type_copper:
1114 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1115 mac->ops.check_link = ixgbe_check_link_t_X550em;
1123 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1124 * @hw: pointer to hardware structure
1125 * @speed: pointer to link speed
1126 * @autoneg: true when autoneg or autotry is enabled
1128 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1129 ixgbe_link_speed *speed,
1132 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1135 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1137 /* CS4227 SFP must not enable auto-negotiation */
1140 /* Check if 1G SFP module. */
1141 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1142 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1143 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1144 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1145 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1146 return IXGBE_SUCCESS;
1149 /* Link capabilities are based on SFP */
1150 if (hw->phy.multispeed_fiber)
1151 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1152 IXGBE_LINK_SPEED_1GB_FULL;
1154 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1156 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1157 IXGBE_LINK_SPEED_1GB_FULL;
1161 return IXGBE_SUCCESS;
1165 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1166 * @hw: pointer to hardware structure
1167 * @lsc: pointer to boolean flag which indicates whether external Base T
1168 * PHY interrupt is lsc
1170 * Determime if external Base T PHY interrupt cause is high temperature
1171 * failure alarm or link status change.
1173 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1174 * failure alarm, else return PHY access status.
1176 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1183 /* Vendor alarm triggered */
1184 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1185 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1188 if (status != IXGBE_SUCCESS ||
1189 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1192 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1193 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1194 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1197 if (status != IXGBE_SUCCESS ||
1198 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1199 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1202 /* High temperature failure alarm triggered */
1203 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1204 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1207 if (status != IXGBE_SUCCESS)
1210 /* If high temperature failure, then return over temp error and exit */
1211 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1212 /* power down the PHY in case the PHY FW didn't already */
1213 ixgbe_set_copper_phy_power(hw, false);
1214 return IXGBE_ERR_OVERTEMP;
1217 /* Vendor alarm 2 triggered */
1218 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1219 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1221 if (status != IXGBE_SUCCESS ||
1222 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1225 /* link connect/disconnect event occurred */
1226 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1227 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1229 if (status != IXGBE_SUCCESS)
1233 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1236 return IXGBE_SUCCESS;
1240 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1241 * @hw: pointer to hardware structure
1243 * Enable link status change and temperature failure alarm for the external
1246 * Returns PHY access status
1248 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1254 /* Clear interrupt flags */
1255 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1257 /* Enable link status change alarm */
1258 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1259 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1261 if (status != IXGBE_SUCCESS)
1264 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1266 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1267 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1269 if (status != IXGBE_SUCCESS)
1272 /* Enables high temperature failure alarm */
1273 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1274 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1277 if (status != IXGBE_SUCCESS)
1280 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1282 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1283 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1286 if (status != IXGBE_SUCCESS)
1289 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1290 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1291 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1294 if (status != IXGBE_SUCCESS)
1297 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1298 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1300 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1301 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1304 if (status != IXGBE_SUCCESS)
1307 /* Enable chip-wide vendor alarm */
1308 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1309 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1312 if (status != IXGBE_SUCCESS)
1315 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1317 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1318 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1325 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1326 * @hw: pointer to hardware structure
1328 * Initialize any function pointers that were not able to be
1329 * set during init_shared_code because the PHY/SFP type was
1330 * not known. Perform the SFP init if necessary.
1332 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1334 struct ixgbe_phy_info *phy = &hw->phy;
1337 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1339 hw->mac.ops.set_lan_id(hw);
1341 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1342 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1343 ixgbe_setup_mux_ctl(hw);
1345 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1348 /* Identify the PHY or SFP module */
1349 ret_val = phy->ops.identify(hw);
1350 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1353 /* Setup function pointers based on detected hardware */
1354 ixgbe_init_mac_link_ops_X550em(hw);
1355 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1356 phy->ops.reset = NULL;
1358 /* Set functions pointers based on phy type */
1359 switch (hw->phy.type) {
1360 case ixgbe_phy_x550em_kx4:
1361 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1362 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1363 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1365 case ixgbe_phy_x550em_kr:
1366 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1367 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1368 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1370 case ixgbe_phy_x550em_ext_t:
1371 phy->ops.setup_internal_link =
1372 ixgbe_setup_internal_phy_t_x550em;
1373 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1374 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1375 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1384 * ixgbe_reset_hw_X550em - Perform hardware reset
1385 * @hw: pointer to hardware structure
1387 * Resets the hardware by resetting the transmit and receive units, masks
1388 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1391 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1393 ixgbe_link_speed link_speed;
1397 bool link_up = false;
1399 DEBUGFUNC("ixgbe_reset_hw_X550em");
1401 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1402 status = hw->mac.ops.stop_adapter(hw);
1403 if (status != IXGBE_SUCCESS)
1406 /* flush pending Tx transactions */
1407 ixgbe_clear_tx_pending(hw);
1409 /* PHY ops must be identified and initialized prior to reset */
1411 /* Identify PHY and related function pointers */
1412 status = hw->phy.ops.init(hw);
1414 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1417 /* start the external PHY */
1418 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1419 status = ixgbe_init_ext_t_x550em(hw);
1424 /* Setup SFP module if there is one present. */
1425 if (hw->phy.sfp_setup_needed) {
1426 status = hw->mac.ops.setup_sfp(hw);
1427 hw->phy.sfp_setup_needed = false;
1430 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1434 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1435 hw->phy.ops.reset(hw);
1438 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1439 * If link reset is used when link is up, it might reset the PHY when
1440 * mng is using it. If link is down or the flag to force full link
1441 * reset is set, then perform link reset.
1443 ctrl = IXGBE_CTRL_LNK_RST;
1444 if (!hw->force_full_reset) {
1445 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1447 ctrl = IXGBE_CTRL_RST;
1450 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1451 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1452 IXGBE_WRITE_FLUSH(hw);
1454 /* Poll for reset bit to self-clear meaning reset is complete */
1455 for (i = 0; i < 10; i++) {
1457 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1458 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1462 if (ctrl & IXGBE_CTRL_RST_MASK) {
1463 status = IXGBE_ERR_RESET_FAILED;
1464 DEBUGOUT("Reset polling failed to complete.\n");
1469 /* Double resets are required for recovery from certain error
1470 * conditions. Between resets, it is necessary to stall to
1471 * allow time for any pending HW events to complete.
1473 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1474 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1478 /* Store the permanent mac address */
1479 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1481 /* Store MAC address from RAR0, clear receive address registers, and
1482 * clear the multicast table. Also reset num_rar_entries to 128,
1483 * since we modify this value when programming the SAN MAC address.
1485 hw->mac.num_rar_entries = 128;
1486 hw->mac.ops.init_rx_addrs(hw);
1489 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1490 ixgbe_setup_mux_ctl(hw);
1496 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1497 * @hw: pointer to hardware structure
1499 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1504 status = hw->phy.ops.read_reg(hw,
1505 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1506 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1509 if (status != IXGBE_SUCCESS)
1512 /* If PHY FW reset completed bit is set then this is the first
1513 * SW instance after a power on so the PHY FW must be un-stalled.
1515 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1516 status = hw->phy.ops.read_reg(hw,
1517 IXGBE_MDIO_GLOBAL_RES_PR_10,
1518 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1521 if (status != IXGBE_SUCCESS)
1524 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1526 status = hw->phy.ops.write_reg(hw,
1527 IXGBE_MDIO_GLOBAL_RES_PR_10,
1528 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1531 if (status != IXGBE_SUCCESS)
1539 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1540 * @hw: pointer to hardware structure
1542 * Configures the integrated KR PHY.
1544 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1549 status = ixgbe_read_iosf_sb_reg_x550(hw,
1550 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1551 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1556 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1557 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1558 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1559 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1561 /* Advertise 10G support. */
1562 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1563 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1565 /* Advertise 1G support. */
1566 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1567 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1569 /* Restart auto-negotiation. */
1570 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1571 status = ixgbe_write_iosf_sb_reg_x550(hw,
1572 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1573 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1579 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1580 * @hw: pointer to hardware structure
1582 * Configures the integrated KX4 PHY.
1584 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1589 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1590 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);
1594 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1595 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1597 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1599 /* Advertise 10G support. */
1600 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1601 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1603 /* Advertise 1G support. */
1604 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1605 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1607 /* Restart auto-negotiation. */
1608 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1609 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1610 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1616 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1617 * @hw: pointer to hardware structure
1618 * @speed: the link speed to force
1620 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1621 * internal and external PHY at a specific speed, without autonegotiation.
1623 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1628 /* Disable AN and force speed to 10G Serial. */
1629 status = ixgbe_read_iosf_sb_reg_x550(hw,
1630 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1631 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1632 if (status != IXGBE_SUCCESS)
1635 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1636 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1638 /* Select forced link speed for internal PHY. */
1640 case IXGBE_LINK_SPEED_10GB_FULL:
1641 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1643 case IXGBE_LINK_SPEED_1GB_FULL:
1644 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1647 /* Other link speeds are not supported by internal KR PHY. */
1648 return IXGBE_ERR_LINK_SETUP;
1651 status = ixgbe_write_iosf_sb_reg_x550(hw,
1652 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1653 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1654 if (status != IXGBE_SUCCESS)
1657 /* Disable training protocol FSM. */
1658 status = ixgbe_read_iosf_sb_reg_x550(hw,
1659 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1660 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1661 if (status != IXGBE_SUCCESS)
1663 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1664 status = ixgbe_write_iosf_sb_reg_x550(hw,
1665 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1666 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1667 if (status != IXGBE_SUCCESS)
1670 /* Disable Flex from training TXFFE. */
1671 status = ixgbe_read_iosf_sb_reg_x550(hw,
1672 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1673 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1674 if (status != IXGBE_SUCCESS)
1676 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1677 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1678 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1679 status = ixgbe_write_iosf_sb_reg_x550(hw,
1680 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1681 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1682 if (status != IXGBE_SUCCESS)
1684 status = ixgbe_read_iosf_sb_reg_x550(hw,
1685 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1686 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1687 if (status != IXGBE_SUCCESS)
1689 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1690 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1691 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1692 status = ixgbe_write_iosf_sb_reg_x550(hw,
1693 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1694 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1695 if (status != IXGBE_SUCCESS)
1698 /* Enable override for coefficients. */
1699 status = ixgbe_read_iosf_sb_reg_x550(hw,
1700 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1701 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1702 if (status != IXGBE_SUCCESS)
1704 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1705 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1706 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1707 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1708 status = ixgbe_write_iosf_sb_reg_x550(hw,
1709 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1710 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1711 if (status != IXGBE_SUCCESS)
1714 /* Toggle port SW reset by AN reset. */
1715 status = ixgbe_read_iosf_sb_reg_x550(hw,
1716 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1717 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1718 if (status != IXGBE_SUCCESS)
1720 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1721 status = ixgbe_write_iosf_sb_reg_x550(hw,
1722 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1723 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1729 * ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1730 * @hw: pointer to hardware structure
1732 * Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1734 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1735 ixgbe_link_speed speed,
1736 bool autoneg_wait_to_complete)
1739 u16 reg_slice, reg_val;
1740 bool setup_linear = false;
1741 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1743 /* Check if SFP module is supported and linear */
1744 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1746 /* If no SFP module present, then return success. Return success since
1747 * there is no reason to configure CS4227 and SFP not present error is
1748 * not excepted in the setup MAC link flow.
1750 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1751 return IXGBE_SUCCESS;
1753 if (ret_val != IXGBE_SUCCESS)
1756 /* Configure CS4227 for connection rate. */
1757 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1758 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1759 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1762 /* Configure CS4227 for connection type. */
1763 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1765 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1767 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1768 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1771 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1772 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1773 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1776 /* Configure CS4227 for connection type. */
1777 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1779 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1781 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1782 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1785 /* Configure the internal PHY. */
1786 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1792 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1793 * @hw: point to hardware structure
1795 * Configures the link between the integrated KR PHY and the external X557 PHY
1796 * The driver will call this function when it gets a link status change
1797 * interrupt from the X557 PHY. This function configures the link speed
1798 * between the PHYs to match the link speed of the BASE-T link.
1800 * A return of a non-zero value indicates an error, and the base driver should
1801 * not report link up.
1803 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1806 u16 autoneg_status, speed;
1807 ixgbe_link_speed force_speed;
1809 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1810 return IXGBE_ERR_CONFIG;
1812 /* read this twice back to back to indicate current status */
1813 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1816 if (status != IXGBE_SUCCESS)
1819 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1822 if (status != IXGBE_SUCCESS)
1825 /* If link is not up, then there is no setup necessary so return */
1826 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1827 return IXGBE_SUCCESS;
1829 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1833 /* clear everything but the speed and duplex bits */
1834 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1837 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1838 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1840 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1841 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1844 /* Internal PHY does not support anything else */
1845 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1848 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1852 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1853 * @hw: pointer to hardware structure
1855 * Configures the integrated KR PHY to use internal loopback mode.
1857 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1862 /* Disable AN and force speed to 10G Serial. */
1863 status = ixgbe_read_iosf_sb_reg_x550(hw,
1864 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1865 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1866 if (status != IXGBE_SUCCESS)
1868 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1869 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1870 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1871 status = ixgbe_write_iosf_sb_reg_x550(hw,
1872 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1873 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1874 if (status != IXGBE_SUCCESS)
1877 /* Set near-end loopback clocks. */
1878 status = ixgbe_read_iosf_sb_reg_x550(hw,
1879 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1880 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1881 if (status != IXGBE_SUCCESS)
1883 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1884 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1885 status = ixgbe_write_iosf_sb_reg_x550(hw,
1886 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1887 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1888 if (status != IXGBE_SUCCESS)
1891 /* Set loopback enable. */
1892 status = ixgbe_read_iosf_sb_reg_x550(hw,
1893 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1894 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1895 if (status != IXGBE_SUCCESS)
1897 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1898 status = ixgbe_write_iosf_sb_reg_x550(hw,
1899 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1900 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1901 if (status != IXGBE_SUCCESS)
1904 /* Training bypass. */
1905 status = ixgbe_read_iosf_sb_reg_x550(hw,
1906 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1907 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1908 if (status != IXGBE_SUCCESS)
1910 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1911 status = ixgbe_write_iosf_sb_reg_x550(hw,
1912 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1913 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1919 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1920 * assuming that the semaphore is already obtained.
1921 * @hw: pointer to hardware structure
1922 * @offset: offset of word in the EEPROM to read
1923 * @data: word read from the EEPROM
1925 * Reads a 16 bit word from the EEPROM using the hostif.
1927 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1931 struct ixgbe_hic_read_shadow_ram buffer;
1933 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1934 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1935 buffer.hdr.req.buf_lenh = 0;
1936 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1937 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1939 /* convert offset from words to bytes */
1940 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1942 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1944 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1946 IXGBE_HI_COMMAND_TIMEOUT, false);
1951 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1952 FW_NVM_DATA_OFFSET);
1958 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1959 * @hw: pointer to hardware structure
1960 * @offset: offset of word in the EEPROM to read
1961 * @data: word read from the EEPROM
1963 * Reads a 16 bit word from the EEPROM using the hostif.
1965 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1968 s32 status = IXGBE_SUCCESS;
1970 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1972 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1974 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1975 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1977 status = IXGBE_ERR_SWFW_SYNC;
1984 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1985 * @hw: pointer to hardware structure
1986 * @offset: offset of word in the EEPROM to read
1987 * @words: number of words
1988 * @data: word(s) read from the EEPROM
1990 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1992 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1993 u16 offset, u16 words, u16 *data)
1995 struct ixgbe_hic_read_shadow_ram buffer;
1996 u32 current_word = 0;
2001 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2003 /* Take semaphore for the entire operation. */
2004 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2006 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2010 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2011 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2013 words_to_read = words;
2015 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2016 buffer.hdr.req.buf_lenh = 0;
2017 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2018 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2020 /* convert offset from words to bytes */
2021 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2022 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2024 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2026 IXGBE_HI_COMMAND_TIMEOUT,
2030 DEBUGOUT("Host interface command failed\n");
2034 for (i = 0; i < words_to_read; i++) {
2035 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2037 u32 value = IXGBE_READ_REG(hw, reg);
2039 data[current_word] = (u16)(value & 0xffff);
2042 if (i < words_to_read) {
2044 data[current_word] = (u16)(value & 0xffff);
2048 words -= words_to_read;
2052 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2057 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2058 * @hw: pointer to hardware structure
2059 * @offset: offset of word in the EEPROM to write
2060 * @data: word write to the EEPROM
2062 * Write a 16 bit word to the EEPROM using the hostif.
2064 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2068 struct ixgbe_hic_write_shadow_ram buffer;
2070 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2072 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2073 buffer.hdr.req.buf_lenh = 0;
2074 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2075 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2078 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2080 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2082 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2084 IXGBE_HI_COMMAND_TIMEOUT, false);
2090 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2091 * @hw: pointer to hardware structure
2092 * @offset: offset of word in the EEPROM to write
2093 * @data: word write to the EEPROM
2095 * Write a 16 bit word to the EEPROM using the hostif.
2097 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2100 s32 status = IXGBE_SUCCESS;
2102 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2104 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2106 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2107 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2109 DEBUGOUT("write ee hostif failed to get semaphore");
2110 status = IXGBE_ERR_SWFW_SYNC;
2117 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2118 * @hw: pointer to hardware structure
2119 * @offset: offset of word in the EEPROM to write
2120 * @words: number of words
2121 * @data: word(s) write to the EEPROM
2123 * Write a 16 bit word(s) to the EEPROM using the hostif.
2125 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2126 u16 offset, u16 words, u16 *data)
2128 s32 status = IXGBE_SUCCESS;
2131 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2133 /* Take semaphore for the entire operation. */
2134 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2135 if (status != IXGBE_SUCCESS) {
2136 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2140 for (i = 0; i < words; i++) {
2141 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2144 if (status != IXGBE_SUCCESS) {
2145 DEBUGOUT("Eeprom buffered write failed\n");
2150 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2157 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2158 * @hw: pointer to hardware structure
2159 * @ptr: pointer offset in eeprom
2160 * @size: size of section pointed by ptr, if 0 first word will be used as size
2161 * @csum: address of checksum to update
2163 * Returns error status for any failure
2165 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2166 u16 size, u16 *csum, u16 *buffer,
2171 u16 length, bufsz, i, start;
2174 bufsz = sizeof(buf) / sizeof(buf[0]);
2176 /* Read a chunk at the pointer location */
2178 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2180 DEBUGOUT("Failed to read EEPROM image\n");
2185 if (buffer_size < ptr)
2186 return IXGBE_ERR_PARAM;
2187 local_buffer = &buffer[ptr];
2195 length = local_buffer[0];
2197 /* Skip pointer section if length is invalid. */
2198 if (length == 0xFFFF || length == 0 ||
2199 (ptr + length) >= hw->eeprom.word_size)
2200 return IXGBE_SUCCESS;
2203 if (buffer && ((u32)start + (u32)length > buffer_size))
2204 return IXGBE_ERR_PARAM;
2206 for (i = start; length; i++, length--) {
2207 if (i == bufsz && !buffer) {
2213 /* Read a chunk at the pointer location */
2214 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2217 DEBUGOUT("Failed to read EEPROM image\n");
2221 *csum += local_buffer[i];
2223 return IXGBE_SUCCESS;
2227 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2228 * @hw: pointer to hardware structure
2229 * @buffer: pointer to buffer containing calculated checksum
2230 * @buffer_size: size of buffer
2232 * Returns a negative error code on error, or the 16-bit checksum
2234 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2236 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2240 u16 pointer, i, size;
2242 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2244 hw->eeprom.ops.init_params(hw);
2247 /* Read pointer area */
2248 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2249 IXGBE_EEPROM_LAST_WORD + 1,
2252 DEBUGOUT("Failed to read EEPROM image\n");
2255 local_buffer = eeprom_ptrs;
2257 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2258 return IXGBE_ERR_PARAM;
2259 local_buffer = buffer;
2263 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2264 * checksum word itself
2266 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2267 if (i != IXGBE_EEPROM_CHECKSUM)
2268 checksum += local_buffer[i];
2271 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2272 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2274 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2275 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2278 pointer = local_buffer[i];
2280 /* Skip pointer section if the pointer is invalid. */
2281 if (pointer == 0xFFFF || pointer == 0 ||
2282 pointer >= hw->eeprom.word_size)
2286 case IXGBE_PCIE_GENERAL_PTR:
2287 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2289 case IXGBE_PCIE_CONFIG0_PTR:
2290 case IXGBE_PCIE_CONFIG1_PTR:
2291 size = IXGBE_PCIE_CONFIG_SIZE;
2298 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2299 buffer, buffer_size);
2304 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2306 return (s32)checksum;
2310 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2311 * @hw: pointer to hardware structure
2313 * Returns a negative error code on error, or the 16-bit checksum
2315 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2317 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2321 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2322 * @hw: pointer to hardware structure
2323 * @checksum_val: calculated checksum
2325 * Performs checksum calculation and validates the EEPROM checksum. If the
2326 * caller does not need checksum_val, the value can be NULL.
2328 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2332 u16 read_checksum = 0;
2334 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2336 /* Read the first word from the EEPROM. If this times out or fails, do
2337 * not continue or we could be in for a very long wait while every
2340 status = hw->eeprom.ops.read(hw, 0, &checksum);
2342 DEBUGOUT("EEPROM read failed\n");
2346 status = hw->eeprom.ops.calc_checksum(hw);
2350 checksum = (u16)(status & 0xffff);
2352 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2357 /* Verify read checksum from EEPROM is the same as
2358 * calculated checksum
2360 if (read_checksum != checksum) {
2361 status = IXGBE_ERR_EEPROM_CHECKSUM;
2362 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2363 "Invalid EEPROM checksum");
2366 /* If the user cares, return the calculated checksum */
2368 *checksum_val = checksum;
2374 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2375 * @hw: pointer to hardware structure
2377 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2378 * checksum and updates the EEPROM and instructs the hardware to update
2381 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2386 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2388 /* Read the first word from the EEPROM. If this times out or fails, do
2389 * not continue or we could be in for a very long wait while every
2392 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2394 DEBUGOUT("EEPROM read failed\n");
2398 status = ixgbe_calc_eeprom_checksum_X550(hw);
2402 checksum = (u16)(status & 0xffff);
2404 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2409 status = ixgbe_update_flash_X550(hw);
2415 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2416 * @hw: pointer to hardware structure
2418 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2420 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2422 s32 status = IXGBE_SUCCESS;
2423 union ixgbe_hic_hdr2 buffer;
2425 DEBUGFUNC("ixgbe_update_flash_X550");
2427 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2428 buffer.req.buf_lenh = 0;
2429 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2430 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2432 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2434 IXGBE_HI_COMMAND_TIMEOUT, false);
2440 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2441 * @hw: pointer to hardware structure
2443 * Determines physical layer capabilities of the current configuration.
2445 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2447 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2448 u16 ext_ability = 0;
2450 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2452 hw->phy.ops.identify(hw);
2454 switch (hw->phy.type) {
2455 case ixgbe_phy_x550em_kr:
2456 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2457 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2459 case ixgbe_phy_x550em_kx4:
2460 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2461 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2463 case ixgbe_phy_x550em_ext_t:
2464 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2465 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2467 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2468 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2469 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2470 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2476 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2477 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2479 return physical_layer;
2483 * ixgbe_get_bus_info_x550em - Set PCI bus info
2484 * @hw: pointer to hardware structure
2486 * Sets bus link width and speed to unknown because X550em is
2489 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2492 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2494 hw->bus.width = ixgbe_bus_width_unknown;
2495 hw->bus.speed = ixgbe_bus_speed_unknown;
2497 hw->mac.ops.set_lan_id(hw);
2499 return IXGBE_SUCCESS;
2503 * ixgbe_disable_rx_x550 - Disable RX unit
2505 * Enables the Rx DMA unit for x550
2507 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2509 u32 rxctrl, pfdtxgswc;
2511 struct ixgbe_hic_disable_rxen fw_cmd;
2513 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2515 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2516 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2517 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2518 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2519 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2520 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2521 hw->mac.set_lben = true;
2523 hw->mac.set_lben = false;
2526 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2527 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2528 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2529 fw_cmd.port_number = (u8)hw->bus.lan_id;
2531 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2532 sizeof(struct ixgbe_hic_disable_rxen),
2533 IXGBE_HI_COMMAND_TIMEOUT, true);
2535 /* If we fail - disable RX using register write */
2537 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2538 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2539 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2540 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2547 * ixgbe_enter_lplu_x550em - Transition to low power states
2548 * @hw: pointer to hardware structure
2550 * Configures Low Power Link Up on transition to low power states
2551 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2552 * X557 PHY immediately prior to entering LPLU.
2554 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2556 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2558 ixgbe_link_speed lcd_speed;
2561 /* If blocked by MNG FW, then don't restart AN */
2562 if (ixgbe_check_reset_blocked(hw))
2563 return IXGBE_SUCCESS;
2565 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2566 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2569 if (status != IXGBE_SUCCESS)
2572 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2574 if (status != IXGBE_SUCCESS)
2577 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2578 * disabled, then force link down by entering low power mode.
2580 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2581 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2582 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2583 return ixgbe_set_copper_phy_power(hw, FALSE);
2586 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2588 if (status != IXGBE_SUCCESS)
2591 /* If no valid LCD link speed, then force link down and exit. */
2592 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2593 return ixgbe_set_copper_phy_power(hw, FALSE);
2595 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2596 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2599 if (status != IXGBE_SUCCESS)
2602 /* clear everything but the speed bits */
2603 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2605 /* If current speed is already LCD, then exit. */
2606 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2607 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2608 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2609 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2612 /* Clear AN completed indication */
2613 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2614 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2617 if (status != IXGBE_SUCCESS)
2620 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2621 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2624 if (status != IXGBE_SUCCESS)
2627 status = hw->phy.ops.read_reg(hw,
2628 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2629 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2632 if (status != IXGBE_SUCCESS)
2635 save_autoneg = hw->phy.autoneg_advertised;
2637 /* Setup link at least common link speed */
2638 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2640 /* restore autoneg from before setting lplu speed */
2641 hw->phy.autoneg_advertised = save_autoneg;
2647 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2648 * @hw: pointer to hardware structure
2649 * @lcd_speed: pointer to lowest common link speed
2651 * Determine lowest common link speed with link partner.
2653 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2657 u16 word = hw->eeprom.ctrl_word_3;
2659 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2661 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2662 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2665 if (status != IXGBE_SUCCESS)
2668 /* If link partner advertised 1G, return 1G */
2669 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2670 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2674 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2675 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2676 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2679 /* Link partner not capable of lower speeds, return 10G */
2680 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2685 * ixgbe_setup_fc_X550em - Set up flow control
2686 * @hw: pointer to hardware structure
2688 * Called at init time to set up flow control.
2690 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2692 s32 ret_val = IXGBE_SUCCESS;
2693 u32 pause, asm_dir, reg_val;
2695 DEBUGFUNC("ixgbe_setup_fc_X550em");
2697 /* Validate the requested mode */
2698 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2699 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2700 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2701 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2705 /* 10gig parts do not have a word in the EEPROM to determine the
2706 * default flow control setting, so we explicitly set it to full.
2708 if (hw->fc.requested_mode == ixgbe_fc_default)
2709 hw->fc.requested_mode = ixgbe_fc_full;
2711 /* Determine PAUSE and ASM_DIR bits. */
2712 switch (hw->fc.requested_mode) {
2717 case ixgbe_fc_tx_pause:
2721 case ixgbe_fc_rx_pause:
2722 /* Rx Flow control is enabled and Tx Flow control is
2723 * disabled by software override. Since there really
2724 * isn't a way to advertise that we are capable of RX
2725 * Pause ONLY, we will advertise that we support both
2726 * symmetric and asymmetric Rx PAUSE, as such we fall
2727 * through to the fc_full statement. Later, we will
2728 * disable the adapter's ability to send PAUSE frames.
2735 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2736 "Flow control param set incorrectly\n");
2737 ret_val = IXGBE_ERR_CONFIG;
2741 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2742 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2743 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2744 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2745 if (ret_val != IXGBE_SUCCESS)
2747 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2748 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2750 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2752 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2753 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2754 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2755 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2757 /* Not all devices fully support AN. */
2758 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2759 hw->fc.disable_fc_autoneg = true;
2767 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2768 * @hw: pointer to hardware structure
2769 * @state: set mux if 1, clear if 0
2771 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2775 if (!hw->bus.lan_id)
2777 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2779 esdp |= IXGBE_ESDP_SDP1;
2781 esdp &= ~IXGBE_ESDP_SDP1;
2782 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2783 IXGBE_WRITE_FLUSH(hw);
2787 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2788 * @hw: pointer to hardware structure
2789 * @mask: Mask to specify which semaphore to acquire
2791 * Acquires the SWFW semaphore and sets the I2C MUX
2793 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2797 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2799 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2803 if (mask & IXGBE_GSSR_I2C_MASK)
2804 ixgbe_set_mux(hw, 1);
2806 return IXGBE_SUCCESS;
2810 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2811 * @hw: pointer to hardware structure
2812 * @mask: Mask to specify which semaphore to release
2814 * Releases the SWFW semaphore and sets the I2C MUX
2816 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2818 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2820 if (mask & IXGBE_GSSR_I2C_MASK)
2821 ixgbe_set_mux(hw, 0);
2823 ixgbe_release_swfw_sync_X540(hw, mask);
2827 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2828 * @hw: pointer to hardware structure
2830 * Handle external Base T PHY interrupt. If high temperature
2831 * failure alarm then return error, else if link status change
2832 * then setup internal/external PHY link
2834 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2835 * failure alarm, else return PHY access status.
2837 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2842 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2844 if (status != IXGBE_SUCCESS)
2848 return ixgbe_setup_internal_phy_t_x550em(hw);
2850 return IXGBE_SUCCESS;
2854 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2855 * @hw: pointer to hardware structure
2856 * @speed: new link speed
2857 * @autoneg_wait_to_complete: true when waiting for completion is needed
2859 * Setup internal/external PHY link speed based on link speed, then set
2860 * external PHY auto advertised link speed.
2862 * Returns error status for any failure
2864 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2865 ixgbe_link_speed speed,
2866 bool autoneg_wait_to_complete)
2869 ixgbe_link_speed force_speed;
2871 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2873 /* Setup internal/external PHY link speed to iXFI (10G), unless
2874 * only 1G is auto advertised then setup KX link.
2876 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2877 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2879 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2881 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2883 if (status != IXGBE_SUCCESS)
2886 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2890 * ixgbe_check_link_t_X550em - Determine link and speed status
2891 * @hw: pointer to hardware structure
2892 * @speed: pointer to link speed
2893 * @link_up: true when link is up
2894 * @link_up_wait_to_complete: bool used to wait for link up or not
2896 * Check that both the MAC and X557 external PHY have link.
2898 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2899 bool *link_up, bool link_up_wait_to_complete)
2904 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2905 return IXGBE_ERR_CONFIG;
2907 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2908 link_up_wait_to_complete);
2910 /* If check link fails or MAC link is not up, then return */
2911 if (status != IXGBE_SUCCESS || !(*link_up))
2914 /* MAC link is up, so check external PHY link.
2915 * Read this twice back to back to indicate current status.
2917 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2918 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2921 if (status != IXGBE_SUCCESS)
2924 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2925 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2928 if (status != IXGBE_SUCCESS)
2931 /* If external PHY link is not up, then indicate link not up */
2932 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2935 return IXGBE_SUCCESS;
2939 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2940 * @hw: pointer to hardware structure
2942 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2946 status = ixgbe_reset_phy_generic(hw);
2948 if (status != IXGBE_SUCCESS)
2951 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2952 return ixgbe_enable_lasi_ext_t_x550em(hw);