1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = NULL;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_XFI:
454 hw->phy.type = ixgbe_phy_x550em_xfi;
456 case IXGBE_DEV_ID_X550EM_X_KR:
457 case IXGBE_DEV_ID_X550EM_A_KR:
458 case IXGBE_DEV_ID_X550EM_A_KR_L:
459 hw->phy.type = ixgbe_phy_x550em_kr;
461 case IXGBE_DEV_ID_X550EM_A_10G_T:
462 case IXGBE_DEV_ID_X550EM_X_10G_T:
463 return ixgbe_identify_phy_generic(hw);
464 case IXGBE_DEV_ID_X550EM_X_1G_T:
465 hw->phy.type = ixgbe_phy_ext_1g_t;
466 hw->phy.ops.read_reg = NULL;
467 hw->phy.ops.write_reg = NULL;
469 case IXGBE_DEV_ID_X550EM_A_1G_T:
470 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
471 hw->phy.type = ixgbe_phy_fw;
472 hw->phy.ops.read_reg = NULL;
473 hw->phy.ops.write_reg = NULL;
475 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
482 return IXGBE_SUCCESS;
486 * ixgbe_fw_phy_activity - Perform an activity on a PHY
487 * @hw: pointer to hardware structure
488 * @activity: activity to perform
489 * @data: Pointer to 4 32-bit words of data
491 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
492 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
495 struct ixgbe_hic_phy_activity_req cmd;
496 struct ixgbe_hic_phy_activity_resp rsp;
498 u16 retries = FW_PHY_ACT_RETRIES;
503 memset(&hic, 0, sizeof(hic));
504 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
505 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
506 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
507 hic.cmd.port_number = hw->bus.lan_id;
508 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
509 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
510 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
512 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
514 IXGBE_HI_COMMAND_TIMEOUT,
516 if (rc != IXGBE_SUCCESS)
518 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
519 FW_CEM_RESP_STATUS_SUCCESS) {
520 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
521 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
522 return IXGBE_SUCCESS;
526 } while (retries > 0);
528 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
531 static const struct {
533 ixgbe_link_speed phy_speed;
535 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
536 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
537 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
538 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
539 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
540 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
544 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
545 * @hw: pointer to hardware structure
549 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
551 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
557 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
561 hw->phy.speeds_supported = 0;
562 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
563 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
564 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
565 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
567 if (!hw->phy.autoneg_advertised)
568 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
570 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
571 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
572 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
573 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
574 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
575 return IXGBE_ERR_PHY_ADDR_INVALID;
576 return IXGBE_SUCCESS;
580 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
581 * @hw: pointer to hardware structure
585 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
588 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
590 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
592 hw->phy.type = ixgbe_phy_fw;
593 hw->phy.ops.read_reg = NULL;
594 hw->phy.ops.write_reg = NULL;
595 return ixgbe_get_phy_id_fw(hw);
599 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
600 * @hw: pointer to hardware structure
604 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
606 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
608 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
609 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
612 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
613 u32 device_type, u16 *phy_data)
615 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
616 return IXGBE_NOT_IMPLEMENTED;
619 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
620 u32 device_type, u16 phy_data)
622 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
623 return IXGBE_NOT_IMPLEMENTED;
627 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
628 * @hw: pointer to the hardware structure
629 * @addr: I2C bus address to read from
630 * @reg: I2C device register to read from
631 * @val: pointer to location to receive read value
633 * Returns an error code on error.
635 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
638 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
642 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
643 * @hw: pointer to the hardware structure
644 * @addr: I2C bus address to read from
645 * @reg: I2C device register to read from
646 * @val: pointer to location to receive read value
648 * Returns an error code on error.
651 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
654 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
658 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
659 * @hw: pointer to the hardware structure
660 * @addr: I2C bus address to write to
661 * @reg: I2C device register to write to
662 * @val: value to write
664 * Returns an error code on error.
666 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
667 u8 addr, u16 reg, u16 val)
669 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
673 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
674 * @hw: pointer to the hardware structure
675 * @addr: I2C bus address to write to
676 * @reg: I2C device register to write to
677 * @val: value to write
679 * Returns an error code on error.
682 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
683 u8 addr, u16 reg, u16 val)
685 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
689 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
690 * @hw: pointer to hardware structure
692 * Initialize the function pointers and for MAC type X550EM.
693 * Does not touch the hardware.
695 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
697 struct ixgbe_mac_info *mac = &hw->mac;
698 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
699 struct ixgbe_phy_info *phy = &hw->phy;
702 DEBUGFUNC("ixgbe_init_ops_X550EM");
704 /* Similar to X550 so start there. */
705 ret_val = ixgbe_init_ops_X550(hw);
707 /* Since this function eventually calls
708 * ixgbe_init_ops_540 by design, we are setting
709 * the pointers to NULL explicitly here to overwrite
710 * the values being set in the x540 function.
712 /* Thermal sensor not supported in x550EM */
713 mac->ops.get_thermal_sensor_data = NULL;
714 mac->ops.init_thermal_sensor_thresh = NULL;
715 mac->thermal_sensor_enabled = false;
717 /* FCOE not supported in x550EM */
718 mac->ops.get_san_mac_addr = NULL;
719 mac->ops.set_san_mac_addr = NULL;
720 mac->ops.get_wwn_prefix = NULL;
721 mac->ops.get_fcoe_boot_status = NULL;
723 /* IPsec not supported in x550EM */
724 mac->ops.disable_sec_rx_path = NULL;
725 mac->ops.enable_sec_rx_path = NULL;
727 /* AUTOC register is not present in x550EM. */
728 mac->ops.prot_autoc_read = NULL;
729 mac->ops.prot_autoc_write = NULL;
731 /* X550EM bus type is internal*/
732 hw->bus.type = ixgbe_bus_type_internal;
733 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
736 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
737 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
738 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
739 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
740 mac->ops.get_supported_physical_layer =
741 ixgbe_get_supported_physical_layer_X550em;
743 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
744 mac->ops.setup_fc = ixgbe_setup_fc_generic;
746 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
749 phy->ops.init = ixgbe_init_phy_ops_X550em;
750 switch (hw->device_id) {
751 case IXGBE_DEV_ID_X550EM_A_1G_T:
752 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
753 mac->ops.setup_fc = NULL;
754 phy->ops.identify = ixgbe_identify_phy_fw;
755 phy->ops.set_phy_power = NULL;
756 phy->ops.get_firmware_version = NULL;
758 case IXGBE_DEV_ID_X550EM_X_1G_T:
759 mac->ops.setup_fc = NULL;
760 phy->ops.identify = ixgbe_identify_phy_x550em;
761 phy->ops.set_phy_power = NULL;
764 phy->ops.identify = ixgbe_identify_phy_x550em;
767 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
768 phy->ops.set_phy_power = NULL;
772 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
773 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
774 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
775 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
776 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
777 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
778 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
779 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
785 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
786 * @hw: pointer to hardware structure
788 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
790 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
794 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
797 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
798 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
799 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
800 return IXGBE_ERR_INVALID_LINK_SETTINGS;
803 switch (hw->fc.requested_mode) {
805 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
806 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
808 case ixgbe_fc_rx_pause:
809 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
810 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
812 case ixgbe_fc_tx_pause:
813 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
814 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
820 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
821 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
822 setup[0] |= ixgbe_fw_map[i].fw_speed;
824 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
826 if (hw->phy.eee_speeds_advertised)
827 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
829 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
832 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
833 return IXGBE_ERR_OVERTEMP;
834 return IXGBE_SUCCESS;
838 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
839 * @hw: pointer to hardware structure
841 * Called at init time to set up flow control.
843 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
845 if (hw->fc.requested_mode == ixgbe_fc_default)
846 hw->fc.requested_mode = ixgbe_fc_full;
848 return ixgbe_setup_fw_link(hw);
852 * ixgbe_setup_eee_fw - Enable/disable EEE support
853 * @hw: pointer to the HW structure
854 * @enable_eee: boolean flag to enable EEE
856 * Enable/disable EEE based on enable_eee flag.
857 * This function controls EEE for firmware-based PHY implementations.
859 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
861 if (!!hw->phy.eee_speeds_advertised == enable_eee)
862 return IXGBE_SUCCESS;
864 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
866 hw->phy.eee_speeds_advertised = 0;
867 return hw->phy.ops.setup_link(hw);
871 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
872 * @hw: pointer to hardware structure
874 * Initialize the function pointers and for MAC type X550EM_a.
875 * Does not touch the hardware.
877 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
879 struct ixgbe_mac_info *mac = &hw->mac;
882 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
884 /* Start with generic X550EM init */
885 ret_val = ixgbe_init_ops_X550EM(hw);
887 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
888 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
889 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
890 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
892 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
893 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
895 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
896 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
898 switch (mac->ops.get_media_type(hw)) {
899 case ixgbe_media_type_fiber:
900 mac->ops.setup_fc = NULL;
901 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
903 case ixgbe_media_type_backplane:
904 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
905 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
911 switch (hw->device_id) {
912 case IXGBE_DEV_ID_X550EM_A_1G_T:
913 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
914 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
915 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
916 mac->ops.setup_eee = ixgbe_setup_eee_fw;
917 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
918 IXGBE_LINK_SPEED_1GB_FULL;
919 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
929 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
930 * @hw: pointer to hardware structure
932 * Initialize the function pointers and for MAC type X550EM_x.
933 * Does not touch the hardware.
935 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
937 struct ixgbe_mac_info *mac = &hw->mac;
938 struct ixgbe_link_info *link = &hw->link;
941 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
943 /* Start with generic X550EM init */
944 ret_val = ixgbe_init_ops_X550EM(hw);
946 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
947 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
948 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
949 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
950 link->ops.read_link = ixgbe_read_i2c_combined_generic;
951 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
952 link->ops.write_link = ixgbe_write_i2c_combined_generic;
953 link->ops.write_link_unlocked =
954 ixgbe_write_i2c_combined_generic_unlocked;
955 link->addr = IXGBE_CS4227;
957 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
958 mac->ops.setup_fc = NULL;
959 mac->ops.setup_eee = NULL;
966 * ixgbe_dmac_config_X550
967 * @hw: pointer to hardware structure
969 * Configure DMA coalescing. If enabling dmac, dmac is activated.
970 * When disabling dmac, dmac enable dmac bit is cleared.
972 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
974 u32 reg, high_pri_tc;
976 DEBUGFUNC("ixgbe_dmac_config_X550");
978 /* Disable DMA coalescing before configuring */
979 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
980 reg &= ~IXGBE_DMACR_DMAC_EN;
981 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
983 /* Disable DMA Coalescing if the watchdog timer is 0 */
984 if (!hw->mac.dmac_config.watchdog_timer)
987 ixgbe_dmac_config_tcs_X550(hw);
989 /* Configure DMA Coalescing Control Register */
990 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
992 /* Set the watchdog timer in units of 40.96 usec */
993 reg &= ~IXGBE_DMACR_DMACWT_MASK;
994 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
996 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
997 /* If fcoe is enabled, set high priority traffic class */
998 if (hw->mac.dmac_config.fcoe_en) {
999 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
1000 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
1001 IXGBE_DMACR_HIGH_PRI_TC_MASK);
1003 reg |= IXGBE_DMACR_EN_MNG_IND;
1005 /* Enable DMA coalescing after configuration */
1006 reg |= IXGBE_DMACR_DMAC_EN;
1007 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1010 return IXGBE_SUCCESS;
1014 * ixgbe_dmac_config_tcs_X550
1015 * @hw: pointer to hardware structure
1017 * Configure DMA coalescing threshold per TC. The dmac enable bit must
1018 * be cleared before configuring.
1020 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1022 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1024 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1026 /* Configure DMA coalescing enabled */
1027 switch (hw->mac.dmac_config.link_speed) {
1028 case IXGBE_LINK_SPEED_10_FULL:
1029 case IXGBE_LINK_SPEED_100_FULL:
1030 pb_headroom = IXGBE_DMACRXT_100M;
1032 case IXGBE_LINK_SPEED_1GB_FULL:
1033 pb_headroom = IXGBE_DMACRXT_1G;
1036 pb_headroom = IXGBE_DMACRXT_10G;
1040 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1041 IXGBE_MHADD_MFS_SHIFT) / 1024);
1043 /* Set the per Rx packet buffer receive threshold */
1044 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1045 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1046 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1048 if (tc < hw->mac.dmac_config.num_tcs) {
1049 /* Get Rx PB size */
1050 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1051 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1052 IXGBE_RXPBSIZE_SHIFT;
1054 /* Calculate receive buffer threshold in kilobytes */
1055 if (rx_pb_size > pb_headroom)
1056 rx_pb_size = rx_pb_size - pb_headroom;
1060 /* Minimum of MFS shall be set for DMCTH */
1061 reg |= (rx_pb_size > maxframe_size_kb) ?
1062 rx_pb_size : maxframe_size_kb;
1064 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1066 return IXGBE_SUCCESS;
1070 * ixgbe_dmac_update_tcs_X550
1071 * @hw: pointer to hardware structure
1073 * Disables dmac, updates per TC settings, and then enables dmac.
1075 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1079 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1081 /* Disable DMA coalescing before configuring */
1082 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1083 reg &= ~IXGBE_DMACR_DMAC_EN;
1084 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1086 ixgbe_dmac_config_tcs_X550(hw);
1088 /* Enable DMA coalescing after configuration */
1089 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1090 reg |= IXGBE_DMACR_DMAC_EN;
1091 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1093 return IXGBE_SUCCESS;
1097 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1098 * @hw: pointer to hardware structure
1100 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1101 * ixgbe_hw struct in order to set up EEPROM access.
1103 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1105 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1109 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1111 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1112 eeprom->semaphore_delay = 10;
1113 eeprom->type = ixgbe_flash;
1115 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1116 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1117 IXGBE_EEC_SIZE_SHIFT);
1118 eeprom->word_size = 1 << (eeprom_size +
1119 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1121 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1122 eeprom->type, eeprom->word_size);
1125 return IXGBE_SUCCESS;
1129 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1130 * @hw: pointer to hardware structure
1131 * @enable: enable or disable source address pruning
1132 * @pool: Rx pool to set source address pruning for
1134 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1139 /* max rx pool is 63 */
1143 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1144 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1147 pfflp |= (1ULL << pool);
1149 pfflp &= ~(1ULL << pool);
1151 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1152 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1156 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1157 * @hw: pointer to hardware structure
1158 * @enable: enable or disable switch for Ethertype anti-spoofing
1159 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1162 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1163 bool enable, int vf)
1165 int vf_target_reg = vf >> 3;
1166 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1169 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1171 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1173 pfvfspoof |= (1 << vf_target_shift);
1175 pfvfspoof &= ~(1 << vf_target_shift);
1177 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1181 * ixgbe_iosf_wait - Wait for IOSF command completion
1182 * @hw: pointer to hardware structure
1183 * @ctrl: pointer to location to receive final IOSF control value
1185 * Returns failing status on timeout
1187 * Note: ctrl can be NULL if the IOSF control register value is not needed
1189 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1193 /* Check every 10 usec to see if the address cycle completed.
1194 * The SB IOSF BUSY bit will clear when the operation is
1197 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1198 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1199 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1205 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1206 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1207 return IXGBE_ERR_PHY;
1210 return IXGBE_SUCCESS;
1214 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1215 * of the IOSF device
1216 * @hw: pointer to hardware structure
1217 * @reg_addr: 32 bit PHY register to write
1218 * @device_type: 3 bit device type
1219 * @data: Data to write to the register
1221 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1222 u32 device_type, u32 data)
1224 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1228 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1229 if (ret != IXGBE_SUCCESS)
1232 ret = ixgbe_iosf_wait(hw, NULL);
1233 if (ret != IXGBE_SUCCESS)
1236 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1237 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1239 /* Write IOSF control register */
1240 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1242 /* Write IOSF data register */
1243 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1245 ret = ixgbe_iosf_wait(hw, &command);
1247 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1248 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1249 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1250 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1251 "Failed to write, error %x\n", error);
1252 ret = IXGBE_ERR_PHY;
1256 ixgbe_release_swfw_semaphore(hw, gssr);
1261 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1262 * @hw: pointer to hardware structure
1263 * @reg_addr: 32 bit PHY register to write
1264 * @device_type: 3 bit device type
1265 * @data: Pointer to read data from the register
1267 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1268 u32 device_type, u32 *data)
1270 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1274 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1275 if (ret != IXGBE_SUCCESS)
1278 ret = ixgbe_iosf_wait(hw, NULL);
1279 if (ret != IXGBE_SUCCESS)
1282 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1283 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1285 /* Write IOSF control register */
1286 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1288 ret = ixgbe_iosf_wait(hw, &command);
1290 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1291 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1292 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1293 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1294 "Failed to read, error %x\n", error);
1295 ret = IXGBE_ERR_PHY;
1298 if (ret == IXGBE_SUCCESS)
1299 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1302 ixgbe_release_swfw_semaphore(hw, gssr);
1307 * ixgbe_get_phy_token - Get the token for shared phy access
1308 * @hw: Pointer to hardware structure
1311 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1313 struct ixgbe_hic_phy_token_req token_cmd;
1316 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1317 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1318 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1319 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1320 token_cmd.port_number = hw->bus.lan_id;
1321 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1323 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1325 IXGBE_HI_COMMAND_TIMEOUT,
1328 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1332 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1333 return IXGBE_SUCCESS;
1334 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1335 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1336 token_cmd.hdr.cmd_or_resp.ret_status);
1337 return IXGBE_ERR_FW_RESP_INVALID;
1340 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n");
1341 return IXGBE_ERR_TOKEN_RETRY;
1345 * ixgbe_put_phy_token - Put the token for shared phy access
1346 * @hw: Pointer to hardware structure
1349 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1351 struct ixgbe_hic_phy_token_req token_cmd;
1354 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1355 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1356 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1357 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1358 token_cmd.port_number = hw->bus.lan_id;
1359 token_cmd.command_type = FW_PHY_TOKEN_REL;
1361 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1363 IXGBE_HI_COMMAND_TIMEOUT,
1367 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1368 return IXGBE_SUCCESS;
1370 DEBUGOUT("Put PHY Token host interface command failed");
1371 return IXGBE_ERR_FW_RESP_INVALID;
1375 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1376 * of the IOSF device
1377 * @hw: pointer to hardware structure
1378 * @reg_addr: 32 bit PHY register to write
1379 * @device_type: 3 bit device type
1380 * @data: Data to write to the register
1382 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1383 u32 device_type, u32 data)
1385 struct ixgbe_hic_internal_phy_req write_cmd;
1387 UNREFERENCED_1PARAMETER(device_type);
1389 memset(&write_cmd, 0, sizeof(write_cmd));
1390 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1391 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1392 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1393 write_cmd.port_number = hw->bus.lan_id;
1394 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1395 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1396 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1398 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1400 IXGBE_HI_COMMAND_TIMEOUT, false);
1406 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1407 * @hw: pointer to hardware structure
1408 * @reg_addr: 32 bit PHY register to write
1409 * @device_type: 3 bit device type
1410 * @data: Pointer to read data from the register
1412 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1413 u32 device_type, u32 *data)
1416 struct ixgbe_hic_internal_phy_req cmd;
1417 struct ixgbe_hic_internal_phy_resp rsp;
1420 UNREFERENCED_1PARAMETER(device_type);
1422 memset(&hic, 0, sizeof(hic));
1423 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1424 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1425 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1426 hic.cmd.port_number = hw->bus.lan_id;
1427 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1428 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1430 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1432 IXGBE_HI_COMMAND_TIMEOUT, true);
1434 /* Extract the register value from the response. */
1435 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1441 * ixgbe_disable_mdd_X550
1442 * @hw: pointer to hardware structure
1444 * Disable malicious driver detection
1446 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1450 DEBUGFUNC("ixgbe_disable_mdd_X550");
1452 /* Disable MDD for TX DMA and interrupt */
1453 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1454 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1455 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1457 /* Disable MDD for RX and interrupt */
1458 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1459 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1460 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1464 * ixgbe_enable_mdd_X550
1465 * @hw: pointer to hardware structure
1467 * Enable malicious driver detection
1469 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1473 DEBUGFUNC("ixgbe_enable_mdd_X550");
1475 /* Enable MDD for TX DMA and interrupt */
1476 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1477 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1478 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1480 /* Enable MDD for RX and interrupt */
1481 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1482 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1483 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1487 * ixgbe_restore_mdd_vf_X550
1488 * @hw: pointer to hardware structure
1491 * Restore VF that was disabled during malicious driver detection event
1493 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1495 u32 idx, reg, num_qs, start_q, bitmask;
1497 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1499 /* Map VF to queues */
1500 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1501 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1502 case IXGBE_MRQC_VMDQRT8TCEN:
1503 num_qs = 8; /* 16 VFs / pools */
1504 bitmask = 0x000000FF;
1506 case IXGBE_MRQC_VMDQRSS32EN:
1507 case IXGBE_MRQC_VMDQRT4TCEN:
1508 num_qs = 4; /* 32 VFs / pools */
1509 bitmask = 0x0000000F;
1511 default: /* 64 VFs / pools */
1513 bitmask = 0x00000003;
1516 start_q = vf * num_qs;
1518 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1521 reg |= (bitmask << (start_q % 32));
1522 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1523 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1527 * ixgbe_mdd_event_X550
1528 * @hw: pointer to hardware structure
1529 * @vf_bitmap: vf bitmap of malicious vfs
1531 * Handle malicious driver detection event.
1533 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1536 u32 i, j, reg, q, shift, vf, idx;
1538 DEBUGFUNC("ixgbe_mdd_event_X550");
1540 /* figure out pool size for mapping to vf's */
1541 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1542 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1543 case IXGBE_MRQC_VMDQRT8TCEN:
1544 shift = 3; /* 16 VFs / pools */
1546 case IXGBE_MRQC_VMDQRSS32EN:
1547 case IXGBE_MRQC_VMDQRT4TCEN:
1548 shift = 2; /* 32 VFs / pools */
1551 shift = 1; /* 64 VFs / pools */
1555 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1556 for (i = 0; i < 4; i++) {
1557 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1558 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1563 /* Get malicious queue */
1564 for (j = 0; j < 32 && wqbr; j++) {
1566 if (!(wqbr & (1 << j)))
1569 /* Get queue from bitmask */
1572 /* Map queue to vf */
1575 /* Set vf bit in vf_bitmap */
1577 vf_bitmap[idx] |= (1 << (vf % 32));
1584 * ixgbe_get_media_type_X550em - Get media type
1585 * @hw: pointer to hardware structure
1587 * Returns the media type (fiber, copper, backplane)
1589 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1591 enum ixgbe_media_type media_type;
1593 DEBUGFUNC("ixgbe_get_media_type_X550em");
1595 /* Detect if there is a copper PHY attached. */
1596 switch (hw->device_id) {
1597 case IXGBE_DEV_ID_X550EM_X_KR:
1598 case IXGBE_DEV_ID_X550EM_X_KX4:
1599 case IXGBE_DEV_ID_X550EM_X_XFI:
1600 case IXGBE_DEV_ID_X550EM_A_KR:
1601 case IXGBE_DEV_ID_X550EM_A_KR_L:
1602 media_type = ixgbe_media_type_backplane;
1604 case IXGBE_DEV_ID_X550EM_X_SFP:
1605 case IXGBE_DEV_ID_X550EM_A_SFP:
1606 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1607 case IXGBE_DEV_ID_X550EM_A_QSFP:
1608 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1609 media_type = ixgbe_media_type_fiber;
1611 case IXGBE_DEV_ID_X550EM_X_1G_T:
1612 case IXGBE_DEV_ID_X550EM_X_10G_T:
1613 case IXGBE_DEV_ID_X550EM_A_10G_T:
1614 media_type = ixgbe_media_type_copper;
1616 case IXGBE_DEV_ID_X550EM_A_SGMII:
1617 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1618 media_type = ixgbe_media_type_backplane;
1619 hw->phy.type = ixgbe_phy_sgmii;
1621 case IXGBE_DEV_ID_X550EM_A_1G_T:
1622 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1623 media_type = ixgbe_media_type_copper;
1626 media_type = ixgbe_media_type_unknown;
1633 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1634 * @hw: pointer to hardware structure
1635 * @linear: true if SFP module is linear
1637 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1639 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1641 switch (hw->phy.sfp_type) {
1642 case ixgbe_sfp_type_not_present:
1643 return IXGBE_ERR_SFP_NOT_PRESENT;
1644 case ixgbe_sfp_type_da_cu_core0:
1645 case ixgbe_sfp_type_da_cu_core1:
1648 case ixgbe_sfp_type_srlr_core0:
1649 case ixgbe_sfp_type_srlr_core1:
1650 case ixgbe_sfp_type_da_act_lmt_core0:
1651 case ixgbe_sfp_type_da_act_lmt_core1:
1652 case ixgbe_sfp_type_1g_sx_core0:
1653 case ixgbe_sfp_type_1g_sx_core1:
1654 case ixgbe_sfp_type_1g_lx_core0:
1655 case ixgbe_sfp_type_1g_lx_core1:
1658 case ixgbe_sfp_type_unknown:
1659 case ixgbe_sfp_type_1g_cu_core0:
1660 case ixgbe_sfp_type_1g_cu_core1:
1662 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1665 return IXGBE_SUCCESS;
1669 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1670 * @hw: pointer to hardware structure
1672 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1674 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1679 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1681 status = ixgbe_identify_module_generic(hw);
1683 if (status != IXGBE_SUCCESS)
1686 /* Check if SFP module is supported */
1687 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1693 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1694 * @hw: pointer to hardware structure
1696 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1701 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1703 /* Check if SFP module is supported */
1704 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1706 if (status != IXGBE_SUCCESS)
1709 ixgbe_init_mac_link_ops_X550em(hw);
1710 hw->phy.ops.reset = NULL;
1712 return IXGBE_SUCCESS;
1716 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1718 * @hw: pointer to hardware structure
1720 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1725 /* Restart auto-negotiation. */
1726 status = hw->mac.ops.read_iosf_sb_reg(hw,
1727 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1728 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1731 DEBUGOUT("Auto-negotiation did not complete\n");
1735 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1736 status = hw->mac.ops.write_iosf_sb_reg(hw,
1737 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1738 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1740 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1743 /* Indicate to FW that AN restart has been asserted */
1744 status = hw->mac.ops.read_iosf_sb_reg(hw,
1745 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1746 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1749 DEBUGOUT("Auto-negotiation did not complete\n");
1753 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1754 status = hw->mac.ops.write_iosf_sb_reg(hw,
1755 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1756 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1763 * ixgbe_setup_sgmii - Set up link for sgmii
1764 * @hw: pointer to hardware structure
1766 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1769 struct ixgbe_mac_info *mac = &hw->mac;
1770 u32 lval, sval, flx_val;
1773 rc = mac->ops.read_iosf_sb_reg(hw,
1774 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1775 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1779 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1780 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1781 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1782 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1783 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1784 rc = mac->ops.write_iosf_sb_reg(hw,
1785 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1786 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1790 rc = mac->ops.read_iosf_sb_reg(hw,
1791 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1792 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1796 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1797 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1798 rc = mac->ops.write_iosf_sb_reg(hw,
1799 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1800 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1804 rc = mac->ops.read_iosf_sb_reg(hw,
1805 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1806 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1810 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1811 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1812 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1813 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1814 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1816 rc = mac->ops.write_iosf_sb_reg(hw,
1817 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1818 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1822 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1826 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1830 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1831 * @hw: pointer to hardware structure
1833 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1836 struct ixgbe_mac_info *mac = &hw->mac;
1837 u32 lval, sval, flx_val;
1840 rc = mac->ops.read_iosf_sb_reg(hw,
1841 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1842 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1846 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1847 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1848 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1849 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1850 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1851 rc = mac->ops.write_iosf_sb_reg(hw,
1852 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1853 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1857 rc = mac->ops.read_iosf_sb_reg(hw,
1858 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1859 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1863 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1864 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1865 rc = mac->ops.write_iosf_sb_reg(hw,
1866 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1867 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1871 rc = mac->ops.write_iosf_sb_reg(hw,
1872 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1873 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1877 rc = mac->ops.read_iosf_sb_reg(hw,
1878 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1879 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1883 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1884 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1885 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1886 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1887 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1889 rc = mac->ops.write_iosf_sb_reg(hw,
1890 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1891 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1895 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1897 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1901 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1902 * @hw: pointer to hardware structure
1904 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1906 struct ixgbe_mac_info *mac = &hw->mac;
1908 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1910 switch (hw->mac.ops.get_media_type(hw)) {
1911 case ixgbe_media_type_fiber:
1912 /* CS4227 does not support autoneg, so disable the laser control
1913 * functions for SFP+ fiber
1915 mac->ops.disable_tx_laser = NULL;
1916 mac->ops.enable_tx_laser = NULL;
1917 mac->ops.flap_tx_laser = NULL;
1918 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1919 mac->ops.set_rate_select_speed =
1920 ixgbe_set_soft_rate_select_speed;
1922 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1923 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1924 mac->ops.setup_mac_link =
1925 ixgbe_setup_mac_link_sfp_x550a;
1927 mac->ops.setup_mac_link =
1928 ixgbe_setup_mac_link_sfp_x550em;
1930 case ixgbe_media_type_copper:
1931 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1933 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1934 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1935 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1936 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1937 mac->ops.check_link =
1938 ixgbe_check_mac_link_generic;
1940 mac->ops.setup_link =
1941 ixgbe_setup_mac_link_t_X550em;
1944 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1945 mac->ops.check_link = ixgbe_check_link_t_X550em;
1948 case ixgbe_media_type_backplane:
1949 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1950 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1951 mac->ops.setup_link = ixgbe_setup_sgmii;
1959 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1960 * @hw: pointer to hardware structure
1961 * @speed: pointer to link speed
1962 * @autoneg: true when autoneg or autotry is enabled
1964 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1965 ixgbe_link_speed *speed,
1968 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1971 if (hw->phy.type == ixgbe_phy_fw) {
1973 *speed = hw->phy.speeds_supported;
1978 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1980 /* CS4227 SFP must not enable auto-negotiation */
1983 /* Check if 1G SFP module. */
1984 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1985 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1986 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1987 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1988 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1989 return IXGBE_SUCCESS;
1992 /* Link capabilities are based on SFP */
1993 if (hw->phy.multispeed_fiber)
1994 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1995 IXGBE_LINK_SPEED_1GB_FULL;
1997 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1999 switch (hw->phy.type) {
2000 case ixgbe_phy_ext_1g_t:
2001 case ixgbe_phy_sgmii:
2002 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2004 case ixgbe_phy_x550em_kr:
2005 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2006 /* check different backplane modes */
2007 if (hw->phy.nw_mng_if_sel &
2008 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2009 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2011 } else if (hw->device_id ==
2012 IXGBE_DEV_ID_X550EM_A_KR_L) {
2013 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2019 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2020 IXGBE_LINK_SPEED_1GB_FULL;
2026 return IXGBE_SUCCESS;
2030 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2031 * @hw: pointer to hardware structure
2032 * @lsc: pointer to boolean flag which indicates whether external Base T
2033 * PHY interrupt is lsc
2035 * Determime if external Base T PHY interrupt cause is high temperature
2036 * failure alarm or link status change.
2038 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2039 * failure alarm, else return PHY access status.
2041 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2048 /* Vendor alarm triggered */
2049 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2050 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2053 if (status != IXGBE_SUCCESS ||
2054 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2057 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2058 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2059 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2062 if (status != IXGBE_SUCCESS ||
2063 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2064 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2067 /* Global alarm triggered */
2068 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2069 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2072 if (status != IXGBE_SUCCESS)
2075 /* If high temperature failure, then return over temp error and exit */
2076 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2077 /* power down the PHY in case the PHY FW didn't already */
2078 ixgbe_set_copper_phy_power(hw, false);
2079 return IXGBE_ERR_OVERTEMP;
2080 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2081 /* device fault alarm triggered */
2082 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2083 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2086 if (status != IXGBE_SUCCESS)
2089 /* if device fault was due to high temp alarm handle and exit */
2090 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2091 /* power down the PHY in case the PHY FW didn't */
2092 ixgbe_set_copper_phy_power(hw, false);
2093 return IXGBE_ERR_OVERTEMP;
2097 /* Vendor alarm 2 triggered */
2098 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2101 if (status != IXGBE_SUCCESS ||
2102 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2105 /* link connect/disconnect event occurred */
2106 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2109 if (status != IXGBE_SUCCESS)
2113 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2116 return IXGBE_SUCCESS;
2120 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2121 * @hw: pointer to hardware structure
2123 * Enable link status change and temperature failure alarm for the external
2126 * Returns PHY access status
2128 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2134 /* Clear interrupt flags */
2135 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2137 /* Enable link status change alarm */
2139 /* Enable the LASI interrupts on X552 devices to receive notifications
2140 * of the link configurations of the external PHY and correspondingly
2141 * support the configuration of the internal iXFI link, since iXFI does
2142 * not support auto-negotiation. This is not required for X553 devices
2143 * having KR support, which performs auto-negotiations and which is used
2144 * as the internal link to the external PHY. Hence adding a check here
2145 * to avoid enabling LASI interrupts for X553 devices.
2147 if (hw->mac.type != ixgbe_mac_X550EM_a) {
2148 status = hw->phy.ops.read_reg(hw,
2149 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2150 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2152 if (status != IXGBE_SUCCESS)
2155 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2157 status = hw->phy.ops.write_reg(hw,
2158 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2159 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2161 if (status != IXGBE_SUCCESS)
2165 /* Enable high temperature failure and global fault alarms */
2166 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2167 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2170 if (status != IXGBE_SUCCESS)
2173 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2174 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2176 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2177 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2180 if (status != IXGBE_SUCCESS)
2183 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2184 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2185 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2188 if (status != IXGBE_SUCCESS)
2191 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2192 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2194 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2195 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2198 if (status != IXGBE_SUCCESS)
2201 /* Enable chip-wide vendor alarm */
2202 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2203 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2206 if (status != IXGBE_SUCCESS)
2209 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2211 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2212 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2219 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2220 * @hw: pointer to hardware structure
2221 * @speed: link speed
2223 * Configures the integrated KR PHY.
2225 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2226 ixgbe_link_speed speed)
2231 status = hw->mac.ops.read_iosf_sb_reg(hw,
2232 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2233 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2237 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2238 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2239 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2241 /* Advertise 10G support. */
2242 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2243 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2245 /* Advertise 1G support. */
2246 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2247 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2249 status = hw->mac.ops.write_iosf_sb_reg(hw,
2250 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2251 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2253 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2254 /* Set lane mode to KR auto negotiation */
2255 status = hw->mac.ops.read_iosf_sb_reg(hw,
2256 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2257 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2262 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2263 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2264 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2265 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2266 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2268 status = hw->mac.ops.write_iosf_sb_reg(hw,
2269 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2270 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2273 return ixgbe_restart_an_internal_phy_x550em(hw);
2277 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2278 * @hw: pointer to hardware structure
2280 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2282 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2285 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2286 return IXGBE_SUCCESS;
2288 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2291 memset(store, 0, sizeof(store));
2293 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2297 return ixgbe_setup_fw_link(hw);
2301 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2302 * @hw: pointer to hardware structure
2304 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2306 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2309 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2313 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2314 ixgbe_shutdown_fw_phy(hw);
2315 return IXGBE_ERR_OVERTEMP;
2317 return IXGBE_SUCCESS;
2321 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2322 * @hw: pointer to hardware structure
2324 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2327 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2329 /* Save NW management interface connected on board. This is used
2330 * to determine internal PHY mode.
2332 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2334 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2335 * PHY address. This register field was has only been used for X552.
2337 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2338 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2339 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2344 return IXGBE_SUCCESS;
2348 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2349 * @hw: pointer to hardware structure
2351 * Initialize any function pointers that were not able to be
2352 * set during init_shared_code because the PHY/SFP type was
2353 * not known. Perform the SFP init if necessary.
2355 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2357 struct ixgbe_phy_info *phy = &hw->phy;
2360 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2362 hw->mac.ops.set_lan_id(hw);
2363 ixgbe_read_mng_if_sel_x550em(hw);
2365 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2366 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2367 ixgbe_setup_mux_ctl(hw);
2368 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2371 switch (hw->device_id) {
2372 case IXGBE_DEV_ID_X550EM_A_1G_T:
2373 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2374 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2375 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2376 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2377 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2378 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2380 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2382 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2385 case IXGBE_DEV_ID_X550EM_A_10G_T:
2386 case IXGBE_DEV_ID_X550EM_A_SFP:
2387 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2388 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2390 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2392 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2394 case IXGBE_DEV_ID_X550EM_X_SFP:
2395 /* set up for CS4227 usage */
2396 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2402 /* Identify the PHY or SFP module */
2403 ret_val = phy->ops.identify(hw);
2404 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2405 ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2408 /* Setup function pointers based on detected hardware */
2409 ixgbe_init_mac_link_ops_X550em(hw);
2410 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2411 phy->ops.reset = NULL;
2413 /* Set functions pointers based on phy type */
2414 switch (hw->phy.type) {
2415 case ixgbe_phy_x550em_kx4:
2416 phy->ops.setup_link = NULL;
2417 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2418 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2420 case ixgbe_phy_x550em_kr:
2421 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2422 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2423 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2425 case ixgbe_phy_ext_1g_t:
2426 /* link is managed by FW */
2427 phy->ops.setup_link = NULL;
2429 case ixgbe_phy_x550em_xfi:
2430 /* link is managed by HW */
2431 phy->ops.setup_link = NULL;
2432 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2433 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2435 case ixgbe_phy_x550em_ext_t:
2436 /* If internal link mode is XFI, then setup iXFI internal link,
2437 * else setup KR now.
2439 phy->ops.setup_internal_link =
2440 ixgbe_setup_internal_phy_t_x550em;
2442 /* setup SW LPLU only for first revision of X550EM_x */
2443 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2444 !(IXGBE_FUSES0_REV_MASK &
2445 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2446 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2448 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2449 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2451 case ixgbe_phy_sgmii:
2452 phy->ops.setup_link = NULL;
2455 phy->ops.setup_link = ixgbe_setup_fw_link;
2456 phy->ops.reset = ixgbe_reset_phy_fw;
2465 * ixgbe_set_mdio_speed - Set MDIO clock speed
2466 * @hw: pointer to hardware structure
2468 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2472 switch (hw->device_id) {
2473 case IXGBE_DEV_ID_X550EM_X_10G_T:
2474 case IXGBE_DEV_ID_X550EM_A_SGMII:
2475 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2476 case IXGBE_DEV_ID_X550EM_A_10G_T:
2477 case IXGBE_DEV_ID_X550EM_A_SFP:
2478 case IXGBE_DEV_ID_X550EM_A_QSFP:
2479 /* Config MDIO clock speed before the first MDIO PHY access */
2480 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2481 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2482 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2484 case IXGBE_DEV_ID_X550EM_A_1G_T:
2485 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2486 /* Select fast MDIO clock speed for these devices */
2487 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2488 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2489 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2497 * ixgbe_reset_hw_X550em - Perform hardware reset
2498 * @hw: pointer to hardware structure
2500 * Resets the hardware by resetting the transmit and receive units, masks
2501 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2504 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2506 ixgbe_link_speed link_speed;
2510 bool link_up = false;
2511 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2513 DEBUGFUNC("ixgbe_reset_hw_X550em");
2515 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2516 status = hw->mac.ops.stop_adapter(hw);
2517 if (status != IXGBE_SUCCESS) {
2518 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2521 /* flush pending Tx transactions */
2522 ixgbe_clear_tx_pending(hw);
2524 ixgbe_set_mdio_speed(hw);
2526 /* PHY ops must be identified and initialized prior to reset */
2527 status = hw->phy.ops.init(hw);
2530 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2533 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2534 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2538 /* start the external PHY */
2539 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2540 status = ixgbe_init_ext_t_x550em(hw);
2542 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2548 /* Setup SFP module if there is one present. */
2549 if (hw->phy.sfp_setup_needed) {
2550 status = hw->mac.ops.setup_sfp(hw);
2551 hw->phy.sfp_setup_needed = false;
2554 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2558 if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2559 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2560 return IXGBE_ERR_OVERTEMP;
2564 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2565 * If link reset is used when link is up, it might reset the PHY when
2566 * mng is using it. If link is down or the flag to force full link
2567 * reset is set, then perform link reset.
2569 ctrl = IXGBE_CTRL_LNK_RST;
2570 if (!hw->force_full_reset) {
2571 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2573 ctrl = IXGBE_CTRL_RST;
2576 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2577 if (status != IXGBE_SUCCESS) {
2578 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2579 "semaphore failed with %d", status);
2580 return IXGBE_ERR_SWFW_SYNC;
2582 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2583 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2584 IXGBE_WRITE_FLUSH(hw);
2585 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2587 /* Poll for reset bit to self-clear meaning reset is complete */
2588 for (i = 0; i < 10; i++) {
2590 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2591 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2595 if (ctrl & IXGBE_CTRL_RST_MASK) {
2596 status = IXGBE_ERR_RESET_FAILED;
2597 DEBUGOUT("Reset polling failed to complete.\n");
2602 /* Double resets are required for recovery from certain error
2603 * conditions. Between resets, it is necessary to stall to
2604 * allow time for any pending HW events to complete.
2606 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2607 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2611 /* Store the permanent mac address */
2612 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2614 /* Store MAC address from RAR0, clear receive address registers, and
2615 * clear the multicast table. Also reset num_rar_entries to 128,
2616 * since we modify this value when programming the SAN MAC address.
2618 hw->mac.num_rar_entries = 128;
2619 hw->mac.ops.init_rx_addrs(hw);
2621 ixgbe_set_mdio_speed(hw);
2623 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2624 ixgbe_setup_mux_ctl(hw);
2626 if (status != IXGBE_SUCCESS)
2627 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2633 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2634 * @hw: pointer to hardware structure
2636 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2641 status = hw->phy.ops.read_reg(hw,
2642 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2643 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2646 if (status != IXGBE_SUCCESS)
2649 /* If PHY FW reset completed bit is set then this is the first
2650 * SW instance after a power on so the PHY FW must be un-stalled.
2652 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2653 status = hw->phy.ops.read_reg(hw,
2654 IXGBE_MDIO_GLOBAL_RES_PR_10,
2655 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2658 if (status != IXGBE_SUCCESS)
2661 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2663 status = hw->phy.ops.write_reg(hw,
2664 IXGBE_MDIO_GLOBAL_RES_PR_10,
2665 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2668 if (status != IXGBE_SUCCESS)
2676 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2677 * @hw: pointer to hardware structure
2679 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2681 /* leave link alone for 2.5G */
2682 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2683 return IXGBE_SUCCESS;
2685 if (ixgbe_check_reset_blocked(hw))
2688 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2692 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2693 * @hw: pointer to hardware structure
2695 * Configure the external PHY and the integrated KR PHY for SFP support.
2697 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2698 ixgbe_link_speed speed,
2699 bool autoneg_wait_to_complete)
2702 u16 reg_slice, reg_val;
2703 bool setup_linear = false;
2704 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2706 /* Check if SFP module is supported and linear */
2707 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2709 /* If no SFP module present, then return success. Return success since
2710 * there is no reason to configure CS4227 and SFP not present error is
2711 * not excepted in the setup MAC link flow.
2713 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2714 return IXGBE_SUCCESS;
2716 if (ret_val != IXGBE_SUCCESS)
2719 /* Configure internal PHY for KR/KX. */
2720 ixgbe_setup_kr_speed_x550em(hw, speed);
2722 /* Configure CS4227 LINE side to proper mode. */
2723 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2724 (hw->bus.lan_id << 12);
2726 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2728 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2729 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2735 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2736 * @hw: pointer to hardware structure
2737 * @speed: the link speed to force
2739 * Configures the integrated PHY for native SFI mode. Used to connect the
2740 * internal PHY directly to an SFP cage, without autonegotiation.
2742 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2744 struct ixgbe_mac_info *mac = &hw->mac;
2748 /* Disable all AN and force speed to 10G Serial. */
2749 status = mac->ops.read_iosf_sb_reg(hw,
2750 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2751 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2752 if (status != IXGBE_SUCCESS)
2755 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2756 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2757 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2758 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2760 /* Select forced link speed for internal PHY. */
2762 case IXGBE_LINK_SPEED_10GB_FULL:
2763 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2765 case IXGBE_LINK_SPEED_1GB_FULL:
2766 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2769 /* Other link speeds are not supported by internal PHY. */
2770 return IXGBE_ERR_LINK_SETUP;
2773 status = mac->ops.write_iosf_sb_reg(hw,
2774 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2775 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2777 /* Toggle port SW reset by AN reset. */
2778 status = ixgbe_restart_an_internal_phy_x550em(hw);
2784 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2785 * @hw: pointer to hardware structure
2787 * Configure the the integrated PHY for SFP support.
2789 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2790 ixgbe_link_speed speed,
2791 bool autoneg_wait_to_complete)
2795 bool setup_linear = false;
2796 u32 reg_slice, reg_phy_int, slice_offset;
2798 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2800 /* Check if SFP module is supported and linear */
2801 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2803 /* If no SFP module present, then return success. Return success since
2804 * SFP not present error is not excepted in the setup MAC link flow.
2806 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2807 return IXGBE_SUCCESS;
2809 if (ret_val != IXGBE_SUCCESS)
2812 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2813 /* Configure internal PHY for native SFI based on module type */
2814 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2815 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2816 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2818 if (ret_val != IXGBE_SUCCESS)
2821 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2823 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2825 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2826 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2827 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2829 if (ret_val != IXGBE_SUCCESS)
2832 /* Setup SFI internal link. */
2833 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2835 /* Configure internal PHY for KR/KX. */
2836 ixgbe_setup_kr_speed_x550em(hw, speed);
2838 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2840 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2841 return IXGBE_ERR_PHY_ADDR_INVALID;
2844 /* Get external PHY SKU id */
2845 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2846 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2848 if (ret_val != IXGBE_SUCCESS)
2851 /* When configuring quad port CS4223, the MAC instance is part
2852 * of the slice offset.
2854 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2855 slice_offset = (hw->bus.lan_id +
2856 (hw->bus.instance_id << 1)) << 12;
2858 slice_offset = hw->bus.lan_id << 12;
2860 /* Configure CS4227/CS4223 LINE side to proper mode. */
2861 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2863 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2864 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2866 if (ret_val != IXGBE_SUCCESS)
2869 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2870 (IXGBE_CS4227_EDC_MODE_SR << 1));
2873 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2875 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2876 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2877 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2879 /* Flush previous write with a read */
2880 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2881 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2887 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2888 * @hw: pointer to hardware structure
2890 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2892 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2894 struct ixgbe_mac_info *mac = &hw->mac;
2898 /* Disable training protocol FSM. */
2899 status = mac->ops.read_iosf_sb_reg(hw,
2900 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2901 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2902 if (status != IXGBE_SUCCESS)
2904 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2905 status = mac->ops.write_iosf_sb_reg(hw,
2906 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2907 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2908 if (status != IXGBE_SUCCESS)
2911 /* Disable Flex from training TXFFE. */
2912 status = mac->ops.read_iosf_sb_reg(hw,
2913 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2914 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2915 if (status != IXGBE_SUCCESS)
2917 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2918 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2919 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2920 status = mac->ops.write_iosf_sb_reg(hw,
2921 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2922 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2923 if (status != IXGBE_SUCCESS)
2925 status = mac->ops.read_iosf_sb_reg(hw,
2926 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2927 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2928 if (status != IXGBE_SUCCESS)
2930 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2931 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2932 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2933 status = mac->ops.write_iosf_sb_reg(hw,
2934 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2935 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2936 if (status != IXGBE_SUCCESS)
2939 /* Enable override for coefficients. */
2940 status = mac->ops.read_iosf_sb_reg(hw,
2941 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2942 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2943 if (status != IXGBE_SUCCESS)
2945 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2946 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2947 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2948 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2949 status = mac->ops.write_iosf_sb_reg(hw,
2950 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2951 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2956 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2957 * @hw: pointer to hardware structure
2958 * @speed: the link speed to force
2960 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2961 * internal and external PHY at a specific speed, without autonegotiation.
2963 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2965 struct ixgbe_mac_info *mac = &hw->mac;
2969 /* iXFI is only supported with X552 */
2970 if (mac->type != ixgbe_mac_X550EM_x)
2971 return IXGBE_ERR_LINK_SETUP;
2973 /* Disable AN and force speed to 10G Serial. */
2974 status = mac->ops.read_iosf_sb_reg(hw,
2975 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2976 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2977 if (status != IXGBE_SUCCESS)
2980 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2981 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2983 /* Select forced link speed for internal PHY. */
2985 case IXGBE_LINK_SPEED_10GB_FULL:
2986 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2988 case IXGBE_LINK_SPEED_1GB_FULL:
2989 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2992 /* Other link speeds are not supported by internal KR PHY. */
2993 return IXGBE_ERR_LINK_SETUP;
2996 status = mac->ops.write_iosf_sb_reg(hw,
2997 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2998 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2999 if (status != IXGBE_SUCCESS)
3002 /* Additional configuration needed for x550em_x */
3003 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3004 status = ixgbe_setup_ixfi_x550em_x(hw);
3005 if (status != IXGBE_SUCCESS)
3009 /* Toggle port SW reset by AN reset. */
3010 status = ixgbe_restart_an_internal_phy_x550em(hw);
3016 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3017 * @hw: address of hardware structure
3018 * @link_up: address of boolean to indicate link status
3020 * Returns error code if unable to get link status.
3022 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3029 /* read this twice back to back to indicate current status */
3030 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3031 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3033 if (ret != IXGBE_SUCCESS)
3036 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3037 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3039 if (ret != IXGBE_SUCCESS)
3042 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3044 return IXGBE_SUCCESS;
3048 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3049 * @hw: point to hardware structure
3051 * Configures the link between the integrated KR PHY and the external X557 PHY
3052 * The driver will call this function when it gets a link status change
3053 * interrupt from the X557 PHY. This function configures the link speed
3054 * between the PHYs to match the link speed of the BASE-T link.
3056 * A return of a non-zero value indicates an error, and the base driver should
3057 * not report link up.
3059 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3061 ixgbe_link_speed force_speed;
3066 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3067 return IXGBE_ERR_CONFIG;
3069 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3070 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3071 /* If link is down, there is no setup necessary so return */
3072 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3073 if (status != IXGBE_SUCCESS)
3077 return IXGBE_SUCCESS;
3079 status = hw->phy.ops.read_reg(hw,
3080 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3081 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3083 if (status != IXGBE_SUCCESS)
3086 /* If link is still down - no setup is required so return */
3087 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3088 if (status != IXGBE_SUCCESS)
3091 return IXGBE_SUCCESS;
3093 /* clear everything but the speed and duplex bits */
3094 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3097 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3098 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3100 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3101 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3104 /* Internal PHY does not support anything else */
3105 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3108 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3110 speed = IXGBE_LINK_SPEED_10GB_FULL |
3111 IXGBE_LINK_SPEED_1GB_FULL;
3112 return ixgbe_setup_kr_speed_x550em(hw, speed);
3117 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3118 * @hw: pointer to hardware structure
3120 * Configures the integrated KR PHY to use internal loopback mode.
3122 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3127 /* Disable AN and force speed to 10G Serial. */
3128 status = hw->mac.ops.read_iosf_sb_reg(hw,
3129 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3130 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3131 if (status != IXGBE_SUCCESS)
3133 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3134 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3135 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3136 status = hw->mac.ops.write_iosf_sb_reg(hw,
3137 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3138 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3139 if (status != IXGBE_SUCCESS)
3142 /* Set near-end loopback clocks. */
3143 status = hw->mac.ops.read_iosf_sb_reg(hw,
3144 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3145 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3146 if (status != IXGBE_SUCCESS)
3148 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3149 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3150 status = hw->mac.ops.write_iosf_sb_reg(hw,
3151 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3152 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3153 if (status != IXGBE_SUCCESS)
3156 /* Set loopback enable. */
3157 status = hw->mac.ops.read_iosf_sb_reg(hw,
3158 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3159 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3160 if (status != IXGBE_SUCCESS)
3162 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3163 status = hw->mac.ops.write_iosf_sb_reg(hw,
3164 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3165 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3166 if (status != IXGBE_SUCCESS)
3169 /* Training bypass. */
3170 status = hw->mac.ops.read_iosf_sb_reg(hw,
3171 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3172 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3173 if (status != IXGBE_SUCCESS)
3175 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3176 status = hw->mac.ops.write_iosf_sb_reg(hw,
3177 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3178 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3184 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3185 * assuming that the semaphore is already obtained.
3186 * @hw: pointer to hardware structure
3187 * @offset: offset of word in the EEPROM to read
3188 * @data: word read from the EEPROM
3190 * Reads a 16 bit word from the EEPROM using the hostif.
3192 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3194 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3195 struct ixgbe_hic_read_shadow_ram buffer;
3198 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3199 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3200 buffer.hdr.req.buf_lenh = 0;
3201 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3202 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3204 /* convert offset from words to bytes */
3205 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3207 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3209 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3213 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3214 IXGBE_HI_COMMAND_TIMEOUT);
3216 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3217 FW_NVM_DATA_OFFSET);
3220 hw->mac.ops.release_swfw_sync(hw, mask);
3225 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3226 * @hw: pointer to hardware structure
3227 * @offset: offset of word in the EEPROM to read
3228 * @words: number of words
3229 * @data: word(s) read from the EEPROM
3231 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3233 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3234 u16 offset, u16 words, u16 *data)
3236 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3237 struct ixgbe_hic_read_shadow_ram buffer;
3238 u32 current_word = 0;
3243 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3245 /* Take semaphore for the entire operation. */
3246 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3248 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3253 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3254 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3256 words_to_read = words;
3258 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3259 buffer.hdr.req.buf_lenh = 0;
3260 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3261 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3263 /* convert offset from words to bytes */
3264 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3265 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3267 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3268 IXGBE_HI_COMMAND_TIMEOUT);
3271 DEBUGOUT("Host interface command failed\n");
3275 for (i = 0; i < words_to_read; i++) {
3276 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3278 u32 value = IXGBE_READ_REG(hw, reg);
3280 data[current_word] = (u16)(value & 0xffff);
3283 if (i < words_to_read) {
3285 data[current_word] = (u16)(value & 0xffff);
3289 words -= words_to_read;
3293 hw->mac.ops.release_swfw_sync(hw, mask);
3298 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3299 * @hw: pointer to hardware structure
3300 * @offset: offset of word in the EEPROM to write
3301 * @data: word write to the EEPROM
3303 * Write a 16 bit word to the EEPROM using the hostif.
3305 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3309 struct ixgbe_hic_write_shadow_ram buffer;
3311 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3313 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3314 buffer.hdr.req.buf_lenh = 0;
3315 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3316 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3319 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3321 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3323 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3325 IXGBE_HI_COMMAND_TIMEOUT, false);
3331 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3332 * @hw: pointer to hardware structure
3333 * @offset: offset of word in the EEPROM to write
3334 * @data: word write to the EEPROM
3336 * Write a 16 bit word to the EEPROM using the hostif.
3338 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3341 s32 status = IXGBE_SUCCESS;
3343 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3345 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3347 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3348 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3350 DEBUGOUT("write ee hostif failed to get semaphore");
3351 status = IXGBE_ERR_SWFW_SYNC;
3358 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3359 * @hw: pointer to hardware structure
3360 * @offset: offset of word in the EEPROM to write
3361 * @words: number of words
3362 * @data: word(s) write to the EEPROM
3364 * Write a 16 bit word(s) to the EEPROM using the hostif.
3366 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3367 u16 offset, u16 words, u16 *data)
3369 s32 status = IXGBE_SUCCESS;
3372 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3374 /* Take semaphore for the entire operation. */
3375 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3376 if (status != IXGBE_SUCCESS) {
3377 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3381 for (i = 0; i < words; i++) {
3382 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3385 if (status != IXGBE_SUCCESS) {
3386 DEBUGOUT("Eeprom buffered write failed\n");
3391 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3398 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3399 * @hw: pointer to hardware structure
3400 * @ptr: pointer offset in eeprom
3401 * @size: size of section pointed by ptr, if 0 first word will be used as size
3402 * @csum: address of checksum to update
3404 * Returns error status for any failure
3406 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3407 u16 size, u16 *csum, u16 *buffer,
3412 u16 length, bufsz, i, start;
3415 bufsz = sizeof(buf) / sizeof(buf[0]);
3417 /* Read a chunk at the pointer location */
3419 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3421 DEBUGOUT("Failed to read EEPROM image\n");
3426 if (buffer_size < ptr)
3427 return IXGBE_ERR_PARAM;
3428 local_buffer = &buffer[ptr];
3436 length = local_buffer[0];
3438 /* Skip pointer section if length is invalid. */
3439 if (length == 0xFFFF || length == 0 ||
3440 (ptr + length) >= hw->eeprom.word_size)
3441 return IXGBE_SUCCESS;
3444 if (buffer && ((u32)start + (u32)length > buffer_size))
3445 return IXGBE_ERR_PARAM;
3447 for (i = start; length; i++, length--) {
3448 if (i == bufsz && !buffer) {
3454 /* Read a chunk at the pointer location */
3455 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3458 DEBUGOUT("Failed to read EEPROM image\n");
3462 *csum += local_buffer[i];
3464 return IXGBE_SUCCESS;
3468 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3469 * @hw: pointer to hardware structure
3470 * @buffer: pointer to buffer containing calculated checksum
3471 * @buffer_size: size of buffer
3473 * Returns a negative error code on error, or the 16-bit checksum
3475 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3477 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3481 u16 pointer, i, size;
3483 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3485 hw->eeprom.ops.init_params(hw);
3488 /* Read pointer area */
3489 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3490 IXGBE_EEPROM_LAST_WORD + 1,
3493 DEBUGOUT("Failed to read EEPROM image\n");
3496 local_buffer = eeprom_ptrs;
3498 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3499 return IXGBE_ERR_PARAM;
3500 local_buffer = buffer;
3504 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3505 * checksum word itself
3507 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3508 if (i != IXGBE_EEPROM_CHECKSUM)
3509 checksum += local_buffer[i];
3512 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3513 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3515 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3516 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3519 pointer = local_buffer[i];
3521 /* Skip pointer section if the pointer is invalid. */
3522 if (pointer == 0xFFFF || pointer == 0 ||
3523 pointer >= hw->eeprom.word_size)
3527 case IXGBE_PCIE_GENERAL_PTR:
3528 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3530 case IXGBE_PCIE_CONFIG0_PTR:
3531 case IXGBE_PCIE_CONFIG1_PTR:
3532 size = IXGBE_PCIE_CONFIG_SIZE;
3539 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3540 buffer, buffer_size);
3545 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3547 return (s32)checksum;
3551 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3552 * @hw: pointer to hardware structure
3554 * Returns a negative error code on error, or the 16-bit checksum
3556 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3558 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3562 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3563 * @hw: pointer to hardware structure
3564 * @checksum_val: calculated checksum
3566 * Performs checksum calculation and validates the EEPROM checksum. If the
3567 * caller does not need checksum_val, the value can be NULL.
3569 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3573 u16 read_checksum = 0;
3575 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3577 /* Read the first word from the EEPROM. If this times out or fails, do
3578 * not continue or we could be in for a very long wait while every
3581 status = hw->eeprom.ops.read(hw, 0, &checksum);
3583 DEBUGOUT("EEPROM read failed\n");
3587 status = hw->eeprom.ops.calc_checksum(hw);
3591 checksum = (u16)(status & 0xffff);
3593 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3598 /* Verify read checksum from EEPROM is the same as
3599 * calculated checksum
3601 if (read_checksum != checksum) {
3602 status = IXGBE_ERR_EEPROM_CHECKSUM;
3603 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3604 "Invalid EEPROM checksum");
3607 /* If the user cares, return the calculated checksum */
3609 *checksum_val = checksum;
3615 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3616 * @hw: pointer to hardware structure
3618 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3619 * checksum and updates the EEPROM and instructs the hardware to update
3622 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3627 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3629 /* Read the first word from the EEPROM. If this times out or fails, do
3630 * not continue or we could be in for a very long wait while every
3633 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3635 DEBUGOUT("EEPROM read failed\n");
3639 status = ixgbe_calc_eeprom_checksum_X550(hw);
3643 checksum = (u16)(status & 0xffff);
3645 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3650 status = ixgbe_update_flash_X550(hw);
3656 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3657 * @hw: pointer to hardware structure
3659 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3661 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3663 s32 status = IXGBE_SUCCESS;
3664 union ixgbe_hic_hdr2 buffer;
3666 DEBUGFUNC("ixgbe_update_flash_X550");
3668 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3669 buffer.req.buf_lenh = 0;
3670 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3671 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3673 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3675 IXGBE_HI_COMMAND_TIMEOUT, false);
3681 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3682 * @hw: pointer to hardware structure
3684 * Determines physical layer capabilities of the current configuration.
3686 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3688 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3689 u16 ext_ability = 0;
3691 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3693 hw->phy.ops.identify(hw);
3695 switch (hw->phy.type) {
3696 case ixgbe_phy_x550em_kr:
3697 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3698 if (hw->phy.nw_mng_if_sel &
3699 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3701 IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3703 } else if (hw->device_id ==
3704 IXGBE_DEV_ID_X550EM_A_KR_L) {
3706 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3711 case ixgbe_phy_x550em_xfi:
3712 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3713 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3715 case ixgbe_phy_x550em_kx4:
3716 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3717 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3719 case ixgbe_phy_x550em_ext_t:
3720 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3721 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3723 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3724 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3725 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3726 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3729 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3730 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3731 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3732 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3733 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3734 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3736 case ixgbe_phy_sgmii:
3737 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3739 case ixgbe_phy_ext_1g_t:
3740 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3746 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3747 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3749 return physical_layer;
3753 * ixgbe_get_bus_info_x550em - Set PCI bus info
3754 * @hw: pointer to hardware structure
3756 * Sets bus link width and speed to unknown because X550em is
3759 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3762 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3764 hw->bus.width = ixgbe_bus_width_unknown;
3765 hw->bus.speed = ixgbe_bus_speed_unknown;
3767 hw->mac.ops.set_lan_id(hw);
3769 return IXGBE_SUCCESS;
3773 * ixgbe_disable_rx_x550 - Disable RX unit
3775 * Enables the Rx DMA unit for x550
3777 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3779 u32 rxctrl, pfdtxgswc;
3781 struct ixgbe_hic_disable_rxen fw_cmd;
3783 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3785 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3786 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3787 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3788 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3789 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3790 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3791 hw->mac.set_lben = true;
3793 hw->mac.set_lben = false;
3796 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3797 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3798 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3799 fw_cmd.port_number = (u8)hw->bus.lan_id;
3801 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3802 sizeof(struct ixgbe_hic_disable_rxen),
3803 IXGBE_HI_COMMAND_TIMEOUT, true);
3805 /* If we fail - disable RX using register write */
3807 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3808 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3809 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3810 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3817 * ixgbe_enter_lplu_x550em - Transition to low power states
3818 * @hw: pointer to hardware structure
3820 * Configures Low Power Link Up on transition to low power states
3821 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3822 * X557 PHY immediately prior to entering LPLU.
3824 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3826 u16 an_10g_cntl_reg, autoneg_reg, speed;
3828 ixgbe_link_speed lcd_speed;
3832 /* SW LPLU not required on later HW revisions. */
3833 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3834 (IXGBE_FUSES0_REV_MASK &
3835 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3836 return IXGBE_SUCCESS;
3838 /* If blocked by MNG FW, then don't restart AN */
3839 if (ixgbe_check_reset_blocked(hw))
3840 return IXGBE_SUCCESS;
3842 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3843 if (status != IXGBE_SUCCESS)
3846 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3848 if (status != IXGBE_SUCCESS)
3851 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3852 * disabled, then force link down by entering low power mode.
3854 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3855 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3856 return ixgbe_set_copper_phy_power(hw, FALSE);
3859 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3861 if (status != IXGBE_SUCCESS)
3864 /* If no valid LCD link speed, then force link down and exit. */
3865 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3866 return ixgbe_set_copper_phy_power(hw, FALSE);
3868 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3869 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3872 if (status != IXGBE_SUCCESS)
3875 /* If no link now, speed is invalid so take link down */
3876 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3877 if (status != IXGBE_SUCCESS)
3878 return ixgbe_set_copper_phy_power(hw, false);
3880 /* clear everything but the speed bits */
3881 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3883 /* If current speed is already LCD, then exit. */
3884 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3885 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3886 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3887 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3890 /* Clear AN completed indication */
3891 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3892 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3895 if (status != IXGBE_SUCCESS)
3898 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3902 if (status != IXGBE_SUCCESS)
3905 status = hw->phy.ops.read_reg(hw,
3906 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3907 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3910 if (status != IXGBE_SUCCESS)
3913 save_autoneg = hw->phy.autoneg_advertised;
3915 /* Setup link at least common link speed */
3916 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3918 /* restore autoneg from before setting lplu speed */
3919 hw->phy.autoneg_advertised = save_autoneg;
3925 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3926 * @hw: pointer to hardware structure
3927 * @lcd_speed: pointer to lowest common link speed
3929 * Determine lowest common link speed with link partner.
3931 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3935 u16 word = hw->eeprom.ctrl_word_3;
3937 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3939 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3940 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3943 if (status != IXGBE_SUCCESS)
3946 /* If link partner advertised 1G, return 1G */
3947 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3948 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3952 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3953 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3954 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3957 /* Link partner not capable of lower speeds, return 10G */
3958 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3963 * ixgbe_setup_fc_X550em - Set up flow control
3964 * @hw: pointer to hardware structure
3966 * Called at init time to set up flow control.
3968 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3970 s32 ret_val = IXGBE_SUCCESS;
3971 u32 pause, asm_dir, reg_val;
3973 DEBUGFUNC("ixgbe_setup_fc_X550em");
3975 /* Validate the requested mode */
3976 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3977 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3978 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3979 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3983 /* 10gig parts do not have a word in the EEPROM to determine the
3984 * default flow control setting, so we explicitly set it to full.
3986 if (hw->fc.requested_mode == ixgbe_fc_default)
3987 hw->fc.requested_mode = ixgbe_fc_full;
3989 /* Determine PAUSE and ASM_DIR bits. */
3990 switch (hw->fc.requested_mode) {
3995 case ixgbe_fc_tx_pause:
3999 case ixgbe_fc_rx_pause:
4000 /* Rx Flow control is enabled and Tx Flow control is
4001 * disabled by software override. Since there really
4002 * isn't a way to advertise that we are capable of RX
4003 * Pause ONLY, we will advertise that we support both
4004 * symmetric and asymmetric Rx PAUSE, as such we fall
4005 * through to the fc_full statement. Later, we will
4006 * disable the adapter's ability to send PAUSE frames.
4013 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4014 "Flow control param set incorrectly\n");
4015 ret_val = IXGBE_ERR_CONFIG;
4019 switch (hw->device_id) {
4020 case IXGBE_DEV_ID_X550EM_X_KR:
4021 case IXGBE_DEV_ID_X550EM_A_KR:
4022 case IXGBE_DEV_ID_X550EM_A_KR_L:
4023 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4024 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4025 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4026 if (ret_val != IXGBE_SUCCESS)
4028 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4029 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4031 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4033 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4034 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4035 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4036 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4038 /* This device does not fully support AN. */
4039 hw->fc.disable_fc_autoneg = true;
4041 case IXGBE_DEV_ID_X550EM_X_XFI:
4042 hw->fc.disable_fc_autoneg = true;
4053 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4054 * @hw: pointer to hardware structure
4056 * Enable flow control according to IEEE clause 37.
4058 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4060 u32 link_s1, lp_an_page_low, an_cntl_1;
4061 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4062 ixgbe_link_speed speed;
4065 /* AN should have completed when the cable was plugged in.
4066 * Look for reasons to bail out. Bail out if:
4067 * - FC autoneg is disabled, or if
4070 if (hw->fc.disable_fc_autoneg) {
4071 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4072 "Flow control autoneg is disabled");
4076 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4078 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4082 /* Check at auto-negotiation has completed */
4083 status = hw->mac.ops.read_iosf_sb_reg(hw,
4084 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4085 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4087 if (status != IXGBE_SUCCESS ||
4088 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4089 DEBUGOUT("Auto-Negotiation did not complete\n");
4090 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4094 /* Read the 10g AN autoc and LP ability registers and resolve
4095 * local flow control settings accordingly
4097 status = hw->mac.ops.read_iosf_sb_reg(hw,
4098 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4099 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4101 if (status != IXGBE_SUCCESS) {
4102 DEBUGOUT("Auto-Negotiation did not complete\n");
4106 status = hw->mac.ops.read_iosf_sb_reg(hw,
4107 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4108 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4110 if (status != IXGBE_SUCCESS) {
4111 DEBUGOUT("Auto-Negotiation did not complete\n");
4115 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4116 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4117 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4118 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4119 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4122 if (status == IXGBE_SUCCESS) {
4123 hw->fc.fc_was_autonegged = true;
4125 hw->fc.fc_was_autonegged = false;
4126 hw->fc.current_mode = hw->fc.requested_mode;
4131 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4132 * @hw: pointer to hardware structure
4135 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4137 hw->fc.fc_was_autonegged = false;
4138 hw->fc.current_mode = hw->fc.requested_mode;
4142 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4143 * @hw: pointer to hardware structure
4145 * Enable flow control according to IEEE clause 37.
4147 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4149 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4150 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4151 ixgbe_link_speed speed;
4154 /* AN should have completed when the cable was plugged in.
4155 * Look for reasons to bail out. Bail out if:
4156 * - FC autoneg is disabled, or if
4159 if (hw->fc.disable_fc_autoneg) {
4160 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4161 "Flow control autoneg is disabled");
4165 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4167 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4171 /* Check if auto-negotiation has completed */
4172 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4173 if (status != IXGBE_SUCCESS ||
4174 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4175 DEBUGOUT("Auto-Negotiation did not complete\n");
4176 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4180 /* Negotiate the flow control */
4181 status = ixgbe_negotiate_fc(hw, info[0], info[0],
4182 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4183 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4184 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4185 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4188 if (status == IXGBE_SUCCESS) {
4189 hw->fc.fc_was_autonegged = true;
4191 hw->fc.fc_was_autonegged = false;
4192 hw->fc.current_mode = hw->fc.requested_mode;
4197 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4198 * @hw: pointer to hardware structure
4200 * Called at init time to set up flow control.
4202 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4204 s32 status = IXGBE_SUCCESS;
4207 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4209 /* Validate the requested mode */
4210 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4211 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4212 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4213 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4216 if (hw->fc.requested_mode == ixgbe_fc_default)
4217 hw->fc.requested_mode = ixgbe_fc_full;
4219 /* Set up the 1G and 10G flow control advertisement registers so the
4220 * HW will be able to do FC autoneg once the cable is plugged in. If
4221 * we link at 10G, the 1G advertisement is harmless and vice versa.
4223 status = hw->mac.ops.read_iosf_sb_reg(hw,
4224 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4225 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4227 if (status != IXGBE_SUCCESS) {
4228 DEBUGOUT("Auto-Negotiation did not complete\n");
4232 /* The possible values of fc.requested_mode are:
4233 * 0: Flow control is completely disabled
4234 * 1: Rx flow control is enabled (we can receive pause frames,
4235 * but not send pause frames).
4236 * 2: Tx flow control is enabled (we can send pause frames but
4237 * we do not support receiving pause frames).
4238 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4241 switch (hw->fc.requested_mode) {
4243 /* Flow control completely disabled by software override. */
4244 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4245 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4247 case ixgbe_fc_tx_pause:
4248 /* Tx Flow control is enabled, and Rx Flow control is
4249 * disabled by software override.
4251 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4252 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4254 case ixgbe_fc_rx_pause:
4255 /* Rx Flow control is enabled and Tx Flow control is
4256 * disabled by software override. Since there really
4257 * isn't a way to advertise that we are capable of RX
4258 * Pause ONLY, we will advertise that we support both
4259 * symmetric and asymmetric Rx PAUSE, as such we fall
4260 * through to the fc_full statement. Later, we will
4261 * disable the adapter's ability to send PAUSE frames.
4264 /* Flow control (both Rx and Tx) is enabled by SW override. */
4265 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4266 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4269 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4270 "Flow control param set incorrectly\n");
4271 return IXGBE_ERR_CONFIG;
4274 status = hw->mac.ops.write_iosf_sb_reg(hw,
4275 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4276 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4278 /* Restart auto-negotiation. */
4279 status = ixgbe_restart_an_internal_phy_x550em(hw);
4285 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4286 * @hw: pointer to hardware structure
4287 * @state: set mux if 1, clear if 0
4289 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4293 if (!hw->bus.lan_id)
4295 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4297 esdp |= IXGBE_ESDP_SDP1;
4299 esdp &= ~IXGBE_ESDP_SDP1;
4300 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4301 IXGBE_WRITE_FLUSH(hw);
4305 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4306 * @hw: pointer to hardware structure
4307 * @mask: Mask to specify which semaphore to acquire
4309 * Acquires the SWFW semaphore and sets the I2C MUX
4311 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4315 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4317 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4321 if (mask & IXGBE_GSSR_I2C_MASK)
4322 ixgbe_set_mux(hw, 1);
4324 return IXGBE_SUCCESS;
4328 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4329 * @hw: pointer to hardware structure
4330 * @mask: Mask to specify which semaphore to release
4332 * Releases the SWFW semaphore and sets the I2C MUX
4334 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4336 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4338 if (mask & IXGBE_GSSR_I2C_MASK)
4339 ixgbe_set_mux(hw, 0);
4341 ixgbe_release_swfw_sync_X540(hw, mask);
4345 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4346 * @hw: pointer to hardware structure
4347 * @mask: Mask to specify which semaphore to acquire
4349 * Acquires the SWFW semaphore and get the shared phy token as needed
4351 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4353 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4354 int retries = FW_PHY_TOKEN_RETRIES;
4355 s32 status = IXGBE_SUCCESS;
4357 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4360 status = IXGBE_SUCCESS;
4362 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4364 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4368 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4369 return IXGBE_SUCCESS;
4371 status = ixgbe_get_phy_token(hw);
4372 if (status == IXGBE_ERR_TOKEN_RETRY)
4373 DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4376 if (status == IXGBE_SUCCESS)
4377 return IXGBE_SUCCESS;
4380 ixgbe_release_swfw_sync_X540(hw, hmask);
4382 if (status != IXGBE_ERR_TOKEN_RETRY) {
4383 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4389 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4395 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4396 * @hw: pointer to hardware structure
4397 * @mask: Mask to specify which semaphore to release
4399 * Releases the SWFW semaphore and puts the shared phy token as needed
4401 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4403 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4405 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4407 if (mask & IXGBE_GSSR_TOKEN_SM)
4408 ixgbe_put_phy_token(hw);
4411 ixgbe_release_swfw_sync_X540(hw, hmask);
4415 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4416 * @hw: pointer to hardware structure
4417 * @reg_addr: 32 bit address of PHY register to read
4418 * @phy_data: Pointer to read data from PHY register
4420 * Reads a value from a specified PHY register using the SWFW lock and PHY
4421 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4424 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4425 u32 device_type, u16 *phy_data)
4428 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4430 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4432 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4433 return IXGBE_ERR_SWFW_SYNC;
4435 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4437 hw->mac.ops.release_swfw_sync(hw, mask);
4443 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4444 * @hw: pointer to hardware structure
4445 * @reg_addr: 32 bit PHY register to write
4446 * @device_type: 5 bit device type
4447 * @phy_data: Data to write to the PHY register
4449 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4450 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4452 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4453 u32 device_type, u16 phy_data)
4456 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4458 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4460 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4461 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4463 hw->mac.ops.release_swfw_sync(hw, mask);
4465 status = IXGBE_ERR_SWFW_SYNC;
4472 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4473 * @hw: pointer to hardware structure
4475 * Handle external Base T PHY interrupt. If high temperature
4476 * failure alarm then return error, else if link status change
4477 * then setup internal/external PHY link
4479 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4480 * failure alarm, else return PHY access status.
4482 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4487 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4489 if (status != IXGBE_SUCCESS)
4493 return ixgbe_setup_internal_phy(hw);
4495 return IXGBE_SUCCESS;
4499 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4500 * @hw: pointer to hardware structure
4501 * @speed: new link speed
4502 * @autoneg_wait_to_complete: true when waiting for completion is needed
4504 * Setup internal/external PHY link speed based on link speed, then set
4505 * external PHY auto advertised link speed.
4507 * Returns error status for any failure
4509 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4510 ixgbe_link_speed speed,
4511 bool autoneg_wait_to_complete)
4514 ixgbe_link_speed force_speed;
4516 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4518 /* Setup internal/external PHY link speed to iXFI (10G), unless
4519 * only 1G is auto advertised then setup KX link.
4521 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4522 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4524 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4526 /* If X552 and internal link mode is XFI, then setup XFI internal link.
4528 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4529 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4530 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4532 if (status != IXGBE_SUCCESS)
4536 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4540 * ixgbe_check_link_t_X550em - Determine link and speed status
4541 * @hw: pointer to hardware structure
4542 * @speed: pointer to link speed
4543 * @link_up: true when link is up
4544 * @link_up_wait_to_complete: bool used to wait for link up or not
4546 * Check that both the MAC and X557 external PHY have link.
4548 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4549 bool *link_up, bool link_up_wait_to_complete)
4552 u16 i, autoneg_status = 0;
4554 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4555 return IXGBE_ERR_CONFIG;
4557 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4558 link_up_wait_to_complete);
4560 /* If check link fails or MAC link is not up, then return */
4561 if (status != IXGBE_SUCCESS || !(*link_up))
4564 /* MAC link is up, so check external PHY link.
4565 * X557 PHY. Link status is latching low, and can only be used to detect
4566 * link drop, and not the current status of the link without performing
4567 * back-to-back reads.
4569 for (i = 0; i < 2; i++) {
4570 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4571 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4574 if (status != IXGBE_SUCCESS)
4578 /* If external PHY link is not up, then indicate link not up */
4579 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4582 return IXGBE_SUCCESS;
4586 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4587 * @hw: pointer to hardware structure
4589 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4593 status = ixgbe_reset_phy_generic(hw);
4595 if (status != IXGBE_SUCCESS)
4598 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4599 return ixgbe_enable_lasi_ext_t_x550em(hw);
4603 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4604 * @hw: pointer to hardware structure
4605 * @led_idx: led number to turn on
4607 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4611 DEBUGFUNC("ixgbe_led_on_t_X550em");
4613 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4614 return IXGBE_ERR_PARAM;
4616 /* To turn on the LED, set mode to ON. */
4617 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4618 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4619 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4620 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4621 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4623 /* Some designs have the LEDs wired to the MAC */
4624 return ixgbe_led_on_generic(hw, led_idx);
4628 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4629 * @hw: pointer to hardware structure
4630 * @led_idx: led number to turn off
4632 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4636 DEBUGFUNC("ixgbe_led_off_t_X550em");
4638 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4639 return IXGBE_ERR_PARAM;
4641 /* To turn on the LED, set mode to ON. */
4642 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4643 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4644 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4645 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4646 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4648 /* Some designs have the LEDs wired to the MAC */
4649 return ixgbe_led_off_generic(hw, led_idx);
4653 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4654 * @hw: pointer to the HW structure
4655 * @maj: driver version major number
4656 * @min: driver version minor number
4657 * @build: driver version build number
4658 * @sub: driver version sub build number
4659 * @len: length of driver_ver string
4660 * @driver_ver: driver string
4662 * Sends driver version number to firmware through the manageability
4663 * block. On success return IXGBE_SUCCESS
4664 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4665 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4667 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4668 u8 build, u8 sub, u16 len, const char *driver_ver)
4670 struct ixgbe_hic_drv_info2 fw_cmd;
4671 s32 ret_val = IXGBE_SUCCESS;
4674 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4676 if ((len == 0) || (driver_ver == NULL) ||
4677 (len > sizeof(fw_cmd.driver_string)))
4678 return IXGBE_ERR_INVALID_ARGUMENT;
4680 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4681 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4682 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4683 fw_cmd.port_num = (u8)hw->bus.func;
4684 fw_cmd.ver_maj = maj;
4685 fw_cmd.ver_min = min;
4686 fw_cmd.ver_build = build;
4687 fw_cmd.ver_sub = sub;
4688 fw_cmd.hdr.checksum = 0;
4689 memcpy(fw_cmd.driver_string, driver_ver, len);
4690 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4691 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4693 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4694 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4696 IXGBE_HI_COMMAND_TIMEOUT,
4698 if (ret_val != IXGBE_SUCCESS)
4701 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4702 FW_CEM_RESP_STATUS_SUCCESS)
4703 ret_val = IXGBE_SUCCESS;
4705 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;