1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_identify_phy_x550em - Get PHY type based on device id
333 * @hw: pointer to hardware structure
337 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
339 switch (hw->device_id) {
340 case IXGBE_DEV_ID_X550EM_A_SFP:
341 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
343 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
345 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
346 return ixgbe_identify_module_generic(hw);
347 case IXGBE_DEV_ID_X550EM_X_SFP:
348 /* set up for CS4227 usage */
349 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
350 ixgbe_setup_mux_ctl(hw);
351 ixgbe_check_cs4227(hw);
354 case IXGBE_DEV_ID_X550EM_A_SFP_N:
355 return ixgbe_identify_module_generic(hw);
357 case IXGBE_DEV_ID_X550EM_X_KX4:
358 hw->phy.type = ixgbe_phy_x550em_kx4;
360 case IXGBE_DEV_ID_X550EM_X_KR:
361 case IXGBE_DEV_ID_X550EM_A_KR:
362 case IXGBE_DEV_ID_X550EM_A_KR_L:
363 hw->phy.type = ixgbe_phy_x550em_kr;
365 case IXGBE_DEV_ID_X550EM_X_1G_T:
366 case IXGBE_DEV_ID_X550EM_X_10G_T:
367 case IXGBE_DEV_ID_X550EM_A_1G_T:
368 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
369 case IXGBE_DEV_ID_X550EM_A_10G_T:
370 return ixgbe_identify_phy_generic(hw);
374 return IXGBE_SUCCESS;
377 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
378 u32 device_type, u16 *phy_data)
380 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
381 return IXGBE_NOT_IMPLEMENTED;
384 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
385 u32 device_type, u16 phy_data)
387 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
388 return IXGBE_NOT_IMPLEMENTED;
392 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
393 * @hw: pointer to the hardware structure
394 * @addr: I2C bus address to read from
395 * @reg: I2C device register to read from
396 * @val: pointer to location to receive read value
398 * Returns an error code on error.
400 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
403 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
407 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
408 * @hw: pointer to the hardware structure
409 * @addr: I2C bus address to read from
410 * @reg: I2C device register to read from
411 * @val: pointer to location to receive read value
413 * Returns an error code on error.
416 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
419 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
423 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
424 * @hw: pointer to the hardware structure
425 * @addr: I2C bus address to write to
426 * @reg: I2C device register to write to
427 * @val: value to write
429 * Returns an error code on error.
431 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
432 u8 addr, u16 reg, u16 val)
434 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
438 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
439 * @hw: pointer to the hardware structure
440 * @addr: I2C bus address to write to
441 * @reg: I2C device register to write to
442 * @val: value to write
444 * Returns an error code on error.
447 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
448 u8 addr, u16 reg, u16 val)
450 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
454 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
455 * @hw: pointer to hardware structure
457 * Initialize the function pointers and for MAC type X550EM.
458 * Does not touch the hardware.
460 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
462 struct ixgbe_mac_info *mac = &hw->mac;
463 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
464 struct ixgbe_phy_info *phy = &hw->phy;
465 struct ixgbe_link_info *link = &hw->link;
468 DEBUGFUNC("ixgbe_init_ops_X550EM");
470 /* Similar to X550 so start there. */
471 ret_val = ixgbe_init_ops_X550(hw);
473 /* Since this function eventually calls
474 * ixgbe_init_ops_540 by design, we are setting
475 * the pointers to NULL explicitly here to overwrite
476 * the values being set in the x540 function.
478 /* Thermal sensor not supported in x550EM */
479 mac->ops.get_thermal_sensor_data = NULL;
480 mac->ops.init_thermal_sensor_thresh = NULL;
481 mac->thermal_sensor_enabled = false;
483 /* FCOE not supported in x550EM */
484 mac->ops.get_san_mac_addr = NULL;
485 mac->ops.set_san_mac_addr = NULL;
486 mac->ops.get_wwn_prefix = NULL;
487 mac->ops.get_fcoe_boot_status = NULL;
489 /* IPsec not supported in x550EM */
490 mac->ops.disable_sec_rx_path = NULL;
491 mac->ops.enable_sec_rx_path = NULL;
493 /* AUTOC register is not present in x550EM. */
494 mac->ops.prot_autoc_read = NULL;
495 mac->ops.prot_autoc_write = NULL;
497 /* X550EM bus type is internal*/
498 hw->bus.type = ixgbe_bus_type_internal;
499 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
501 if (hw->mac.type == ixgbe_mac_X550EM_x) {
502 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
503 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
504 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
505 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
506 link->ops.read_link = ixgbe_read_i2c_combined_generic;
507 link->ops.read_link_unlocked =
508 ixgbe_read_i2c_combined_generic_unlocked;
509 link->ops.write_link = ixgbe_write_i2c_combined_generic;
510 link->ops.write_link_unlocked =
511 ixgbe_write_i2c_combined_generic_unlocked;
512 link->addr = IXGBE_CS4227;
514 if (hw->mac.type == ixgbe_mac_X550EM_a) {
515 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
516 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
517 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
518 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
521 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
522 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
523 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
524 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
525 mac->ops.get_supported_physical_layer =
526 ixgbe_get_supported_physical_layer_X550em;
528 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
529 mac->ops.setup_fc = ixgbe_setup_fc_generic;
531 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
534 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
535 mac->ops.setup_eee = NULL;
538 phy->ops.init = ixgbe_init_phy_ops_X550em;
539 phy->ops.identify = ixgbe_identify_phy_x550em;
540 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
541 phy->ops.set_phy_power = NULL;
545 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
546 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
547 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
548 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
549 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
550 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
551 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
552 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
558 * ixgbe_dmac_config_X550
559 * @hw: pointer to hardware structure
561 * Configure DMA coalescing. If enabling dmac, dmac is activated.
562 * When disabling dmac, dmac enable dmac bit is cleared.
564 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
566 u32 reg, high_pri_tc;
568 DEBUGFUNC("ixgbe_dmac_config_X550");
570 /* Disable DMA coalescing before configuring */
571 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
572 reg &= ~IXGBE_DMACR_DMAC_EN;
573 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
575 /* Disable DMA Coalescing if the watchdog timer is 0 */
576 if (!hw->mac.dmac_config.watchdog_timer)
579 ixgbe_dmac_config_tcs_X550(hw);
581 /* Configure DMA Coalescing Control Register */
582 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
584 /* Set the watchdog timer in units of 40.96 usec */
585 reg &= ~IXGBE_DMACR_DMACWT_MASK;
586 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
588 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
589 /* If fcoe is enabled, set high priority traffic class */
590 if (hw->mac.dmac_config.fcoe_en) {
591 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
592 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
593 IXGBE_DMACR_HIGH_PRI_TC_MASK);
595 reg |= IXGBE_DMACR_EN_MNG_IND;
597 /* Enable DMA coalescing after configuration */
598 reg |= IXGBE_DMACR_DMAC_EN;
599 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
602 return IXGBE_SUCCESS;
606 * ixgbe_dmac_config_tcs_X550
607 * @hw: pointer to hardware structure
609 * Configure DMA coalescing threshold per TC. The dmac enable bit must
610 * be cleared before configuring.
612 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
614 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
616 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
618 /* Configure DMA coalescing enabled */
619 switch (hw->mac.dmac_config.link_speed) {
620 case IXGBE_LINK_SPEED_100_FULL:
621 pb_headroom = IXGBE_DMACRXT_100M;
623 case IXGBE_LINK_SPEED_1GB_FULL:
624 pb_headroom = IXGBE_DMACRXT_1G;
627 pb_headroom = IXGBE_DMACRXT_10G;
631 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
632 IXGBE_MHADD_MFS_SHIFT) / 1024);
634 /* Set the per Rx packet buffer receive threshold */
635 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
636 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
637 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
639 if (tc < hw->mac.dmac_config.num_tcs) {
641 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
642 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
643 IXGBE_RXPBSIZE_SHIFT;
645 /* Calculate receive buffer threshold in kilobytes */
646 if (rx_pb_size > pb_headroom)
647 rx_pb_size = rx_pb_size - pb_headroom;
651 /* Minimum of MFS shall be set for DMCTH */
652 reg |= (rx_pb_size > maxframe_size_kb) ?
653 rx_pb_size : maxframe_size_kb;
655 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
657 return IXGBE_SUCCESS;
661 * ixgbe_dmac_update_tcs_X550
662 * @hw: pointer to hardware structure
664 * Disables dmac, updates per TC settings, and then enables dmac.
666 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
670 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
672 /* Disable DMA coalescing before configuring */
673 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
674 reg &= ~IXGBE_DMACR_DMAC_EN;
675 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
677 ixgbe_dmac_config_tcs_X550(hw);
679 /* Enable DMA coalescing after configuration */
680 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
681 reg |= IXGBE_DMACR_DMAC_EN;
682 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
684 return IXGBE_SUCCESS;
688 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
689 * @hw: pointer to hardware structure
691 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
692 * ixgbe_hw struct in order to set up EEPROM access.
694 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
696 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
700 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
702 if (eeprom->type == ixgbe_eeprom_uninitialized) {
703 eeprom->semaphore_delay = 10;
704 eeprom->type = ixgbe_flash;
706 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
707 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
708 IXGBE_EEC_SIZE_SHIFT);
709 eeprom->word_size = 1 << (eeprom_size +
710 IXGBE_EEPROM_WORD_SIZE_SHIFT);
712 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
713 eeprom->type, eeprom->word_size);
716 return IXGBE_SUCCESS;
720 * ixgbe_setup_eee_X550 - Enable/disable EEE support
721 * @hw: pointer to the HW structure
722 * @enable_eee: boolean flag to enable EEE
724 * Enable/disable EEE based on enable_eee flag.
725 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
729 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
736 DEBUGFUNC("ixgbe_setup_eee_X550");
738 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
739 /* Enable or disable EEE per flag */
741 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
743 if (hw->mac.type == ixgbe_mac_X550) {
744 /* Advertise EEE capability */
745 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
748 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
749 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
750 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
752 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
754 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
755 /* Not supported on first revision of X550EM_x. */
756 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
757 !(IXGBE_FUSES0_REV_MASK &
758 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
759 return IXGBE_SUCCESS;
761 status = ixgbe_read_iosf_sb_reg_x550(hw,
762 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
763 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
764 if (status != IXGBE_SUCCESS)
767 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
768 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
770 /* Don't advertise FEC capability when EEE enabled. */
771 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
773 status = ixgbe_write_iosf_sb_reg_x550(hw,
774 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
775 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
776 if (status != IXGBE_SUCCESS)
780 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
782 if (hw->mac.type == ixgbe_mac_X550) {
783 /* Disable advertised EEE capability */
784 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
785 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
787 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
788 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
789 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
791 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
793 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
794 status = ixgbe_read_iosf_sb_reg_x550(hw,
795 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
796 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
797 if (status != IXGBE_SUCCESS)
800 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
801 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
803 /* Advertise FEC capability when EEE is disabled. */
804 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
806 status = ixgbe_write_iosf_sb_reg_x550(hw,
807 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
808 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
809 if (status != IXGBE_SUCCESS)
813 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
815 return IXGBE_SUCCESS;
819 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
820 * @hw: pointer to hardware structure
821 * @enable: enable or disable source address pruning
822 * @pool: Rx pool to set source address pruning for
824 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
829 /* max rx pool is 63 */
833 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
834 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
837 pfflp |= (1ULL << pool);
839 pfflp &= ~(1ULL << pool);
841 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
842 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
846 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
847 * @hw: pointer to hardware structure
848 * @enable: enable or disable switch for Ethertype anti-spoofing
849 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
852 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
855 int vf_target_reg = vf >> 3;
856 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
859 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
861 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
863 pfvfspoof |= (1 << vf_target_shift);
865 pfvfspoof &= ~(1 << vf_target_shift);
867 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
871 * ixgbe_iosf_wait - Wait for IOSF command completion
872 * @hw: pointer to hardware structure
873 * @ctrl: pointer to location to receive final IOSF control value
875 * Returns failing status on timeout
877 * Note: ctrl can be NULL if the IOSF control register value is not needed
879 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
883 /* Check every 10 usec to see if the address cycle completed.
884 * The SB IOSF BUSY bit will clear when the operation is
887 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
888 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
889 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
895 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
896 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
897 return IXGBE_ERR_PHY;
900 return IXGBE_SUCCESS;
904 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
906 * @hw: pointer to hardware structure
907 * @reg_addr: 32 bit PHY register to write
908 * @device_type: 3 bit device type
909 * @data: Data to write to the register
911 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
912 u32 device_type, u32 data)
914 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
918 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
919 if (ret != IXGBE_SUCCESS)
922 ret = ixgbe_iosf_wait(hw, NULL);
923 if (ret != IXGBE_SUCCESS)
926 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
927 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
929 /* Write IOSF control register */
930 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
932 /* Write IOSF data register */
933 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
935 ret = ixgbe_iosf_wait(hw, &command);
937 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
938 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
939 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
940 ERROR_REPORT2(IXGBE_ERROR_POLLING,
941 "Failed to write, error %x\n", error);
946 ixgbe_release_swfw_semaphore(hw, gssr);
951 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
953 * @hw: pointer to hardware structure
954 * @reg_addr: 32 bit PHY register to write
955 * @device_type: 3 bit device type
956 * @phy_data: Pointer to read data from the register
958 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
959 u32 device_type, u32 *data)
961 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
965 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
966 if (ret != IXGBE_SUCCESS)
969 ret = ixgbe_iosf_wait(hw, NULL);
970 if (ret != IXGBE_SUCCESS)
973 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
974 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
976 /* Write IOSF control register */
977 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
979 ret = ixgbe_iosf_wait(hw, &command);
981 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
982 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
983 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
984 ERROR_REPORT2(IXGBE_ERROR_POLLING,
985 "Failed to read, error %x\n", error);
989 if (ret == IXGBE_SUCCESS)
990 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
993 ixgbe_release_swfw_semaphore(hw, gssr);
998 * ixgbe_get_phy_token - Get the token for shared phy access
999 * @hw: Pointer to hardware structure
1002 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1004 struct ixgbe_hic_phy_token_req token_cmd;
1007 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1008 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1009 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1010 token_cmd.port_number = hw->bus.lan_id;
1011 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1013 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1015 IXGBE_HI_COMMAND_TIMEOUT,
1019 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1020 return IXGBE_SUCCESS;
1021 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1022 return IXGBE_ERR_FW_RESP_INVALID;
1024 return IXGBE_ERR_TOKEN_RETRY;
1028 * ixgbe_put_phy_token - Put the token for shared phy access
1029 * @hw: Pointer to hardware structure
1032 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1034 struct ixgbe_hic_phy_token_req token_cmd;
1037 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1038 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1039 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1040 token_cmd.port_number = hw->bus.lan_id;
1041 token_cmd.command_type = FW_PHY_TOKEN_REL;
1043 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1045 IXGBE_HI_COMMAND_TIMEOUT,
1049 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1050 return IXGBE_SUCCESS;
1051 return IXGBE_ERR_FW_RESP_INVALID;
1055 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1056 * of the IOSF device
1057 * @hw: pointer to hardware structure
1058 * @reg_addr: 32 bit PHY register to write
1059 * @device_type: 3 bit device type
1060 * @data: Data to write to the register
1062 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1063 u32 device_type, u32 data)
1065 struct ixgbe_hic_internal_phy_req write_cmd;
1067 UNREFERENCED_1PARAMETER(device_type);
1069 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1070 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1071 write_cmd.port_number = hw->bus.lan_id;
1072 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1073 write_cmd.address = (u16)reg_addr;
1075 write_cmd.write_data = data;
1078 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1079 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
1085 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1086 * of the IOSF device.
1087 * @hw: pointer to hardware structure
1088 * @reg_addr: 32 bit PHY register to write
1089 * @device_type: 3 bit device type
1090 * @data: Pointer to read data from the register
1092 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1093 u32 device_type, u32 *data)
1095 struct ixgbe_hic_internal_phy_req read_cmd;
1097 UNREFERENCED_1PARAMETER(device_type);
1099 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1100 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1101 read_cmd.port_number = hw->bus.lan_id;
1102 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1103 read_cmd.address = (u16)reg_addr;
1105 read_cmd.write_data = 0;
1108 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1109 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
1111 /* Extract the register value from the response. */
1112 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1118 * ixgbe_disable_mdd_X550
1119 * @hw: pointer to hardware structure
1121 * Disable malicious driver detection
1123 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1127 DEBUGFUNC("ixgbe_disable_mdd_X550");
1129 /* Disable MDD for TX DMA and interrupt */
1130 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1131 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1132 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1134 /* Disable MDD for RX and interrupt */
1135 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1136 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1137 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1141 * ixgbe_enable_mdd_X550
1142 * @hw: pointer to hardware structure
1144 * Enable malicious driver detection
1146 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1150 DEBUGFUNC("ixgbe_enable_mdd_X550");
1152 /* Enable MDD for TX DMA and interrupt */
1153 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1154 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1155 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1157 /* Enable MDD for RX and interrupt */
1158 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1159 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1160 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1164 * ixgbe_restore_mdd_vf_X550
1165 * @hw: pointer to hardware structure
1168 * Restore VF that was disabled during malicious driver detection event
1170 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1172 u32 idx, reg, num_qs, start_q, bitmask;
1174 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1176 /* Map VF to queues */
1177 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1178 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1179 case IXGBE_MRQC_VMDQRT8TCEN:
1180 num_qs = 8; /* 16 VFs / pools */
1181 bitmask = 0x000000FF;
1183 case IXGBE_MRQC_VMDQRSS32EN:
1184 case IXGBE_MRQC_VMDQRT4TCEN:
1185 num_qs = 4; /* 32 VFs / pools */
1186 bitmask = 0x0000000F;
1188 default: /* 64 VFs / pools */
1190 bitmask = 0x00000003;
1193 start_q = vf * num_qs;
1195 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1198 reg |= (bitmask << (start_q % 32));
1199 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1200 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1204 * ixgbe_mdd_event_X550
1205 * @hw: pointer to hardware structure
1206 * @vf_bitmap: vf bitmap of malicious vfs
1208 * Handle malicious driver detection event.
1210 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1213 u32 i, j, reg, q, shift, vf, idx;
1215 DEBUGFUNC("ixgbe_mdd_event_X550");
1217 /* figure out pool size for mapping to vf's */
1218 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1219 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1220 case IXGBE_MRQC_VMDQRT8TCEN:
1221 shift = 3; /* 16 VFs / pools */
1223 case IXGBE_MRQC_VMDQRSS32EN:
1224 case IXGBE_MRQC_VMDQRT4TCEN:
1225 shift = 2; /* 32 VFs / pools */
1228 shift = 1; /* 64 VFs / pools */
1232 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1233 for (i = 0; i < 4; i++) {
1234 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1235 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1240 /* Get malicious queue */
1241 for (j = 0; j < 32 && wqbr; j++) {
1243 if (!(wqbr & (1 << j)))
1246 /* Get queue from bitmask */
1249 /* Map queue to vf */
1252 /* Set vf bit in vf_bitmap */
1254 vf_bitmap[idx] |= (1 << (vf % 32));
1261 * ixgbe_get_media_type_X550em - Get media type
1262 * @hw: pointer to hardware structure
1264 * Returns the media type (fiber, copper, backplane)
1266 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1268 enum ixgbe_media_type media_type;
1270 DEBUGFUNC("ixgbe_get_media_type_X550em");
1272 /* Detect if there is a copper PHY attached. */
1273 switch (hw->device_id) {
1274 case IXGBE_DEV_ID_X550EM_X_KR:
1275 case IXGBE_DEV_ID_X550EM_X_KX4:
1276 case IXGBE_DEV_ID_X550EM_A_KR:
1277 case IXGBE_DEV_ID_X550EM_A_KR_L:
1278 media_type = ixgbe_media_type_backplane;
1280 case IXGBE_DEV_ID_X550EM_X_SFP:
1281 case IXGBE_DEV_ID_X550EM_A_SFP:
1282 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1283 case IXGBE_DEV_ID_X550EM_A_QSFP:
1284 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1285 media_type = ixgbe_media_type_fiber;
1287 case IXGBE_DEV_ID_X550EM_X_1G_T:
1288 case IXGBE_DEV_ID_X550EM_X_10G_T:
1289 case IXGBE_DEV_ID_X550EM_A_1G_T:
1290 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1291 case IXGBE_DEV_ID_X550EM_A_10G_T:
1292 media_type = ixgbe_media_type_copper;
1295 media_type = ixgbe_media_type_unknown;
1302 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1303 * @hw: pointer to hardware structure
1304 * @linear: true if SFP module is linear
1306 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1308 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1310 switch (hw->phy.sfp_type) {
1311 case ixgbe_sfp_type_not_present:
1312 return IXGBE_ERR_SFP_NOT_PRESENT;
1313 case ixgbe_sfp_type_da_cu_core0:
1314 case ixgbe_sfp_type_da_cu_core1:
1317 case ixgbe_sfp_type_srlr_core0:
1318 case ixgbe_sfp_type_srlr_core1:
1319 case ixgbe_sfp_type_da_act_lmt_core0:
1320 case ixgbe_sfp_type_da_act_lmt_core1:
1321 case ixgbe_sfp_type_1g_sx_core0:
1322 case ixgbe_sfp_type_1g_sx_core1:
1323 case ixgbe_sfp_type_1g_lx_core0:
1324 case ixgbe_sfp_type_1g_lx_core1:
1327 case ixgbe_sfp_type_unknown:
1328 case ixgbe_sfp_type_1g_cu_core0:
1329 case ixgbe_sfp_type_1g_cu_core1:
1331 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1334 return IXGBE_SUCCESS;
1338 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1339 * @hw: pointer to hardware structure
1341 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1343 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1348 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1350 status = ixgbe_identify_module_generic(hw);
1352 if (status != IXGBE_SUCCESS)
1355 /* Check if SFP module is supported */
1356 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1362 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1363 * @hw: pointer to hardware structure
1365 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1370 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1372 /* Check if SFP module is supported */
1373 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1375 if (status != IXGBE_SUCCESS)
1378 ixgbe_init_mac_link_ops_X550em(hw);
1379 hw->phy.ops.reset = NULL;
1381 return IXGBE_SUCCESS;
1385 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1386 * @hw: pointer to hardware structure
1388 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1390 struct ixgbe_mac_info *mac = &hw->mac;
1392 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1394 switch (hw->mac.ops.get_media_type(hw)) {
1395 case ixgbe_media_type_fiber:
1396 /* CS4227 does not support autoneg, so disable the laser control
1397 * functions for SFP+ fiber
1399 mac->ops.disable_tx_laser = NULL;
1400 mac->ops.enable_tx_laser = NULL;
1401 mac->ops.flap_tx_laser = NULL;
1402 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1403 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1404 mac->ops.set_rate_select_speed =
1405 ixgbe_set_soft_rate_select_speed;
1407 case ixgbe_media_type_copper:
1408 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1409 mac->ops.check_link = ixgbe_check_link_t_X550em;
1417 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1418 * @hw: pointer to hardware structure
1419 * @speed: pointer to link speed
1420 * @autoneg: true when autoneg or autotry is enabled
1422 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1423 ixgbe_link_speed *speed,
1426 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1429 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1431 /* CS4227 SFP must not enable auto-negotiation */
1434 /* Check if 1G SFP module. */
1435 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1436 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1437 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1438 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1439 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1440 return IXGBE_SUCCESS;
1443 /* Link capabilities are based on SFP */
1444 if (hw->phy.multispeed_fiber)
1445 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1446 IXGBE_LINK_SPEED_1GB_FULL;
1448 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1450 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1451 IXGBE_LINK_SPEED_1GB_FULL;
1455 return IXGBE_SUCCESS;
1459 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1460 * @hw: pointer to hardware structure
1461 * @lsc: pointer to boolean flag which indicates whether external Base T
1462 * PHY interrupt is lsc
1464 * Determime if external Base T PHY interrupt cause is high temperature
1465 * failure alarm or link status change.
1467 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1468 * failure alarm, else return PHY access status.
1470 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1477 /* Vendor alarm triggered */
1478 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1479 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1482 if (status != IXGBE_SUCCESS ||
1483 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1486 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1487 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1488 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1491 if (status != IXGBE_SUCCESS ||
1492 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1493 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1496 /* Global alarm triggered */
1497 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1498 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1501 if (status != IXGBE_SUCCESS)
1504 /* If high temperature failure, then return over temp error and exit */
1505 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1506 /* power down the PHY in case the PHY FW didn't already */
1507 ixgbe_set_copper_phy_power(hw, false);
1508 return IXGBE_ERR_OVERTEMP;
1509 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1510 /* device fault alarm triggered */
1511 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1512 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1515 if (status != IXGBE_SUCCESS)
1518 /* if device fault was due to high temp alarm handle and exit */
1519 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1520 /* power down the PHY in case the PHY FW didn't */
1521 ixgbe_set_copper_phy_power(hw, false);
1522 return IXGBE_ERR_OVERTEMP;
1526 /* Vendor alarm 2 triggered */
1527 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1528 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1530 if (status != IXGBE_SUCCESS ||
1531 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1534 /* link connect/disconnect event occurred */
1535 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1536 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1538 if (status != IXGBE_SUCCESS)
1542 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1545 return IXGBE_SUCCESS;
1549 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1550 * @hw: pointer to hardware structure
1552 * Enable link status change and temperature failure alarm for the external
1555 * Returns PHY access status
1557 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1563 /* Clear interrupt flags */
1564 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1566 /* Enable link status change alarm */
1567 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1568 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1570 if (status != IXGBE_SUCCESS)
1573 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1575 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1576 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1578 if (status != IXGBE_SUCCESS)
1581 /* Enable high temperature failure and global fault alarms */
1582 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1583 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1586 if (status != IXGBE_SUCCESS)
1589 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1590 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1592 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1593 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1596 if (status != IXGBE_SUCCESS)
1599 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1600 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1601 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1604 if (status != IXGBE_SUCCESS)
1607 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1608 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1610 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1611 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1614 if (status != IXGBE_SUCCESS)
1617 /* Enable chip-wide vendor alarm */
1618 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1619 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1622 if (status != IXGBE_SUCCESS)
1625 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1627 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1628 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1635 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1636 * @hw: pointer to hardware structure
1637 * @speed: link speed
1639 * Configures the integrated KR PHY.
1641 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1642 ixgbe_link_speed speed)
1647 status = ixgbe_read_iosf_sb_reg_x550(hw,
1648 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1649 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1653 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1654 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1655 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1657 /* Advertise 10G support. */
1658 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1659 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1661 /* Advertise 1G support. */
1662 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1663 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1665 /* Restart auto-negotiation. */
1666 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1667 status = ixgbe_write_iosf_sb_reg_x550(hw,
1668 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1675 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1676 * @hw: pointer to hardware structure
1678 * Initialize any function pointers that were not able to be
1679 * set during init_shared_code because the PHY/SFP type was
1680 * not known. Perform the SFP init if necessary.
1682 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1684 struct ixgbe_phy_info *phy = &hw->phy;
1687 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1689 hw->mac.ops.set_lan_id(hw);
1691 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1692 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1693 ixgbe_setup_mux_ctl(hw);
1695 /* Save NW management interface connected on board. This is used
1696 * to determine internal PHY mode.
1698 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1699 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1702 /* Identify the PHY or SFP module */
1703 ret_val = phy->ops.identify(hw);
1704 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1707 /* Setup function pointers based on detected hardware */
1708 ixgbe_init_mac_link_ops_X550em(hw);
1709 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1710 phy->ops.reset = NULL;
1712 /* Set functions pointers based on phy type */
1713 switch (hw->phy.type) {
1714 case ixgbe_phy_x550em_kx4:
1715 phy->ops.setup_link = NULL;
1716 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1717 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1719 case ixgbe_phy_x550em_kr:
1720 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1721 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1722 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1724 case ixgbe_phy_x550em_ext_t:
1725 /* Save NW management interface connected on board. This is used
1726 * to determine internal PHY mode
1728 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1730 /* If internal link mode is XFI, then setup iXFI internal link,
1731 * else setup KR now.
1733 phy->ops.setup_internal_link =
1734 ixgbe_setup_internal_phy_t_x550em;
1736 /* setup SW LPLU only for first revision of X550EM_x */
1737 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1738 !(IXGBE_FUSES0_REV_MASK &
1739 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1740 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1742 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1743 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1752 * ixgbe_set_mdio_speed - Set MDIO clock speed
1753 * @hw: pointer to hardware structure
1755 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1759 switch (hw->device_id) {
1760 case IXGBE_DEV_ID_X550EM_X_10G_T:
1761 case IXGBE_DEV_ID_X550EM_A_1G_T:
1762 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1763 case IXGBE_DEV_ID_X550EM_A_10G_T:
1764 case IXGBE_DEV_ID_X550EM_A_SFP:
1765 case IXGBE_DEV_ID_X550EM_A_QSFP:
1766 /* Config MDIO clock speed before the first MDIO PHY access */
1767 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1768 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1769 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1777 * ixgbe_reset_hw_X550em - Perform hardware reset
1778 * @hw: pointer to hardware structure
1780 * Resets the hardware by resetting the transmit and receive units, masks
1781 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1784 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1786 ixgbe_link_speed link_speed;
1790 bool link_up = false;
1792 DEBUGFUNC("ixgbe_reset_hw_X550em");
1794 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1795 status = hw->mac.ops.stop_adapter(hw);
1796 if (status != IXGBE_SUCCESS)
1799 /* flush pending Tx transactions */
1800 ixgbe_clear_tx_pending(hw);
1802 ixgbe_set_mdio_speed(hw);
1804 /* PHY ops must be identified and initialized prior to reset */
1805 status = hw->phy.ops.init(hw);
1807 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1810 /* start the external PHY */
1811 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1812 status = ixgbe_init_ext_t_x550em(hw);
1817 /* Setup SFP module if there is one present. */
1818 if (hw->phy.sfp_setup_needed) {
1819 status = hw->mac.ops.setup_sfp(hw);
1820 hw->phy.sfp_setup_needed = false;
1823 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1827 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1828 hw->phy.ops.reset(hw);
1831 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1832 * If link reset is used when link is up, it might reset the PHY when
1833 * mng is using it. If link is down or the flag to force full link
1834 * reset is set, then perform link reset.
1836 ctrl = IXGBE_CTRL_LNK_RST;
1837 if (!hw->force_full_reset) {
1838 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1840 ctrl = IXGBE_CTRL_RST;
1843 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1844 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1845 IXGBE_WRITE_FLUSH(hw);
1847 /* Poll for reset bit to self-clear meaning reset is complete */
1848 for (i = 0; i < 10; i++) {
1850 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1851 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1855 if (ctrl & IXGBE_CTRL_RST_MASK) {
1856 status = IXGBE_ERR_RESET_FAILED;
1857 DEBUGOUT("Reset polling failed to complete.\n");
1862 /* Double resets are required for recovery from certain error
1863 * conditions. Between resets, it is necessary to stall to
1864 * allow time for any pending HW events to complete.
1866 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1867 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1871 /* Store the permanent mac address */
1872 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1874 /* Store MAC address from RAR0, clear receive address registers, and
1875 * clear the multicast table. Also reset num_rar_entries to 128,
1876 * since we modify this value when programming the SAN MAC address.
1878 hw->mac.num_rar_entries = 128;
1879 hw->mac.ops.init_rx_addrs(hw);
1881 ixgbe_set_mdio_speed(hw);
1883 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1884 ixgbe_setup_mux_ctl(hw);
1890 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1891 * @hw: pointer to hardware structure
1893 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1898 status = hw->phy.ops.read_reg(hw,
1899 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1900 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1903 if (status != IXGBE_SUCCESS)
1906 /* If PHY FW reset completed bit is set then this is the first
1907 * SW instance after a power on so the PHY FW must be un-stalled.
1909 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1910 status = hw->phy.ops.read_reg(hw,
1911 IXGBE_MDIO_GLOBAL_RES_PR_10,
1912 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1915 if (status != IXGBE_SUCCESS)
1918 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1920 status = hw->phy.ops.write_reg(hw,
1921 IXGBE_MDIO_GLOBAL_RES_PR_10,
1922 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1925 if (status != IXGBE_SUCCESS)
1933 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1934 * @hw: pointer to hardware structure
1936 * Configures the integrated KR PHY.
1938 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1940 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1944 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1945 * @hw: pointer to hardware structure
1947 * Configure the external PHY and the integrated KR PHY for SFP support.
1949 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1950 ixgbe_link_speed speed,
1951 bool autoneg_wait_to_complete)
1954 u16 reg_slice, reg_val;
1955 bool setup_linear = false;
1956 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1958 /* Check if SFP module is supported and linear */
1959 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1961 /* If no SFP module present, then return success. Return success since
1962 * there is no reason to configure CS4227 and SFP not present error is
1963 * not excepted in the setup MAC link flow.
1965 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1966 return IXGBE_SUCCESS;
1968 if (ret_val != IXGBE_SUCCESS)
1971 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1972 /* Configure CS4227 LINE side to 10G SR. */
1973 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1974 (hw->bus.lan_id << 12);
1975 reg_val = IXGBE_CS4227_SPEED_10G;
1976 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1979 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1980 (hw->bus.lan_id << 12);
1981 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1982 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1985 /* Configure CS4227 for HOST connection rate then type. */
1986 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1987 (hw->bus.lan_id << 12);
1988 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1989 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1990 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1993 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1994 (hw->bus.lan_id << 12);
1996 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1998 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1999 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2002 /* Setup XFI internal link. */
2003 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2005 /* Configure internal PHY for KR/KX. */
2006 ixgbe_setup_kr_speed_x550em(hw, speed);
2008 /* Configure CS4227 LINE side to proper mode. */
2009 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2010 (hw->bus.lan_id << 12);
2012 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2014 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2015 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2022 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2023 * @hw: pointer to hardware structure
2025 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2027 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2032 /* Disable training protocol FSM. */
2033 status = ixgbe_read_iosf_sb_reg_x550(hw,
2034 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2036 if (status != IXGBE_SUCCESS)
2038 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2039 status = ixgbe_write_iosf_sb_reg_x550(hw,
2040 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2041 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2042 if (status != IXGBE_SUCCESS)
2045 /* Disable Flex from training TXFFE. */
2046 status = ixgbe_read_iosf_sb_reg_x550(hw,
2047 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2048 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2049 if (status != IXGBE_SUCCESS)
2051 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2052 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2053 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2054 status = ixgbe_write_iosf_sb_reg_x550(hw,
2055 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2056 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2057 if (status != IXGBE_SUCCESS)
2059 status = ixgbe_read_iosf_sb_reg_x550(hw,
2060 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2061 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2062 if (status != IXGBE_SUCCESS)
2064 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2065 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2066 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2067 status = ixgbe_write_iosf_sb_reg_x550(hw,
2068 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2069 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2070 if (status != IXGBE_SUCCESS)
2073 /* Enable override for coefficients. */
2074 status = ixgbe_read_iosf_sb_reg_x550(hw,
2075 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2076 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2077 if (status != IXGBE_SUCCESS)
2079 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2080 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2081 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2082 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2083 status = ixgbe_write_iosf_sb_reg_x550(hw,
2084 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2085 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2090 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2091 * @hw: pointer to hardware structure
2092 * @speed: the link speed to force
2094 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2095 * internal and external PHY at a specific speed, without autonegotiation.
2097 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2102 /* Disable AN and force speed to 10G Serial. */
2103 status = ixgbe_read_iosf_sb_reg_x550(hw,
2104 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2105 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2106 if (status != IXGBE_SUCCESS)
2109 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2110 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2112 /* Select forced link speed for internal PHY. */
2114 case IXGBE_LINK_SPEED_10GB_FULL:
2115 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2117 case IXGBE_LINK_SPEED_1GB_FULL:
2118 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2121 /* Other link speeds are not supported by internal KR PHY. */
2122 return IXGBE_ERR_LINK_SETUP;
2125 status = ixgbe_write_iosf_sb_reg_x550(hw,
2126 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2127 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2128 if (status != IXGBE_SUCCESS)
2131 /* Additional configuration needed for x550em_x */
2132 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2133 status = ixgbe_setup_ixfi_x550em_x(hw);
2134 if (status != IXGBE_SUCCESS)
2138 /* Toggle port SW reset by AN reset. */
2139 status = ixgbe_read_iosf_sb_reg_x550(hw,
2140 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2141 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2142 if (status != IXGBE_SUCCESS)
2144 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2145 status = ixgbe_write_iosf_sb_reg_x550(hw,
2146 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2147 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2153 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2154 * @hw: address of hardware structure
2155 * @link_up: address of boolean to indicate link status
2157 * Returns error code if unable to get link status.
2159 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2166 /* read this twice back to back to indicate current status */
2167 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2168 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2170 if (ret != IXGBE_SUCCESS)
2173 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2174 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2176 if (ret != IXGBE_SUCCESS)
2179 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2181 return IXGBE_SUCCESS;
2185 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2186 * @hw: point to hardware structure
2188 * Configures the link between the integrated KR PHY and the external X557 PHY
2189 * The driver will call this function when it gets a link status change
2190 * interrupt from the X557 PHY. This function configures the link speed
2191 * between the PHYs to match the link speed of the BASE-T link.
2193 * A return of a non-zero value indicates an error, and the base driver should
2194 * not report link up.
2196 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2198 ixgbe_link_speed force_speed;
2203 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2204 return IXGBE_ERR_CONFIG;
2206 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2207 /* If link is down, there is no setup necessary so return */
2208 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2209 if (status != IXGBE_SUCCESS)
2213 return IXGBE_SUCCESS;
2215 status = hw->phy.ops.read_reg(hw,
2216 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2217 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2219 if (status != IXGBE_SUCCESS)
2222 /* If link is still down - no setup is required so return */
2223 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2224 if (status != IXGBE_SUCCESS)
2227 return IXGBE_SUCCESS;
2229 /* clear everything but the speed and duplex bits */
2230 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2233 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2234 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2236 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2237 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2240 /* Internal PHY does not support anything else */
2241 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2244 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2246 speed = IXGBE_LINK_SPEED_10GB_FULL |
2247 IXGBE_LINK_SPEED_1GB_FULL;
2248 return ixgbe_setup_kr_speed_x550em(hw, speed);
2253 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2254 * @hw: pointer to hardware structure
2256 * Configures the integrated KR PHY to use internal loopback mode.
2258 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2263 /* Disable AN and force speed to 10G Serial. */
2264 status = ixgbe_read_iosf_sb_reg_x550(hw,
2265 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2266 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2267 if (status != IXGBE_SUCCESS)
2269 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2270 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2271 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2272 status = ixgbe_write_iosf_sb_reg_x550(hw,
2273 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2274 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2275 if (status != IXGBE_SUCCESS)
2278 /* Set near-end loopback clocks. */
2279 status = ixgbe_read_iosf_sb_reg_x550(hw,
2280 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2281 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2282 if (status != IXGBE_SUCCESS)
2284 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2285 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2286 status = ixgbe_write_iosf_sb_reg_x550(hw,
2287 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2288 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2289 if (status != IXGBE_SUCCESS)
2292 /* Set loopback enable. */
2293 status = ixgbe_read_iosf_sb_reg_x550(hw,
2294 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2295 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2296 if (status != IXGBE_SUCCESS)
2298 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2299 status = ixgbe_write_iosf_sb_reg_x550(hw,
2300 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2301 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2302 if (status != IXGBE_SUCCESS)
2305 /* Training bypass. */
2306 status = ixgbe_read_iosf_sb_reg_x550(hw,
2307 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2308 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2309 if (status != IXGBE_SUCCESS)
2311 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2312 status = ixgbe_write_iosf_sb_reg_x550(hw,
2313 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2314 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2320 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2321 * assuming that the semaphore is already obtained.
2322 * @hw: pointer to hardware structure
2323 * @offset: offset of word in the EEPROM to read
2324 * @data: word read from the EEPROM
2326 * Reads a 16 bit word from the EEPROM using the hostif.
2328 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2332 struct ixgbe_hic_read_shadow_ram buffer;
2334 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2335 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2336 buffer.hdr.req.buf_lenh = 0;
2337 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2338 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2340 /* convert offset from words to bytes */
2341 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2343 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2345 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2347 IXGBE_HI_COMMAND_TIMEOUT, false);
2352 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2353 FW_NVM_DATA_OFFSET);
2359 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2360 * @hw: pointer to hardware structure
2361 * @offset: offset of word in the EEPROM to read
2362 * @data: word read from the EEPROM
2364 * Reads a 16 bit word from the EEPROM using the hostif.
2366 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2369 s32 status = IXGBE_SUCCESS;
2371 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2373 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2375 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2376 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2378 status = IXGBE_ERR_SWFW_SYNC;
2385 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2386 * @hw: pointer to hardware structure
2387 * @offset: offset of word in the EEPROM to read
2388 * @words: number of words
2389 * @data: word(s) read from the EEPROM
2391 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2393 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2394 u16 offset, u16 words, u16 *data)
2396 struct ixgbe_hic_read_shadow_ram buffer;
2397 u32 current_word = 0;
2402 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2404 /* Take semaphore for the entire operation. */
2405 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2407 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2411 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2412 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2414 words_to_read = words;
2416 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2417 buffer.hdr.req.buf_lenh = 0;
2418 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2419 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2421 /* convert offset from words to bytes */
2422 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2423 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2425 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2427 IXGBE_HI_COMMAND_TIMEOUT,
2431 DEBUGOUT("Host interface command failed\n");
2435 for (i = 0; i < words_to_read; i++) {
2436 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2438 u32 value = IXGBE_READ_REG(hw, reg);
2440 data[current_word] = (u16)(value & 0xffff);
2443 if (i < words_to_read) {
2445 data[current_word] = (u16)(value & 0xffff);
2449 words -= words_to_read;
2453 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2458 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2459 * @hw: pointer to hardware structure
2460 * @offset: offset of word in the EEPROM to write
2461 * @data: word write to the EEPROM
2463 * Write a 16 bit word to the EEPROM using the hostif.
2465 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2469 struct ixgbe_hic_write_shadow_ram buffer;
2471 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2473 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2474 buffer.hdr.req.buf_lenh = 0;
2475 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2476 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2479 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2481 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2483 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2485 IXGBE_HI_COMMAND_TIMEOUT, false);
2491 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2492 * @hw: pointer to hardware structure
2493 * @offset: offset of word in the EEPROM to write
2494 * @data: word write to the EEPROM
2496 * Write a 16 bit word to the EEPROM using the hostif.
2498 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2501 s32 status = IXGBE_SUCCESS;
2503 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2505 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2507 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2508 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2510 DEBUGOUT("write ee hostif failed to get semaphore");
2511 status = IXGBE_ERR_SWFW_SYNC;
2518 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2519 * @hw: pointer to hardware structure
2520 * @offset: offset of word in the EEPROM to write
2521 * @words: number of words
2522 * @data: word(s) write to the EEPROM
2524 * Write a 16 bit word(s) to the EEPROM using the hostif.
2526 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2527 u16 offset, u16 words, u16 *data)
2529 s32 status = IXGBE_SUCCESS;
2532 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2534 /* Take semaphore for the entire operation. */
2535 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2536 if (status != IXGBE_SUCCESS) {
2537 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2541 for (i = 0; i < words; i++) {
2542 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2545 if (status != IXGBE_SUCCESS) {
2546 DEBUGOUT("Eeprom buffered write failed\n");
2551 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2558 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2559 * @hw: pointer to hardware structure
2560 * @ptr: pointer offset in eeprom
2561 * @size: size of section pointed by ptr, if 0 first word will be used as size
2562 * @csum: address of checksum to update
2564 * Returns error status for any failure
2566 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2567 u16 size, u16 *csum, u16 *buffer,
2572 u16 length, bufsz, i, start;
2575 bufsz = sizeof(buf) / sizeof(buf[0]);
2577 /* Read a chunk at the pointer location */
2579 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2581 DEBUGOUT("Failed to read EEPROM image\n");
2586 if (buffer_size < ptr)
2587 return IXGBE_ERR_PARAM;
2588 local_buffer = &buffer[ptr];
2596 length = local_buffer[0];
2598 /* Skip pointer section if length is invalid. */
2599 if (length == 0xFFFF || length == 0 ||
2600 (ptr + length) >= hw->eeprom.word_size)
2601 return IXGBE_SUCCESS;
2604 if (buffer && ((u32)start + (u32)length > buffer_size))
2605 return IXGBE_ERR_PARAM;
2607 for (i = start; length; i++, length--) {
2608 if (i == bufsz && !buffer) {
2614 /* Read a chunk at the pointer location */
2615 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2618 DEBUGOUT("Failed to read EEPROM image\n");
2622 *csum += local_buffer[i];
2624 return IXGBE_SUCCESS;
2628 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2629 * @hw: pointer to hardware structure
2630 * @buffer: pointer to buffer containing calculated checksum
2631 * @buffer_size: size of buffer
2633 * Returns a negative error code on error, or the 16-bit checksum
2635 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2637 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2641 u16 pointer, i, size;
2643 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2645 hw->eeprom.ops.init_params(hw);
2648 /* Read pointer area */
2649 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2650 IXGBE_EEPROM_LAST_WORD + 1,
2653 DEBUGOUT("Failed to read EEPROM image\n");
2656 local_buffer = eeprom_ptrs;
2658 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2659 return IXGBE_ERR_PARAM;
2660 local_buffer = buffer;
2664 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2665 * checksum word itself
2667 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2668 if (i != IXGBE_EEPROM_CHECKSUM)
2669 checksum += local_buffer[i];
2672 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2673 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2675 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2676 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2679 pointer = local_buffer[i];
2681 /* Skip pointer section if the pointer is invalid. */
2682 if (pointer == 0xFFFF || pointer == 0 ||
2683 pointer >= hw->eeprom.word_size)
2687 case IXGBE_PCIE_GENERAL_PTR:
2688 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2690 case IXGBE_PCIE_CONFIG0_PTR:
2691 case IXGBE_PCIE_CONFIG1_PTR:
2692 size = IXGBE_PCIE_CONFIG_SIZE;
2699 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2700 buffer, buffer_size);
2705 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2707 return (s32)checksum;
2711 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2712 * @hw: pointer to hardware structure
2714 * Returns a negative error code on error, or the 16-bit checksum
2716 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2718 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2722 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2723 * @hw: pointer to hardware structure
2724 * @checksum_val: calculated checksum
2726 * Performs checksum calculation and validates the EEPROM checksum. If the
2727 * caller does not need checksum_val, the value can be NULL.
2729 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2733 u16 read_checksum = 0;
2735 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2737 /* Read the first word from the EEPROM. If this times out or fails, do
2738 * not continue or we could be in for a very long wait while every
2741 status = hw->eeprom.ops.read(hw, 0, &checksum);
2743 DEBUGOUT("EEPROM read failed\n");
2747 status = hw->eeprom.ops.calc_checksum(hw);
2751 checksum = (u16)(status & 0xffff);
2753 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2758 /* Verify read checksum from EEPROM is the same as
2759 * calculated checksum
2761 if (read_checksum != checksum) {
2762 status = IXGBE_ERR_EEPROM_CHECKSUM;
2763 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2764 "Invalid EEPROM checksum");
2767 /* If the user cares, return the calculated checksum */
2769 *checksum_val = checksum;
2775 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2776 * @hw: pointer to hardware structure
2778 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2779 * checksum and updates the EEPROM and instructs the hardware to update
2782 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2787 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2789 /* Read the first word from the EEPROM. If this times out or fails, do
2790 * not continue or we could be in for a very long wait while every
2793 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2795 DEBUGOUT("EEPROM read failed\n");
2799 status = ixgbe_calc_eeprom_checksum_X550(hw);
2803 checksum = (u16)(status & 0xffff);
2805 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2810 status = ixgbe_update_flash_X550(hw);
2816 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2817 * @hw: pointer to hardware structure
2819 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2821 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2823 s32 status = IXGBE_SUCCESS;
2824 union ixgbe_hic_hdr2 buffer;
2826 DEBUGFUNC("ixgbe_update_flash_X550");
2828 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2829 buffer.req.buf_lenh = 0;
2830 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2831 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2833 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2835 IXGBE_HI_COMMAND_TIMEOUT, false);
2841 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2842 * @hw: pointer to hardware structure
2844 * Determines physical layer capabilities of the current configuration.
2846 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2848 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2849 u16 ext_ability = 0;
2851 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2853 hw->phy.ops.identify(hw);
2855 switch (hw->phy.type) {
2856 case ixgbe_phy_x550em_kr:
2857 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2858 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2860 case ixgbe_phy_x550em_kx4:
2861 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2862 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2864 case ixgbe_phy_x550em_ext_t:
2865 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2866 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2868 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2869 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2870 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2871 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2877 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2878 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2880 return physical_layer;
2884 * ixgbe_get_bus_info_x550em - Set PCI bus info
2885 * @hw: pointer to hardware structure
2887 * Sets bus link width and speed to unknown because X550em is
2890 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2893 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2895 hw->bus.width = ixgbe_bus_width_unknown;
2896 hw->bus.speed = ixgbe_bus_speed_unknown;
2898 hw->mac.ops.set_lan_id(hw);
2900 return IXGBE_SUCCESS;
2904 * ixgbe_disable_rx_x550 - Disable RX unit
2906 * Enables the Rx DMA unit for x550
2908 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2910 u32 rxctrl, pfdtxgswc;
2912 struct ixgbe_hic_disable_rxen fw_cmd;
2914 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2916 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2917 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2918 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2919 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2920 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2921 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2922 hw->mac.set_lben = true;
2924 hw->mac.set_lben = false;
2927 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2928 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2929 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2930 fw_cmd.port_number = (u8)hw->bus.lan_id;
2932 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2933 sizeof(struct ixgbe_hic_disable_rxen),
2934 IXGBE_HI_COMMAND_TIMEOUT, true);
2936 /* If we fail - disable RX using register write */
2938 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2939 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2940 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2941 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2948 * ixgbe_enter_lplu_x550em - Transition to low power states
2949 * @hw: pointer to hardware structure
2951 * Configures Low Power Link Up on transition to low power states
2952 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2953 * X557 PHY immediately prior to entering LPLU.
2955 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2957 u16 an_10g_cntl_reg, autoneg_reg, speed;
2959 ixgbe_link_speed lcd_speed;
2963 /* SW LPLU not required on later HW revisions. */
2964 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2965 (IXGBE_FUSES0_REV_MASK &
2966 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2967 return IXGBE_SUCCESS;
2969 /* If blocked by MNG FW, then don't restart AN */
2970 if (ixgbe_check_reset_blocked(hw))
2971 return IXGBE_SUCCESS;
2973 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2974 if (status != IXGBE_SUCCESS)
2977 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2979 if (status != IXGBE_SUCCESS)
2982 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2983 * disabled, then force link down by entering low power mode.
2985 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2986 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2987 return ixgbe_set_copper_phy_power(hw, FALSE);
2990 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2992 if (status != IXGBE_SUCCESS)
2995 /* If no valid LCD link speed, then force link down and exit. */
2996 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2997 return ixgbe_set_copper_phy_power(hw, FALSE);
2999 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3000 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3003 if (status != IXGBE_SUCCESS)
3006 /* If no link now, speed is invalid so take link down */
3007 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3008 if (status != IXGBE_SUCCESS)
3009 return ixgbe_set_copper_phy_power(hw, false);
3011 /* clear everything but the speed bits */
3012 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3014 /* If current speed is already LCD, then exit. */
3015 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3016 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3017 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3018 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3021 /* Clear AN completed indication */
3022 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3023 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3026 if (status != IXGBE_SUCCESS)
3029 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3033 if (status != IXGBE_SUCCESS)
3036 status = hw->phy.ops.read_reg(hw,
3037 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3038 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3041 if (status != IXGBE_SUCCESS)
3044 save_autoneg = hw->phy.autoneg_advertised;
3046 /* Setup link at least common link speed */
3047 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3049 /* restore autoneg from before setting lplu speed */
3050 hw->phy.autoneg_advertised = save_autoneg;
3056 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3057 * @hw: pointer to hardware structure
3058 * @lcd_speed: pointer to lowest common link speed
3060 * Determine lowest common link speed with link partner.
3062 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3066 u16 word = hw->eeprom.ctrl_word_3;
3068 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3070 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3074 if (status != IXGBE_SUCCESS)
3077 /* If link partner advertised 1G, return 1G */
3078 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3079 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3083 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3084 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3085 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3088 /* Link partner not capable of lower speeds, return 10G */
3089 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3094 * ixgbe_setup_fc_X550em - Set up flow control
3095 * @hw: pointer to hardware structure
3097 * Called at init time to set up flow control.
3099 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3101 s32 ret_val = IXGBE_SUCCESS;
3102 u32 pause, asm_dir, reg_val;
3104 DEBUGFUNC("ixgbe_setup_fc_X550em");
3106 /* Validate the requested mode */
3107 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3108 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3109 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3110 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3114 /* 10gig parts do not have a word in the EEPROM to determine the
3115 * default flow control setting, so we explicitly set it to full.
3117 if (hw->fc.requested_mode == ixgbe_fc_default)
3118 hw->fc.requested_mode = ixgbe_fc_full;
3120 /* Determine PAUSE and ASM_DIR bits. */
3121 switch (hw->fc.requested_mode) {
3126 case ixgbe_fc_tx_pause:
3130 case ixgbe_fc_rx_pause:
3131 /* Rx Flow control is enabled and Tx Flow control is
3132 * disabled by software override. Since there really
3133 * isn't a way to advertise that we are capable of RX
3134 * Pause ONLY, we will advertise that we support both
3135 * symmetric and asymmetric Rx PAUSE, as such we fall
3136 * through to the fc_full statement. Later, we will
3137 * disable the adapter's ability to send PAUSE frames.
3144 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3145 "Flow control param set incorrectly\n");
3146 ret_val = IXGBE_ERR_CONFIG;
3150 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3151 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3152 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3153 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3154 if (ret_val != IXGBE_SUCCESS)
3156 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3157 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3159 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3161 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3162 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3163 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3164 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3166 /* This device does not fully support AN. */
3167 hw->fc.disable_fc_autoneg = true;
3175 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3176 * @hw: pointer to hardware structure
3177 * @state: set mux if 1, clear if 0
3179 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3183 if (!hw->bus.lan_id)
3185 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3187 esdp |= IXGBE_ESDP_SDP1;
3189 esdp &= ~IXGBE_ESDP_SDP1;
3190 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3191 IXGBE_WRITE_FLUSH(hw);
3195 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3196 * @hw: pointer to hardware structure
3197 * @mask: Mask to specify which semaphore to acquire
3199 * Acquires the SWFW semaphore and sets the I2C MUX
3201 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3205 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3207 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3211 if (mask & IXGBE_GSSR_I2C_MASK)
3212 ixgbe_set_mux(hw, 1);
3214 return IXGBE_SUCCESS;
3218 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3219 * @hw: pointer to hardware structure
3220 * @mask: Mask to specify which semaphore to release
3222 * Releases the SWFW semaphore and sets the I2C MUX
3224 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3226 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3228 if (mask & IXGBE_GSSR_I2C_MASK)
3229 ixgbe_set_mux(hw, 0);
3231 ixgbe_release_swfw_sync_X540(hw, mask);
3235 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3236 * @hw: pointer to hardware structure
3237 * @mask: Mask to specify which semaphore to acquire
3239 * Acquires the SWFW semaphore and get the shared phy token as needed
3241 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3243 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3244 int retries = FW_PHY_TOKEN_RETRIES;
3245 s32 status = IXGBE_SUCCESS;
3247 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3251 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3254 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3256 status = ixgbe_get_phy_token(hw);
3257 if (status != IXGBE_ERR_TOKEN_RETRY)
3260 ixgbe_release_swfw_sync_X540(hw, hmask);
3261 msec_delay(FW_PHY_TOKEN_DELAY);
3268 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3269 * @hw: pointer to hardware structure
3270 * @mask: Mask to specify which semaphore to release
3272 * Releases the SWFW semaphore and puts the shared phy token as needed
3274 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3276 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3278 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3280 if (mask & IXGBE_GSSR_TOKEN_SM)
3281 ixgbe_put_phy_token(hw);
3284 ixgbe_release_swfw_sync_X540(hw, hmask);
3288 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3289 * @hw: pointer to hardware structure
3291 * Handle external Base T PHY interrupt. If high temperature
3292 * failure alarm then return error, else if link status change
3293 * then setup internal/external PHY link
3295 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3296 * failure alarm, else return PHY access status.
3298 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3303 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3305 if (status != IXGBE_SUCCESS)
3309 return ixgbe_setup_internal_phy(hw);
3311 return IXGBE_SUCCESS;
3315 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3316 * @hw: pointer to hardware structure
3317 * @speed: new link speed
3318 * @autoneg_wait_to_complete: true when waiting for completion is needed
3320 * Setup internal/external PHY link speed based on link speed, then set
3321 * external PHY auto advertised link speed.
3323 * Returns error status for any failure
3325 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3326 ixgbe_link_speed speed,
3327 bool autoneg_wait_to_complete)
3330 ixgbe_link_speed force_speed;
3332 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3334 /* Setup internal/external PHY link speed to iXFI (10G), unless
3335 * only 1G is auto advertised then setup KX link.
3337 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3338 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3340 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3342 /* If internal link mode is XFI, then setup XFI internal link. */
3343 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3344 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3346 if (status != IXGBE_SUCCESS)
3350 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3354 * ixgbe_check_link_t_X550em - Determine link and speed status
3355 * @hw: pointer to hardware structure
3356 * @speed: pointer to link speed
3357 * @link_up: true when link is up
3358 * @link_up_wait_to_complete: bool used to wait for link up or not
3360 * Check that both the MAC and X557 external PHY have link.
3362 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3363 bool *link_up, bool link_up_wait_to_complete)
3368 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3369 return IXGBE_ERR_CONFIG;
3371 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3372 link_up_wait_to_complete);
3374 /* If check link fails or MAC link is not up, then return */
3375 if (status != IXGBE_SUCCESS || !(*link_up))
3378 /* MAC link is up, so check external PHY link.
3379 * Read this twice back to back to indicate current status.
3381 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3382 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3385 if (status != IXGBE_SUCCESS)
3388 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3389 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3392 if (status != IXGBE_SUCCESS)
3395 /* If external PHY link is not up, then indicate link not up */
3396 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3399 return IXGBE_SUCCESS;
3403 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3404 * @hw: pointer to hardware structure
3406 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3410 status = ixgbe_reset_phy_generic(hw);
3412 if (status != IXGBE_SUCCESS)
3415 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3416 return ixgbe_enable_lasi_ext_t_x550em(hw);
3420 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3421 * @hw: pointer to hardware structure
3422 * @led_idx: led number to turn on
3424 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3428 DEBUGFUNC("ixgbe_led_on_t_X550em");
3430 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3431 return IXGBE_ERR_PARAM;
3433 /* To turn on the LED, set mode to ON. */
3434 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3435 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3436 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3437 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3438 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3440 return IXGBE_SUCCESS;
3444 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3445 * @hw: pointer to hardware structure
3446 * @led_idx: led number to turn off
3448 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3452 DEBUGFUNC("ixgbe_led_off_t_X550em");
3454 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3455 return IXGBE_ERR_PARAM;
3457 /* To turn on the LED, set mode to ON. */
3458 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3459 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3460 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3461 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3462 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3464 return IXGBE_SUCCESS;