4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
159 struct rte_eth_dev_info *dev_info);
160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
165 uint16_t vlan_id, int on);
166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
168 uint16_t queue, bool on);
169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_pfc_conf *pfc_conf);
185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
193 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
194 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
195 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
196 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
198 static void ixgbe_dev_interrupt_delayed_handler(void *param);
199 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
200 uint32_t index, uint32_t pool);
201 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
202 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
203 struct ether_addr *mac_addr);
204 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
206 /* For Virtual Function support */
207 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
208 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
209 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
210 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
211 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
218 struct rte_eth_stats *stats);
219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
221 uint16_t vlan_id, int on);
222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
223 uint16_t queue, int on);
224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
226 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
228 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
230 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
232 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
233 uint8_t queue, uint8_t msix_vector);
234 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
236 /* For Eth VMDQ APIs support */
237 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
238 ether_addr* mac_addr,uint8_t on);
239 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
240 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
241 uint16_t rx_mask, uint8_t on);
242 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
243 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
244 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
245 uint64_t pool_mask,uint8_t vlan_on);
246 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
247 struct rte_eth_mirror_conf *mirror_conf,
248 uint8_t rule_id, uint8_t on);
249 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
251 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
253 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
255 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
256 uint8_t queue, uint8_t msix_vector);
257 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
259 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
260 uint16_t queue_idx, uint16_t tx_rate);
261 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
262 uint16_t tx_rate, uint64_t q_msk);
264 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
265 struct ether_addr *mac_addr,
266 uint32_t index, uint32_t pool);
267 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
268 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr);
270 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
271 struct rte_eth_syn_filter *filter,
273 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
274 struct rte_eth_syn_filter *filter);
275 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
276 enum rte_filter_op filter_op,
278 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
279 struct ixgbe_5tuple_filter *filter);
280 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
281 struct ixgbe_5tuple_filter *filter);
282 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
283 struct rte_eth_ntuple_filter *filter,
285 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
286 enum rte_filter_op filter_op,
288 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
289 struct rte_eth_ntuple_filter *filter);
290 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
291 struct rte_eth_ethertype_filter *filter,
293 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
294 enum rte_filter_op filter_op,
296 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
297 struct rte_eth_ethertype_filter *filter);
298 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
299 enum rte_filter_type filter_type,
300 enum rte_filter_op filter_op,
302 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
304 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
305 struct ether_addr *mc_addr_set,
306 uint32_t nb_mc_addr);
308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
310 struct rte_dev_reg_info *regs);
311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
313 struct rte_dev_eeprom_info *eeprom);
314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
315 struct rte_dev_eeprom_info *eeprom);
317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
319 struct rte_dev_reg_info *regs);
321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
324 struct timespec *timestamp,
326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
327 struct timespec *timestamp);
330 * Define VF Stats MACRO for Non "cleared on read" register
332 #define UPDATE_VF_STAT(reg, last, cur) \
334 uint32_t latest = IXGBE_READ_REG(hw, reg); \
335 cur += (latest - last) & UINT_MAX; \
339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
341 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
342 u64 new_msb = IXGBE_READ_REG(hw, msb); \
343 u64 latest = ((new_msb << 32) | new_lsb); \
344 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
348 #define IXGBE_SET_HWSTRIP(h, q) do{\
349 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
350 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
351 (h)->bitmap[idx] |= 1 << bit;\
354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
355 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
356 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
357 (h)->bitmap[idx] &= ~(1 << bit);\
360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
361 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
362 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
363 (r) = (h)->bitmap[idx] >> bit & 1;\
367 * The set of PCI devices this driver supports
369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
372 #include "rte_pci_dev_ids.h"
374 { .vendor_id = 0, /* sentinel */ },
379 * The set of PCI devices this driver supports (for 82599 VF)
381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
384 #include "rte_pci_dev_ids.h"
385 { .vendor_id = 0, /* sentinel */ },
389 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
390 .dev_configure = ixgbe_dev_configure,
391 .dev_start = ixgbe_dev_start,
392 .dev_stop = ixgbe_dev_stop,
393 .dev_set_link_up = ixgbe_dev_set_link_up,
394 .dev_set_link_down = ixgbe_dev_set_link_down,
395 .dev_close = ixgbe_dev_close,
396 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
397 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
398 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
399 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
400 .link_update = ixgbe_dev_link_update,
401 .stats_get = ixgbe_dev_stats_get,
402 .xstats_get = ixgbe_dev_xstats_get,
403 .stats_reset = ixgbe_dev_stats_reset,
404 .xstats_reset = ixgbe_dev_xstats_reset,
405 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
406 .dev_infos_get = ixgbe_dev_info_get,
407 .mtu_set = ixgbe_dev_mtu_set,
408 .vlan_filter_set = ixgbe_vlan_filter_set,
409 .vlan_tpid_set = ixgbe_vlan_tpid_set,
410 .vlan_offload_set = ixgbe_vlan_offload_set,
411 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
412 .rx_queue_start = ixgbe_dev_rx_queue_start,
413 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
414 .tx_queue_start = ixgbe_dev_tx_queue_start,
415 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
416 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
417 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
418 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
419 .rx_queue_release = ixgbe_dev_rx_queue_release,
420 .rx_queue_count = ixgbe_dev_rx_queue_count,
421 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
422 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
423 .tx_queue_release = ixgbe_dev_tx_queue_release,
424 .dev_led_on = ixgbe_dev_led_on,
425 .dev_led_off = ixgbe_dev_led_off,
426 .flow_ctrl_get = ixgbe_flow_ctrl_get,
427 .flow_ctrl_set = ixgbe_flow_ctrl_set,
428 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
429 .mac_addr_add = ixgbe_add_rar,
430 .mac_addr_remove = ixgbe_remove_rar,
431 .mac_addr_set = ixgbe_set_default_mac_addr,
432 .uc_hash_table_set = ixgbe_uc_hash_table_set,
433 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
434 .mirror_rule_set = ixgbe_mirror_rule_set,
435 .mirror_rule_reset = ixgbe_mirror_rule_reset,
436 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
437 .set_vf_rx = ixgbe_set_pool_rx,
438 .set_vf_tx = ixgbe_set_pool_tx,
439 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
440 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
441 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
442 .reta_update = ixgbe_dev_rss_reta_update,
443 .reta_query = ixgbe_dev_rss_reta_query,
444 #ifdef RTE_NIC_BYPASS
445 .bypass_init = ixgbe_bypass_init,
446 .bypass_state_set = ixgbe_bypass_state_store,
447 .bypass_state_show = ixgbe_bypass_state_show,
448 .bypass_event_set = ixgbe_bypass_event_store,
449 .bypass_event_show = ixgbe_bypass_event_show,
450 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
451 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
452 .bypass_ver_show = ixgbe_bypass_ver_show,
453 .bypass_wd_reset = ixgbe_bypass_wd_reset,
454 #endif /* RTE_NIC_BYPASS */
455 .rss_hash_update = ixgbe_dev_rss_hash_update,
456 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
457 .filter_ctrl = ixgbe_dev_filter_ctrl,
458 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
459 .timesync_enable = ixgbe_timesync_enable,
460 .timesync_disable = ixgbe_timesync_disable,
461 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
462 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
463 .get_reg_length = ixgbe_get_reg_length,
464 .get_reg = ixgbe_get_regs,
465 .get_eeprom_length = ixgbe_get_eeprom_length,
466 .get_eeprom = ixgbe_get_eeprom,
467 .set_eeprom = ixgbe_set_eeprom,
471 * dev_ops for virtual function, bare necessities for basic vf
472 * operation have been implemented
474 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
475 .dev_configure = ixgbevf_dev_configure,
476 .dev_start = ixgbevf_dev_start,
477 .dev_stop = ixgbevf_dev_stop,
478 .link_update = ixgbe_dev_link_update,
479 .stats_get = ixgbevf_dev_stats_get,
480 .stats_reset = ixgbevf_dev_stats_reset,
481 .dev_close = ixgbevf_dev_close,
482 .dev_infos_get = ixgbevf_dev_info_get,
483 .mtu_set = ixgbevf_dev_set_mtu,
484 .vlan_filter_set = ixgbevf_vlan_filter_set,
485 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
486 .vlan_offload_set = ixgbevf_vlan_offload_set,
487 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
488 .rx_queue_release = ixgbe_dev_rx_queue_release,
489 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
490 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
491 .tx_queue_release = ixgbe_dev_tx_queue_release,
492 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
493 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
494 .mac_addr_add = ixgbevf_add_mac_addr,
495 .mac_addr_remove = ixgbevf_remove_mac_addr,
496 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
497 .mac_addr_set = ixgbevf_set_default_mac_addr,
498 .get_reg_length = ixgbevf_get_reg_length,
499 .get_reg = ixgbevf_get_regs,
502 /* store statistics names and its offset in stats structure */
503 struct rte_ixgbe_xstats_name_off {
504 char name[RTE_ETH_XSTATS_NAME_SIZE];
508 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
509 {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
510 {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
511 {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
512 {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
513 {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
514 {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
515 {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
516 {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
517 {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
518 {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
519 {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
520 {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
521 {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
522 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
523 {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
524 {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
525 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
526 {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
527 {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
528 {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
529 {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
530 {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
531 {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
534 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) / \
535 sizeof(rte_ixgbe_stats_strings[0]))
538 * Atomically reads the link status information from global
539 * structure rte_eth_dev.
542 * - Pointer to the structure rte_eth_dev to read from.
543 * - Pointer to the buffer to be saved with the link status.
546 * - On success, zero.
547 * - On failure, negative value.
550 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
551 struct rte_eth_link *link)
553 struct rte_eth_link *dst = link;
554 struct rte_eth_link *src = &(dev->data->dev_link);
556 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
557 *(uint64_t *)src) == 0)
564 * Atomically writes the link status information into global
565 * structure rte_eth_dev.
568 * - Pointer to the structure rte_eth_dev to read from.
569 * - Pointer to the buffer to be saved with the link status.
572 * - On success, zero.
573 * - On failure, negative value.
576 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
577 struct rte_eth_link *link)
579 struct rte_eth_link *dst = &(dev->data->dev_link);
580 struct rte_eth_link *src = link;
582 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
583 *(uint64_t *)src) == 0)
590 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
593 ixgbe_is_sfp(struct ixgbe_hw *hw)
595 switch (hw->phy.type) {
596 case ixgbe_phy_sfp_avago:
597 case ixgbe_phy_sfp_ftl:
598 case ixgbe_phy_sfp_intel:
599 case ixgbe_phy_sfp_unknown:
600 case ixgbe_phy_sfp_passive_tyco:
601 case ixgbe_phy_sfp_passive_unknown:
608 static inline int32_t
609 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
614 status = ixgbe_reset_hw(hw);
616 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
617 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
618 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
619 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
620 IXGBE_WRITE_FLUSH(hw);
626 ixgbe_enable_intr(struct rte_eth_dev *dev)
628 struct ixgbe_interrupt *intr =
629 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
630 struct ixgbe_hw *hw =
631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
634 IXGBE_WRITE_FLUSH(hw);
638 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
641 ixgbe_disable_intr(struct ixgbe_hw *hw)
643 PMD_INIT_FUNC_TRACE();
645 if (hw->mac.type == ixgbe_mac_82598EB) {
646 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
648 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
649 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
650 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
652 IXGBE_WRITE_FLUSH(hw);
656 * This function resets queue statistics mapping registers.
657 * From Niantic datasheet, Initialization of Statistics section:
658 * "...if software requires the queue counters, the RQSMR and TQSM registers
659 * must be re-programmed following a device reset.
662 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
666 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
667 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
668 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
674 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
679 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
680 #define NB_QMAP_FIELDS_PER_QSM_REG 4
681 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
683 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
684 struct ixgbe_stat_mapping_registers *stat_mappings =
685 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
686 uint32_t qsmr_mask = 0;
687 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
691 if ((hw->mac.type != ixgbe_mac_82599EB) &&
692 (hw->mac.type != ixgbe_mac_X540) &&
693 (hw->mac.type != ixgbe_mac_X550) &&
694 (hw->mac.type != ixgbe_mac_X550EM_x))
697 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
698 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
701 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
702 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
703 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
706 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
708 /* Now clear any previous stat_idx set */
709 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
711 stat_mappings->tqsm[n] &= ~clearing_mask;
713 stat_mappings->rqsmr[n] &= ~clearing_mask;
715 q_map = (uint32_t)stat_idx;
716 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
717 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
719 stat_mappings->tqsm[n] |= qsmr_mask;
721 stat_mappings->rqsmr[n] |= qsmr_mask;
723 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
724 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
726 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
727 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
729 /* Now write the mapping in the appropriate register */
731 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
732 stat_mappings->rqsmr[n], n);
733 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
736 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
737 stat_mappings->tqsm[n], n);
738 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
744 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
746 struct ixgbe_stat_mapping_registers *stat_mappings =
747 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751 /* write whatever was in stat mapping table to the NIC */
752 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
754 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
757 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
762 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
765 struct ixgbe_dcb_tc_config *tc;
766 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
768 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
769 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
770 for (i = 0; i < dcb_max_tc; i++) {
771 tc = &dcb_config->tc_config[i];
772 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
773 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
774 (uint8_t)(100/dcb_max_tc + (i & 1));
775 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
776 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
777 (uint8_t)(100/dcb_max_tc + (i & 1));
778 tc->pfc = ixgbe_dcb_pfc_disabled;
781 /* Initialize default user to priority mapping, UPx->TC0 */
782 tc = &dcb_config->tc_config[0];
783 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
784 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
785 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
786 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
787 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
789 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
790 dcb_config->pfc_mode_enable = false;
791 dcb_config->vt_mode = true;
792 dcb_config->round_robin_enable = false;
793 /* support all DCB capabilities in 82599 */
794 dcb_config->support.capabilities = 0xFF;
796 /*we only support 4 Tcs for X540, X550 */
797 if (hw->mac.type == ixgbe_mac_X540 ||
798 hw->mac.type == ixgbe_mac_X550 ||
799 hw->mac.type == ixgbe_mac_X550EM_x) {
800 dcb_config->num_tcs.pg_tcs = 4;
801 dcb_config->num_tcs.pfc_tcs = 4;
806 * Ensure that all locks are released before first NVM or PHY access
809 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
814 * Phy lock should not fail in this early stage. If this is the case,
815 * it is due to an improper exit of the application.
816 * So force the release of the faulty lock. Release of common lock
817 * is done automatically by swfw_sync function.
819 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
820 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
821 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
823 ixgbe_release_swfw_semaphore(hw, mask);
826 * These ones are more tricky since they are common to all ports; but
827 * swfw_sync retries last long enough (1s) to be almost sure that if
828 * lock can not be taken it is due to an improper lock of the
831 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
832 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
833 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
835 ixgbe_release_swfw_semaphore(hw, mask);
839 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
840 * It returns 0 on success.
843 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
845 struct rte_pci_device *pci_dev;
846 struct ixgbe_hw *hw =
847 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
848 struct ixgbe_vfta * shadow_vfta =
849 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
850 struct ixgbe_hwstrip *hwstrip =
851 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
852 struct ixgbe_dcb_config *dcb_config =
853 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
854 struct ixgbe_filter_info *filter_info =
855 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
860 PMD_INIT_FUNC_TRACE();
862 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
863 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
864 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
867 * For secondary processes, we don't initialise any further as primary
868 * has already done this work. Only check we don't need a different
869 * RX and TX function.
871 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
872 struct ixgbe_tx_queue *txq;
873 /* TX queue function in primary, set by last queue initialized
874 * Tx queue may not initialized by primary process */
875 if (eth_dev->data->tx_queues) {
876 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
877 ixgbe_set_tx_function(eth_dev, txq);
879 /* Use default TX function if we get here */
880 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
881 "Using default TX function.");
884 ixgbe_set_rx_function(eth_dev);
888 pci_dev = eth_dev->pci_dev;
890 /* Vendor and Device ID need to be set before init of shared code */
891 hw->device_id = pci_dev->id.device_id;
892 hw->vendor_id = pci_dev->id.vendor_id;
893 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
894 hw->allow_unsupported_sfp = 1;
896 /* Initialize the shared code (base driver) */
897 #ifdef RTE_NIC_BYPASS
898 diag = ixgbe_bypass_init_shared_code(hw);
900 diag = ixgbe_init_shared_code(hw);
901 #endif /* RTE_NIC_BYPASS */
903 if (diag != IXGBE_SUCCESS) {
904 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
908 /* pick up the PCI bus settings for reporting later */
909 ixgbe_get_bus_info(hw);
911 /* Unlock any pending hardware semaphore */
912 ixgbe_swfw_lock_reset(hw);
914 /* Initialize DCB configuration*/
915 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
916 ixgbe_dcb_init(hw,dcb_config);
917 /* Get Hardware Flow Control setting */
918 hw->fc.requested_mode = ixgbe_fc_full;
919 hw->fc.current_mode = ixgbe_fc_full;
920 hw->fc.pause_time = IXGBE_FC_PAUSE;
921 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
922 hw->fc.low_water[i] = IXGBE_FC_LO;
923 hw->fc.high_water[i] = IXGBE_FC_HI;
927 /* Make sure we have a good EEPROM before we read from it */
928 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
929 if (diag != IXGBE_SUCCESS) {
930 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
934 #ifdef RTE_NIC_BYPASS
935 diag = ixgbe_bypass_init_hw(hw);
937 diag = ixgbe_init_hw(hw);
938 #endif /* RTE_NIC_BYPASS */
941 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
942 * is called too soon after the kernel driver unbinding/binding occurs.
943 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
944 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
945 * also called. See ixgbe_identify_phy_82599(). The reason for the
946 * failure is not known, and only occuts when virtualisation features
947 * are disabled in the bios. A delay of 100ms was found to be enough by
948 * trial-and-error, and is doubled to be safe.
950 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
952 diag = ixgbe_init_hw(hw);
955 if (diag == IXGBE_ERR_EEPROM_VERSION) {
956 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
957 "LOM. Please be aware there may be issues associated "
958 "with your hardware.");
959 PMD_INIT_LOG(ERR, "If you are experiencing problems "
960 "please contact your Intel or hardware representative "
961 "who provided you with this hardware.");
962 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
963 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
965 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
969 /* Reset the hw statistics */
970 ixgbe_dev_stats_reset(eth_dev);
972 /* disable interrupt */
973 ixgbe_disable_intr(hw);
975 /* reset mappings for queue statistics hw counters*/
976 ixgbe_reset_qstat_mappings(hw);
978 /* Allocate memory for storing MAC addresses */
979 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
980 hw->mac.num_rar_entries, 0);
981 if (eth_dev->data->mac_addrs == NULL) {
983 "Failed to allocate %u bytes needed to store "
985 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
988 /* Copy the permanent MAC address */
989 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
990 ð_dev->data->mac_addrs[0]);
992 /* Allocate memory for storing hash filter MAC addresses */
993 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
994 IXGBE_VMDQ_NUM_UC_MAC, 0);
995 if (eth_dev->data->hash_mac_addrs == NULL) {
997 "Failed to allocate %d bytes needed to store MAC addresses",
998 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1002 /* initialize the vfta */
1003 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1005 /* initialize the hw strip bitmap*/
1006 memset(hwstrip, 0, sizeof(*hwstrip));
1008 /* initialize PF if max_vfs not zero */
1009 ixgbe_pf_host_init(eth_dev);
1011 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1012 /* let hardware know driver is loaded */
1013 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1014 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1015 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1016 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1017 IXGBE_WRITE_FLUSH(hw);
1019 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1020 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1021 (int) hw->mac.type, (int) hw->phy.type,
1022 (int) hw->phy.sfp_type);
1024 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1025 (int) hw->mac.type, (int) hw->phy.type);
1027 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1028 eth_dev->data->port_id, pci_dev->id.vendor_id,
1029 pci_dev->id.device_id);
1031 /* enable support intr */
1032 ixgbe_enable_intr(eth_dev);
1034 /* initialize 5tuple filter list */
1035 TAILQ_INIT(&filter_info->fivetuple_list);
1036 memset(filter_info->fivetuple_mask, 0,
1037 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1043 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1045 struct rte_pci_device *pci_dev;
1046 struct ixgbe_hw *hw;
1048 PMD_INIT_FUNC_TRACE();
1050 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1053 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1054 pci_dev = eth_dev->pci_dev;
1056 if (hw->adapter_stopped == 0)
1057 ixgbe_dev_close(eth_dev);
1059 eth_dev->dev_ops = NULL;
1060 eth_dev->rx_pkt_burst = NULL;
1061 eth_dev->tx_pkt_burst = NULL;
1063 /* Unlock any pending hardware semaphore */
1064 ixgbe_swfw_lock_reset(hw);
1066 /* disable uio intr before callback unregister */
1067 rte_intr_disable(&(pci_dev->intr_handle));
1068 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1069 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1071 /* uninitialize PF if max_vfs not zero */
1072 ixgbe_pf_host_uninit(eth_dev);
1074 rte_free(eth_dev->data->mac_addrs);
1075 eth_dev->data->mac_addrs = NULL;
1077 rte_free(eth_dev->data->hash_mac_addrs);
1078 eth_dev->data->hash_mac_addrs = NULL;
1084 * Negotiate mailbox API version with the PF.
1085 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1086 * Then we try to negotiate starting with the most recent one.
1087 * If all negotiation attempts fail, then we will proceed with
1088 * the default one (ixgbe_mbox_api_10).
1091 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1095 /* start with highest supported, proceed down */
1096 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1102 i != RTE_DIM(sup_ver) &&
1103 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1109 generate_random_mac_addr(struct ether_addr *mac_addr)
1113 /* Set Organizationally Unique Identifier (OUI) prefix. */
1114 mac_addr->addr_bytes[0] = 0x00;
1115 mac_addr->addr_bytes[1] = 0x09;
1116 mac_addr->addr_bytes[2] = 0xC0;
1117 /* Force indication of locally assigned MAC address. */
1118 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1119 /* Generate the last 3 bytes of the MAC address with a random number. */
1120 random = rte_rand();
1121 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1125 * Virtual Function device init
1128 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1132 struct rte_pci_device *pci_dev;
1133 struct ixgbe_hw *hw =
1134 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1135 struct ixgbe_vfta * shadow_vfta =
1136 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1137 struct ixgbe_hwstrip *hwstrip =
1138 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1139 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1141 PMD_INIT_FUNC_TRACE();
1143 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147 /* for secondary processes, we don't initialise any further as primary
1148 * has already done this work. Only check we don't need a different
1150 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1151 if (eth_dev->data->scattered_rx)
1152 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1156 pci_dev = eth_dev->pci_dev;
1158 hw->device_id = pci_dev->id.device_id;
1159 hw->vendor_id = pci_dev->id.vendor_id;
1160 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1162 /* initialize the vfta */
1163 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1165 /* initialize the hw strip bitmap*/
1166 memset(hwstrip, 0, sizeof(*hwstrip));
1168 /* Initialize the shared code (base driver) */
1169 diag = ixgbe_init_shared_code(hw);
1170 if (diag != IXGBE_SUCCESS) {
1171 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1175 /* init_mailbox_params */
1176 hw->mbx.ops.init_params(hw);
1178 /* Reset the hw statistics */
1179 ixgbevf_dev_stats_reset(eth_dev);
1181 /* Disable the interrupts for VF */
1182 ixgbevf_intr_disable(hw);
1184 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1185 diag = hw->mac.ops.reset_hw(hw);
1188 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1189 * the underlying PF driver has not assigned a MAC address to the VF.
1190 * In this case, assign a random MAC address.
1192 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1193 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1197 /* negotiate mailbox API version to use with the PF. */
1198 ixgbevf_negotiate_api(hw);
1200 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1201 ixgbevf_get_queues(hw, &tcs, &tc);
1203 /* Allocate memory for storing MAC addresses */
1204 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1205 hw->mac.num_rar_entries, 0);
1206 if (eth_dev->data->mac_addrs == NULL) {
1208 "Failed to allocate %u bytes needed to store "
1210 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1214 /* Generate a random MAC address, if none was assigned by PF. */
1215 if (is_zero_ether_addr(perm_addr)) {
1216 generate_random_mac_addr(perm_addr);
1217 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1219 rte_free(eth_dev->data->mac_addrs);
1220 eth_dev->data->mac_addrs = NULL;
1223 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1224 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1225 "%02x:%02x:%02x:%02x:%02x:%02x",
1226 perm_addr->addr_bytes[0],
1227 perm_addr->addr_bytes[1],
1228 perm_addr->addr_bytes[2],
1229 perm_addr->addr_bytes[3],
1230 perm_addr->addr_bytes[4],
1231 perm_addr->addr_bytes[5]);
1234 /* Copy the permanent MAC address */
1235 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1237 /* reset the hardware with the new settings */
1238 diag = hw->mac.ops.start_hw(hw);
1244 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1248 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1249 eth_dev->data->port_id, pci_dev->id.vendor_id,
1250 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1255 /* Virtual Function device uninit */
1258 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1260 struct ixgbe_hw *hw;
1263 PMD_INIT_FUNC_TRACE();
1265 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1268 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1270 if (hw->adapter_stopped == 0)
1271 ixgbevf_dev_close(eth_dev);
1273 eth_dev->dev_ops = NULL;
1274 eth_dev->rx_pkt_burst = NULL;
1275 eth_dev->tx_pkt_burst = NULL;
1277 /* Disable the interrupts for VF */
1278 ixgbevf_intr_disable(hw);
1280 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1281 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1282 eth_dev->data->rx_queues[i] = NULL;
1284 eth_dev->data->nb_rx_queues = 0;
1286 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1287 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1288 eth_dev->data->tx_queues[i] = NULL;
1290 eth_dev->data->nb_tx_queues = 0;
1292 rte_free(eth_dev->data->mac_addrs);
1293 eth_dev->data->mac_addrs = NULL;
1298 static struct eth_driver rte_ixgbe_pmd = {
1300 .name = "rte_ixgbe_pmd",
1301 .id_table = pci_id_ixgbe_map,
1302 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1303 RTE_PCI_DRV_DETACHABLE,
1305 .eth_dev_init = eth_ixgbe_dev_init,
1306 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1307 .dev_private_size = sizeof(struct ixgbe_adapter),
1311 * virtual function driver struct
1313 static struct eth_driver rte_ixgbevf_pmd = {
1315 .name = "rte_ixgbevf_pmd",
1316 .id_table = pci_id_ixgbevf_map,
1317 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1319 .eth_dev_init = eth_ixgbevf_dev_init,
1320 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1321 .dev_private_size = sizeof(struct ixgbe_adapter),
1325 * Driver initialization routine.
1326 * Invoked once at EAL init time.
1327 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1330 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1332 PMD_INIT_FUNC_TRACE();
1334 rte_eth_driver_register(&rte_ixgbe_pmd);
1339 * VF Driver initialization routine.
1340 * Invoked one at EAL init time.
1341 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1344 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1346 PMD_INIT_FUNC_TRACE();
1348 rte_eth_driver_register(&rte_ixgbevf_pmd);
1353 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1355 struct ixgbe_hw *hw =
1356 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 struct ixgbe_vfta * shadow_vfta =
1358 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1363 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1364 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1365 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1370 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1372 /* update local VFTA copy */
1373 shadow_vfta->vfta[vid_idx] = vfta;
1379 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1382 ixgbe_vlan_hw_strip_enable(dev, queue);
1384 ixgbe_vlan_hw_strip_disable(dev, queue);
1388 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1390 struct ixgbe_hw *hw =
1391 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393 /* Only the high 16-bits is valid */
1394 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1398 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1400 struct ixgbe_hw *hw =
1401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404 PMD_INIT_FUNC_TRACE();
1406 /* Filter Table Disable */
1407 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1408 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1410 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1414 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1416 struct ixgbe_hw *hw =
1417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 struct ixgbe_vfta * shadow_vfta =
1419 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1423 PMD_INIT_FUNC_TRACE();
1425 /* Filter Table Enable */
1426 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1427 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1428 vlnctrl |= IXGBE_VLNCTRL_VFE;
1430 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1432 /* write whatever is in local vfta copy */
1433 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1434 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1438 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1440 struct ixgbe_hwstrip *hwstrip =
1441 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1443 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1447 IXGBE_SET_HWSTRIP(hwstrip, queue);
1449 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1453 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1455 struct ixgbe_hw *hw =
1456 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459 PMD_INIT_FUNC_TRACE();
1461 if (hw->mac.type == ixgbe_mac_82598EB) {
1462 /* No queue level support */
1463 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1467 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1468 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1469 ctrl &= ~IXGBE_RXDCTL_VME;
1470 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1472 /* record those setting for HW strip per queue */
1473 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1477 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1479 struct ixgbe_hw *hw =
1480 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483 PMD_INIT_FUNC_TRACE();
1485 if (hw->mac.type == ixgbe_mac_82598EB) {
1486 /* No queue level supported */
1487 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1491 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1492 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1493 ctrl |= IXGBE_RXDCTL_VME;
1494 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1496 /* record those setting for HW strip per queue */
1497 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1501 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1503 struct ixgbe_hw *hw =
1504 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508 PMD_INIT_FUNC_TRACE();
1510 if (hw->mac.type == ixgbe_mac_82598EB) {
1511 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1512 ctrl &= ~IXGBE_VLNCTRL_VME;
1513 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1516 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1517 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1518 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1519 ctrl &= ~IXGBE_RXDCTL_VME;
1520 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1522 /* record those setting for HW strip per queue */
1523 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1529 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1531 struct ixgbe_hw *hw =
1532 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536 PMD_INIT_FUNC_TRACE();
1538 if (hw->mac.type == ixgbe_mac_82598EB) {
1539 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1540 ctrl |= IXGBE_VLNCTRL_VME;
1541 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1544 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1545 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1546 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1547 ctrl |= IXGBE_RXDCTL_VME;
1548 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1550 /* record those setting for HW strip per queue */
1551 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1557 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1559 struct ixgbe_hw *hw =
1560 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563 PMD_INIT_FUNC_TRACE();
1565 /* DMATXCTRL: Geric Double VLAN Disable */
1566 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1567 ctrl &= ~IXGBE_DMATXCTL_GDV;
1568 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1570 /* CTRL_EXT: Global Double VLAN Disable */
1571 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1572 ctrl &= ~IXGBE_EXTENDED_VLAN;
1573 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1578 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1580 struct ixgbe_hw *hw =
1581 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584 PMD_INIT_FUNC_TRACE();
1586 /* DMATXCTRL: Geric Double VLAN Enable */
1587 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1588 ctrl |= IXGBE_DMATXCTL_GDV;
1589 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1591 /* CTRL_EXT: Global Double VLAN Enable */
1592 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1593 ctrl |= IXGBE_EXTENDED_VLAN;
1594 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1597 * VET EXT field in the EXVET register = 0x8100 by default
1598 * So no need to change. Same to VT field of DMATXCTL register
1603 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1605 if(mask & ETH_VLAN_STRIP_MASK){
1606 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1607 ixgbe_vlan_hw_strip_enable_all(dev);
1609 ixgbe_vlan_hw_strip_disable_all(dev);
1612 if(mask & ETH_VLAN_FILTER_MASK){
1613 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1614 ixgbe_vlan_hw_filter_enable(dev);
1616 ixgbe_vlan_hw_filter_disable(dev);
1619 if(mask & ETH_VLAN_EXTEND_MASK){
1620 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1621 ixgbe_vlan_hw_extend_enable(dev);
1623 ixgbe_vlan_hw_extend_disable(dev);
1628 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1630 struct ixgbe_hw *hw =
1631 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1633 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1634 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1635 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1639 ixgbe_dev_configure(struct rte_eth_dev *dev)
1641 struct ixgbe_interrupt *intr =
1642 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1643 struct ixgbe_adapter *adapter =
1644 (struct ixgbe_adapter *)dev->data->dev_private;
1646 PMD_INIT_FUNC_TRACE();
1648 /* set flag to update link status after init */
1649 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1652 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1653 * allocation or vector Rx preconditions we will reset it.
1655 adapter->rx_bulk_alloc_allowed = true;
1656 adapter->rx_vec_allowed = true;
1662 * Configure device link speed and setup link.
1663 * It returns 0 on success.
1666 ixgbe_dev_start(struct rte_eth_dev *dev)
1668 struct ixgbe_hw *hw =
1669 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670 struct ixgbe_vf_info *vfinfo =
1671 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1672 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1673 uint32_t intr_vector = 0;
1674 int err, link_up = 0, negotiate = 0;
1680 PMD_INIT_FUNC_TRACE();
1682 /* IXGBE devices don't support half duplex */
1683 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1684 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1685 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1686 dev->data->dev_conf.link_duplex,
1687 dev->data->port_id);
1692 hw->adapter_stopped = 0;
1693 ixgbe_stop_adapter(hw);
1695 /* reinitialize adapter
1696 * this calls reset and start */
1697 status = ixgbe_pf_reset_hw(hw);
1700 hw->mac.ops.start_hw(hw);
1701 hw->mac.get_link_status = true;
1703 /* configure PF module if SRIOV enabled */
1704 ixgbe_pf_host_configure(dev);
1706 /* check and configure queue intr-vector mapping */
1707 if (dev->data->dev_conf.intr_conf.rxq != 0)
1708 intr_vector = dev->data->nb_rx_queues;
1710 if (rte_intr_efd_enable(intr_handle, intr_vector))
1713 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1714 intr_handle->intr_vec =
1715 rte_zmalloc("intr_vec",
1716 dev->data->nb_rx_queues * sizeof(int),
1718 if (intr_handle->intr_vec == NULL) {
1719 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1720 " intr_vec\n", dev->data->nb_rx_queues);
1725 /* confiugre msix for sleep until rx interrupt */
1726 ixgbe_configure_msix(dev);
1728 /* initialize transmission unit */
1729 ixgbe_dev_tx_init(dev);
1731 /* This can fail when allocating mbufs for descriptor rings */
1732 err = ixgbe_dev_rx_init(dev);
1734 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1738 err = ixgbe_dev_rxtx_start(dev);
1740 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1744 /* Skip link setup if loopback mode is enabled for 82599. */
1745 if (hw->mac.type == ixgbe_mac_82599EB &&
1746 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1747 goto skip_link_setup;
1749 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1750 err = hw->mac.ops.setup_sfp(hw);
1755 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1756 /* Turn on the copper */
1757 ixgbe_set_phy_power(hw, true);
1759 /* Turn on the laser */
1760 ixgbe_enable_tx_laser(hw);
1763 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1766 dev->data->dev_link.link_status = link_up;
1768 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1772 switch(dev->data->dev_conf.link_speed) {
1773 case ETH_LINK_SPEED_AUTONEG:
1774 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1775 IXGBE_LINK_SPEED_82599_AUTONEG :
1776 IXGBE_LINK_SPEED_82598_AUTONEG;
1778 case ETH_LINK_SPEED_100:
1780 * Invalid for 82598 but error will be detected by
1781 * ixgbe_setup_link()
1783 speed = IXGBE_LINK_SPEED_100_FULL;
1785 case ETH_LINK_SPEED_1000:
1786 speed = IXGBE_LINK_SPEED_1GB_FULL;
1788 case ETH_LINK_SPEED_10000:
1789 speed = IXGBE_LINK_SPEED_10GB_FULL;
1792 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1793 dev->data->dev_conf.link_speed,
1794 dev->data->port_id);
1798 err = ixgbe_setup_link(hw, speed, link_up);
1804 /* check if lsc interrupt is enabled */
1805 if (dev->data->dev_conf.intr_conf.lsc != 0) {
1806 if (rte_intr_allow_others(intr_handle)) {
1807 rte_intr_callback_register(intr_handle,
1808 ixgbe_dev_interrupt_handler,
1810 ixgbe_dev_lsc_interrupt_setup(dev);
1812 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1813 " no intr multiplex\n");
1816 /* check if rxq interrupt is enabled */
1817 if (dev->data->dev_conf.intr_conf.rxq != 0)
1818 ixgbe_dev_rxq_interrupt_setup(dev);
1820 /* enable uio/vfio intr/eventfd mapping */
1821 rte_intr_enable(intr_handle);
1823 /* resume enabled intr since hw reset */
1824 ixgbe_enable_intr(dev);
1826 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1827 ETH_VLAN_EXTEND_MASK;
1828 ixgbe_vlan_offload_set(dev, mask);
1830 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1831 /* Enable vlan filtering for VMDq */
1832 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1835 /* Configure DCB hw */
1836 ixgbe_configure_dcb(dev);
1838 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1839 err = ixgbe_fdir_configure(dev);
1844 /* Restore vf rate limit */
1845 if (vfinfo != NULL) {
1846 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1847 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1848 if (vfinfo[vf].tx_rate[idx] != 0)
1849 ixgbe_set_vf_rate_limit(dev, vf,
1850 vfinfo[vf].tx_rate[idx],
1854 ixgbe_restore_statistics_mapping(dev);
1859 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1860 ixgbe_dev_clear_queues(dev);
1865 * Stop device: disable rx and tx functions to allow for reconfiguring.
1868 ixgbe_dev_stop(struct rte_eth_dev *dev)
1870 struct rte_eth_link link;
1871 struct ixgbe_hw *hw =
1872 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873 struct ixgbe_vf_info *vfinfo =
1874 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1875 struct ixgbe_filter_info *filter_info =
1876 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1877 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1878 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1881 PMD_INIT_FUNC_TRACE();
1883 /* disable interrupts */
1884 ixgbe_disable_intr(hw);
1886 /* disable intr eventfd mapping */
1887 rte_intr_disable(intr_handle);
1890 ixgbe_pf_reset_hw(hw);
1891 hw->adapter_stopped = 0;
1894 ixgbe_stop_adapter(hw);
1896 for (vf = 0; vfinfo != NULL &&
1897 vf < dev->pci_dev->max_vfs; vf++)
1898 vfinfo[vf].clear_to_send = false;
1900 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1901 /* Turn off the copper */
1902 ixgbe_set_phy_power(hw, false);
1904 /* Turn off the laser */
1905 ixgbe_disable_tx_laser(hw);
1908 ixgbe_dev_clear_queues(dev);
1910 /* Clear stored conf */
1911 dev->data->scattered_rx = 0;
1914 /* Clear recorded link status */
1915 memset(&link, 0, sizeof(link));
1916 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1918 /* Remove all ntuple filters of the device */
1919 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1920 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1921 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1922 TAILQ_REMOVE(&filter_info->fivetuple_list,
1926 memset(filter_info->fivetuple_mask, 0,
1927 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1929 /* Clean datapath event and queue/vec mapping */
1930 rte_intr_efd_disable(intr_handle);
1931 if (intr_handle->intr_vec != NULL) {
1932 rte_free(intr_handle->intr_vec);
1933 intr_handle->intr_vec = NULL;
1938 * Set device link up: enable tx.
1941 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1943 struct ixgbe_hw *hw =
1944 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 if (hw->mac.type == ixgbe_mac_82599EB) {
1946 #ifdef RTE_NIC_BYPASS
1947 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1948 /* Not suported in bypass mode */
1949 PMD_INIT_LOG(ERR, "Set link up is not supported "
1950 "by device id 0x%x", hw->device_id);
1956 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1957 /* Turn on the copper */
1958 ixgbe_set_phy_power(hw, true);
1960 /* Turn on the laser */
1961 ixgbe_enable_tx_laser(hw);
1968 * Set device link down: disable tx.
1971 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1973 struct ixgbe_hw *hw =
1974 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975 if (hw->mac.type == ixgbe_mac_82599EB) {
1976 #ifdef RTE_NIC_BYPASS
1977 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1978 /* Not suported in bypass mode */
1979 PMD_INIT_LOG(ERR, "Set link down is not supported "
1980 "by device id 0x%x", hw->device_id);
1986 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1987 /* Turn off the copper */
1988 ixgbe_set_phy_power(hw, false);
1990 /* Turn off the laser */
1991 ixgbe_disable_tx_laser(hw);
1998 * Reest and stop device.
2001 ixgbe_dev_close(struct rte_eth_dev *dev)
2003 struct ixgbe_hw *hw =
2004 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 PMD_INIT_FUNC_TRACE();
2008 ixgbe_pf_reset_hw(hw);
2010 ixgbe_dev_stop(dev);
2011 hw->adapter_stopped = 1;
2013 ixgbe_dev_free_queues(dev);
2015 ixgbe_disable_pcie_master(hw);
2017 /* reprogram the RAR[0] in case user changed it. */
2018 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2022 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2023 *hw_stats, uint64_t *total_missed_rx,
2024 uint64_t *total_qbrc, uint64_t *total_qprc,
2025 uint64_t *total_qprdc)
2027 uint32_t bprc, lxon, lxoff, total;
2030 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2031 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2032 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2033 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2035 for (i = 0; i < 8; i++) {
2037 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2038 /* global total per queue */
2039 hw_stats->mpc[i] += mp;
2040 /* Running comprehensive total for stats display */
2041 *total_missed_rx += hw_stats->mpc[i];
2042 if (hw->mac.type == ixgbe_mac_82598EB) {
2043 hw_stats->rnbc[i] +=
2044 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2045 hw_stats->pxonrxc[i] +=
2046 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2047 hw_stats->pxoffrxc[i] +=
2048 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2050 hw_stats->pxonrxc[i] +=
2051 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2052 hw_stats->pxoffrxc[i] +=
2053 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2054 hw_stats->pxon2offc[i] +=
2055 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2057 hw_stats->pxontxc[i] +=
2058 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2059 hw_stats->pxofftxc[i] +=
2060 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2062 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2063 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2064 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2065 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2066 hw_stats->qbrc[i] +=
2067 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2068 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2069 hw_stats->qbtc[i] +=
2070 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2071 *total_qprdc += hw_stats->qprdc[i] +=
2072 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2074 *total_qprc += hw_stats->qprc[i];
2075 *total_qbrc += hw_stats->qbrc[i];
2077 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2078 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2079 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2081 /* Note that gprc counts missed packets */
2082 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2084 if (hw->mac.type != ixgbe_mac_82598EB) {
2085 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2086 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2087 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2088 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2089 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2090 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2091 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2092 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2094 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2095 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2096 /* 82598 only has a counter in the high register */
2097 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2098 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2099 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2103 * Workaround: mprc hardware is incorrectly counting
2104 * broadcasts, so for now we subtract those.
2106 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2107 hw_stats->bprc += bprc;
2108 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2109 if (hw->mac.type == ixgbe_mac_82598EB)
2110 hw_stats->mprc -= bprc;
2112 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2113 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2114 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2115 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2116 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2117 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2119 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2120 hw_stats->lxontxc += lxon;
2121 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2122 hw_stats->lxofftxc += lxoff;
2123 total = lxon + lxoff;
2125 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2126 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2127 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2128 hw_stats->gptc -= total;
2129 hw_stats->mptc -= total;
2130 hw_stats->ptc64 -= total;
2131 hw_stats->gotc -= total * ETHER_MIN_LEN;
2133 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2134 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2135 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2136 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2137 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2138 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2139 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2140 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2141 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2142 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2143 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2144 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2145 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2146 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2147 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2148 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2149 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2150 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2151 /* Only read FCOE on 82599 */
2152 if (hw->mac.type != ixgbe_mac_82598EB) {
2153 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2154 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2155 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2156 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2157 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2160 /* Flow Director Stats registers */
2161 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2162 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2166 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2169 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2171 struct ixgbe_hw *hw =
2172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173 struct ixgbe_hw_stats *hw_stats =
2174 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2175 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2178 total_missed_rx = 0;
2183 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2184 &total_qprc, &total_qprdc);
2189 /* Fill out the rte_eth_stats statistics structure */
2190 stats->ipackets = total_qprc;
2191 stats->ibytes = total_qbrc;
2192 stats->opackets = hw_stats->gptc;
2193 stats->obytes = hw_stats->gotc;
2195 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2196 stats->q_ipackets[i] = hw_stats->qprc[i];
2197 stats->q_opackets[i] = hw_stats->qptc[i];
2198 stats->q_ibytes[i] = hw_stats->qbrc[i];
2199 stats->q_obytes[i] = hw_stats->qbtc[i];
2200 stats->q_errors[i] = hw_stats->qprdc[i];
2204 stats->ierrors = hw_stats->crcerrs +
2224 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2226 struct ixgbe_hw_stats *stats =
2227 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2229 /* HW registers are cleared on read */
2230 ixgbe_dev_stats_get(dev, NULL);
2232 /* Reset software totals */
2233 memset(stats, 0, sizeof(*stats));
2237 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2240 struct ixgbe_hw *hw =
2241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242 struct ixgbe_hw_stats *hw_stats =
2243 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2244 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2245 unsigned i, count = IXGBE_NB_XSTATS;
2250 total_missed_rx = 0;
2255 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2256 &total_qprc, &total_qprdc);
2258 /* If this is a reset xstats is NULL, and we have cleared the
2259 * registers by reading them.
2264 /* Extended stats */
2265 for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2266 snprintf(xstats[i].name, sizeof(xstats[i].name),
2267 "%s", rte_ixgbe_stats_strings[i].name);
2268 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2269 rte_ixgbe_stats_strings[i].offset);
2276 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2278 struct ixgbe_hw_stats *stats =
2279 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2281 /* HW registers are cleared on read */
2282 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2284 /* Reset software totals */
2285 memset(stats, 0, sizeof(*stats));
2289 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2293 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2295 /* Good Rx packet, include VF loopback */
2296 UPDATE_VF_STAT(IXGBE_VFGPRC,
2297 hw_stats->last_vfgprc, hw_stats->vfgprc);
2299 /* Good Rx octets, include VF loopback */
2300 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2301 hw_stats->last_vfgorc, hw_stats->vfgorc);
2303 /* Good Tx packet, include VF loopback */
2304 UPDATE_VF_STAT(IXGBE_VFGPTC,
2305 hw_stats->last_vfgptc, hw_stats->vfgptc);
2307 /* Good Tx octets, include VF loopback */
2308 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2309 hw_stats->last_vfgotc, hw_stats->vfgotc);
2311 /* Rx Multicst Packet */
2312 UPDATE_VF_STAT(IXGBE_VFMPRC,
2313 hw_stats->last_vfmprc, hw_stats->vfmprc);
2318 stats->ipackets = hw_stats->vfgprc;
2319 stats->ibytes = hw_stats->vfgorc;
2320 stats->opackets = hw_stats->vfgptc;
2321 stats->obytes = hw_stats->vfgotc;
2322 stats->imcasts = hw_stats->vfmprc;
2323 /* stats->imcasts should be removed as imcasts is deprecated */
2327 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2329 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2330 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2332 /* Sync HW register to the last stats */
2333 ixgbevf_dev_stats_get(dev, NULL);
2335 /* reset HW current stats*/
2336 hw_stats->vfgprc = 0;
2337 hw_stats->vfgorc = 0;
2338 hw_stats->vfgptc = 0;
2339 hw_stats->vfgotc = 0;
2340 hw_stats->vfmprc = 0;
2345 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2350 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2351 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2352 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2353 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2354 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2355 dev_info->max_vfs = dev->pci_dev->max_vfs;
2356 if (hw->mac.type == ixgbe_mac_82598EB)
2357 dev_info->max_vmdq_pools = ETH_16_POOLS;
2359 dev_info->max_vmdq_pools = ETH_64_POOLS;
2360 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2361 dev_info->rx_offload_capa =
2362 DEV_RX_OFFLOAD_VLAN_STRIP |
2363 DEV_RX_OFFLOAD_IPV4_CKSUM |
2364 DEV_RX_OFFLOAD_UDP_CKSUM |
2365 DEV_RX_OFFLOAD_TCP_CKSUM;
2368 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2371 if ((hw->mac.type == ixgbe_mac_82599EB ||
2372 hw->mac.type == ixgbe_mac_X540) &&
2373 !RTE_ETH_DEV_SRIOV(dev).active)
2374 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2376 dev_info->tx_offload_capa =
2377 DEV_TX_OFFLOAD_VLAN_INSERT |
2378 DEV_TX_OFFLOAD_IPV4_CKSUM |
2379 DEV_TX_OFFLOAD_UDP_CKSUM |
2380 DEV_TX_OFFLOAD_TCP_CKSUM |
2381 DEV_TX_OFFLOAD_SCTP_CKSUM |
2382 DEV_TX_OFFLOAD_TCP_TSO;
2384 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2386 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2387 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2388 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2390 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2394 dev_info->default_txconf = (struct rte_eth_txconf) {
2396 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2397 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2398 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2400 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2401 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2402 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2403 ETH_TXQ_FLAGS_NOOFFLOADS,
2405 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2406 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2407 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2411 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2412 struct rte_eth_dev_info *dev_info)
2414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2417 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2418 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2419 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2420 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2421 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2422 dev_info->max_vfs = dev->pci_dev->max_vfs;
2423 if (hw->mac.type == ixgbe_mac_82598EB)
2424 dev_info->max_vmdq_pools = ETH_16_POOLS;
2426 dev_info->max_vmdq_pools = ETH_64_POOLS;
2427 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2428 DEV_RX_OFFLOAD_IPV4_CKSUM |
2429 DEV_RX_OFFLOAD_UDP_CKSUM |
2430 DEV_RX_OFFLOAD_TCP_CKSUM;
2431 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2432 DEV_TX_OFFLOAD_IPV4_CKSUM |
2433 DEV_TX_OFFLOAD_UDP_CKSUM |
2434 DEV_TX_OFFLOAD_TCP_CKSUM |
2435 DEV_TX_OFFLOAD_SCTP_CKSUM |
2436 DEV_TX_OFFLOAD_TCP_TSO;
2438 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2440 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2441 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2442 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2444 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2448 dev_info->default_txconf = (struct rte_eth_txconf) {
2450 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2451 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2452 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2454 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2455 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2456 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2457 ETH_TXQ_FLAGS_NOOFFLOADS,
2461 /* return 0 means link status changed, -1 means not changed */
2463 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 struct rte_eth_link link, old;
2467 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2471 link.link_status = 0;
2472 link.link_speed = 0;
2473 link.link_duplex = 0;
2474 memset(&old, 0, sizeof(old));
2475 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2477 hw->mac.get_link_status = true;
2479 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2480 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2481 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2483 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2486 link.link_speed = ETH_LINK_SPEED_100;
2487 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2488 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2489 if (link.link_status == old.link_status)
2495 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2496 if (link.link_status == old.link_status)
2500 link.link_status = 1;
2501 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2503 switch (link_speed) {
2505 case IXGBE_LINK_SPEED_UNKNOWN:
2506 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2507 link.link_speed = ETH_LINK_SPEED_100;
2510 case IXGBE_LINK_SPEED_100_FULL:
2511 link.link_speed = ETH_LINK_SPEED_100;
2514 case IXGBE_LINK_SPEED_1GB_FULL:
2515 link.link_speed = ETH_LINK_SPEED_1000;
2518 case IXGBE_LINK_SPEED_10GB_FULL:
2519 link.link_speed = ETH_LINK_SPEED_10000;
2522 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2524 if (link.link_status == old.link_status)
2531 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2537 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2538 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2542 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2544 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2548 fctrl &= (~IXGBE_FCTRL_UPE);
2549 if (dev->data->all_multicast == 1)
2550 fctrl |= IXGBE_FCTRL_MPE;
2552 fctrl &= (~IXGBE_FCTRL_MPE);
2553 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2557 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2563 fctrl |= IXGBE_FCTRL_MPE;
2564 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2568 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2570 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573 if (dev->data->promiscuous == 1)
2574 return; /* must remain in all_multicast mode */
2576 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2577 fctrl &= (~IXGBE_FCTRL_MPE);
2578 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2582 * It clears the interrupt causes and enables the interrupt.
2583 * It will be called once only during nic initialized.
2586 * Pointer to struct rte_eth_dev.
2589 * - On success, zero.
2590 * - On failure, a negative value.
2593 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2595 struct ixgbe_interrupt *intr =
2596 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2598 ixgbe_dev_link_status_print(dev);
2599 intr->mask |= IXGBE_EICR_LSC;
2605 * It clears the interrupt causes and enables the interrupt.
2606 * It will be called once only during nic initialized.
2609 * Pointer to struct rte_eth_dev.
2612 * - On success, zero.
2613 * - On failure, a negative value.
2616 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2618 struct ixgbe_interrupt *intr =
2619 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2621 intr->mask |= IXGBE_EICR_RTX_QUEUE;
2627 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2630 * Pointer to struct rte_eth_dev.
2633 * - On success, zero.
2634 * - On failure, a negative value.
2637 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2640 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641 struct ixgbe_interrupt *intr =
2642 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2644 /* clear all cause mask */
2645 ixgbe_disable_intr(hw);
2647 /* read-on-clear nic registers here */
2648 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2649 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2653 /* set flag for async link update */
2654 if (eicr & IXGBE_EICR_LSC)
2655 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2657 if (eicr & IXGBE_EICR_MAILBOX)
2658 intr->flags |= IXGBE_FLAG_MAILBOX;
2664 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2667 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 struct ixgbe_interrupt *intr =
2669 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2671 /* clear all cause mask */
2672 ixgbevf_intr_disable(hw);
2674 /* read-on-clear nic registers here */
2675 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2676 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2680 /* set flag for async link update */
2681 if (eicr & IXGBE_EICR_LSC)
2682 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2688 * It gets and then prints the link status.
2691 * Pointer to struct rte_eth_dev.
2694 * - On success, zero.
2695 * - On failure, a negative value.
2698 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2700 struct rte_eth_link link;
2702 memset(&link, 0, sizeof(link));
2703 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2704 if (link.link_status) {
2705 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2706 (int)(dev->data->port_id),
2707 (unsigned)link.link_speed,
2708 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2709 "full-duplex" : "half-duplex");
2711 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2712 (int)(dev->data->port_id));
2714 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2715 dev->pci_dev->addr.domain,
2716 dev->pci_dev->addr.bus,
2717 dev->pci_dev->addr.devid,
2718 dev->pci_dev->addr.function);
2722 * It executes link_update after knowing an interrupt occurred.
2725 * Pointer to struct rte_eth_dev.
2728 * - On success, zero.
2729 * - On failure, a negative value.
2732 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2734 struct ixgbe_interrupt *intr =
2735 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2737 struct rte_eth_link link;
2738 int intr_enable_delay = false;
2740 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2742 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2743 ixgbe_pf_mbx_process(dev);
2744 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2747 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2748 /* get the link status before link update, for predicting later */
2749 memset(&link, 0, sizeof(link));
2750 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2752 ixgbe_dev_link_update(dev, 0);
2755 if (!link.link_status)
2756 /* handle it 1 sec later, wait it being stable */
2757 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2758 /* likely to down */
2760 /* handle it 4 sec later, wait it being stable */
2761 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2763 ixgbe_dev_link_status_print(dev);
2765 intr_enable_delay = true;
2768 if (intr_enable_delay) {
2769 if (rte_eal_alarm_set(timeout * 1000,
2770 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2771 PMD_DRV_LOG(ERR, "Error setting alarm");
2773 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2774 ixgbe_enable_intr(dev);
2775 rte_intr_enable(&(dev->pci_dev->intr_handle));
2783 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2785 struct ixgbe_hw *hw =
2786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2789 ixgbevf_intr_enable(hw);
2790 rte_intr_enable(&dev->pci_dev->intr_handle);
2795 * Interrupt handler which shall be registered for alarm callback for delayed
2796 * handling specific interrupt to wait for the stable nic state. As the
2797 * NIC interrupt state is not stable for ixgbe after link is just down,
2798 * it needs to wait 4 seconds to get the stable status.
2801 * Pointer to interrupt handle.
2803 * The address of parameter (struct rte_eth_dev *) regsitered before.
2809 ixgbe_dev_interrupt_delayed_handler(void *param)
2811 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2812 struct ixgbe_interrupt *intr =
2813 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2814 struct ixgbe_hw *hw =
2815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2819 if (eicr & IXGBE_EICR_MAILBOX)
2820 ixgbe_pf_mbx_process(dev);
2822 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2823 ixgbe_dev_link_update(dev, 0);
2824 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2825 ixgbe_dev_link_status_print(dev);
2826 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2829 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2830 ixgbe_enable_intr(dev);
2831 rte_intr_enable(&(dev->pci_dev->intr_handle));
2835 * Interrupt handler triggered by NIC for handling
2836 * specific interrupt.
2839 * Pointer to interrupt handle.
2841 * The address of parameter (struct rte_eth_dev *) regsitered before.
2847 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2850 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2852 ixgbe_dev_interrupt_get_status(dev);
2853 ixgbe_dev_interrupt_action(dev);
2857 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2860 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2862 ixgbevf_dev_interrupt_get_status(dev);
2863 ixgbevf_dev_interrupt_action(dev);
2867 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2869 struct ixgbe_hw *hw;
2871 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2876 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2878 struct ixgbe_hw *hw;
2880 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2885 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2887 struct ixgbe_hw *hw;
2893 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 fc_conf->pause_time = hw->fc.pause_time;
2896 fc_conf->high_water = hw->fc.high_water[0];
2897 fc_conf->low_water = hw->fc.low_water[0];
2898 fc_conf->send_xon = hw->fc.send_xon;
2899 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2902 * Return rx_pause status according to actual setting of
2905 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2906 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2912 * Return tx_pause status according to actual setting of
2915 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2916 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2921 if (rx_pause && tx_pause)
2922 fc_conf->mode = RTE_FC_FULL;
2924 fc_conf->mode = RTE_FC_RX_PAUSE;
2926 fc_conf->mode = RTE_FC_TX_PAUSE;
2928 fc_conf->mode = RTE_FC_NONE;
2934 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2936 struct ixgbe_hw *hw;
2938 uint32_t rx_buf_size;
2939 uint32_t max_high_water;
2941 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2948 PMD_INIT_FUNC_TRACE();
2950 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2952 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2955 * At least reserve one Ethernet frame for watermark
2956 * high_water/low_water in kilo bytes for ixgbe
2958 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2959 if ((fc_conf->high_water > max_high_water) ||
2960 (fc_conf->high_water < fc_conf->low_water)) {
2961 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2962 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2966 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2967 hw->fc.pause_time = fc_conf->pause_time;
2968 hw->fc.high_water[0] = fc_conf->high_water;
2969 hw->fc.low_water[0] = fc_conf->low_water;
2970 hw->fc.send_xon = fc_conf->send_xon;
2971 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2973 err = ixgbe_fc_enable(hw);
2975 /* Not negotiated is not an error case */
2976 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2978 /* check if we want to forward MAC frames - driver doesn't have native
2979 * capability to do that, so we'll write the registers ourselves */
2981 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2983 /* set or clear MFLCN.PMCF bit depending on configuration */
2984 if (fc_conf->mac_ctrl_frame_fwd != 0)
2985 mflcn |= IXGBE_MFLCN_PMCF;
2987 mflcn &= ~IXGBE_MFLCN_PMCF;
2989 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2990 IXGBE_WRITE_FLUSH(hw);
2995 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3000 * ixgbe_pfc_enable_generic - Enable flow control
3001 * @hw: pointer to hardware structure
3002 * @tc_num: traffic class number
3003 * Enable flow control according to the current settings.
3006 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3009 uint32_t mflcn_reg, fccfg_reg;
3011 uint32_t fcrtl, fcrth;
3015 /* Validate the water mark configuration */
3016 if (!hw->fc.pause_time) {
3017 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3021 /* Low water mark of zero causes XOFF floods */
3022 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3023 /* High/Low water can not be 0 */
3024 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3025 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3026 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3030 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3031 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3032 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3036 /* Negotiate the fc mode to use */
3037 ixgbe_fc_autoneg(hw);
3039 /* Disable any previous flow control settings */
3040 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3041 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3043 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3044 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3046 switch (hw->fc.current_mode) {
3049 * If the count of enabled RX Priority Flow control >1,
3050 * and the TX pause can not be disabled
3053 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3054 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3055 if (reg & IXGBE_FCRTH_FCEN)
3059 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3061 case ixgbe_fc_rx_pause:
3063 * Rx Flow control is enabled and Tx Flow control is
3064 * disabled by software override. Since there really
3065 * isn't a way to advertise that we are capable of RX
3066 * Pause ONLY, we will advertise that we support both
3067 * symmetric and asymmetric Rx PAUSE. Later, we will
3068 * disable the adapter's ability to send PAUSE frames.
3070 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3072 * If the count of enabled RX Priority Flow control >1,
3073 * and the TX pause can not be disabled
3076 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3077 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3078 if (reg & IXGBE_FCRTH_FCEN)
3082 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3084 case ixgbe_fc_tx_pause:
3086 * Tx Flow control is enabled, and Rx Flow control is
3087 * disabled by software override.
3089 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3092 /* Flow control (both Rx and Tx) is enabled by SW override. */
3093 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3094 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3097 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3098 ret_val = IXGBE_ERR_CONFIG;
3103 /* Set 802.3x based flow control settings. */
3104 mflcn_reg |= IXGBE_MFLCN_DPF;
3105 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3106 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3108 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3109 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3110 hw->fc.high_water[tc_num]) {
3111 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3112 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3113 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3115 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3117 * In order to prevent Tx hangs when the internal Tx
3118 * switch is enabled we must set the high water mark
3119 * to the maximum FCRTH value. This allows the Tx
3120 * switch to function even under heavy Rx workloads.
3122 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3124 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3126 /* Configure pause time (2 TCs per register) */
3127 reg = hw->fc.pause_time * 0x00010001;
3128 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3129 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3131 /* Configure flow control refresh threshold value */
3132 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3139 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3144 if(hw->mac.type != ixgbe_mac_82598EB) {
3145 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3151 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3154 uint32_t rx_buf_size;
3155 uint32_t max_high_water;
3157 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3158 struct ixgbe_hw *hw =
3159 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160 struct ixgbe_dcb_config *dcb_config =
3161 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3163 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3170 PMD_INIT_FUNC_TRACE();
3172 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3173 tc_num = map[pfc_conf->priority];
3174 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3175 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3177 * At least reserve one Ethernet frame for watermark
3178 * high_water/low_water in kilo bytes for ixgbe
3180 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3181 if ((pfc_conf->fc.high_water > max_high_water) ||
3182 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3183 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3184 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3188 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3189 hw->fc.pause_time = pfc_conf->fc.pause_time;
3190 hw->fc.send_xon = pfc_conf->fc.send_xon;
3191 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3192 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3194 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3196 /* Not negotiated is not an error case */
3197 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3200 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3205 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3206 struct rte_eth_rss_reta_entry64 *reta_conf,
3211 uint16_t idx, shift;
3212 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 PMD_INIT_FUNC_TRACE();
3215 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3216 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3217 "(%d) doesn't match the number hardware can supported "
3218 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3222 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3223 idx = i / RTE_RETA_GROUP_SIZE;
3224 shift = i % RTE_RETA_GROUP_SIZE;
3225 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3229 if (mask == IXGBE_4_BIT_MASK)
3232 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3233 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3234 if (mask & (0x1 << j))
3235 reta |= reta_conf[idx].reta[shift + j] <<
3238 reta |= r & (IXGBE_8_BIT_MASK <<
3241 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3248 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3249 struct rte_eth_rss_reta_entry64 *reta_conf,
3254 uint16_t idx, shift;
3255 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257 PMD_INIT_FUNC_TRACE();
3258 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3259 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3260 "(%d) doesn't match the number hardware can supported "
3261 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3265 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3266 idx = i / RTE_RETA_GROUP_SIZE;
3267 shift = i % RTE_RETA_GROUP_SIZE;
3268 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3273 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3274 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3275 if (mask & (0x1 << j))
3276 reta_conf[idx].reta[shift + j] =
3277 ((reta >> (CHAR_BIT * j)) &
3286 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3287 uint32_t index, uint32_t pool)
3289 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290 uint32_t enable_addr = 1;
3292 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3296 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3298 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 ixgbe_clear_rar(hw, index);
3304 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3306 ixgbe_remove_rar(dev, 0);
3308 ixgbe_add_rar(dev, addr, 0, 0);
3312 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3316 struct ixgbe_hw *hw;
3317 struct rte_eth_dev_info dev_info;
3318 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3320 ixgbe_dev_info_get(dev, &dev_info);
3322 /* check that mtu is within the allowed range */
3323 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3326 /* refuse mtu that requires the support of scattered packets when this
3327 * feature has not been enabled before. */
3328 if (!dev->data->scattered_rx &&
3329 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3330 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3333 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3336 /* switch to jumbo mode if needed */
3337 if (frame_size > ETHER_MAX_LEN) {
3338 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3339 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3341 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3342 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3344 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3346 /* update max frame size */
3347 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3349 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3350 maxfrs &= 0x0000FFFF;
3351 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3352 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3358 * Virtual Function operations
3361 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3363 PMD_INIT_FUNC_TRACE();
3365 /* Clear interrupt mask to stop from interrupts being generated */
3366 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3368 IXGBE_WRITE_FLUSH(hw);
3372 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3374 PMD_INIT_FUNC_TRACE();
3376 /* VF enable interrupt autoclean */
3377 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3378 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3379 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3381 IXGBE_WRITE_FLUSH(hw);
3385 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3387 struct rte_eth_conf* conf = &dev->data->dev_conf;
3388 struct ixgbe_adapter *adapter =
3389 (struct ixgbe_adapter *)dev->data->dev_private;
3391 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3392 dev->data->port_id);
3395 * VF has no ability to enable/disable HW CRC
3396 * Keep the persistent behavior the same as Host PF
3398 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3399 if (!conf->rxmode.hw_strip_crc) {
3400 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3401 conf->rxmode.hw_strip_crc = 1;
3404 if (conf->rxmode.hw_strip_crc) {
3405 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3406 conf->rxmode.hw_strip_crc = 0;
3411 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3412 * allocation or vector Rx preconditions we will reset it.
3414 adapter->rx_bulk_alloc_allowed = true;
3415 adapter->rx_vec_allowed = true;
3421 ixgbevf_dev_start(struct rte_eth_dev *dev)
3423 struct ixgbe_hw *hw =
3424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 uint32_t intr_vector = 0;
3426 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3430 PMD_INIT_FUNC_TRACE();
3432 hw->mac.ops.reset_hw(hw);
3433 hw->mac.get_link_status = true;
3435 /* negotiate mailbox API version to use with the PF. */
3436 ixgbevf_negotiate_api(hw);
3438 ixgbevf_dev_tx_init(dev);
3440 /* This can fail when allocating mbufs for descriptor rings */
3441 err = ixgbevf_dev_rx_init(dev);
3443 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3444 ixgbe_dev_clear_queues(dev);
3449 ixgbevf_set_vfta_all(dev,1);
3452 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3453 ETH_VLAN_EXTEND_MASK;
3454 ixgbevf_vlan_offload_set(dev, mask);
3456 ixgbevf_dev_rxtx_start(dev);
3458 /* check and configure queue intr-vector mapping */
3459 if (dev->data->dev_conf.intr_conf.rxq != 0)
3460 intr_vector = dev->data->nb_rx_queues;
3462 if (rte_intr_efd_enable(intr_handle, intr_vector))
3465 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3466 intr_handle->intr_vec =
3467 rte_zmalloc("intr_vec",
3468 dev->data->nb_rx_queues * sizeof(int), 0);
3469 if (intr_handle->intr_vec == NULL) {
3470 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3471 " intr_vec\n", dev->data->nb_rx_queues);
3475 ixgbevf_configure_msix(dev);
3477 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3478 if (rte_intr_allow_others(intr_handle))
3479 rte_intr_callback_register(intr_handle,
3480 ixgbevf_dev_interrupt_handler,
3483 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3484 " no intr multiplex\n");
3487 rte_intr_enable(intr_handle);
3489 /* Re-enable interrupt for VF */
3490 ixgbevf_intr_enable(hw);
3496 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3498 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3501 PMD_INIT_FUNC_TRACE();
3503 hw->adapter_stopped = 1;
3504 ixgbe_stop_adapter(hw);
3507 * Clear what we set, but we still keep shadow_vfta to
3508 * restore after device starts
3510 ixgbevf_set_vfta_all(dev,0);
3512 /* Clear stored conf */
3513 dev->data->scattered_rx = 0;
3515 ixgbe_dev_clear_queues(dev);
3517 /* disable intr eventfd mapping */
3518 rte_intr_disable(intr_handle);
3520 /* Clean datapath event and queue/vec mapping */
3521 rte_intr_efd_disable(intr_handle);
3522 if (intr_handle->intr_vec != NULL) {
3523 rte_free(intr_handle->intr_vec);
3524 intr_handle->intr_vec = NULL;
3529 ixgbevf_dev_close(struct rte_eth_dev *dev)
3531 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532 struct rte_pci_device *pci_dev;
3534 PMD_INIT_FUNC_TRACE();
3538 ixgbevf_dev_stop(dev);
3540 ixgbe_dev_free_queues(dev);
3542 /* reprogram the RAR[0] in case user changed it. */
3543 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3545 pci_dev = dev->pci_dev;
3546 if (pci_dev->intr_handle.intr_vec) {
3547 rte_free(pci_dev->intr_handle.intr_vec);
3548 pci_dev->intr_handle.intr_vec = NULL;
3552 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555 struct ixgbe_vfta * shadow_vfta =
3556 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3557 int i = 0, j = 0, vfta = 0, mask = 1;
3559 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3560 vfta = shadow_vfta->vfta[i];
3563 for (j = 0; j < 32; j++){
3565 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3574 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3576 struct ixgbe_hw *hw =
3577 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 struct ixgbe_vfta * shadow_vfta =
3579 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3580 uint32_t vid_idx = 0;
3581 uint32_t vid_bit = 0;
3584 PMD_INIT_FUNC_TRACE();
3586 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3587 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3589 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3592 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3593 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3595 /* Save what we set and retore it after device reset */
3597 shadow_vfta->vfta[vid_idx] |= vid_bit;
3599 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3605 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3607 struct ixgbe_hw *hw =
3608 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611 PMD_INIT_FUNC_TRACE();
3613 if(queue >= hw->mac.max_rx_queues)
3616 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3618 ctrl |= IXGBE_RXDCTL_VME;
3620 ctrl &= ~IXGBE_RXDCTL_VME;
3621 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3623 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3627 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3629 struct ixgbe_hw *hw =
3630 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634 /* VF function only support hw strip feature, others are not support */
3635 if(mask & ETH_VLAN_STRIP_MASK){
3636 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3638 for(i=0; i < hw->mac.max_rx_queues; i++)
3639 ixgbevf_vlan_strip_queue_set(dev,i,on);
3644 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3648 /* we only need to do this if VMDq is enabled */
3649 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3650 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3651 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3659 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3661 uint32_t vector = 0;
3662 switch (hw->mac.mc_filter_type) {
3663 case 0: /* use bits [47:36] of the address */
3664 vector = ((uc_addr->addr_bytes[4] >> 4) |
3665 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3667 case 1: /* use bits [46:35] of the address */
3668 vector = ((uc_addr->addr_bytes[4] >> 3) |
3669 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3671 case 2: /* use bits [45:34] of the address */
3672 vector = ((uc_addr->addr_bytes[4] >> 2) |
3673 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3675 case 3: /* use bits [43:32] of the address */
3676 vector = ((uc_addr->addr_bytes[4]) |
3677 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3679 default: /* Invalid mc_filter_type */
3683 /* vector can only be 12-bits or boundary will be exceeded */
3689 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3697 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3698 const uint32_t ixgbe_uta_bit_shift = 5;
3699 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3700 const uint32_t bit1 = 0x1;
3702 struct ixgbe_hw *hw =
3703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704 struct ixgbe_uta_info *uta_info =
3705 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3707 /* The UTA table only exists on 82599 hardware and newer */
3708 if (hw->mac.type < ixgbe_mac_82599EB)
3711 vector = ixgbe_uta_vector(hw,mac_addr);
3712 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3713 uta_shift = vector & ixgbe_uta_bit_mask;
3715 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3719 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3721 uta_info->uta_in_use++;
3722 reg_val |= (bit1 << uta_shift);
3723 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3725 uta_info->uta_in_use--;
3726 reg_val &= ~(bit1 << uta_shift);
3727 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3730 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3732 if (uta_info->uta_in_use > 0)
3733 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3734 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3736 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3742 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3745 struct ixgbe_hw *hw =
3746 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747 struct ixgbe_uta_info *uta_info =
3748 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3750 /* The UTA table only exists on 82599 hardware and newer */
3751 if (hw->mac.type < ixgbe_mac_82599EB)
3755 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3756 uta_info->uta_shadow[i] = ~0;
3757 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3760 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3761 uta_info->uta_shadow[i] = 0;
3762 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3770 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3772 uint32_t new_val = orig_val;
3774 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3775 new_val |= IXGBE_VMOLR_AUPE;
3776 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3777 new_val |= IXGBE_VMOLR_ROMPE;
3778 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3779 new_val |= IXGBE_VMOLR_ROPE;
3780 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3781 new_val |= IXGBE_VMOLR_BAM;
3782 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3783 new_val |= IXGBE_VMOLR_MPE;
3789 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3790 uint16_t rx_mask, uint8_t on)
3794 struct ixgbe_hw *hw =
3795 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3798 if (hw->mac.type == ixgbe_mac_82598EB) {
3799 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3800 " on 82599 hardware and newer");
3803 if (ixgbe_vmdq_mode_check(hw) < 0)
3806 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3813 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3819 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3823 const uint8_t bit1 = 0x1;
3825 struct ixgbe_hw *hw =
3826 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828 if (ixgbe_vmdq_mode_check(hw) < 0)
3831 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3832 reg = IXGBE_READ_REG(hw, addr);
3840 IXGBE_WRITE_REG(hw, addr,reg);
3846 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3850 const uint8_t bit1 = 0x1;
3852 struct ixgbe_hw *hw =
3853 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855 if (ixgbe_vmdq_mode_check(hw) < 0)
3858 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3859 reg = IXGBE_READ_REG(hw, addr);
3867 IXGBE_WRITE_REG(hw, addr,reg);
3873 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3874 uint64_t pool_mask, uint8_t vlan_on)
3878 struct ixgbe_hw *hw =
3879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881 if (ixgbe_vmdq_mode_check(hw) < 0)
3883 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3884 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3885 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3893 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
3894 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
3895 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
3896 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
3897 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3898 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3899 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3902 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3903 struct rte_eth_mirror_conf *mirror_conf,
3904 uint8_t rule_id, uint8_t on)
3906 uint32_t mr_ctl,vlvf;
3907 uint32_t mp_lsb = 0;
3908 uint32_t mv_msb = 0;
3909 uint32_t mv_lsb = 0;
3910 uint32_t mp_msb = 0;
3913 uint64_t vlan_mask = 0;
3915 const uint8_t pool_mask_offset = 32;
3916 const uint8_t vlan_mask_offset = 32;
3917 const uint8_t dst_pool_offset = 8;
3918 const uint8_t rule_mr_offset = 4;
3919 const uint8_t mirror_rule_mask= 0x0F;
3921 struct ixgbe_mirror_info *mr_info =
3922 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3923 struct ixgbe_hw *hw =
3924 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925 uint8_t mirror_type = 0;
3927 if (ixgbe_vmdq_mode_check(hw) < 0)
3930 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3933 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3934 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3935 mirror_conf->rule_type);
3939 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3940 mirror_type |= IXGBE_MRCTL_VLME;
3941 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3942 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3943 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3944 /* search vlan id related pool vlan filter index */
3945 reg_index = ixgbe_find_vlvf_slot(hw,
3946 mirror_conf->vlan.vlan_id[i]);
3949 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3950 if ((vlvf & IXGBE_VLVF_VIEN) &&
3951 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3952 mirror_conf->vlan.vlan_id[i]))
3953 vlan_mask |= (1ULL << reg_index);
3960 mv_lsb = vlan_mask & 0xFFFFFFFF;
3961 mv_msb = vlan_mask >> vlan_mask_offset;
3963 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3964 mirror_conf->vlan.vlan_mask;
3965 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3966 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3967 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3968 mirror_conf->vlan.vlan_id[i];
3973 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3974 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3975 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3980 * if enable pool mirror, write related pool mask register,if disable
3981 * pool mirror, clear PFMRVM register
3983 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3984 mirror_type |= IXGBE_MRCTL_VPME;
3986 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3987 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3988 mr_info->mr_conf[rule_id].pool_mask =
3989 mirror_conf->pool_mask;
3994 mr_info->mr_conf[rule_id].pool_mask = 0;
3997 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3998 mirror_type |= IXGBE_MRCTL_UPME;
3999 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4000 mirror_type |= IXGBE_MRCTL_DPME;
4002 /* read mirror control register and recalculate it */
4003 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4006 mr_ctl |= mirror_type;
4007 mr_ctl &= mirror_rule_mask;
4008 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4010 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4012 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4013 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4015 /* write mirrror control register */
4016 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4018 /* write pool mirrror control register */
4019 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4020 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4021 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4024 /* write VLAN mirrror control register */
4025 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4026 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4027 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4035 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4038 uint32_t lsb_val = 0;
4039 uint32_t msb_val = 0;
4040 const uint8_t rule_mr_offset = 4;
4042 struct ixgbe_hw *hw =
4043 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044 struct ixgbe_mirror_info *mr_info =
4045 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4047 if (ixgbe_vmdq_mode_check(hw) < 0)
4050 memset(&mr_info->mr_conf[rule_id], 0,
4051 sizeof(struct rte_eth_mirror_conf));
4053 /* clear PFVMCTL register */
4054 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4056 /* clear pool mask register */
4057 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4058 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4060 /* clear vlan mask register */
4061 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4062 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4068 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4071 struct ixgbe_hw *hw =
4072 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4075 mask |= (1 << queue_id);
4076 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4078 rte_intr_enable(&dev->pci_dev->intr_handle);
4084 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4087 struct ixgbe_hw *hw =
4088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4091 mask &= ~(1 << queue_id);
4092 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4098 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4101 struct ixgbe_hw *hw =
4102 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103 struct ixgbe_interrupt *intr =
4104 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106 if (queue_id < 16) {
4107 ixgbe_disable_intr(hw);
4108 intr->mask |= (1 << queue_id);
4109 ixgbe_enable_intr(dev);
4110 } else if (queue_id < 32) {
4111 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4112 mask &= (1 << queue_id);
4113 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4114 } else if (queue_id < 64) {
4115 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4116 mask &= (1 << (queue_id - 32));
4117 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4119 rte_intr_enable(&dev->pci_dev->intr_handle);
4125 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4128 struct ixgbe_hw *hw =
4129 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130 struct ixgbe_interrupt *intr =
4131 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4133 if (queue_id < 16) {
4134 ixgbe_disable_intr(hw);
4135 intr->mask &= ~(1 << queue_id);
4136 ixgbe_enable_intr(dev);
4137 } else if (queue_id < 32) {
4138 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4139 mask &= ~(1 << queue_id);
4140 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4141 } else if (queue_id < 64) {
4142 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4143 mask &= ~(1 << (queue_id - 32));
4144 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4151 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4152 uint8_t queue, uint8_t msix_vector)
4156 if (direction == -1) {
4158 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4159 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4162 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4164 /* rx or tx cause */
4165 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4166 idx = ((16 * (queue & 1)) + (8 * direction));
4167 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4168 tmp &= ~(0xFF << idx);
4169 tmp |= (msix_vector << idx);
4170 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4175 * set the IVAR registers, mapping interrupt causes to vectors
4177 * pointer to ixgbe_hw struct
4179 * 0 for Rx, 1 for Tx, -1 for other causes
4181 * queue to map the corresponding interrupt to
4183 * the vector to map to the corresponding queue
4186 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4187 uint8_t queue, uint8_t msix_vector)
4191 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4192 if (hw->mac.type == ixgbe_mac_82598EB) {
4193 if (direction == -1)
4195 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4196 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4197 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4198 tmp |= (msix_vector << (8 * (queue & 0x3)));
4199 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4200 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4201 (hw->mac.type == ixgbe_mac_X540)) {
4202 if (direction == -1) {
4204 idx = ((queue & 1) * 8);
4205 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4206 tmp &= ~(0xFF << idx);
4207 tmp |= (msix_vector << idx);
4208 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4210 /* rx or tx causes */
4211 idx = ((16 * (queue & 1)) + (8 * direction));
4212 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4213 tmp &= ~(0xFF << idx);
4214 tmp |= (msix_vector << idx);
4215 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4221 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4223 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4224 struct ixgbe_hw *hw =
4225 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227 uint32_t vector_idx = 0;
4229 /* won't configure msix register if no mapping is done
4230 * between intr vector and event fd.
4232 if (!rte_intr_dp_is_en(intr_handle))
4235 /* Configure all RX queues of VF */
4236 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4237 /* Force all queue use vector 0,
4238 * as IXGBE_VF_MAXMSIVECOTR = 1
4240 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4241 intr_handle->intr_vec[q_idx] = vector_idx;
4244 /* Configure VF Rx queue ivar */
4245 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4249 * Sets up the hardware to properly generate MSI-X interrupts
4251 * board private structure
4254 ixgbe_configure_msix(struct rte_eth_dev *dev)
4256 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4257 struct ixgbe_hw *hw =
4258 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259 uint32_t queue_id, vec = 0;
4263 /* won't configure msix register if no mapping is done
4264 * between intr vector and event fd
4266 if (!rte_intr_dp_is_en(intr_handle))
4269 /* setup GPIE for MSI-x mode */
4270 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4271 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4272 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4273 /* auto clearing and auto setting corresponding bits in EIMS
4274 * when MSI-X interrupt is triggered
4276 if (hw->mac.type == ixgbe_mac_82598EB) {
4277 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4279 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4280 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4282 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4284 /* Populate the IVAR table and set the ITR values to the
4285 * corresponding register.
4287 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4289 /* by default, 1:1 mapping */
4290 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4291 intr_handle->intr_vec[queue_id] = vec;
4292 if (vec < intr_handle->nb_efd - 1)
4296 switch (hw->mac.type) {
4297 case ixgbe_mac_82598EB:
4298 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4299 intr_handle->max_intr - 1);
4301 case ixgbe_mac_82599EB:
4302 case ixgbe_mac_X540:
4303 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4308 IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4309 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4311 /* set up to autoclear timer, and the vectors */
4312 mask = IXGBE_EIMS_ENABLE_MASK;
4313 mask &= ~(IXGBE_EIMS_OTHER |
4314 IXGBE_EIMS_MAILBOX |
4317 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4320 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4321 uint16_t queue_idx, uint16_t tx_rate)
4323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324 uint32_t rf_dec, rf_int;
4326 uint16_t link_speed = dev->data->dev_link.link_speed;
4328 if (queue_idx >= hw->mac.max_tx_queues)
4332 /* Calculate the rate factor values to set */
4333 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4334 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4335 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4337 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4338 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4339 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4340 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4346 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4347 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4350 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4351 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4352 IXGBE_MAX_JUMBO_FRAME_SIZE))
4353 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4354 IXGBE_MMW_SIZE_JUMBO_FRAME);
4356 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4357 IXGBE_MMW_SIZE_DEFAULT);
4359 /* Set RTTBCNRC of queue X */
4360 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4361 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4362 IXGBE_WRITE_FLUSH(hw);
4367 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4368 uint16_t tx_rate, uint64_t q_msk)
4370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371 struct ixgbe_vf_info *vfinfo =
4372 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4373 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4374 uint32_t queue_stride =
4375 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4376 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4377 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4378 uint16_t total_rate = 0;
4380 if (queue_end >= hw->mac.max_tx_queues)
4383 if (vfinfo != NULL) {
4384 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4387 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4389 total_rate += vfinfo[vf_idx].tx_rate[idx];
4394 /* Store tx_rate for this vf. */
4395 for (idx = 0; idx < nb_q_per_pool; idx++) {
4396 if (((uint64_t)0x1 << idx) & q_msk) {
4397 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4398 vfinfo[vf].tx_rate[idx] = tx_rate;
4399 total_rate += tx_rate;
4403 if (total_rate > dev->data->dev_link.link_speed) {
4405 * Reset stored TX rate of the VF if it causes exceed
4408 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4412 /* Set RTTBCNRC of each queue/pool for vf X */
4413 for (; queue_idx <= queue_end; queue_idx++) {
4415 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4423 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4424 __attribute__((unused)) uint32_t index,
4425 __attribute__((unused)) uint32_t pool)
4427 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4432 * operation. Trap this case to avoid exhausting the [very limited]
4433 * set of PF resources used to store VF MAC addresses.
4435 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4437 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4440 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4444 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4448 struct ether_addr *mac_addr;
4453 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4454 * not support the deletion of a given MAC address.
4455 * Instead, it imposes to delete all MAC addresses, then to add again
4456 * all MAC addresses with the exception of the one to be deleted.
4458 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4461 * Add again all MAC addresses, with the exception of the deleted one
4462 * and of the permanent MAC address.
4464 for (i = 0, mac_addr = dev->data->mac_addrs;
4465 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4466 /* Skip the deleted MAC address */
4469 /* Skip NULL MAC addresses */
4470 if (is_zero_ether_addr(mac_addr))
4472 /* Skip the permanent MAC address */
4473 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4475 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4478 "Adding again MAC address "
4479 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4481 mac_addr->addr_bytes[0],
4482 mac_addr->addr_bytes[1],
4483 mac_addr->addr_bytes[2],
4484 mac_addr->addr_bytes[3],
4485 mac_addr->addr_bytes[4],
4486 mac_addr->addr_bytes[5],
4492 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4494 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4499 #define MAC_TYPE_FILTER_SUP(type) do {\
4500 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4501 (type) != ixgbe_mac_X550)\
4506 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4507 struct rte_eth_syn_filter *filter,
4510 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4516 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4519 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4521 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4522 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4524 if (filter->hig_pri)
4525 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4527 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4529 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4531 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4533 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4534 IXGBE_WRITE_FLUSH(hw);
4539 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4540 struct rte_eth_syn_filter *filter)
4542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4545 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4546 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4547 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4554 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4555 enum rte_filter_op filter_op,
4558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561 MAC_TYPE_FILTER_SUP(hw->mac.type);
4563 if (filter_op == RTE_ETH_FILTER_NOP)
4567 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4572 switch (filter_op) {
4573 case RTE_ETH_FILTER_ADD:
4574 ret = ixgbe_syn_filter_set(dev,
4575 (struct rte_eth_syn_filter *)arg,
4578 case RTE_ETH_FILTER_DELETE:
4579 ret = ixgbe_syn_filter_set(dev,
4580 (struct rte_eth_syn_filter *)arg,
4583 case RTE_ETH_FILTER_GET:
4584 ret = ixgbe_syn_filter_get(dev,
4585 (struct rte_eth_syn_filter *)arg);
4588 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4597 static inline enum ixgbe_5tuple_protocol
4598 convert_protocol_type(uint8_t protocol_value)
4600 if (protocol_value == IPPROTO_TCP)
4601 return IXGBE_FILTER_PROTOCOL_TCP;
4602 else if (protocol_value == IPPROTO_UDP)
4603 return IXGBE_FILTER_PROTOCOL_UDP;
4604 else if (protocol_value == IPPROTO_SCTP)
4605 return IXGBE_FILTER_PROTOCOL_SCTP;
4607 return IXGBE_FILTER_PROTOCOL_NONE;
4611 * add a 5tuple filter
4614 * dev: Pointer to struct rte_eth_dev.
4615 * index: the index the filter allocates.
4616 * filter: ponter to the filter that will be added.
4617 * rx_queue: the queue id the filter assigned to.
4620 * - On success, zero.
4621 * - On failure, a negative value.
4624 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4625 struct ixgbe_5tuple_filter *filter)
4627 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4628 struct ixgbe_filter_info *filter_info =
4629 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4631 uint32_t ftqf, sdpqf;
4632 uint32_t l34timir = 0;
4633 uint8_t mask = 0xff;
4636 * look for an unused 5tuple filter index,
4637 * and insert the filter to list.
4639 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4640 idx = i / (sizeof(uint32_t) * NBBY);
4641 shift = i % (sizeof(uint32_t) * NBBY);
4642 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4643 filter_info->fivetuple_mask[idx] |= 1 << shift;
4645 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4651 if (i >= IXGBE_MAX_FTQF_FILTERS) {
4652 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4656 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4657 IXGBE_SDPQF_DSTPORT_SHIFT);
4658 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4660 ftqf = (uint32_t)(filter->filter_info.proto &
4661 IXGBE_FTQF_PROTOCOL_MASK);
4662 ftqf |= (uint32_t)((filter->filter_info.priority &
4663 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4664 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4665 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4666 if (filter->filter_info.dst_ip_mask == 0)
4667 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4668 if (filter->filter_info.src_port_mask == 0)
4669 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4670 if (filter->filter_info.dst_port_mask == 0)
4671 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4672 if (filter->filter_info.proto_mask == 0)
4673 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4674 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4675 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4676 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4678 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4679 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4680 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4681 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4683 l34timir |= IXGBE_L34T_IMIR_RESERVE;
4684 l34timir |= (uint32_t)(filter->queue <<
4685 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4686 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4691 * remove a 5tuple filter
4694 * dev: Pointer to struct rte_eth_dev.
4695 * filter: the pointer of the filter will be removed.
4698 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4699 struct ixgbe_5tuple_filter *filter)
4701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 struct ixgbe_filter_info *filter_info =
4703 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4704 uint16_t index = filter->index;
4706 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4707 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4708 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4711 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4712 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4713 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4714 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4715 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4719 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4721 struct ixgbe_hw *hw;
4722 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4724 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4726 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4729 /* refuse mtu that requires the support of scattered packets when this
4730 * feature has not been enabled before. */
4731 if (!dev->data->scattered_rx &&
4732 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4733 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4737 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4738 * request of the version 2.0 of the mailbox API.
4739 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4740 * of the mailbox API.
4741 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4742 * prior to 3.11.33 which contains the following change:
4743 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4745 ixgbevf_rlpml_set_vf(hw, max_frame);
4747 /* update max frame size */
4748 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4752 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
4753 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4757 static inline struct ixgbe_5tuple_filter *
4758 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4759 struct ixgbe_5tuple_filter_info *key)
4761 struct ixgbe_5tuple_filter *it;
4763 TAILQ_FOREACH(it, filter_list, entries) {
4764 if (memcmp(key, &it->filter_info,
4765 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4772 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4774 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4775 struct ixgbe_5tuple_filter_info *filter_info)
4777 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4778 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4779 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4782 switch (filter->dst_ip_mask) {
4784 filter_info->dst_ip_mask = 0;
4785 filter_info->dst_ip = filter->dst_ip;
4788 filter_info->dst_ip_mask = 1;
4791 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4795 switch (filter->src_ip_mask) {
4797 filter_info->src_ip_mask = 0;
4798 filter_info->src_ip = filter->src_ip;
4801 filter_info->src_ip_mask = 1;
4804 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4808 switch (filter->dst_port_mask) {
4810 filter_info->dst_port_mask = 0;
4811 filter_info->dst_port = filter->dst_port;
4814 filter_info->dst_port_mask = 1;
4817 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4821 switch (filter->src_port_mask) {
4823 filter_info->src_port_mask = 0;
4824 filter_info->src_port = filter->src_port;
4827 filter_info->src_port_mask = 1;
4830 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4834 switch (filter->proto_mask) {
4836 filter_info->proto_mask = 0;
4837 filter_info->proto =
4838 convert_protocol_type(filter->proto);
4841 filter_info->proto_mask = 1;
4844 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4848 filter_info->priority = (uint8_t)filter->priority;
4853 * add or delete a ntuple filter
4856 * dev: Pointer to struct rte_eth_dev.
4857 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4858 * add: if true, add filter, if false, remove filter
4861 * - On success, zero.
4862 * - On failure, a negative value.
4865 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4866 struct rte_eth_ntuple_filter *ntuple_filter,
4869 struct ixgbe_filter_info *filter_info =
4870 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4871 struct ixgbe_5tuple_filter_info filter_5tuple;
4872 struct ixgbe_5tuple_filter *filter;
4875 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4876 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4880 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4881 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4885 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4887 if (filter != NULL && add) {
4888 PMD_DRV_LOG(ERR, "filter exists.");
4891 if (filter == NULL && !add) {
4892 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4897 filter = rte_zmalloc("ixgbe_5tuple_filter",
4898 sizeof(struct ixgbe_5tuple_filter), 0);
4901 (void)rte_memcpy(&filter->filter_info,
4903 sizeof(struct ixgbe_5tuple_filter_info));
4904 filter->queue = ntuple_filter->queue;
4905 ret = ixgbe_add_5tuple_filter(dev, filter);
4911 ixgbe_remove_5tuple_filter(dev, filter);
4917 * get a ntuple filter
4920 * dev: Pointer to struct rte_eth_dev.
4921 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4924 * - On success, zero.
4925 * - On failure, a negative value.
4928 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4929 struct rte_eth_ntuple_filter *ntuple_filter)
4931 struct ixgbe_filter_info *filter_info =
4932 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4933 struct ixgbe_5tuple_filter_info filter_5tuple;
4934 struct ixgbe_5tuple_filter *filter;
4937 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4938 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4942 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4943 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4947 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4949 if (filter == NULL) {
4950 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4953 ntuple_filter->queue = filter->queue;
4958 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4959 * @dev: pointer to rte_eth_dev structure
4960 * @filter_op:operation will be taken.
4961 * @arg: a pointer to specific structure corresponding to the filter_op
4964 * - On success, zero.
4965 * - On failure, a negative value.
4968 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4969 enum rte_filter_op filter_op,
4972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4977 if (filter_op == RTE_ETH_FILTER_NOP)
4981 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4986 switch (filter_op) {
4987 case RTE_ETH_FILTER_ADD:
4988 ret = ixgbe_add_del_ntuple_filter(dev,
4989 (struct rte_eth_ntuple_filter *)arg,
4992 case RTE_ETH_FILTER_DELETE:
4993 ret = ixgbe_add_del_ntuple_filter(dev,
4994 (struct rte_eth_ntuple_filter *)arg,
4997 case RTE_ETH_FILTER_GET:
4998 ret = ixgbe_get_ntuple_filter(dev,
4999 (struct rte_eth_ntuple_filter *)arg);
5002 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5010 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5015 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5016 if (filter_info->ethertype_filters[i] == ethertype &&
5017 (filter_info->ethertype_mask & (1 << i)))
5024 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5029 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5030 if (!(filter_info->ethertype_mask & (1 << i))) {
5031 filter_info->ethertype_mask |= 1 << i;
5032 filter_info->ethertype_filters[i] = ethertype;
5040 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5043 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5045 filter_info->ethertype_mask &= ~(1 << idx);
5046 filter_info->ethertype_filters[idx] = 0;
5051 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5052 struct rte_eth_ethertype_filter *filter,
5055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056 struct ixgbe_filter_info *filter_info =
5057 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5062 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5065 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5066 filter->ether_type == ETHER_TYPE_IPv6) {
5067 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5068 " ethertype filter.", filter->ether_type);
5072 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5073 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5076 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5077 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5081 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5082 if (ret >= 0 && add) {
5083 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5084 filter->ether_type);
5087 if (ret < 0 && !add) {
5088 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5089 filter->ether_type);
5094 ret = ixgbe_ethertype_filter_insert(filter_info,
5095 filter->ether_type);
5097 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5100 etqf = IXGBE_ETQF_FILTER_EN;
5101 etqf |= (uint32_t)filter->ether_type;
5102 etqs |= (uint32_t)((filter->queue <<
5103 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5104 IXGBE_ETQS_RX_QUEUE);
5105 etqs |= IXGBE_ETQS_QUEUE_EN;
5107 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5111 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5112 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5113 IXGBE_WRITE_FLUSH(hw);
5119 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5120 struct rte_eth_ethertype_filter *filter)
5122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 struct ixgbe_filter_info *filter_info =
5124 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5125 uint32_t etqf, etqs;
5128 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5130 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5131 filter->ether_type);
5135 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5136 if (etqf & IXGBE_ETQF_FILTER_EN) {
5137 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5138 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5140 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5141 IXGBE_ETQS_RX_QUEUE_SHIFT;
5148 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5149 * @dev: pointer to rte_eth_dev structure
5150 * @filter_op:operation will be taken.
5151 * @arg: a pointer to specific structure corresponding to the filter_op
5154 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5155 enum rte_filter_op filter_op,
5158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161 MAC_TYPE_FILTER_SUP(hw->mac.type);
5163 if (filter_op == RTE_ETH_FILTER_NOP)
5167 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5172 switch (filter_op) {
5173 case RTE_ETH_FILTER_ADD:
5174 ret = ixgbe_add_del_ethertype_filter(dev,
5175 (struct rte_eth_ethertype_filter *)arg,
5178 case RTE_ETH_FILTER_DELETE:
5179 ret = ixgbe_add_del_ethertype_filter(dev,
5180 (struct rte_eth_ethertype_filter *)arg,
5183 case RTE_ETH_FILTER_GET:
5184 ret = ixgbe_get_ethertype_filter(dev,
5185 (struct rte_eth_ethertype_filter *)arg);
5188 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5196 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5197 enum rte_filter_type filter_type,
5198 enum rte_filter_op filter_op,
5203 switch (filter_type) {
5204 case RTE_ETH_FILTER_NTUPLE:
5205 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5207 case RTE_ETH_FILTER_ETHERTYPE:
5208 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5210 case RTE_ETH_FILTER_SYN:
5211 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5213 case RTE_ETH_FILTER_FDIR:
5214 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5217 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5226 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5227 u8 **mc_addr_ptr, u32 *vmdq)
5232 mc_addr = *mc_addr_ptr;
5233 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5238 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5239 struct ether_addr *mc_addr_set,
5240 uint32_t nb_mc_addr)
5242 struct ixgbe_hw *hw;
5245 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246 mc_addr_list = (u8 *)mc_addr_set;
5247 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5248 ixgbe_dev_addr_list_itr, TRUE);
5252 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5258 /* Enable system time for platforms where it isn't on by default. */
5259 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5260 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5261 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5263 /* Start incrementing the register used to timestamp PTP packets. */
5264 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5266 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5267 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5269 IXGBE_ETQF_FILTER_EN |
5272 /* Enable timestamping of received PTP packets. */
5273 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5274 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5275 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5277 /* Enable timestamping of transmitted PTP packets. */
5278 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5279 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5280 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5286 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291 /* Disable timestamping of transmitted PTP packets. */
5292 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5293 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5294 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5296 /* Disable timestamping of received PTP packets. */
5297 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5298 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5299 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5301 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5302 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5304 /* Stop incrementating the System Time registers. */
5305 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5311 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5312 struct timespec *timestamp,
5313 uint32_t flags __rte_unused)
5315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5316 uint32_t tsync_rxctl;
5320 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5321 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5324 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5325 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5327 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5328 timestamp->tv_nsec = 0;
5334 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5335 struct timespec *timestamp)
5337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338 uint32_t tsync_txctl;
5342 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5343 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5346 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5347 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5349 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5350 timestamp->tv_nsec = 0;
5356 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5361 const struct reg_info *reg_group;
5362 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5363 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5365 while ((reg_group = reg_set[g_ind++]))
5366 count += ixgbe_regs_group_count(reg_group);
5372 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5376 const struct reg_info *reg_group;
5378 while ((reg_group = ixgbevf_regs[g_ind++]))
5379 count += ixgbe_regs_group_count(reg_group);
5385 ixgbe_get_regs(struct rte_eth_dev *dev,
5386 struct rte_dev_reg_info *regs)
5388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389 uint32_t *data = regs->data;
5392 const struct reg_info *reg_group;
5393 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5394 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5396 /* Support only full register dump */
5397 if ((regs->length == 0) ||
5398 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5399 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5401 while ((reg_group = reg_set[g_ind++]))
5402 count += ixgbe_read_regs_group(dev, &data[count],
5411 ixgbevf_get_regs(struct rte_eth_dev *dev,
5412 struct rte_dev_reg_info *regs)
5414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415 uint32_t *data = regs->data;
5418 const struct reg_info *reg_group;
5420 /* Support only full register dump */
5421 if ((regs->length == 0) ||
5422 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5423 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5425 while ((reg_group = ixgbevf_regs[g_ind++]))
5426 count += ixgbe_read_regs_group(dev, &data[count],
5435 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5439 /* Return unit is byte count */
5440 return hw->eeprom.word_size * 2;
5444 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5445 struct rte_dev_eeprom_info *in_eeprom)
5447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5449 uint16_t *data = in_eeprom->data;
5452 first = in_eeprom->offset >> 1;
5453 length = in_eeprom->length >> 1;
5454 if ((first >= hw->eeprom.word_size) ||
5455 ((first + length) >= hw->eeprom.word_size))
5458 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5460 return eeprom->ops.read_buffer(hw, first, length, data);
5464 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5465 struct rte_dev_eeprom_info *in_eeprom)
5467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5469 uint16_t *data = in_eeprom->data;
5472 first = in_eeprom->offset >> 1;
5473 length = in_eeprom->length >> 1;
5474 if ((first >= hw->eeprom.word_size) ||
5475 ((first + length) >= hw->eeprom.word_size))
5478 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5480 return eeprom->ops.write_buffer(hw, first, length, data);
5483 static struct rte_driver rte_ixgbe_driver = {
5485 .init = rte_ixgbe_pmd_init,
5488 static struct rte_driver rte_ixgbevf_driver = {
5490 .init = rte_ixgbevf_pmd_init,
5493 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5494 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);