4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
64 #include <rte_security_driver.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
187 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
188 uint64_t *values, unsigned int n);
189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
191 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
192 struct rte_eth_xstat_name *xstats_names,
194 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, unsigned limit);
196 static int ixgbe_dev_xstats_get_names_by_id(
197 struct rte_eth_dev *dev,
198 struct rte_eth_xstat_name *xstats_names,
201 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
205 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
207 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
210 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
211 struct rte_eth_dev_info *dev_info);
212 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
214 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
215 uint16_t vlan_id, int on);
216 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
217 enum rte_vlan_type vlan_type,
219 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
220 uint16_t queue, bool on);
221 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
223 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
224 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
226 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
227 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
230 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
231 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
232 struct rte_eth_fc_conf *fc_conf);
233 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
234 struct rte_eth_fc_conf *fc_conf);
235 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
236 struct rte_eth_pfc_conf *pfc_conf);
237 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
241 struct rte_eth_rss_reta_entry64 *reta_conf,
243 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
244 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
245 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
248 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
249 struct rte_intr_handle *handle);
250 static void ixgbe_dev_interrupt_handler(void *param);
251 static void ixgbe_dev_interrupt_delayed_handler(void *param);
252 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
253 uint32_t index, uint32_t pool);
254 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
255 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
256 struct ether_addr *mac_addr);
257 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
258 static bool is_device_supported(struct rte_eth_dev *dev,
259 struct rte_pci_driver *drv);
261 /* For Virtual Function support */
262 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
263 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
264 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
266 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
267 int wait_to_complete);
268 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
269 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
270 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
271 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
272 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
273 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
274 struct rte_eth_stats *stats);
275 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
276 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
277 uint16_t vlan_id, int on);
278 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
279 uint16_t queue, int on);
280 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
282 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
284 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
286 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
287 uint8_t queue, uint8_t msix_vector);
288 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
289 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
290 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
292 /* For Eth VMDQ APIs support */
293 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
294 ether_addr * mac_addr, uint8_t on);
295 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
296 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
297 struct rte_eth_mirror_conf *mirror_conf,
298 uint8_t rule_id, uint8_t on);
299 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
301 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
303 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
305 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
306 uint8_t queue, uint8_t msix_vector);
307 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
309 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
310 struct ether_addr *mac_addr,
311 uint32_t index, uint32_t pool);
312 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
313 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
314 struct ether_addr *mac_addr);
315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
316 struct rte_eth_syn_filter *filter);
317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ntuple_filter *filter);
329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
330 enum rte_filter_op filter_op,
332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ethertype_filter *filter);
334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
335 enum rte_filter_type filter_type,
336 enum rte_filter_op filter_op,
338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
341 struct ether_addr *mc_addr_set,
342 uint32_t nb_mc_addr);
343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
344 struct rte_eth_dcb_info *dcb_info);
346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
351 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
353 struct rte_dev_eeprom_info *eeprom);
355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
357 struct rte_dev_reg_info *regs);
359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp,
364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
368 struct timespec *timestamp);
369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
370 const struct timespec *timestamp);
371 static void ixgbevf_dev_interrupt_handler(void *param);
373 static int ixgbe_dev_l2_tunnel_eth_type_conf
374 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
375 static int ixgbe_dev_l2_tunnel_offload_set
376 (struct rte_eth_dev *dev,
377 struct rte_eth_l2_tunnel_conf *l2_tunnel,
380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
381 enum rte_filter_op filter_op,
384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
389 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
392 * Define VF Stats MACRO for Non "cleared on read" register
394 #define UPDATE_VF_STAT(reg, last, cur) \
396 uint32_t latest = IXGBE_READ_REG(hw, reg); \
397 cur += (latest - last) & UINT_MAX; \
401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
403 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
404 u64 new_msb = IXGBE_READ_REG(hw, msb); \
405 u64 latest = ((new_msb << 32) | new_lsb); \
406 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
410 #define IXGBE_SET_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] |= 1 << bit;\
416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] &= ~(1 << bit);\
422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (r) = (h)->bitmap[idx] >> bit & 1;\
429 * The set of PCI devices this driver supports
431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
483 { .vendor_id = 0, /* sentinel */ },
487 * The set of PCI devices this driver supports (for 82599 VF)
489 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
500 { .vendor_id = 0, /* sentinel */ },
503 static const struct rte_eth_desc_lim rx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_RXD_ALIGN,
509 static const struct rte_eth_desc_lim tx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_TXD_ALIGN,
513 .nb_seg_max = IXGBE_TX_MAX_SEG,
514 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
517 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
518 .dev_configure = ixgbe_dev_configure,
519 .dev_start = ixgbe_dev_start,
520 .dev_stop = ixgbe_dev_stop,
521 .dev_set_link_up = ixgbe_dev_set_link_up,
522 .dev_set_link_down = ixgbe_dev_set_link_down,
523 .dev_close = ixgbe_dev_close,
524 .dev_reset = ixgbe_dev_reset,
525 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
526 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
527 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
528 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
529 .link_update = ixgbe_dev_link_update,
530 .stats_get = ixgbe_dev_stats_get,
531 .xstats_get = ixgbe_dev_xstats_get,
532 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
533 .stats_reset = ixgbe_dev_stats_reset,
534 .xstats_reset = ixgbe_dev_xstats_reset,
535 .xstats_get_names = ixgbe_dev_xstats_get_names,
536 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
557 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
558 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
559 .tx_queue_release = ixgbe_dev_tx_queue_release,
560 .dev_led_on = ixgbe_dev_led_on,
561 .dev_led_off = ixgbe_dev_led_off,
562 .flow_ctrl_get = ixgbe_flow_ctrl_get,
563 .flow_ctrl_set = ixgbe_flow_ctrl_set,
564 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
565 .mac_addr_add = ixgbe_add_rar,
566 .mac_addr_remove = ixgbe_remove_rar,
567 .mac_addr_set = ixgbe_set_default_mac_addr,
568 .uc_hash_table_set = ixgbe_uc_hash_table_set,
569 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
570 .mirror_rule_set = ixgbe_mirror_rule_set,
571 .mirror_rule_reset = ixgbe_mirror_rule_reset,
572 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
573 .reta_update = ixgbe_dev_rss_reta_update,
574 .reta_query = ixgbe_dev_rss_reta_query,
575 .rss_hash_update = ixgbe_dev_rss_hash_update,
576 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
577 .filter_ctrl = ixgbe_dev_filter_ctrl,
578 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
579 .rxq_info_get = ixgbe_rxq_info_get,
580 .txq_info_get = ixgbe_txq_info_get,
581 .timesync_enable = ixgbe_timesync_enable,
582 .timesync_disable = ixgbe_timesync_disable,
583 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
584 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
585 .get_reg = ixgbe_get_regs,
586 .get_eeprom_length = ixgbe_get_eeprom_length,
587 .get_eeprom = ixgbe_get_eeprom,
588 .set_eeprom = ixgbe_set_eeprom,
589 .get_dcb_info = ixgbe_dev_get_dcb_info,
590 .timesync_adjust_time = ixgbe_timesync_adjust_time,
591 .timesync_read_time = ixgbe_timesync_read_time,
592 .timesync_write_time = ixgbe_timesync_write_time,
593 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
594 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
595 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
596 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
597 .tm_ops_get = ixgbe_tm_ops_get,
601 * dev_ops for virtual function, bare necessities for basic vf
602 * operation have been implemented
604 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
605 .dev_configure = ixgbevf_dev_configure,
606 .dev_start = ixgbevf_dev_start,
607 .dev_stop = ixgbevf_dev_stop,
608 .link_update = ixgbevf_dev_link_update,
609 .stats_get = ixgbevf_dev_stats_get,
610 .xstats_get = ixgbevf_dev_xstats_get,
611 .stats_reset = ixgbevf_dev_stats_reset,
612 .xstats_reset = ixgbevf_dev_stats_reset,
613 .xstats_get_names = ixgbevf_dev_xstats_get_names,
614 .dev_close = ixgbevf_dev_close,
615 .dev_reset = ixgbevf_dev_reset,
616 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
617 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
618 .dev_infos_get = ixgbevf_dev_info_get,
619 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
620 .mtu_set = ixgbevf_dev_set_mtu,
621 .vlan_filter_set = ixgbevf_vlan_filter_set,
622 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
623 .vlan_offload_set = ixgbevf_vlan_offload_set,
624 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
625 .rx_queue_release = ixgbe_dev_rx_queue_release,
626 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
627 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
628 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
629 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
630 .tx_queue_release = ixgbe_dev_tx_queue_release,
631 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
632 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
633 .mac_addr_add = ixgbevf_add_mac_addr,
634 .mac_addr_remove = ixgbevf_remove_mac_addr,
635 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
636 .rxq_info_get = ixgbe_rxq_info_get,
637 .txq_info_get = ixgbe_txq_info_get,
638 .mac_addr_set = ixgbevf_set_default_mac_addr,
639 .get_reg = ixgbevf_get_regs,
640 .reta_update = ixgbe_dev_rss_reta_update,
641 .reta_query = ixgbe_dev_rss_reta_query,
642 .rss_hash_update = ixgbe_dev_rss_hash_update,
643 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
646 /* store statistics names and its offset in stats structure */
647 struct rte_ixgbe_xstats_name_off {
648 char name[RTE_ETH_XSTATS_NAME_SIZE];
652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
653 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
654 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
655 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
656 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
657 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
658 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
659 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
660 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
661 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
662 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
663 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
664 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
665 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
666 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
667 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
672 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
673 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
674 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
675 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
676 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
677 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
678 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
679 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
680 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
681 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
682 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
683 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
684 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
685 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
686 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
687 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
689 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
692 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
693 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
694 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
696 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
698 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
709 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
710 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
711 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
713 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
714 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
715 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
716 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
717 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
719 {"rx_fcoe_no_direct_data_placement_ext_buff",
720 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
722 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
724 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
734 sizeof(rte_ixgbe_stats_strings[0]))
736 /* MACsec statistics */
737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
738 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
740 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
741 out_pkts_encrypted)},
742 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_protected)},
744 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
745 out_octets_encrypted)},
746 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
747 out_octets_protected)},
748 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
755 in_pkts_unknownsci)},
756 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
757 in_octets_decrypted)},
758 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
759 in_octets_validated)},
760 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
775 in_pkts_notusingsa)},
778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
779 sizeof(rte_ixgbe_macsec_strings[0]))
781 /* Per-queue statistics */
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
783 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
784 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
785 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
786 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
790 sizeof(rte_ixgbe_rxq_strings[0]))
791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
794 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
795 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
796 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
801 sizeof(rte_ixgbe_txq_strings[0]))
802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
805 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
809 sizeof(rte_ixgbevf_stats_strings[0]))
812 * Atomically reads the link status information from global
813 * structure rte_eth_dev.
816 * - Pointer to the structure rte_eth_dev to read from.
817 * - Pointer to the buffer to be saved with the link status.
820 * - On success, zero.
821 * - On failure, negative value.
824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
825 struct rte_eth_link *link)
827 struct rte_eth_link *dst = link;
828 struct rte_eth_link *src = &(dev->data->dev_link);
830 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
831 *(uint64_t *)src) == 0)
838 * Atomically writes the link status information into global
839 * structure rte_eth_dev.
842 * - Pointer to the structure rte_eth_dev to read from.
843 * - Pointer to the buffer to be saved with the link status.
846 * - On success, zero.
847 * - On failure, negative value.
850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
851 struct rte_eth_link *link)
853 struct rte_eth_link *dst = &(dev->data->dev_link);
854 struct rte_eth_link *src = link;
856 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
857 *(uint64_t *)src) == 0)
864 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
867 ixgbe_is_sfp(struct ixgbe_hw *hw)
869 switch (hw->phy.type) {
870 case ixgbe_phy_sfp_avago:
871 case ixgbe_phy_sfp_ftl:
872 case ixgbe_phy_sfp_intel:
873 case ixgbe_phy_sfp_unknown:
874 case ixgbe_phy_sfp_passive_tyco:
875 case ixgbe_phy_sfp_passive_unknown:
882 static inline int32_t
883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
888 status = ixgbe_reset_hw(hw);
890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
894 IXGBE_WRITE_FLUSH(hw);
896 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
897 status = IXGBE_SUCCESS;
902 ixgbe_enable_intr(struct rte_eth_dev *dev)
904 struct ixgbe_interrupt *intr =
905 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
906 struct ixgbe_hw *hw =
907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
909 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
910 IXGBE_WRITE_FLUSH(hw);
914 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
917 ixgbe_disable_intr(struct ixgbe_hw *hw)
919 PMD_INIT_FUNC_TRACE();
921 if (hw->mac.type == ixgbe_mac_82598EB) {
922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
928 IXGBE_WRITE_FLUSH(hw);
932 * This function resets queue statistics mapping registers.
933 * From Niantic datasheet, Initialization of Statistics section:
934 * "...if software requires the queue counters, the RQSMR and TQSM registers
935 * must be re-programmed following a device reset.
938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
942 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
943 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
960 struct ixgbe_stat_mapping_registers *stat_mappings =
961 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
962 uint32_t qsmr_mask = 0;
963 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
967 if ((hw->mac.type != ixgbe_mac_82599EB) &&
968 (hw->mac.type != ixgbe_mac_X540) &&
969 (hw->mac.type != ixgbe_mac_X550) &&
970 (hw->mac.type != ixgbe_mac_X550EM_x) &&
971 (hw->mac.type != ixgbe_mac_X550EM_a))
974 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
975 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
978 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
979 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
980 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
983 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
985 /* Now clear any previous stat_idx set */
986 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
988 stat_mappings->tqsm[n] &= ~clearing_mask;
990 stat_mappings->rqsmr[n] &= ~clearing_mask;
992 q_map = (uint32_t)stat_idx;
993 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
994 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
996 stat_mappings->tqsm[n] |= qsmr_mask;
998 stat_mappings->rqsmr[n] |= qsmr_mask;
1000 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002 queue_id, stat_idx);
1003 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006 /* Now write the mapping in the appropriate register */
1008 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009 stat_mappings->rqsmr[n], n);
1010 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013 stat_mappings->tqsm[n], n);
1014 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 struct ixgbe_stat_mapping_registers *stat_mappings =
1023 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 /* write whatever was in stat mapping table to the NIC */
1028 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1033 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1041 struct ixgbe_dcb_tc_config *tc;
1042 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046 for (i = 0; i < dcb_max_tc; i++) {
1047 tc = &dcb_config->tc_config[i];
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050 (uint8_t)(100/dcb_max_tc + (i & 1));
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->pfc = ixgbe_dcb_pfc_disabled;
1057 /* Initialize default user to priority mapping, UPx->TC0 */
1058 tc = &dcb_config->tc_config[0];
1059 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066 dcb_config->pfc_mode_enable = false;
1067 dcb_config->vt_mode = true;
1068 dcb_config->round_robin_enable = false;
1069 /* support all DCB capabilities in 82599 */
1070 dcb_config->support.capabilities = 0xFF;
1072 /*we only support 4 Tcs for X540, X550 */
1073 if (hw->mac.type == ixgbe_mac_X540 ||
1074 hw->mac.type == ixgbe_mac_X550 ||
1075 hw->mac.type == ixgbe_mac_X550EM_x ||
1076 hw->mac.type == ixgbe_mac_X550EM_a) {
1077 dcb_config->num_tcs.pg_tcs = 4;
1078 dcb_config->num_tcs.pfc_tcs = 4;
1083 * Ensure that all locks are released before first NVM or PHY access
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 * Phy lock should not fail in this early stage. If this is the case,
1092 * it is due to an improper exit of the application.
1093 * So force the release of the faulty lock. Release of common lock
1094 * is done automatically by swfw_sync function.
1096 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100 ixgbe_release_swfw_semaphore(hw, mask);
1103 * These ones are more tricky since they are common to all ports; but
1104 * swfw_sync retries last long enough (1s) to be almost sure that if
1105 * lock can not be taken it is due to an improper lock of the
1108 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112 ixgbe_release_swfw_semaphore(hw, mask);
1116 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117 * It returns 0 on success.
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124 struct ixgbe_hw *hw =
1125 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126 struct ixgbe_vfta *shadow_vfta =
1127 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128 struct ixgbe_hwstrip *hwstrip =
1129 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130 struct ixgbe_dcb_config *dcb_config =
1131 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132 struct ixgbe_filter_info *filter_info =
1133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134 struct ixgbe_bw_conf *bw_conf =
1135 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140 PMD_INIT_FUNC_TRACE();
1142 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148 * For secondary processes, we don't initialise any further as primary
1149 * has already done this work. Only check we don't need a different
1150 * RX and TX function.
1152 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153 struct ixgbe_tx_queue *txq;
1154 /* TX queue function in primary, set by last queue initialized
1155 * Tx queue may not initialized by primary process
1157 if (eth_dev->data->tx_queues) {
1158 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159 ixgbe_set_tx_function(eth_dev, txq);
1161 /* Use default TX function if we get here */
1162 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163 "Using default TX function.");
1166 ixgbe_set_rx_function(eth_dev);
1171 /* Initialize security_ctx only for primary process*/
1172 eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1173 if (eth_dev->security_ctx == NULL)
1176 rte_eth_copy_pci_info(eth_dev, pci_dev);
1177 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1179 /* Vendor and Device ID need to be set before init of shared code */
1180 hw->device_id = pci_dev->id.device_id;
1181 hw->vendor_id = pci_dev->id.vendor_id;
1182 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1183 hw->allow_unsupported_sfp = 1;
1185 /* Initialize the shared code (base driver) */
1186 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1187 diag = ixgbe_bypass_init_shared_code(hw);
1189 diag = ixgbe_init_shared_code(hw);
1190 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1192 if (diag != IXGBE_SUCCESS) {
1193 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1197 /* pick up the PCI bus settings for reporting later */
1198 ixgbe_get_bus_info(hw);
1200 /* Unlock any pending hardware semaphore */
1201 ixgbe_swfw_lock_reset(hw);
1203 /* Initialize DCB configuration*/
1204 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1205 ixgbe_dcb_init(hw, dcb_config);
1206 /* Get Hardware Flow Control setting */
1207 hw->fc.requested_mode = ixgbe_fc_full;
1208 hw->fc.current_mode = ixgbe_fc_full;
1209 hw->fc.pause_time = IXGBE_FC_PAUSE;
1210 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1211 hw->fc.low_water[i] = IXGBE_FC_LO;
1212 hw->fc.high_water[i] = IXGBE_FC_HI;
1214 hw->fc.send_xon = 1;
1216 /* Make sure we have a good EEPROM before we read from it */
1217 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1218 if (diag != IXGBE_SUCCESS) {
1219 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1223 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1224 diag = ixgbe_bypass_init_hw(hw);
1226 diag = ixgbe_init_hw(hw);
1227 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1230 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1231 * is called too soon after the kernel driver unbinding/binding occurs.
1232 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1233 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1234 * also called. See ixgbe_identify_phy_82599(). The reason for the
1235 * failure is not known, and only occuts when virtualisation features
1236 * are disabled in the bios. A delay of 100ms was found to be enough by
1237 * trial-and-error, and is doubled to be safe.
1239 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1241 diag = ixgbe_init_hw(hw);
1244 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1245 diag = IXGBE_SUCCESS;
1247 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1248 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1249 "LOM. Please be aware there may be issues associated "
1250 "with your hardware.");
1251 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1252 "please contact your Intel or hardware representative "
1253 "who provided you with this hardware.");
1254 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1255 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1257 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1261 /* Reset the hw statistics */
1262 ixgbe_dev_stats_reset(eth_dev);
1264 /* disable interrupt */
1265 ixgbe_disable_intr(hw);
1267 /* reset mappings for queue statistics hw counters*/
1268 ixgbe_reset_qstat_mappings(hw);
1270 /* Allocate memory for storing MAC addresses */
1271 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1272 hw->mac.num_rar_entries, 0);
1273 if (eth_dev->data->mac_addrs == NULL) {
1275 "Failed to allocate %u bytes needed to store "
1277 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1280 /* Copy the permanent MAC address */
1281 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1282 ð_dev->data->mac_addrs[0]);
1284 /* Allocate memory for storing hash filter MAC addresses */
1285 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1286 IXGBE_VMDQ_NUM_UC_MAC, 0);
1287 if (eth_dev->data->hash_mac_addrs == NULL) {
1289 "Failed to allocate %d bytes needed to store MAC addresses",
1290 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1294 /* initialize the vfta */
1295 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1297 /* initialize the hw strip bitmap*/
1298 memset(hwstrip, 0, sizeof(*hwstrip));
1300 /* initialize PF if max_vfs not zero */
1301 ixgbe_pf_host_init(eth_dev);
1303 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1304 /* let hardware know driver is loaded */
1305 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1306 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1307 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1308 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1309 IXGBE_WRITE_FLUSH(hw);
1311 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1312 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1313 (int) hw->mac.type, (int) hw->phy.type,
1314 (int) hw->phy.sfp_type);
1316 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1317 (int) hw->mac.type, (int) hw->phy.type);
1319 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1320 eth_dev->data->port_id, pci_dev->id.vendor_id,
1321 pci_dev->id.device_id);
1323 rte_intr_callback_register(intr_handle,
1324 ixgbe_dev_interrupt_handler, eth_dev);
1326 /* enable uio/vfio intr/eventfd mapping */
1327 rte_intr_enable(intr_handle);
1329 /* enable support intr */
1330 ixgbe_enable_intr(eth_dev);
1332 /* initialize filter info */
1333 memset(filter_info, 0,
1334 sizeof(struct ixgbe_filter_info));
1336 /* initialize 5tuple filter list */
1337 TAILQ_INIT(&filter_info->fivetuple_list);
1339 /* initialize flow director filter list & hash */
1340 ixgbe_fdir_filter_init(eth_dev);
1342 /* initialize l2 tunnel filter list & hash */
1343 ixgbe_l2_tn_filter_init(eth_dev);
1345 /* initialize flow filter lists */
1346 ixgbe_filterlist_init();
1348 /* initialize bandwidth configuration info */
1349 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1351 /* initialize Traffic Manager configuration */
1352 ixgbe_tm_conf_init(eth_dev);
1358 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1360 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1361 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1362 struct ixgbe_hw *hw;
1364 PMD_INIT_FUNC_TRACE();
1366 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1369 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1371 if (hw->adapter_stopped == 0)
1372 ixgbe_dev_close(eth_dev);
1374 eth_dev->dev_ops = NULL;
1375 eth_dev->rx_pkt_burst = NULL;
1376 eth_dev->tx_pkt_burst = NULL;
1378 /* Unlock any pending hardware semaphore */
1379 ixgbe_swfw_lock_reset(hw);
1381 /* disable uio intr before callback unregister */
1382 rte_intr_disable(intr_handle);
1383 rte_intr_callback_unregister(intr_handle,
1384 ixgbe_dev_interrupt_handler, eth_dev);
1386 /* uninitialize PF if max_vfs not zero */
1387 ixgbe_pf_host_uninit(eth_dev);
1389 rte_free(eth_dev->data->mac_addrs);
1390 eth_dev->data->mac_addrs = NULL;
1392 rte_free(eth_dev->data->hash_mac_addrs);
1393 eth_dev->data->hash_mac_addrs = NULL;
1395 /* remove all the fdir filters & hash */
1396 ixgbe_fdir_filter_uninit(eth_dev);
1398 /* remove all the L2 tunnel filters & hash */
1399 ixgbe_l2_tn_filter_uninit(eth_dev);
1401 /* Remove all ntuple filters of the device */
1402 ixgbe_ntuple_filter_uninit(eth_dev);
1404 /* clear all the filters list */
1405 ixgbe_filterlist_flush();
1407 /* Remove all Traffic Manager configuration */
1408 ixgbe_tm_conf_uninit(eth_dev);
1410 rte_free(eth_dev->security_ctx);
1415 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1417 struct ixgbe_filter_info *filter_info =
1418 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1419 struct ixgbe_5tuple_filter *p_5tuple;
1421 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1422 TAILQ_REMOVE(&filter_info->fivetuple_list,
1427 memset(filter_info->fivetuple_mask, 0,
1428 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1433 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1435 struct ixgbe_hw_fdir_info *fdir_info =
1436 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1437 struct ixgbe_fdir_filter *fdir_filter;
1439 if (fdir_info->hash_map)
1440 rte_free(fdir_info->hash_map);
1441 if (fdir_info->hash_handle)
1442 rte_hash_free(fdir_info->hash_handle);
1444 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1445 TAILQ_REMOVE(&fdir_info->fdir_list,
1448 rte_free(fdir_filter);
1454 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_l2_tn_info *l2_tn_info =
1457 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458 struct ixgbe_l2_tn_filter *l2_tn_filter;
1460 if (l2_tn_info->hash_map)
1461 rte_free(l2_tn_info->hash_map);
1462 if (l2_tn_info->hash_handle)
1463 rte_hash_free(l2_tn_info->hash_handle);
1465 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1466 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1469 rte_free(l2_tn_filter);
1475 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1477 struct ixgbe_hw_fdir_info *fdir_info =
1478 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1479 char fdir_hash_name[RTE_HASH_NAMESIZE];
1480 struct rte_hash_parameters fdir_hash_params = {
1481 .name = fdir_hash_name,
1482 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1483 .key_len = sizeof(union ixgbe_atr_input),
1484 .hash_func = rte_hash_crc,
1485 .hash_func_init_val = 0,
1486 .socket_id = rte_socket_id(),
1489 TAILQ_INIT(&fdir_info->fdir_list);
1490 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1491 "fdir_%s", eth_dev->device->name);
1492 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1493 if (!fdir_info->hash_handle) {
1494 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1497 fdir_info->hash_map = rte_zmalloc("ixgbe",
1498 sizeof(struct ixgbe_fdir_filter *) *
1499 IXGBE_MAX_FDIR_FILTER_NUM,
1501 if (!fdir_info->hash_map) {
1503 "Failed to allocate memory for fdir hash map!");
1506 fdir_info->mask_added = FALSE;
1511 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1513 struct ixgbe_l2_tn_info *l2_tn_info =
1514 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1515 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1516 struct rte_hash_parameters l2_tn_hash_params = {
1517 .name = l2_tn_hash_name,
1518 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1519 .key_len = sizeof(struct ixgbe_l2_tn_key),
1520 .hash_func = rte_hash_crc,
1521 .hash_func_init_val = 0,
1522 .socket_id = rte_socket_id(),
1525 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1526 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1527 "l2_tn_%s", eth_dev->device->name);
1528 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1529 if (!l2_tn_info->hash_handle) {
1530 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1533 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1534 sizeof(struct ixgbe_l2_tn_filter *) *
1535 IXGBE_MAX_L2_TN_FILTER_NUM,
1537 if (!l2_tn_info->hash_map) {
1539 "Failed to allocate memory for L2 TN hash map!");
1542 l2_tn_info->e_tag_en = FALSE;
1543 l2_tn_info->e_tag_fwd_en = FALSE;
1544 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1549 * Negotiate mailbox API version with the PF.
1550 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1551 * Then we try to negotiate starting with the most recent one.
1552 * If all negotiation attempts fail, then we will proceed with
1553 * the default one (ixgbe_mbox_api_10).
1556 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1560 /* start with highest supported, proceed down */
1561 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1568 i != RTE_DIM(sup_ver) &&
1569 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1575 generate_random_mac_addr(struct ether_addr *mac_addr)
1579 /* Set Organizationally Unique Identifier (OUI) prefix. */
1580 mac_addr->addr_bytes[0] = 0x00;
1581 mac_addr->addr_bytes[1] = 0x09;
1582 mac_addr->addr_bytes[2] = 0xC0;
1583 /* Force indication of locally assigned MAC address. */
1584 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1585 /* Generate the last 3 bytes of the MAC address with a random number. */
1586 random = rte_rand();
1587 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1591 * Virtual Function device init
1594 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1600 struct ixgbe_hw *hw =
1601 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1602 struct ixgbe_vfta *shadow_vfta =
1603 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1604 struct ixgbe_hwstrip *hwstrip =
1605 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1606 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1608 PMD_INIT_FUNC_TRACE();
1610 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1611 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1612 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1614 /* for secondary processes, we don't initialise any further as primary
1615 * has already done this work. Only check we don't need a different
1618 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1619 struct ixgbe_tx_queue *txq;
1620 /* TX queue function in primary, set by last queue initialized
1621 * Tx queue may not initialized by primary process
1623 if (eth_dev->data->tx_queues) {
1624 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1625 ixgbe_set_tx_function(eth_dev, txq);
1627 /* Use default TX function if we get here */
1628 PMD_INIT_LOG(NOTICE,
1629 "No TX queues configured yet. Using default TX function.");
1632 ixgbe_set_rx_function(eth_dev);
1637 rte_eth_copy_pci_info(eth_dev, pci_dev);
1638 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1640 hw->device_id = pci_dev->id.device_id;
1641 hw->vendor_id = pci_dev->id.vendor_id;
1642 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1644 /* initialize the vfta */
1645 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1647 /* initialize the hw strip bitmap*/
1648 memset(hwstrip, 0, sizeof(*hwstrip));
1650 /* Initialize the shared code (base driver) */
1651 diag = ixgbe_init_shared_code(hw);
1652 if (diag != IXGBE_SUCCESS) {
1653 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1657 /* init_mailbox_params */
1658 hw->mbx.ops.init_params(hw);
1660 /* Reset the hw statistics */
1661 ixgbevf_dev_stats_reset(eth_dev);
1663 /* Disable the interrupts for VF */
1664 ixgbevf_intr_disable(hw);
1666 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1667 diag = hw->mac.ops.reset_hw(hw);
1670 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1671 * the underlying PF driver has not assigned a MAC address to the VF.
1672 * In this case, assign a random MAC address.
1674 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1675 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1679 /* negotiate mailbox API version to use with the PF. */
1680 ixgbevf_negotiate_api(hw);
1682 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1683 ixgbevf_get_queues(hw, &tcs, &tc);
1685 /* Allocate memory for storing MAC addresses */
1686 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1687 hw->mac.num_rar_entries, 0);
1688 if (eth_dev->data->mac_addrs == NULL) {
1690 "Failed to allocate %u bytes needed to store "
1692 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1696 /* Generate a random MAC address, if none was assigned by PF. */
1697 if (is_zero_ether_addr(perm_addr)) {
1698 generate_random_mac_addr(perm_addr);
1699 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1701 rte_free(eth_dev->data->mac_addrs);
1702 eth_dev->data->mac_addrs = NULL;
1705 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1706 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1707 "%02x:%02x:%02x:%02x:%02x:%02x",
1708 perm_addr->addr_bytes[0],
1709 perm_addr->addr_bytes[1],
1710 perm_addr->addr_bytes[2],
1711 perm_addr->addr_bytes[3],
1712 perm_addr->addr_bytes[4],
1713 perm_addr->addr_bytes[5]);
1716 /* Copy the permanent MAC address */
1717 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1719 /* reset the hardware with the new settings */
1720 diag = hw->mac.ops.start_hw(hw);
1726 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1730 rte_intr_callback_register(intr_handle,
1731 ixgbevf_dev_interrupt_handler, eth_dev);
1732 rte_intr_enable(intr_handle);
1733 ixgbevf_intr_enable(hw);
1735 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1736 eth_dev->data->port_id, pci_dev->id.vendor_id,
1737 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1742 /* Virtual Function device uninit */
1745 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1747 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1748 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1749 struct ixgbe_hw *hw;
1751 PMD_INIT_FUNC_TRACE();
1753 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1756 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1758 if (hw->adapter_stopped == 0)
1759 ixgbevf_dev_close(eth_dev);
1761 eth_dev->dev_ops = NULL;
1762 eth_dev->rx_pkt_burst = NULL;
1763 eth_dev->tx_pkt_burst = NULL;
1765 /* Disable the interrupts for VF */
1766 ixgbevf_intr_disable(hw);
1768 rte_free(eth_dev->data->mac_addrs);
1769 eth_dev->data->mac_addrs = NULL;
1771 rte_intr_disable(intr_handle);
1772 rte_intr_callback_unregister(intr_handle,
1773 ixgbevf_dev_interrupt_handler, eth_dev);
1778 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1779 struct rte_pci_device *pci_dev)
1781 return rte_eth_dev_pci_generic_probe(pci_dev,
1782 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1787 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1790 static struct rte_pci_driver rte_ixgbe_pmd = {
1791 .id_table = pci_id_ixgbe_map,
1792 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1793 RTE_PCI_DRV_IOVA_AS_VA,
1794 .probe = eth_ixgbe_pci_probe,
1795 .remove = eth_ixgbe_pci_remove,
1798 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1799 struct rte_pci_device *pci_dev)
1801 return rte_eth_dev_pci_generic_probe(pci_dev,
1802 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1805 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1807 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1811 * virtual function driver struct
1813 static struct rte_pci_driver rte_ixgbevf_pmd = {
1814 .id_table = pci_id_ixgbevf_map,
1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1816 .probe = eth_ixgbevf_pci_probe,
1817 .remove = eth_ixgbevf_pci_remove,
1821 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1823 struct ixgbe_hw *hw =
1824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825 struct ixgbe_vfta *shadow_vfta =
1826 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1831 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1832 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1833 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1838 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1840 /* update local VFTA copy */
1841 shadow_vfta->vfta[vid_idx] = vfta;
1847 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1850 ixgbe_vlan_hw_strip_enable(dev, queue);
1852 ixgbe_vlan_hw_strip_disable(dev, queue);
1856 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1857 enum rte_vlan_type vlan_type,
1860 struct ixgbe_hw *hw =
1861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 qinq &= IXGBE_DMATXCTL_GDV;
1869 switch (vlan_type) {
1870 case ETH_VLAN_TYPE_INNER:
1872 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881 PMD_DRV_LOG(ERR, "Inner type is not supported"
1885 case ETH_VLAN_TYPE_OUTER:
1887 /* Only the high 16-bits is valid */
1888 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1889 IXGBE_EXVET_VET_EXT_SHIFT);
1891 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1913 struct ixgbe_hw *hw =
1914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 PMD_INIT_FUNC_TRACE();
1919 /* Filter Table Disable */
1920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1927 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1929 struct ixgbe_hw *hw =
1930 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931 struct ixgbe_vfta *shadow_vfta =
1932 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1936 PMD_INIT_FUNC_TRACE();
1938 /* Filter Table Enable */
1939 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1941 vlnctrl |= IXGBE_VLNCTRL_VFE;
1943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1945 /* write whatever is in local vfta copy */
1946 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1947 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1951 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1953 struct ixgbe_hwstrip *hwstrip =
1954 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1955 struct ixgbe_rx_queue *rxq;
1957 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1961 IXGBE_SET_HWSTRIP(hwstrip, queue);
1963 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1965 if (queue >= dev->data->nb_rx_queues)
1968 rxq = dev->data->rx_queues[queue];
1971 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1973 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 struct ixgbe_hw *hw =
1980 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983 PMD_INIT_FUNC_TRACE();
1985 if (hw->mac.type == ixgbe_mac_82598EB) {
1986 /* No queue level support */
1987 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1991 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993 ctrl &= ~IXGBE_RXDCTL_VME;
1994 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996 /* record those setting for HW strip per queue */
1997 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 struct ixgbe_hw *hw =
2004 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007 PMD_INIT_FUNC_TRACE();
2009 if (hw->mac.type == ixgbe_mac_82598EB) {
2010 /* No queue level supported */
2011 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2015 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017 ctrl |= IXGBE_RXDCTL_VME;
2018 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020 /* record those setting for HW strip per queue */
2021 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2025 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031 struct ixgbe_rx_queue *rxq;
2033 PMD_INIT_FUNC_TRACE();
2035 if (hw->mac.type == ixgbe_mac_82598EB) {
2036 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037 ctrl &= ~IXGBE_VLNCTRL_VME;
2038 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042 rxq = dev->data->rx_queues[i];
2043 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044 ctrl &= ~IXGBE_RXDCTL_VME;
2045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2047 /* record those setting for HW strip per queue */
2048 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2054 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2056 struct ixgbe_hw *hw =
2057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060 struct ixgbe_rx_queue *rxq;
2062 PMD_INIT_FUNC_TRACE();
2064 if (hw->mac.type == ixgbe_mac_82598EB) {
2065 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2066 ctrl |= IXGBE_VLNCTRL_VME;
2067 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2069 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2070 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071 rxq = dev->data->rx_queues[i];
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2073 ctrl |= IXGBE_RXDCTL_VME;
2074 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2076 /* record those setting for HW strip per queue */
2077 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2083 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2085 struct ixgbe_hw *hw =
2086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089 PMD_INIT_FUNC_TRACE();
2091 /* DMATXCTRL: Geric Double VLAN Disable */
2092 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2093 ctrl &= ~IXGBE_DMATXCTL_GDV;
2094 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096 /* CTRL_EXT: Global Double VLAN Disable */
2097 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2098 ctrl &= ~IXGBE_EXTENDED_VLAN;
2099 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2104 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2106 struct ixgbe_hw *hw =
2107 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110 PMD_INIT_FUNC_TRACE();
2112 /* DMATXCTRL: Geric Double VLAN Enable */
2113 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2114 ctrl |= IXGBE_DMATXCTL_GDV;
2115 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2117 /* CTRL_EXT: Global Double VLAN Enable */
2118 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2119 ctrl |= IXGBE_EXTENDED_VLAN;
2120 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2122 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2123 if (hw->mac.type == ixgbe_mac_X550 ||
2124 hw->mac.type == ixgbe_mac_X550EM_x ||
2125 hw->mac.type == ixgbe_mac_X550EM_a) {
2126 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2127 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2128 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2132 * VET EXT field in the EXVET register = 0x8100 by default
2133 * So no need to change. Same to VT field of DMATXCTL register
2138 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2140 if (mask & ETH_VLAN_STRIP_MASK) {
2141 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2142 ixgbe_vlan_hw_strip_enable_all(dev);
2144 ixgbe_vlan_hw_strip_disable_all(dev);
2147 if (mask & ETH_VLAN_FILTER_MASK) {
2148 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2149 ixgbe_vlan_hw_filter_enable(dev);
2151 ixgbe_vlan_hw_filter_disable(dev);
2154 if (mask & ETH_VLAN_EXTEND_MASK) {
2155 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2156 ixgbe_vlan_hw_extend_enable(dev);
2158 ixgbe_vlan_hw_extend_disable(dev);
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2165 struct ixgbe_hw *hw =
2166 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2170 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2177 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2182 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2191 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206 /* check multi-queue mode */
2207 switch (dev_conf->rxmode.mq_mode) {
2208 case ETH_MQ_RX_VMDQ_DCB:
2209 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213 PMD_INIT_LOG(ERR, "SRIOV active,"
2214 " unsupported mq_mode rx %d.",
2215 dev_conf->rxmode.mq_mode);
2218 case ETH_MQ_RX_VMDQ_RSS:
2219 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222 PMD_INIT_LOG(ERR, "SRIOV is active,"
2223 " invalid queue number"
2224 " for VMDQ RSS, allowed"
2225 " value are 1, 2 or 4.");
2229 case ETH_MQ_RX_VMDQ_ONLY:
2230 case ETH_MQ_RX_NONE:
2231 /* if nothing mq mode configure, use default scheme */
2232 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2236 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237 /* SRIOV only works in VMDq enable mode */
2238 PMD_INIT_LOG(ERR, "SRIOV is active,"
2239 " wrong mq_mode rx %d.",
2240 dev_conf->rxmode.mq_mode);
2244 switch (dev_conf->txmode.mq_mode) {
2245 case ETH_MQ_TX_VMDQ_DCB:
2246 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2249 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2254 /* check valid queue number */
2255 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257 PMD_INIT_LOG(ERR, "SRIOV is active,"
2258 " nb_rx_q=%d nb_tx_q=%d queue number"
2259 " must be less than or equal to %d.",
2261 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2265 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2270 /* check configuration for vmdb+dcb mode */
2271 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272 const struct rte_eth_vmdq_dcb_conf *conf;
2274 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276 IXGBE_VMDQ_DCB_NB_QUEUES);
2279 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281 conf->nb_queue_pools == ETH_32_POOLS)) {
2282 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283 " nb_queue_pools must be %d or %d.",
2284 ETH_16_POOLS, ETH_32_POOLS);
2288 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2291 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293 IXGBE_VMDQ_DCB_NB_QUEUES);
2296 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298 conf->nb_queue_pools == ETH_32_POOLS)) {
2299 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300 " nb_queue_pools != %d and"
2301 " nb_queue_pools != %d.",
2302 ETH_16_POOLS, ETH_32_POOLS);
2307 /* For DCB mode check our configuration before we go further */
2308 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309 const struct rte_eth_dcb_rx_conf *conf;
2311 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313 IXGBE_DCB_NB_QUEUES);
2316 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317 if (!(conf->nb_tcs == ETH_4_TCS ||
2318 conf->nb_tcs == ETH_8_TCS)) {
2319 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320 " and nb_tcs != %d.",
2321 ETH_4_TCS, ETH_8_TCS);
2326 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327 const struct rte_eth_dcb_tx_conf *conf;
2329 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331 IXGBE_DCB_NB_QUEUES);
2334 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335 if (!(conf->nb_tcs == ETH_4_TCS ||
2336 conf->nb_tcs == ETH_8_TCS)) {
2337 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338 " and nb_tcs != %d.",
2339 ETH_4_TCS, ETH_8_TCS);
2345 * When DCB/VT is off, maximum number of queues changes,
2346 * except for 82598EB, which remains constant.
2348 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349 hw->mac.type != ixgbe_mac_82598EB) {
2350 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2352 "Neither VT nor DCB are enabled, "
2354 IXGBE_NONE_MODE_TX_NB_QUEUES);
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2365 struct ixgbe_interrupt *intr =
2366 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367 struct ixgbe_adapter *adapter =
2368 (struct ixgbe_adapter *)dev->data->dev_private;
2371 PMD_INIT_FUNC_TRACE();
2372 /* multipe queue mode checking */
2373 ret = ixgbe_check_mq_mode(dev);
2375 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2380 /* set flag to update link status after init */
2381 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385 * allocation or vector Rx preconditions we will reset it.
2387 adapter->rx_bulk_alloc_allowed = true;
2388 adapter->rx_vec_allowed = true;
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2396 struct ixgbe_hw *hw =
2397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 struct ixgbe_interrupt *intr =
2399 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402 /* only set up it on X550EM_X */
2403 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414 uint16_t tx_rate, uint64_t q_msk)
2416 struct ixgbe_hw *hw;
2417 struct ixgbe_vf_info *vfinfo;
2418 struct rte_eth_link link;
2419 uint8_t nb_q_per_pool;
2420 uint32_t queue_stride;
2421 uint32_t queue_idx, idx = 0, vf_idx;
2423 uint16_t total_rate = 0;
2424 struct rte_pci_device *pci_dev;
2426 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427 rte_eth_link_get_nowait(dev->data->port_id, &link);
2429 if (vf >= pci_dev->max_vfs)
2432 if (tx_rate > link.link_speed)
2438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442 queue_idx = vf * queue_stride;
2443 queue_end = queue_idx + nb_q_per_pool - 1;
2444 if (queue_end >= hw->mac.max_tx_queues)
2448 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2453 total_rate += vfinfo[vf_idx].tx_rate[idx];
2459 /* Store tx_rate for this vf. */
2460 for (idx = 0; idx < nb_q_per_pool; idx++) {
2461 if (((uint64_t)0x1 << idx) & q_msk) {
2462 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463 vfinfo[vf].tx_rate[idx] = tx_rate;
2464 total_rate += tx_rate;
2468 if (total_rate > dev->data->dev_link.link_speed) {
2469 /* Reset stored TX rate of the VF if it causes exceed
2472 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2476 /* Set RTTBCNRC of each queue/pool for vf X */
2477 for (; queue_idx <= queue_end; queue_idx++) {
2479 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2487 * Configure device link speed and setup link.
2488 * It returns 0 on success.
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2493 struct ixgbe_hw *hw =
2494 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495 struct ixgbe_vf_info *vfinfo =
2496 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499 uint32_t intr_vector = 0;
2500 int err, link_up = 0, negotiate = 0;
2505 uint32_t *link_speeds;
2506 struct ixgbe_tm_conf *tm_conf =
2507 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2509 PMD_INIT_FUNC_TRACE();
2511 /* IXGBE devices don't support:
2512 * - half duplex (checked afterwards for valid speeds)
2513 * - fixed speed: TODO implement
2515 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2517 "Invalid link_speeds for port %u, fix speed not supported",
2518 dev->data->port_id);
2522 /* disable uio/vfio intr/eventfd mapping */
2523 rte_intr_disable(intr_handle);
2526 hw->adapter_stopped = 0;
2527 ixgbe_stop_adapter(hw);
2529 /* reinitialize adapter
2530 * this calls reset and start
2532 status = ixgbe_pf_reset_hw(hw);
2535 hw->mac.ops.start_hw(hw);
2536 hw->mac.get_link_status = true;
2538 /* configure PF module if SRIOV enabled */
2539 ixgbe_pf_host_configure(dev);
2541 ixgbe_dev_phy_intr_setup(dev);
2543 /* check and configure queue intr-vector mapping */
2544 if ((rte_intr_cap_multiple(intr_handle) ||
2545 !RTE_ETH_DEV_SRIOV(dev).active) &&
2546 dev->data->dev_conf.intr_conf.rxq != 0) {
2547 intr_vector = dev->data->nb_rx_queues;
2548 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2549 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2550 IXGBE_MAX_INTR_QUEUE_NUM);
2553 if (rte_intr_efd_enable(intr_handle, intr_vector))
2557 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2558 intr_handle->intr_vec =
2559 rte_zmalloc("intr_vec",
2560 dev->data->nb_rx_queues * sizeof(int), 0);
2561 if (intr_handle->intr_vec == NULL) {
2562 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2563 " intr_vec", dev->data->nb_rx_queues);
2568 /* confiugre msix for sleep until rx interrupt */
2569 ixgbe_configure_msix(dev);
2571 /* initialize transmission unit */
2572 ixgbe_dev_tx_init(dev);
2574 /* This can fail when allocating mbufs for descriptor rings */
2575 err = ixgbe_dev_rx_init(dev);
2577 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2581 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2582 ETH_VLAN_EXTEND_MASK;
2583 ixgbe_vlan_offload_set(dev, mask);
2585 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2586 /* Enable vlan filtering for VMDq */
2587 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2590 /* Configure DCB hw */
2591 ixgbe_configure_dcb(dev);
2593 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2594 err = ixgbe_fdir_configure(dev);
2599 /* Restore vf rate limit */
2600 if (vfinfo != NULL) {
2601 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2602 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2603 if (vfinfo[vf].tx_rate[idx] != 0)
2604 ixgbe_set_vf_rate_limit(
2606 vfinfo[vf].tx_rate[idx],
2610 ixgbe_restore_statistics_mapping(dev);
2612 err = ixgbe_dev_rxtx_start(dev);
2614 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2618 /* Skip link setup if loopback mode is enabled for 82599. */
2619 if (hw->mac.type == ixgbe_mac_82599EB &&
2620 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2621 goto skip_link_setup;
2623 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2624 err = hw->mac.ops.setup_sfp(hw);
2629 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2630 /* Turn on the copper */
2631 ixgbe_set_phy_power(hw, true);
2633 /* Turn on the laser */
2634 ixgbe_enable_tx_laser(hw);
2637 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2640 dev->data->dev_link.link_status = link_up;
2642 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2646 link_speeds = &dev->data->dev_conf.link_speeds;
2647 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2648 ETH_LINK_SPEED_10G)) {
2649 PMD_INIT_LOG(ERR, "Invalid link setting");
2654 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2655 switch (hw->mac.type) {
2656 case ixgbe_mac_82598EB:
2657 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2659 case ixgbe_mac_82599EB:
2660 case ixgbe_mac_X540:
2661 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2663 case ixgbe_mac_X550:
2664 case ixgbe_mac_X550EM_x:
2665 case ixgbe_mac_X550EM_a:
2666 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2669 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2672 if (*link_speeds & ETH_LINK_SPEED_10G)
2673 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2674 if (*link_speeds & ETH_LINK_SPEED_1G)
2675 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2676 if (*link_speeds & ETH_LINK_SPEED_100M)
2677 speed |= IXGBE_LINK_SPEED_100_FULL;
2680 err = ixgbe_setup_link(hw, speed, link_up);
2686 if (rte_intr_allow_others(intr_handle)) {
2687 /* check if lsc interrupt is enabled */
2688 if (dev->data->dev_conf.intr_conf.lsc != 0)
2689 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2691 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2692 ixgbe_dev_macsec_interrupt_setup(dev);
2694 rte_intr_callback_unregister(intr_handle,
2695 ixgbe_dev_interrupt_handler, dev);
2696 if (dev->data->dev_conf.intr_conf.lsc != 0)
2697 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2698 " no intr multiplex");
2701 /* check if rxq interrupt is enabled */
2702 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2703 rte_intr_dp_is_en(intr_handle))
2704 ixgbe_dev_rxq_interrupt_setup(dev);
2706 /* enable uio/vfio intr/eventfd mapping */
2707 rte_intr_enable(intr_handle);
2709 /* resume enabled intr since hw reset */
2710 ixgbe_enable_intr(dev);
2711 ixgbe_l2_tunnel_conf(dev);
2712 ixgbe_filter_restore(dev);
2714 if (tm_conf->root && !tm_conf->committed)
2715 PMD_DRV_LOG(WARNING,
2716 "please call hierarchy_commit() "
2717 "before starting the port");
2722 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2723 ixgbe_dev_clear_queues(dev);
2728 * Stop device: disable rx and tx functions to allow for reconfiguring.
2731 ixgbe_dev_stop(struct rte_eth_dev *dev)
2733 struct rte_eth_link link;
2734 struct ixgbe_hw *hw =
2735 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736 struct ixgbe_vf_info *vfinfo =
2737 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2738 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2739 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2741 struct ixgbe_tm_conf *tm_conf =
2742 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2744 PMD_INIT_FUNC_TRACE();
2746 /* disable interrupts */
2747 ixgbe_disable_intr(hw);
2750 ixgbe_pf_reset_hw(hw);
2751 hw->adapter_stopped = 0;
2754 ixgbe_stop_adapter(hw);
2756 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2757 vfinfo[vf].clear_to_send = false;
2759 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2760 /* Turn off the copper */
2761 ixgbe_set_phy_power(hw, false);
2763 /* Turn off the laser */
2764 ixgbe_disable_tx_laser(hw);
2767 ixgbe_dev_clear_queues(dev);
2769 /* Clear stored conf */
2770 dev->data->scattered_rx = 0;
2773 /* Clear recorded link status */
2774 memset(&link, 0, sizeof(link));
2775 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2777 if (!rte_intr_allow_others(intr_handle))
2778 /* resume to the default handler */
2779 rte_intr_callback_register(intr_handle,
2780 ixgbe_dev_interrupt_handler,
2783 /* Clean datapath event and queue/vec mapping */
2784 rte_intr_efd_disable(intr_handle);
2785 if (intr_handle->intr_vec != NULL) {
2786 rte_free(intr_handle->intr_vec);
2787 intr_handle->intr_vec = NULL;
2790 /* reset hierarchy commit */
2791 tm_conf->committed = false;
2795 * Set device link up: enable tx.
2798 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2800 struct ixgbe_hw *hw =
2801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802 if (hw->mac.type == ixgbe_mac_82599EB) {
2803 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2804 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2805 /* Not suported in bypass mode */
2806 PMD_INIT_LOG(ERR, "Set link up is not supported "
2807 "by device id 0x%x", hw->device_id);
2813 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2814 /* Turn on the copper */
2815 ixgbe_set_phy_power(hw, true);
2817 /* Turn on the laser */
2818 ixgbe_enable_tx_laser(hw);
2825 * Set device link down: disable tx.
2828 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2830 struct ixgbe_hw *hw =
2831 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832 if (hw->mac.type == ixgbe_mac_82599EB) {
2833 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2834 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2835 /* Not suported in bypass mode */
2836 PMD_INIT_LOG(ERR, "Set link down is not supported "
2837 "by device id 0x%x", hw->device_id);
2843 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2844 /* Turn off the copper */
2845 ixgbe_set_phy_power(hw, false);
2847 /* Turn off the laser */
2848 ixgbe_disable_tx_laser(hw);
2855 * Reset and stop device.
2858 ixgbe_dev_close(struct rte_eth_dev *dev)
2860 struct ixgbe_hw *hw =
2861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863 PMD_INIT_FUNC_TRACE();
2865 ixgbe_pf_reset_hw(hw);
2867 ixgbe_dev_stop(dev);
2868 hw->adapter_stopped = 1;
2870 ixgbe_dev_free_queues(dev);
2872 ixgbe_disable_pcie_master(hw);
2874 /* reprogram the RAR[0] in case user changed it. */
2875 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2882 ixgbe_dev_reset(struct rte_eth_dev *dev)
2886 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2887 * its VF to make them align with it. The detailed notification
2888 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2889 * To avoid unexpected behavior in VF, currently reset of PF with
2890 * SR-IOV activation is not supported. It might be supported later.
2892 if (dev->data->sriov.active)
2895 ret = eth_ixgbe_dev_uninit(dev);
2899 ret = eth_ixgbe_dev_init(dev);
2905 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2906 struct ixgbe_hw_stats *hw_stats,
2907 struct ixgbe_macsec_stats *macsec_stats,
2908 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2909 uint64_t *total_qprc, uint64_t *total_qprdc)
2911 uint32_t bprc, lxon, lxoff, total;
2912 uint32_t delta_gprc = 0;
2914 /* Workaround for RX byte count not including CRC bytes when CRC
2915 * strip is enabled. CRC bytes are removed from counters when crc_strip
2918 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2919 IXGBE_HLREG0_RXCRCSTRP);
2921 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2922 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2923 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2924 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2926 for (i = 0; i < 8; i++) {
2927 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2929 /* global total per queue */
2930 hw_stats->mpc[i] += mp;
2931 /* Running comprehensive total for stats display */
2932 *total_missed_rx += hw_stats->mpc[i];
2933 if (hw->mac.type == ixgbe_mac_82598EB) {
2934 hw_stats->rnbc[i] +=
2935 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2936 hw_stats->pxonrxc[i] +=
2937 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2938 hw_stats->pxoffrxc[i] +=
2939 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2941 hw_stats->pxonrxc[i] +=
2942 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2943 hw_stats->pxoffrxc[i] +=
2944 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2945 hw_stats->pxon2offc[i] +=
2946 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2948 hw_stats->pxontxc[i] +=
2949 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2950 hw_stats->pxofftxc[i] +=
2951 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2953 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2954 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2955 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2956 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2958 delta_gprc += delta_qprc;
2960 hw_stats->qprc[i] += delta_qprc;
2961 hw_stats->qptc[i] += delta_qptc;
2963 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2964 hw_stats->qbrc[i] +=
2965 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2967 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2969 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2970 hw_stats->qbtc[i] +=
2971 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2973 hw_stats->qprdc[i] += delta_qprdc;
2974 *total_qprdc += hw_stats->qprdc[i];
2976 *total_qprc += hw_stats->qprc[i];
2977 *total_qbrc += hw_stats->qbrc[i];
2979 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2980 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2981 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2984 * An errata states that gprc actually counts good + missed packets:
2985 * Workaround to set gprc to summated queue packet receives
2987 hw_stats->gprc = *total_qprc;
2989 if (hw->mac.type != ixgbe_mac_82598EB) {
2990 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2991 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2992 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2993 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2994 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2995 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2996 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2997 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2999 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3000 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3001 /* 82598 only has a counter in the high register */
3002 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3003 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3004 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3006 uint64_t old_tpr = hw_stats->tpr;
3008 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3009 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3012 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3014 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3015 hw_stats->gptc += delta_gptc;
3016 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3017 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3020 * Workaround: mprc hardware is incorrectly counting
3021 * broadcasts, so for now we subtract those.
3023 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3024 hw_stats->bprc += bprc;
3025 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3026 if (hw->mac.type == ixgbe_mac_82598EB)
3027 hw_stats->mprc -= bprc;
3029 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3030 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3031 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3032 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3033 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3034 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3036 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3037 hw_stats->lxontxc += lxon;
3038 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3039 hw_stats->lxofftxc += lxoff;
3040 total = lxon + lxoff;
3042 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3043 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3044 hw_stats->gptc -= total;
3045 hw_stats->mptc -= total;
3046 hw_stats->ptc64 -= total;
3047 hw_stats->gotc -= total * ETHER_MIN_LEN;
3049 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3050 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3051 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3052 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3053 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3054 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3055 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3056 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3057 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3058 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3059 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3060 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3061 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3062 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3063 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3064 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3065 /* Only read FCOE on 82599 */
3066 if (hw->mac.type != ixgbe_mac_82598EB) {
3067 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3068 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3069 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3070 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3071 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3074 /* Flow Director Stats registers */
3075 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3076 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3078 /* MACsec Stats registers */
3079 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3080 macsec_stats->out_pkts_encrypted +=
3081 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3082 macsec_stats->out_pkts_protected +=
3083 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3084 macsec_stats->out_octets_encrypted +=
3085 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3086 macsec_stats->out_octets_protected +=
3087 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3088 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3089 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3090 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3091 macsec_stats->in_pkts_unknownsci +=
3092 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3093 macsec_stats->in_octets_decrypted +=
3094 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3095 macsec_stats->in_octets_validated +=
3096 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3097 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3098 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3099 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3100 for (i = 0; i < 2; i++) {
3101 macsec_stats->in_pkts_ok +=
3102 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3103 macsec_stats->in_pkts_invalid +=
3104 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3105 macsec_stats->in_pkts_notvalid +=
3106 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3108 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3109 macsec_stats->in_pkts_notusingsa +=
3110 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3114 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3117 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3119 struct ixgbe_hw *hw =
3120 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 struct ixgbe_hw_stats *hw_stats =
3122 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123 struct ixgbe_macsec_stats *macsec_stats =
3124 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3125 dev->data->dev_private);
3126 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3129 total_missed_rx = 0;
3134 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3135 &total_qbrc, &total_qprc, &total_qprdc);
3140 /* Fill out the rte_eth_stats statistics structure */
3141 stats->ipackets = total_qprc;
3142 stats->ibytes = total_qbrc;
3143 stats->opackets = hw_stats->gptc;
3144 stats->obytes = hw_stats->gotc;
3146 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3147 stats->q_ipackets[i] = hw_stats->qprc[i];
3148 stats->q_opackets[i] = hw_stats->qptc[i];
3149 stats->q_ibytes[i] = hw_stats->qbrc[i];
3150 stats->q_obytes[i] = hw_stats->qbtc[i];
3151 stats->q_errors[i] = hw_stats->qprdc[i];
3155 stats->imissed = total_missed_rx;
3156 stats->ierrors = hw_stats->crcerrs +
3173 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3175 struct ixgbe_hw_stats *stats =
3176 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3178 /* HW registers are cleared on read */
3179 ixgbe_dev_stats_get(dev, NULL);
3181 /* Reset software totals */
3182 memset(stats, 0, sizeof(*stats));
3185 /* This function calculates the number of xstats based on the current config */
3187 ixgbe_xstats_calc_num(void) {
3188 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3189 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3190 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3193 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3194 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3196 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3197 unsigned stat, i, count;
3199 if (xstats_names != NULL) {
3202 /* Note: limit >= cnt_stats checked upstream
3203 * in rte_eth_xstats_names()
3206 /* Extended stats from ixgbe_hw_stats */
3207 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3208 snprintf(xstats_names[count].name,
3209 sizeof(xstats_names[count].name),
3211 rte_ixgbe_stats_strings[i].name);
3216 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3217 snprintf(xstats_names[count].name,
3218 sizeof(xstats_names[count].name),
3220 rte_ixgbe_macsec_strings[i].name);
3224 /* RX Priority Stats */
3225 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3226 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3227 snprintf(xstats_names[count].name,
3228 sizeof(xstats_names[count].name),
3229 "rx_priority%u_%s", i,
3230 rte_ixgbe_rxq_strings[stat].name);
3235 /* TX Priority Stats */
3236 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3237 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3238 snprintf(xstats_names[count].name,
3239 sizeof(xstats_names[count].name),
3240 "tx_priority%u_%s", i,
3241 rte_ixgbe_txq_strings[stat].name);
3249 static int ixgbe_dev_xstats_get_names_by_id(
3250 struct rte_eth_dev *dev,
3251 struct rte_eth_xstat_name *xstats_names,
3252 const uint64_t *ids,
3256 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3257 unsigned int stat, i, count;
3259 if (xstats_names != NULL) {
3262 /* Note: limit >= cnt_stats checked upstream
3263 * in rte_eth_xstats_names()
3266 /* Extended stats from ixgbe_hw_stats */
3267 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3268 snprintf(xstats_names[count].name,
3269 sizeof(xstats_names[count].name),
3271 rte_ixgbe_stats_strings[i].name);
3276 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3277 snprintf(xstats_names[count].name,
3278 sizeof(xstats_names[count].name),
3280 rte_ixgbe_macsec_strings[i].name);
3284 /* RX Priority Stats */
3285 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3286 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3287 snprintf(xstats_names[count].name,
3288 sizeof(xstats_names[count].name),
3289 "rx_priority%u_%s", i,
3290 rte_ixgbe_rxq_strings[stat].name);
3295 /* TX Priority Stats */
3296 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3297 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3298 snprintf(xstats_names[count].name,
3299 sizeof(xstats_names[count].name),
3300 "tx_priority%u_%s", i,
3301 rte_ixgbe_txq_strings[stat].name);
3310 uint16_t size = ixgbe_xstats_calc_num();
3311 struct rte_eth_xstat_name xstats_names_copy[size];
3313 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3316 for (i = 0; i < limit; i++) {
3317 if (ids[i] >= size) {
3318 PMD_INIT_LOG(ERR, "id value isn't valid");
3321 strcpy(xstats_names[i].name,
3322 xstats_names_copy[ids[i]].name);
3327 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3328 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3332 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3335 if (xstats_names != NULL)
3336 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3337 snprintf(xstats_names[i].name,
3338 sizeof(xstats_names[i].name),
3339 "%s", rte_ixgbevf_stats_strings[i].name);
3340 return IXGBEVF_NB_XSTATS;
3344 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3347 struct ixgbe_hw *hw =
3348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349 struct ixgbe_hw_stats *hw_stats =
3350 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3351 struct ixgbe_macsec_stats *macsec_stats =
3352 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3353 dev->data->dev_private);
3354 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3355 unsigned i, stat, count = 0;
3357 count = ixgbe_xstats_calc_num();
3362 total_missed_rx = 0;
3367 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3368 &total_qbrc, &total_qprc, &total_qprdc);
3370 /* If this is a reset xstats is NULL, and we have cleared the
3371 * registers by reading them.
3376 /* Extended stats from ixgbe_hw_stats */
3378 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3379 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3380 rte_ixgbe_stats_strings[i].offset);
3381 xstats[count].id = count;
3386 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3387 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3388 rte_ixgbe_macsec_strings[i].offset);
3389 xstats[count].id = count;
3393 /* RX Priority Stats */
3394 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3395 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3396 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3397 rte_ixgbe_rxq_strings[stat].offset +
3398 (sizeof(uint64_t) * i));
3399 xstats[count].id = count;
3404 /* TX Priority Stats */
3405 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3406 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3407 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3408 rte_ixgbe_txq_strings[stat].offset +
3409 (sizeof(uint64_t) * i));
3410 xstats[count].id = count;
3418 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3419 uint64_t *values, unsigned int n)
3422 struct ixgbe_hw *hw =
3423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424 struct ixgbe_hw_stats *hw_stats =
3425 IXGBE_DEV_PRIVATE_TO_STATS(
3426 dev->data->dev_private);
3427 struct ixgbe_macsec_stats *macsec_stats =
3428 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3429 dev->data->dev_private);
3430 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3431 unsigned int i, stat, count = 0;
3433 count = ixgbe_xstats_calc_num();
3435 if (!ids && n < count)
3438 total_missed_rx = 0;
3443 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3444 &total_missed_rx, &total_qbrc, &total_qprc,
3447 /* If this is a reset xstats is NULL, and we have cleared the
3448 * registers by reading them.
3450 if (!ids && !values)
3453 /* Extended stats from ixgbe_hw_stats */
3455 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3456 values[count] = *(uint64_t *)(((char *)hw_stats) +
3457 rte_ixgbe_stats_strings[i].offset);
3462 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3463 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3464 rte_ixgbe_macsec_strings[i].offset);
3468 /* RX Priority Stats */
3469 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3470 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3472 *(uint64_t *)(((char *)hw_stats) +
3473 rte_ixgbe_rxq_strings[stat].offset +
3474 (sizeof(uint64_t) * i));
3479 /* TX Priority Stats */
3480 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3481 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3483 *(uint64_t *)(((char *)hw_stats) +
3484 rte_ixgbe_txq_strings[stat].offset +
3485 (sizeof(uint64_t) * i));
3493 uint16_t size = ixgbe_xstats_calc_num();
3494 uint64_t values_copy[size];
3496 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3498 for (i = 0; i < n; i++) {
3499 if (ids[i] >= size) {
3500 PMD_INIT_LOG(ERR, "id value isn't valid");
3503 values[i] = values_copy[ids[i]];
3509 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3511 struct ixgbe_hw_stats *stats =
3512 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3513 struct ixgbe_macsec_stats *macsec_stats =
3514 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3515 dev->data->dev_private);
3517 unsigned count = ixgbe_xstats_calc_num();
3519 /* HW registers are cleared on read */
3520 ixgbe_dev_xstats_get(dev, NULL, count);
3522 /* Reset software totals */
3523 memset(stats, 0, sizeof(*stats));
3524 memset(macsec_stats, 0, sizeof(*macsec_stats));
3528 ixgbevf_update_stats(struct rte_eth_dev *dev)
3530 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3534 /* Good Rx packet, include VF loopback */
3535 UPDATE_VF_STAT(IXGBE_VFGPRC,
3536 hw_stats->last_vfgprc, hw_stats->vfgprc);
3538 /* Good Rx octets, include VF loopback */
3539 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3540 hw_stats->last_vfgorc, hw_stats->vfgorc);
3542 /* Good Tx packet, include VF loopback */
3543 UPDATE_VF_STAT(IXGBE_VFGPTC,
3544 hw_stats->last_vfgptc, hw_stats->vfgptc);
3546 /* Good Tx octets, include VF loopback */
3547 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3548 hw_stats->last_vfgotc, hw_stats->vfgotc);
3550 /* Rx Multicst Packet */
3551 UPDATE_VF_STAT(IXGBE_VFMPRC,
3552 hw_stats->last_vfmprc, hw_stats->vfmprc);
3556 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3559 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3560 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3563 if (n < IXGBEVF_NB_XSTATS)
3564 return IXGBEVF_NB_XSTATS;
3566 ixgbevf_update_stats(dev);
3571 /* Extended stats */
3572 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3574 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3575 rte_ixgbevf_stats_strings[i].offset);
3578 return IXGBEVF_NB_XSTATS;
3582 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3584 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3585 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3587 ixgbevf_update_stats(dev);
3592 stats->ipackets = hw_stats->vfgprc;
3593 stats->ibytes = hw_stats->vfgorc;
3594 stats->opackets = hw_stats->vfgptc;
3595 stats->obytes = hw_stats->vfgotc;
3600 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3602 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3603 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3605 /* Sync HW register to the last stats */
3606 ixgbevf_dev_stats_get(dev, NULL);
3608 /* reset HW current stats*/
3609 hw_stats->vfgprc = 0;
3610 hw_stats->vfgorc = 0;
3611 hw_stats->vfgptc = 0;
3612 hw_stats->vfgotc = 0;
3616 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3618 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619 u16 eeprom_verh, eeprom_verl;
3623 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3624 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3626 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3627 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3629 ret += 1; /* add the size of '\0' */
3630 if (fw_size < (u32)ret)
3637 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3640 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3643 dev_info->pci_dev = pci_dev;
3644 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3645 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3646 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3648 * When DCB/VT is off, maximum number of queues changes,
3649 * except for 82598EB, which remains constant.
3651 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3652 hw->mac.type != ixgbe_mac_82598EB)
3653 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3655 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3656 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3657 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3658 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3659 dev_info->max_vfs = pci_dev->max_vfs;
3660 if (hw->mac.type == ixgbe_mac_82598EB)
3661 dev_info->max_vmdq_pools = ETH_16_POOLS;
3663 dev_info->max_vmdq_pools = ETH_64_POOLS;
3664 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3665 dev_info->rx_offload_capa =
3666 DEV_RX_OFFLOAD_VLAN_STRIP |
3667 DEV_RX_OFFLOAD_IPV4_CKSUM |
3668 DEV_RX_OFFLOAD_UDP_CKSUM |
3669 DEV_RX_OFFLOAD_TCP_CKSUM;
3672 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3675 if ((hw->mac.type == ixgbe_mac_82599EB ||
3676 hw->mac.type == ixgbe_mac_X540) &&
3677 !RTE_ETH_DEV_SRIOV(dev).active)
3678 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3680 if (hw->mac.type == ixgbe_mac_82599EB ||
3681 hw->mac.type == ixgbe_mac_X540)
3682 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3684 if (hw->mac.type == ixgbe_mac_X550 ||
3685 hw->mac.type == ixgbe_mac_X550EM_x ||
3686 hw->mac.type == ixgbe_mac_X550EM_a)
3687 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3689 dev_info->tx_offload_capa =
3690 DEV_TX_OFFLOAD_VLAN_INSERT |
3691 DEV_TX_OFFLOAD_IPV4_CKSUM |
3692 DEV_TX_OFFLOAD_UDP_CKSUM |
3693 DEV_TX_OFFLOAD_TCP_CKSUM |
3694 DEV_TX_OFFLOAD_SCTP_CKSUM |
3695 DEV_TX_OFFLOAD_TCP_TSO;
3697 if (hw->mac.type == ixgbe_mac_82599EB ||
3698 hw->mac.type == ixgbe_mac_X540)
3699 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3701 if (hw->mac.type == ixgbe_mac_X550 ||
3702 hw->mac.type == ixgbe_mac_X550EM_x ||
3703 hw->mac.type == ixgbe_mac_X550EM_a)
3704 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3706 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3707 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3709 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3711 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3712 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3713 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3715 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3719 dev_info->default_txconf = (struct rte_eth_txconf) {
3721 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3722 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3723 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3725 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3726 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3727 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3728 ETH_TXQ_FLAGS_NOOFFLOADS,
3731 dev_info->rx_desc_lim = rx_desc_lim;
3732 dev_info->tx_desc_lim = tx_desc_lim;
3734 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3735 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3736 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3738 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3739 if (hw->mac.type == ixgbe_mac_X540 ||
3740 hw->mac.type == ixgbe_mac_X540_vf ||
3741 hw->mac.type == ixgbe_mac_X550 ||
3742 hw->mac.type == ixgbe_mac_X550_vf) {
3743 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3745 if (hw->mac.type == ixgbe_mac_X550) {
3746 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3747 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3751 static const uint32_t *
3752 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3754 static const uint32_t ptypes[] = {
3755 /* For non-vec functions,
3756 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3757 * for vec functions,
3758 * refers to _recv_raw_pkts_vec().
3762 RTE_PTYPE_L3_IPV4_EXT,
3764 RTE_PTYPE_L3_IPV6_EXT,
3768 RTE_PTYPE_TUNNEL_IP,
3769 RTE_PTYPE_INNER_L3_IPV6,
3770 RTE_PTYPE_INNER_L3_IPV6_EXT,
3771 RTE_PTYPE_INNER_L4_TCP,
3772 RTE_PTYPE_INNER_L4_UDP,
3776 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3777 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3778 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3779 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3782 #if defined(RTE_ARCH_X86)
3783 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3784 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3791 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3792 struct rte_eth_dev_info *dev_info)
3794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3797 dev_info->pci_dev = pci_dev;
3798 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3799 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3800 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3801 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3802 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3803 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3804 dev_info->max_vfs = pci_dev->max_vfs;
3805 if (hw->mac.type == ixgbe_mac_82598EB)
3806 dev_info->max_vmdq_pools = ETH_16_POOLS;
3808 dev_info->max_vmdq_pools = ETH_64_POOLS;
3809 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3810 DEV_RX_OFFLOAD_IPV4_CKSUM |
3811 DEV_RX_OFFLOAD_UDP_CKSUM |
3812 DEV_RX_OFFLOAD_TCP_CKSUM;
3813 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3814 DEV_TX_OFFLOAD_IPV4_CKSUM |
3815 DEV_TX_OFFLOAD_UDP_CKSUM |
3816 DEV_TX_OFFLOAD_TCP_CKSUM |
3817 DEV_TX_OFFLOAD_SCTP_CKSUM |
3818 DEV_TX_OFFLOAD_TCP_TSO;
3820 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3822 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3823 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3824 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3826 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3830 dev_info->default_txconf = (struct rte_eth_txconf) {
3832 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3833 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3834 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3836 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3837 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3838 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3839 ETH_TXQ_FLAGS_NOOFFLOADS,
3842 dev_info->rx_desc_lim = rx_desc_lim;
3843 dev_info->tx_desc_lim = tx_desc_lim;
3847 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3848 int *link_up, int wait_to_complete)
3851 * for a quick link status checking, wait_to_compelet == 0,
3852 * skip PF link status checking
3854 bool no_pflink_check = wait_to_complete == 0;
3855 struct ixgbe_mbx_info *mbx = &hw->mbx;
3856 struct ixgbe_mac_info *mac = &hw->mac;
3857 uint32_t links_reg, in_msg;
3860 /* If we were hit with a reset drop the link */
3861 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3862 mac->get_link_status = true;
3864 if (!mac->get_link_status)
3867 /* if link status is down no point in checking to see if pf is up */
3868 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3869 if (!(links_reg & IXGBE_LINKS_UP))
3872 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3873 * before the link status is correct
3875 if (mac->type == ixgbe_mac_82599_vf) {
3878 for (i = 0; i < 5; i++) {
3880 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3882 if (!(links_reg & IXGBE_LINKS_UP))
3887 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3888 case IXGBE_LINKS_SPEED_10G_82599:
3889 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3890 if (hw->mac.type >= ixgbe_mac_X550) {
3891 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3892 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3895 case IXGBE_LINKS_SPEED_1G_82599:
3896 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3898 case IXGBE_LINKS_SPEED_100_82599:
3899 *speed = IXGBE_LINK_SPEED_100_FULL;
3900 if (hw->mac.type == ixgbe_mac_X550) {
3901 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3902 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3905 case IXGBE_LINKS_SPEED_10_X550EM_A:
3906 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3907 /* Since Reserved in older MAC's */
3908 if (hw->mac.type >= ixgbe_mac_X550)
3909 *speed = IXGBE_LINK_SPEED_10_FULL;
3912 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3915 if (no_pflink_check) {
3916 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3917 mac->get_link_status = true;
3919 mac->get_link_status = false;
3923 /* if the read failed it could just be a mailbox collision, best wait
3924 * until we are called again and don't report an error
3926 if (mbx->ops.read(hw, &in_msg, 1, 0))
3929 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3930 /* msg is not CTS and is NACK we must have lost CTS status */
3931 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3936 /* the pf is talking, if we timed out in the past we reinit */
3937 if (!mbx->timeout) {
3942 /* if we passed all the tests above then the link is up and we no
3943 * longer need to check for link
3945 mac->get_link_status = false;
3948 *link_up = !mac->get_link_status;
3952 /* return 0 means link status changed, -1 means not changed */
3954 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3955 int wait_to_complete, int vf)
3957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958 struct rte_eth_link link, old;
3959 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3960 struct ixgbe_interrupt *intr =
3961 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3966 bool autoneg = false;
3968 link.link_status = ETH_LINK_DOWN;
3969 link.link_speed = 0;
3970 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3971 link.link_autoneg = ETH_LINK_AUTONEG;
3972 memset(&old, 0, sizeof(old));
3973 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3975 hw->mac.get_link_status = true;
3977 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3978 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3979 speed = hw->phy.autoneg_advertised;
3981 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3982 ixgbe_setup_link(hw, speed, true);
3985 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3986 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3990 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3992 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3995 link.link_speed = ETH_SPEED_NUM_100M;
3996 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3997 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3998 if (link.link_status == old.link_status)
4004 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4005 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4006 if (link.link_status == old.link_status)
4010 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4011 link.link_status = ETH_LINK_UP;
4012 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4014 switch (link_speed) {
4016 case IXGBE_LINK_SPEED_UNKNOWN:
4017 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4018 link.link_speed = ETH_SPEED_NUM_100M;
4021 case IXGBE_LINK_SPEED_100_FULL:
4022 link.link_speed = ETH_SPEED_NUM_100M;
4025 case IXGBE_LINK_SPEED_1GB_FULL:
4026 link.link_speed = ETH_SPEED_NUM_1G;
4029 case IXGBE_LINK_SPEED_2_5GB_FULL:
4030 link.link_speed = ETH_SPEED_NUM_2_5G;
4033 case IXGBE_LINK_SPEED_5GB_FULL:
4034 link.link_speed = ETH_SPEED_NUM_5G;
4037 case IXGBE_LINK_SPEED_10GB_FULL:
4038 link.link_speed = ETH_SPEED_NUM_10G;
4041 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4043 if (link.link_status == old.link_status)
4050 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4052 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4056 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4058 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4062 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4069 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4073 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4079 fctrl &= (~IXGBE_FCTRL_UPE);
4080 if (dev->data->all_multicast == 1)
4081 fctrl |= IXGBE_FCTRL_MPE;
4083 fctrl &= (~IXGBE_FCTRL_MPE);
4084 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4088 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4093 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4094 fctrl |= IXGBE_FCTRL_MPE;
4095 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4099 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104 if (dev->data->promiscuous == 1)
4105 return; /* must remain in all_multicast mode */
4107 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4108 fctrl &= (~IXGBE_FCTRL_MPE);
4109 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4113 * It clears the interrupt causes and enables the interrupt.
4114 * It will be called once only during nic initialized.
4117 * Pointer to struct rte_eth_dev.
4119 * Enable or Disable.
4122 * - On success, zero.
4123 * - On failure, a negative value.
4126 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4128 struct ixgbe_interrupt *intr =
4129 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4131 ixgbe_dev_link_status_print(dev);
4133 intr->mask |= IXGBE_EICR_LSC;
4135 intr->mask &= ~IXGBE_EICR_LSC;
4141 * It clears the interrupt causes and enables the interrupt.
4142 * It will be called once only during nic initialized.
4145 * Pointer to struct rte_eth_dev.
4148 * - On success, zero.
4149 * - On failure, a negative value.
4152 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4154 struct ixgbe_interrupt *intr =
4155 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4157 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4163 * It clears the interrupt causes and enables the interrupt.
4164 * It will be called once only during nic initialized.
4167 * Pointer to struct rte_eth_dev.
4170 * - On success, zero.
4171 * - On failure, a negative value.
4174 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4176 struct ixgbe_interrupt *intr =
4177 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4179 intr->mask |= IXGBE_EICR_LINKSEC;
4185 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4188 * Pointer to struct rte_eth_dev.
4191 * - On success, zero.
4192 * - On failure, a negative value.
4195 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4198 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199 struct ixgbe_interrupt *intr =
4200 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4202 /* clear all cause mask */
4203 ixgbe_disable_intr(hw);
4205 /* read-on-clear nic registers here */
4206 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4207 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4211 /* set flag for async link update */
4212 if (eicr & IXGBE_EICR_LSC)
4213 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4215 if (eicr & IXGBE_EICR_MAILBOX)
4216 intr->flags |= IXGBE_FLAG_MAILBOX;
4218 if (eicr & IXGBE_EICR_LINKSEC)
4219 intr->flags |= IXGBE_FLAG_MACSEC;
4221 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4222 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4223 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4224 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4230 * It gets and then prints the link status.
4233 * Pointer to struct rte_eth_dev.
4236 * - On success, zero.
4237 * - On failure, a negative value.
4240 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4242 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4243 struct rte_eth_link link;
4245 memset(&link, 0, sizeof(link));
4246 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4247 if (link.link_status) {
4248 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4249 (int)(dev->data->port_id),
4250 (unsigned)link.link_speed,
4251 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4252 "full-duplex" : "half-duplex");
4254 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4255 (int)(dev->data->port_id));
4257 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4258 pci_dev->addr.domain,
4260 pci_dev->addr.devid,
4261 pci_dev->addr.function);
4265 * It executes link_update after knowing an interrupt occurred.
4268 * Pointer to struct rte_eth_dev.
4271 * - On success, zero.
4272 * - On failure, a negative value.
4275 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4276 struct rte_intr_handle *intr_handle)
4278 struct ixgbe_interrupt *intr =
4279 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4281 struct rte_eth_link link;
4282 struct ixgbe_hw *hw =
4283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4287 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4288 ixgbe_pf_mbx_process(dev);
4289 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4292 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4293 ixgbe_handle_lasi(hw);
4294 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4297 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4298 /* get the link status before link update, for predicting later */
4299 memset(&link, 0, sizeof(link));
4300 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4302 ixgbe_dev_link_update(dev, 0);
4305 if (!link.link_status)
4306 /* handle it 1 sec later, wait it being stable */
4307 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4308 /* likely to down */
4310 /* handle it 4 sec later, wait it being stable */
4311 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4313 ixgbe_dev_link_status_print(dev);
4314 if (rte_eal_alarm_set(timeout * 1000,
4315 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4316 PMD_DRV_LOG(ERR, "Error setting alarm");
4318 /* remember original mask */
4319 intr->mask_original = intr->mask;
4320 /* only disable lsc interrupt */
4321 intr->mask &= ~IXGBE_EIMS_LSC;
4325 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4326 ixgbe_enable_intr(dev);
4327 rte_intr_enable(intr_handle);
4333 * Interrupt handler which shall be registered for alarm callback for delayed
4334 * handling specific interrupt to wait for the stable nic state. As the
4335 * NIC interrupt state is not stable for ixgbe after link is just down,
4336 * it needs to wait 4 seconds to get the stable status.
4339 * Pointer to interrupt handle.
4341 * The address of parameter (struct rte_eth_dev *) regsitered before.
4347 ixgbe_dev_interrupt_delayed_handler(void *param)
4349 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4350 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4351 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4352 struct ixgbe_interrupt *intr =
4353 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4354 struct ixgbe_hw *hw =
4355 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 ixgbe_disable_intr(hw);
4360 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4361 if (eicr & IXGBE_EICR_MAILBOX)
4362 ixgbe_pf_mbx_process(dev);
4364 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4365 ixgbe_handle_lasi(hw);
4366 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4369 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4370 ixgbe_dev_link_update(dev, 0);
4371 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4372 ixgbe_dev_link_status_print(dev);
4373 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4377 if (intr->flags & IXGBE_FLAG_MACSEC) {
4378 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4380 intr->flags &= ~IXGBE_FLAG_MACSEC;
4383 /* restore original mask */
4384 intr->mask = intr->mask_original;
4385 intr->mask_original = 0;
4387 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4388 ixgbe_enable_intr(dev);
4389 rte_intr_enable(intr_handle);
4393 * Interrupt handler triggered by NIC for handling
4394 * specific interrupt.
4397 * Pointer to interrupt handle.
4399 * The address of parameter (struct rte_eth_dev *) regsitered before.
4405 ixgbe_dev_interrupt_handler(void *param)
4407 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4409 ixgbe_dev_interrupt_get_status(dev);
4410 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4414 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4416 struct ixgbe_hw *hw;
4418 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4419 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4423 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4425 struct ixgbe_hw *hw;
4427 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4432 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4434 struct ixgbe_hw *hw;
4440 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4442 fc_conf->pause_time = hw->fc.pause_time;
4443 fc_conf->high_water = hw->fc.high_water[0];
4444 fc_conf->low_water = hw->fc.low_water[0];
4445 fc_conf->send_xon = hw->fc.send_xon;
4446 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4449 * Return rx_pause status according to actual setting of
4452 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4453 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4459 * Return tx_pause status according to actual setting of
4462 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4463 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4468 if (rx_pause && tx_pause)
4469 fc_conf->mode = RTE_FC_FULL;
4471 fc_conf->mode = RTE_FC_RX_PAUSE;
4473 fc_conf->mode = RTE_FC_TX_PAUSE;
4475 fc_conf->mode = RTE_FC_NONE;
4481 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4483 struct ixgbe_hw *hw;
4485 uint32_t rx_buf_size;
4486 uint32_t max_high_water;
4488 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4495 PMD_INIT_FUNC_TRACE();
4497 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4499 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4502 * At least reserve one Ethernet frame for watermark
4503 * high_water/low_water in kilo bytes for ixgbe
4505 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4506 if ((fc_conf->high_water > max_high_water) ||
4507 (fc_conf->high_water < fc_conf->low_water)) {
4508 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4509 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4513 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4514 hw->fc.pause_time = fc_conf->pause_time;
4515 hw->fc.high_water[0] = fc_conf->high_water;
4516 hw->fc.low_water[0] = fc_conf->low_water;
4517 hw->fc.send_xon = fc_conf->send_xon;
4518 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4520 err = ixgbe_fc_enable(hw);
4522 /* Not negotiated is not an error case */
4523 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4525 /* check if we want to forward MAC frames - driver doesn't have native
4526 * capability to do that, so we'll write the registers ourselves */
4528 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4530 /* set or clear MFLCN.PMCF bit depending on configuration */
4531 if (fc_conf->mac_ctrl_frame_fwd != 0)
4532 mflcn |= IXGBE_MFLCN_PMCF;
4534 mflcn &= ~IXGBE_MFLCN_PMCF;
4536 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4537 IXGBE_WRITE_FLUSH(hw);
4542 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4547 * ixgbe_pfc_enable_generic - Enable flow control
4548 * @hw: pointer to hardware structure
4549 * @tc_num: traffic class number
4550 * Enable flow control according to the current settings.
4553 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4556 uint32_t mflcn_reg, fccfg_reg;
4558 uint32_t fcrtl, fcrth;
4562 /* Validate the water mark configuration */
4563 if (!hw->fc.pause_time) {
4564 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4568 /* Low water mark of zero causes XOFF floods */
4569 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4570 /* High/Low water can not be 0 */
4571 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4572 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4573 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4577 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4578 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4579 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4583 /* Negotiate the fc mode to use */
4584 ixgbe_fc_autoneg(hw);
4586 /* Disable any previous flow control settings */
4587 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4588 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4590 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4591 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4593 switch (hw->fc.current_mode) {
4596 * If the count of enabled RX Priority Flow control >1,
4597 * and the TX pause can not be disabled
4600 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4601 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4602 if (reg & IXGBE_FCRTH_FCEN)
4606 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4608 case ixgbe_fc_rx_pause:
4610 * Rx Flow control is enabled and Tx Flow control is
4611 * disabled by software override. Since there really
4612 * isn't a way to advertise that we are capable of RX
4613 * Pause ONLY, we will advertise that we support both
4614 * symmetric and asymmetric Rx PAUSE. Later, we will
4615 * disable the adapter's ability to send PAUSE frames.
4617 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4619 * If the count of enabled RX Priority Flow control >1,
4620 * and the TX pause can not be disabled
4623 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4624 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4625 if (reg & IXGBE_FCRTH_FCEN)
4629 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4631 case ixgbe_fc_tx_pause:
4633 * Tx Flow control is enabled, and Rx Flow control is
4634 * disabled by software override.
4636 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4639 /* Flow control (both Rx and Tx) is enabled by SW override. */
4640 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4641 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4644 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4645 ret_val = IXGBE_ERR_CONFIG;
4649 /* Set 802.3x based flow control settings. */
4650 mflcn_reg |= IXGBE_MFLCN_DPF;
4651 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4652 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4654 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4655 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4656 hw->fc.high_water[tc_num]) {
4657 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4658 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4659 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4661 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4663 * In order to prevent Tx hangs when the internal Tx
4664 * switch is enabled we must set the high water mark
4665 * to the maximum FCRTH value. This allows the Tx
4666 * switch to function even under heavy Rx workloads.
4668 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4670 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4672 /* Configure pause time (2 TCs per register) */
4673 reg = hw->fc.pause_time * 0x00010001;
4674 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4675 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4677 /* Configure flow control refresh threshold value */
4678 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4685 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4687 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4690 if (hw->mac.type != ixgbe_mac_82598EB) {
4691 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4697 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4700 uint32_t rx_buf_size;
4701 uint32_t max_high_water;
4703 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4704 struct ixgbe_hw *hw =
4705 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706 struct ixgbe_dcb_config *dcb_config =
4707 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4709 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4716 PMD_INIT_FUNC_TRACE();
4718 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4719 tc_num = map[pfc_conf->priority];
4720 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4721 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4723 * At least reserve one Ethernet frame for watermark
4724 * high_water/low_water in kilo bytes for ixgbe
4726 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4727 if ((pfc_conf->fc.high_water > max_high_water) ||
4728 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4729 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4730 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4734 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4735 hw->fc.pause_time = pfc_conf->fc.pause_time;
4736 hw->fc.send_xon = pfc_conf->fc.send_xon;
4737 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4738 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4740 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4742 /* Not negotiated is not an error case */
4743 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4746 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4751 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4752 struct rte_eth_rss_reta_entry64 *reta_conf,
4755 uint16_t i, sp_reta_size;
4758 uint16_t idx, shift;
4759 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762 PMD_INIT_FUNC_TRACE();
4764 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4765 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4770 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4771 if (reta_size != sp_reta_size) {
4772 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4773 "(%d) doesn't match the number hardware can supported "
4774 "(%d)", reta_size, sp_reta_size);
4778 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4779 idx = i / RTE_RETA_GROUP_SIZE;
4780 shift = i % RTE_RETA_GROUP_SIZE;
4781 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4785 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4786 if (mask == IXGBE_4_BIT_MASK)
4789 r = IXGBE_READ_REG(hw, reta_reg);
4790 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4791 if (mask & (0x1 << j))
4792 reta |= reta_conf[idx].reta[shift + j] <<
4795 reta |= r & (IXGBE_8_BIT_MASK <<
4798 IXGBE_WRITE_REG(hw, reta_reg, reta);
4805 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4806 struct rte_eth_rss_reta_entry64 *reta_conf,
4809 uint16_t i, sp_reta_size;
4812 uint16_t idx, shift;
4813 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816 PMD_INIT_FUNC_TRACE();
4817 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4818 if (reta_size != sp_reta_size) {
4819 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4820 "(%d) doesn't match the number hardware can supported "
4821 "(%d)", reta_size, sp_reta_size);
4825 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4826 idx = i / RTE_RETA_GROUP_SIZE;
4827 shift = i % RTE_RETA_GROUP_SIZE;
4828 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4833 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4834 reta = IXGBE_READ_REG(hw, reta_reg);
4835 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4836 if (mask & (0x1 << j))
4837 reta_conf[idx].reta[shift + j] =
4838 ((reta >> (CHAR_BIT * j)) &
4847 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4848 uint32_t index, uint32_t pool)
4850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851 uint32_t enable_addr = 1;
4853 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4858 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862 ixgbe_clear_rar(hw, index);
4866 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4870 ixgbe_remove_rar(dev, 0);
4872 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4876 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4878 if (strcmp(dev->device->driver->name, drv->driver.name))
4885 is_ixgbe_supported(struct rte_eth_dev *dev)
4887 return is_device_supported(dev, &rte_ixgbe_pmd);
4891 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4895 struct ixgbe_hw *hw;
4896 struct rte_eth_dev_info dev_info;
4897 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4898 struct rte_eth_dev_data *dev_data = dev->data;
4900 ixgbe_dev_info_get(dev, &dev_info);
4902 /* check that mtu is within the allowed range */
4903 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4906 /* If device is started, refuse mtu that requires the support of
4907 * scattered packets when this feature has not been enabled before.
4909 if (dev_data->dev_started && !dev_data->scattered_rx &&
4910 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4911 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4912 PMD_INIT_LOG(ERR, "Stop port first.");
4916 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4919 /* switch to jumbo mode if needed */
4920 if (frame_size > ETHER_MAX_LEN) {
4921 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4922 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4924 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4925 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4927 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4929 /* update max frame size */
4930 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4932 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4933 maxfrs &= 0x0000FFFF;
4934 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4935 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4941 * Virtual Function operations
4944 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4946 PMD_INIT_FUNC_TRACE();
4948 /* Clear interrupt mask to stop from interrupts being generated */
4949 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4951 IXGBE_WRITE_FLUSH(hw);
4955 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4957 PMD_INIT_FUNC_TRACE();
4959 /* VF enable interrupt autoclean */
4960 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4961 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4962 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4964 IXGBE_WRITE_FLUSH(hw);
4968 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4970 struct rte_eth_conf *conf = &dev->data->dev_conf;
4971 struct ixgbe_adapter *adapter =
4972 (struct ixgbe_adapter *)dev->data->dev_private;
4974 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4975 dev->data->port_id);
4978 * VF has no ability to enable/disable HW CRC
4979 * Keep the persistent behavior the same as Host PF
4981 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4982 if (!conf->rxmode.hw_strip_crc) {
4983 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4984 conf->rxmode.hw_strip_crc = 1;
4987 if (conf->rxmode.hw_strip_crc) {
4988 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4989 conf->rxmode.hw_strip_crc = 0;
4994 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4995 * allocation or vector Rx preconditions we will reset it.
4997 adapter->rx_bulk_alloc_allowed = true;
4998 adapter->rx_vec_allowed = true;
5004 ixgbevf_dev_start(struct rte_eth_dev *dev)
5006 struct ixgbe_hw *hw =
5007 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008 uint32_t intr_vector = 0;
5009 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5010 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5014 PMD_INIT_FUNC_TRACE();
5016 hw->mac.ops.reset_hw(hw);
5017 hw->mac.get_link_status = true;
5019 /* negotiate mailbox API version to use with the PF. */
5020 ixgbevf_negotiate_api(hw);
5022 ixgbevf_dev_tx_init(dev);
5024 /* This can fail when allocating mbufs for descriptor rings */
5025 err = ixgbevf_dev_rx_init(dev);
5027 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5028 ixgbe_dev_clear_queues(dev);
5033 ixgbevf_set_vfta_all(dev, 1);
5036 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5037 ETH_VLAN_EXTEND_MASK;
5038 ixgbevf_vlan_offload_set(dev, mask);
5040 ixgbevf_dev_rxtx_start(dev);
5042 /* check and configure queue intr-vector mapping */
5043 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5044 /* According to datasheet, only vector 0/1/2 can be used,
5045 * now only one vector is used for Rx queue
5048 if (rte_intr_efd_enable(intr_handle, intr_vector))
5052 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5053 intr_handle->intr_vec =
5054 rte_zmalloc("intr_vec",
5055 dev->data->nb_rx_queues * sizeof(int), 0);
5056 if (intr_handle->intr_vec == NULL) {
5057 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5058 " intr_vec", dev->data->nb_rx_queues);
5062 ixgbevf_configure_msix(dev);
5064 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5065 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5066 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5067 * is not cleared, it will fail when following rte_intr_enable( ) tries
5068 * to map Rx queue interrupt to other VFIO vectors.
5069 * So clear uio/vfio intr/evevnfd first to avoid failure.
5071 rte_intr_disable(intr_handle);
5073 rte_intr_enable(intr_handle);
5075 /* Re-enable interrupt for VF */
5076 ixgbevf_intr_enable(hw);
5082 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5086 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5088 PMD_INIT_FUNC_TRACE();
5090 ixgbevf_intr_disable(hw);
5092 hw->adapter_stopped = 1;
5093 ixgbe_stop_adapter(hw);
5096 * Clear what we set, but we still keep shadow_vfta to
5097 * restore after device starts
5099 ixgbevf_set_vfta_all(dev, 0);
5101 /* Clear stored conf */
5102 dev->data->scattered_rx = 0;
5104 ixgbe_dev_clear_queues(dev);
5106 /* Clean datapath event and queue/vec mapping */
5107 rte_intr_efd_disable(intr_handle);
5108 if (intr_handle->intr_vec != NULL) {
5109 rte_free(intr_handle->intr_vec);
5110 intr_handle->intr_vec = NULL;
5115 ixgbevf_dev_close(struct rte_eth_dev *dev)
5117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119 PMD_INIT_FUNC_TRACE();
5123 ixgbevf_dev_stop(dev);
5125 ixgbe_dev_free_queues(dev);
5128 * Remove the VF MAC address ro ensure
5129 * that the VF traffic goes to the PF
5130 * after stop, close and detach of the VF
5132 ixgbevf_remove_mac_addr(dev, 0);
5139 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5143 ret = eth_ixgbevf_dev_uninit(dev);
5147 ret = eth_ixgbevf_dev_init(dev);
5152 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155 struct ixgbe_vfta *shadow_vfta =
5156 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5157 int i = 0, j = 0, vfta = 0, mask = 1;
5159 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5160 vfta = shadow_vfta->vfta[i];
5163 for (j = 0; j < 32; j++) {
5165 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5175 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5177 struct ixgbe_hw *hw =
5178 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179 struct ixgbe_vfta *shadow_vfta =
5180 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5181 uint32_t vid_idx = 0;
5182 uint32_t vid_bit = 0;
5185 PMD_INIT_FUNC_TRACE();
5187 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5188 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5190 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5193 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5194 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5196 /* Save what we set and retore it after device reset */
5198 shadow_vfta->vfta[vid_idx] |= vid_bit;
5200 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5206 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5208 struct ixgbe_hw *hw =
5209 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212 PMD_INIT_FUNC_TRACE();
5214 if (queue >= hw->mac.max_rx_queues)
5217 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5219 ctrl |= IXGBE_RXDCTL_VME;
5221 ctrl &= ~IXGBE_RXDCTL_VME;
5222 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5224 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5228 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5230 struct ixgbe_hw *hw =
5231 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235 /* VF function only support hw strip feature, others are not support */
5236 if (mask & ETH_VLAN_STRIP_MASK) {
5237 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5239 for (i = 0; i < hw->mac.max_rx_queues; i++)
5240 ixgbevf_vlan_strip_queue_set(dev, i, on);
5245 ixgbe_vt_check(struct ixgbe_hw *hw)
5249 /* if Virtualization Technology is enabled */
5250 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5251 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5252 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5260 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5262 uint32_t vector = 0;
5264 switch (hw->mac.mc_filter_type) {
5265 case 0: /* use bits [47:36] of the address */
5266 vector = ((uc_addr->addr_bytes[4] >> 4) |
5267 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5269 case 1: /* use bits [46:35] of the address */
5270 vector = ((uc_addr->addr_bytes[4] >> 3) |
5271 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5273 case 2: /* use bits [45:34] of the address */
5274 vector = ((uc_addr->addr_bytes[4] >> 2) |
5275 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5277 case 3: /* use bits [43:32] of the address */
5278 vector = ((uc_addr->addr_bytes[4]) |
5279 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5281 default: /* Invalid mc_filter_type */
5285 /* vector can only be 12-bits or boundary will be exceeded */
5291 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5299 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5300 const uint32_t ixgbe_uta_bit_shift = 5;
5301 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5302 const uint32_t bit1 = 0x1;
5304 struct ixgbe_hw *hw =
5305 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5306 struct ixgbe_uta_info *uta_info =
5307 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5309 /* The UTA table only exists on 82599 hardware and newer */
5310 if (hw->mac.type < ixgbe_mac_82599EB)
5313 vector = ixgbe_uta_vector(hw, mac_addr);
5314 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5315 uta_shift = vector & ixgbe_uta_bit_mask;
5317 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5321 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5323 uta_info->uta_in_use++;
5324 reg_val |= (bit1 << uta_shift);
5325 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5327 uta_info->uta_in_use--;
5328 reg_val &= ~(bit1 << uta_shift);
5329 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5332 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5334 if (uta_info->uta_in_use > 0)
5335 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5336 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5338 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5344 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5347 struct ixgbe_hw *hw =
5348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349 struct ixgbe_uta_info *uta_info =
5350 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5352 /* The UTA table only exists on 82599 hardware and newer */
5353 if (hw->mac.type < ixgbe_mac_82599EB)
5357 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5358 uta_info->uta_shadow[i] = ~0;
5359 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5362 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5363 uta_info->uta_shadow[i] = 0;
5364 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5372 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5374 uint32_t new_val = orig_val;
5376 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5377 new_val |= IXGBE_VMOLR_AUPE;
5378 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5379 new_val |= IXGBE_VMOLR_ROMPE;
5380 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5381 new_val |= IXGBE_VMOLR_ROPE;
5382 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5383 new_val |= IXGBE_VMOLR_BAM;
5384 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5385 new_val |= IXGBE_VMOLR_MPE;
5390 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5391 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5392 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5393 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5394 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5395 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5396 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5399 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5400 struct rte_eth_mirror_conf *mirror_conf,
5401 uint8_t rule_id, uint8_t on)
5403 uint32_t mr_ctl, vlvf;
5404 uint32_t mp_lsb = 0;
5405 uint32_t mv_msb = 0;
5406 uint32_t mv_lsb = 0;
5407 uint32_t mp_msb = 0;
5410 uint64_t vlan_mask = 0;
5412 const uint8_t pool_mask_offset = 32;
5413 const uint8_t vlan_mask_offset = 32;
5414 const uint8_t dst_pool_offset = 8;
5415 const uint8_t rule_mr_offset = 4;
5416 const uint8_t mirror_rule_mask = 0x0F;
5418 struct ixgbe_mirror_info *mr_info =
5419 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5420 struct ixgbe_hw *hw =
5421 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422 uint8_t mirror_type = 0;
5424 if (ixgbe_vt_check(hw) < 0)
5427 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5430 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5431 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5432 mirror_conf->rule_type);
5436 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5437 mirror_type |= IXGBE_MRCTL_VLME;
5438 /* Check if vlan id is valid and find conresponding VLAN ID
5441 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5442 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5443 /* search vlan id related pool vlan filter
5446 reg_index = ixgbe_find_vlvf_slot(
5448 mirror_conf->vlan.vlan_id[i],
5452 vlvf = IXGBE_READ_REG(hw,
5453 IXGBE_VLVF(reg_index));
5454 if ((vlvf & IXGBE_VLVF_VIEN) &&
5455 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5456 mirror_conf->vlan.vlan_id[i]))
5457 vlan_mask |= (1ULL << reg_index);
5464 mv_lsb = vlan_mask & 0xFFFFFFFF;
5465 mv_msb = vlan_mask >> vlan_mask_offset;
5467 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5468 mirror_conf->vlan.vlan_mask;
5469 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5470 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5471 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5472 mirror_conf->vlan.vlan_id[i];
5477 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5478 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5479 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5484 * if enable pool mirror, write related pool mask register,if disable
5485 * pool mirror, clear PFMRVM register
5487 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5488 mirror_type |= IXGBE_MRCTL_VPME;
5490 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5491 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5492 mr_info->mr_conf[rule_id].pool_mask =
5493 mirror_conf->pool_mask;
5498 mr_info->mr_conf[rule_id].pool_mask = 0;
5501 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5502 mirror_type |= IXGBE_MRCTL_UPME;
5503 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5504 mirror_type |= IXGBE_MRCTL_DPME;
5506 /* read mirror control register and recalculate it */
5507 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5510 mr_ctl |= mirror_type;
5511 mr_ctl &= mirror_rule_mask;
5512 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5514 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5517 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5518 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5520 /* write mirrror control register */
5521 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5523 /* write pool mirrror control register */
5524 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5525 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5526 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5529 /* write VLAN mirrror control register */
5530 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5531 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5532 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5540 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5543 uint32_t lsb_val = 0;
5544 uint32_t msb_val = 0;
5545 const uint8_t rule_mr_offset = 4;
5547 struct ixgbe_hw *hw =
5548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549 struct ixgbe_mirror_info *mr_info =
5550 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5552 if (ixgbe_vt_check(hw) < 0)
5555 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5558 memset(&mr_info->mr_conf[rule_id], 0,
5559 sizeof(struct rte_eth_mirror_conf));
5561 /* clear PFVMCTL register */
5562 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5564 /* clear pool mask register */
5565 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5566 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5568 /* clear vlan mask register */
5569 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5570 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5576 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5578 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5579 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5581 struct ixgbe_hw *hw =
5582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583 uint32_t vec = IXGBE_MISC_VEC_ID;
5585 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5586 if (rte_intr_allow_others(intr_handle))
5587 vec = IXGBE_RX_VEC_START;
5589 RTE_SET_USED(queue_id);
5590 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5592 rte_intr_enable(intr_handle);
5598 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5601 struct ixgbe_hw *hw =
5602 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5604 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5605 uint32_t vec = IXGBE_MISC_VEC_ID;
5607 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5608 if (rte_intr_allow_others(intr_handle))
5609 vec = IXGBE_RX_VEC_START;
5610 mask &= ~(1 << vec);
5611 RTE_SET_USED(queue_id);
5612 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5618 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5620 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5621 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5623 struct ixgbe_hw *hw =
5624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625 struct ixgbe_interrupt *intr =
5626 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5628 if (queue_id < 16) {
5629 ixgbe_disable_intr(hw);
5630 intr->mask |= (1 << queue_id);
5631 ixgbe_enable_intr(dev);
5632 } else if (queue_id < 32) {
5633 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5634 mask &= (1 << queue_id);
5635 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5636 } else if (queue_id < 64) {
5637 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5638 mask &= (1 << (queue_id - 32));
5639 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5641 rte_intr_enable(intr_handle);
5647 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5650 struct ixgbe_hw *hw =
5651 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5652 struct ixgbe_interrupt *intr =
5653 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5655 if (queue_id < 16) {
5656 ixgbe_disable_intr(hw);
5657 intr->mask &= ~(1 << queue_id);
5658 ixgbe_enable_intr(dev);
5659 } else if (queue_id < 32) {
5660 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5661 mask &= ~(1 << queue_id);
5662 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5663 } else if (queue_id < 64) {
5664 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5665 mask &= ~(1 << (queue_id - 32));
5666 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5673 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5674 uint8_t queue, uint8_t msix_vector)
5678 if (direction == -1) {
5680 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5681 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5684 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5686 /* rx or tx cause */
5687 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5688 idx = ((16 * (queue & 1)) + (8 * direction));
5689 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5690 tmp &= ~(0xFF << idx);
5691 tmp |= (msix_vector << idx);
5692 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5697 * set the IVAR registers, mapping interrupt causes to vectors
5699 * pointer to ixgbe_hw struct
5701 * 0 for Rx, 1 for Tx, -1 for other causes
5703 * queue to map the corresponding interrupt to
5705 * the vector to map to the corresponding queue
5708 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5709 uint8_t queue, uint8_t msix_vector)
5713 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5714 if (hw->mac.type == ixgbe_mac_82598EB) {
5715 if (direction == -1)
5717 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5718 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5719 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5720 tmp |= (msix_vector << (8 * (queue & 0x3)));
5721 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5722 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5723 (hw->mac.type == ixgbe_mac_X540) ||
5724 (hw->mac.type == ixgbe_mac_X550)) {
5725 if (direction == -1) {
5727 idx = ((queue & 1) * 8);
5728 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5729 tmp &= ~(0xFF << idx);
5730 tmp |= (msix_vector << idx);
5731 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5733 /* rx or tx causes */
5734 idx = ((16 * (queue & 1)) + (8 * direction));
5735 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5736 tmp &= ~(0xFF << idx);
5737 tmp |= (msix_vector << idx);
5738 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5744 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5746 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5747 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5748 struct ixgbe_hw *hw =
5749 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5752 uint32_t base = IXGBE_MISC_VEC_ID;
5754 /* Configure VF other cause ivar */
5755 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5757 /* won't configure msix register if no mapping is done
5758 * between intr vector and event fd.
5760 if (!rte_intr_dp_is_en(intr_handle))
5763 if (rte_intr_allow_others(intr_handle)) {
5764 base = IXGBE_RX_VEC_START;
5765 vector_idx = IXGBE_RX_VEC_START;
5768 /* Configure all RX queues of VF */
5769 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5770 /* Force all queue use vector 0,
5771 * as IXGBE_VF_MAXMSIVECOTR = 1
5773 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5774 intr_handle->intr_vec[q_idx] = vector_idx;
5775 if (vector_idx < base + intr_handle->nb_efd - 1)
5781 * Sets up the hardware to properly generate MSI-X interrupts
5783 * board private structure
5786 ixgbe_configure_msix(struct rte_eth_dev *dev)
5788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5790 struct ixgbe_hw *hw =
5791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5792 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5793 uint32_t vec = IXGBE_MISC_VEC_ID;
5797 /* won't configure msix register if no mapping is done
5798 * between intr vector and event fd
5800 if (!rte_intr_dp_is_en(intr_handle))
5803 if (rte_intr_allow_others(intr_handle))
5804 vec = base = IXGBE_RX_VEC_START;
5806 /* setup GPIE for MSI-x mode */
5807 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5808 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5809 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5810 /* auto clearing and auto setting corresponding bits in EIMS
5811 * when MSI-X interrupt is triggered
5813 if (hw->mac.type == ixgbe_mac_82598EB) {
5814 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5816 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5817 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5819 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5821 /* Populate the IVAR table and set the ITR values to the
5822 * corresponding register.
5824 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5826 /* by default, 1:1 mapping */
5827 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5828 intr_handle->intr_vec[queue_id] = vec;
5829 if (vec < base + intr_handle->nb_efd - 1)
5833 switch (hw->mac.type) {
5834 case ixgbe_mac_82598EB:
5835 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5838 case ixgbe_mac_82599EB:
5839 case ixgbe_mac_X540:
5840 case ixgbe_mac_X550:
5841 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5846 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5847 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5849 /* set up to autoclear timer, and the vectors */
5850 mask = IXGBE_EIMS_ENABLE_MASK;
5851 mask &= ~(IXGBE_EIMS_OTHER |
5852 IXGBE_EIMS_MAILBOX |
5855 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5859 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5860 uint16_t queue_idx, uint16_t tx_rate)
5862 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5863 uint32_t rf_dec, rf_int;
5865 uint16_t link_speed = dev->data->dev_link.link_speed;
5867 if (queue_idx >= hw->mac.max_tx_queues)
5871 /* Calculate the rate factor values to set */
5872 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5873 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5874 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5876 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5877 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5878 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5879 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5885 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5886 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5889 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5890 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5891 IXGBE_MAX_JUMBO_FRAME_SIZE))
5892 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5893 IXGBE_MMW_SIZE_JUMBO_FRAME);
5895 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5896 IXGBE_MMW_SIZE_DEFAULT);
5898 /* Set RTTBCNRC of queue X */
5899 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5900 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5901 IXGBE_WRITE_FLUSH(hw);
5907 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5908 __attribute__((unused)) uint32_t index,
5909 __attribute__((unused)) uint32_t pool)
5911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5915 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5916 * operation. Trap this case to avoid exhausting the [very limited]
5917 * set of PF resources used to store VF MAC addresses.
5919 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5921 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5923 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5924 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5925 mac_addr->addr_bytes[0],
5926 mac_addr->addr_bytes[1],
5927 mac_addr->addr_bytes[2],
5928 mac_addr->addr_bytes[3],
5929 mac_addr->addr_bytes[4],
5930 mac_addr->addr_bytes[5],
5936 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5940 struct ether_addr *mac_addr;
5945 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5946 * not support the deletion of a given MAC address.
5947 * Instead, it imposes to delete all MAC addresses, then to add again
5948 * all MAC addresses with the exception of the one to be deleted.
5950 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5953 * Add again all MAC addresses, with the exception of the deleted one
5954 * and of the permanent MAC address.
5956 for (i = 0, mac_addr = dev->data->mac_addrs;
5957 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5958 /* Skip the deleted MAC address */
5961 /* Skip NULL MAC addresses */
5962 if (is_zero_ether_addr(mac_addr))
5964 /* Skip the permanent MAC address */
5965 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5967 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5970 "Adding again MAC address "
5971 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5973 mac_addr->addr_bytes[0],
5974 mac_addr->addr_bytes[1],
5975 mac_addr->addr_bytes[2],
5976 mac_addr->addr_bytes[3],
5977 mac_addr->addr_bytes[4],
5978 mac_addr->addr_bytes[5],
5984 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5988 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5992 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5993 struct rte_eth_syn_filter *filter,
5996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5997 struct ixgbe_filter_info *filter_info =
5998 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6002 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6005 syn_info = filter_info->syn_info;
6008 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6010 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6011 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6013 if (filter->hig_pri)
6014 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6016 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6018 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6019 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6021 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6024 filter_info->syn_info = synqf;
6025 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6026 IXGBE_WRITE_FLUSH(hw);
6031 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6032 struct rte_eth_syn_filter *filter)
6034 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6035 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6037 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6038 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6039 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6046 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6047 enum rte_filter_op filter_op,
6050 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6053 MAC_TYPE_FILTER_SUP(hw->mac.type);
6055 if (filter_op == RTE_ETH_FILTER_NOP)
6059 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6064 switch (filter_op) {
6065 case RTE_ETH_FILTER_ADD:
6066 ret = ixgbe_syn_filter_set(dev,
6067 (struct rte_eth_syn_filter *)arg,
6070 case RTE_ETH_FILTER_DELETE:
6071 ret = ixgbe_syn_filter_set(dev,
6072 (struct rte_eth_syn_filter *)arg,
6075 case RTE_ETH_FILTER_GET:
6076 ret = ixgbe_syn_filter_get(dev,
6077 (struct rte_eth_syn_filter *)arg);
6080 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6089 static inline enum ixgbe_5tuple_protocol
6090 convert_protocol_type(uint8_t protocol_value)
6092 if (protocol_value == IPPROTO_TCP)
6093 return IXGBE_FILTER_PROTOCOL_TCP;
6094 else if (protocol_value == IPPROTO_UDP)
6095 return IXGBE_FILTER_PROTOCOL_UDP;
6096 else if (protocol_value == IPPROTO_SCTP)
6097 return IXGBE_FILTER_PROTOCOL_SCTP;
6099 return IXGBE_FILTER_PROTOCOL_NONE;
6102 /* inject a 5-tuple filter to HW */
6104 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6105 struct ixgbe_5tuple_filter *filter)
6107 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109 uint32_t ftqf, sdpqf;
6110 uint32_t l34timir = 0;
6111 uint8_t mask = 0xff;
6115 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6116 IXGBE_SDPQF_DSTPORT_SHIFT);
6117 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6119 ftqf = (uint32_t)(filter->filter_info.proto &
6120 IXGBE_FTQF_PROTOCOL_MASK);
6121 ftqf |= (uint32_t)((filter->filter_info.priority &
6122 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6123 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6124 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6125 if (filter->filter_info.dst_ip_mask == 0)
6126 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6127 if (filter->filter_info.src_port_mask == 0)
6128 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6129 if (filter->filter_info.dst_port_mask == 0)
6130 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6131 if (filter->filter_info.proto_mask == 0)
6132 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6133 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6134 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6135 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6137 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6138 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6139 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6140 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6142 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6143 l34timir |= (uint32_t)(filter->queue <<
6144 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6145 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6149 * add a 5tuple filter
6152 * dev: Pointer to struct rte_eth_dev.
6153 * index: the index the filter allocates.
6154 * filter: ponter to the filter that will be added.
6155 * rx_queue: the queue id the filter assigned to.
6158 * - On success, zero.
6159 * - On failure, a negative value.
6162 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6163 struct ixgbe_5tuple_filter *filter)
6165 struct ixgbe_filter_info *filter_info =
6166 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6170 * look for an unused 5tuple filter index,
6171 * and insert the filter to list.
6173 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6174 idx = i / (sizeof(uint32_t) * NBBY);
6175 shift = i % (sizeof(uint32_t) * NBBY);
6176 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6177 filter_info->fivetuple_mask[idx] |= 1 << shift;
6179 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6185 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6186 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6190 ixgbe_inject_5tuple_filter(dev, filter);
6196 * remove a 5tuple filter
6199 * dev: Pointer to struct rte_eth_dev.
6200 * filter: the pointer of the filter will be removed.
6203 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6204 struct ixgbe_5tuple_filter *filter)
6206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6207 struct ixgbe_filter_info *filter_info =
6208 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6209 uint16_t index = filter->index;
6211 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6212 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6213 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6216 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6217 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6218 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6219 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6220 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6224 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6226 struct ixgbe_hw *hw;
6227 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6228 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6230 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6232 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6235 /* refuse mtu that requires the support of scattered packets when this
6236 * feature has not been enabled before.
6238 if (!rx_conf->enable_scatter &&
6239 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6240 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6244 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6245 * request of the version 2.0 of the mailbox API.
6246 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6247 * of the mailbox API.
6248 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6249 * prior to 3.11.33 which contains the following change:
6250 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6252 ixgbevf_rlpml_set_vf(hw, max_frame);
6254 /* update max frame size */
6255 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6259 static inline struct ixgbe_5tuple_filter *
6260 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6261 struct ixgbe_5tuple_filter_info *key)
6263 struct ixgbe_5tuple_filter *it;
6265 TAILQ_FOREACH(it, filter_list, entries) {
6266 if (memcmp(key, &it->filter_info,
6267 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6274 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6276 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6277 struct ixgbe_5tuple_filter_info *filter_info)
6279 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6280 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6281 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6284 switch (filter->dst_ip_mask) {
6286 filter_info->dst_ip_mask = 0;
6287 filter_info->dst_ip = filter->dst_ip;
6290 filter_info->dst_ip_mask = 1;
6293 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6297 switch (filter->src_ip_mask) {
6299 filter_info->src_ip_mask = 0;
6300 filter_info->src_ip = filter->src_ip;
6303 filter_info->src_ip_mask = 1;
6306 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6310 switch (filter->dst_port_mask) {
6312 filter_info->dst_port_mask = 0;
6313 filter_info->dst_port = filter->dst_port;
6316 filter_info->dst_port_mask = 1;
6319 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6323 switch (filter->src_port_mask) {
6325 filter_info->src_port_mask = 0;
6326 filter_info->src_port = filter->src_port;
6329 filter_info->src_port_mask = 1;
6332 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6336 switch (filter->proto_mask) {
6338 filter_info->proto_mask = 0;
6339 filter_info->proto =
6340 convert_protocol_type(filter->proto);
6343 filter_info->proto_mask = 1;
6346 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6350 filter_info->priority = (uint8_t)filter->priority;
6355 * add or delete a ntuple filter
6358 * dev: Pointer to struct rte_eth_dev.
6359 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6360 * add: if true, add filter, if false, remove filter
6363 * - On success, zero.
6364 * - On failure, a negative value.
6367 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6368 struct rte_eth_ntuple_filter *ntuple_filter,
6371 struct ixgbe_filter_info *filter_info =
6372 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373 struct ixgbe_5tuple_filter_info filter_5tuple;
6374 struct ixgbe_5tuple_filter *filter;
6377 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6378 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6382 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6383 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6387 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6389 if (filter != NULL && add) {
6390 PMD_DRV_LOG(ERR, "filter exists.");
6393 if (filter == NULL && !add) {
6394 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6399 filter = rte_zmalloc("ixgbe_5tuple_filter",
6400 sizeof(struct ixgbe_5tuple_filter), 0);
6403 rte_memcpy(&filter->filter_info,
6405 sizeof(struct ixgbe_5tuple_filter_info));
6406 filter->queue = ntuple_filter->queue;
6407 ret = ixgbe_add_5tuple_filter(dev, filter);
6413 ixgbe_remove_5tuple_filter(dev, filter);
6419 * get a ntuple filter
6422 * dev: Pointer to struct rte_eth_dev.
6423 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6426 * - On success, zero.
6427 * - On failure, a negative value.
6430 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6431 struct rte_eth_ntuple_filter *ntuple_filter)
6433 struct ixgbe_filter_info *filter_info =
6434 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435 struct ixgbe_5tuple_filter_info filter_5tuple;
6436 struct ixgbe_5tuple_filter *filter;
6439 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6440 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6444 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6445 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6449 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6451 if (filter == NULL) {
6452 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6455 ntuple_filter->queue = filter->queue;
6460 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6461 * @dev: pointer to rte_eth_dev structure
6462 * @filter_op:operation will be taken.
6463 * @arg: a pointer to specific structure corresponding to the filter_op
6466 * - On success, zero.
6467 * - On failure, a negative value.
6470 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6471 enum rte_filter_op filter_op,
6474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6477 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6479 if (filter_op == RTE_ETH_FILTER_NOP)
6483 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6488 switch (filter_op) {
6489 case RTE_ETH_FILTER_ADD:
6490 ret = ixgbe_add_del_ntuple_filter(dev,
6491 (struct rte_eth_ntuple_filter *)arg,
6494 case RTE_ETH_FILTER_DELETE:
6495 ret = ixgbe_add_del_ntuple_filter(dev,
6496 (struct rte_eth_ntuple_filter *)arg,
6499 case RTE_ETH_FILTER_GET:
6500 ret = ixgbe_get_ntuple_filter(dev,
6501 (struct rte_eth_ntuple_filter *)arg);
6504 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6512 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6513 struct rte_eth_ethertype_filter *filter,
6516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517 struct ixgbe_filter_info *filter_info =
6518 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6522 struct ixgbe_ethertype_filter ethertype_filter;
6524 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6527 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6528 filter->ether_type == ETHER_TYPE_IPv6) {
6529 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6530 " ethertype filter.", filter->ether_type);
6534 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6535 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6538 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6539 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6543 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6544 if (ret >= 0 && add) {
6545 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6546 filter->ether_type);
6549 if (ret < 0 && !add) {
6550 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6551 filter->ether_type);
6556 etqf = IXGBE_ETQF_FILTER_EN;
6557 etqf |= (uint32_t)filter->ether_type;
6558 etqs |= (uint32_t)((filter->queue <<
6559 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6560 IXGBE_ETQS_RX_QUEUE);
6561 etqs |= IXGBE_ETQS_QUEUE_EN;
6563 ethertype_filter.ethertype = filter->ether_type;
6564 ethertype_filter.etqf = etqf;
6565 ethertype_filter.etqs = etqs;
6566 ethertype_filter.conf = FALSE;
6567 ret = ixgbe_ethertype_filter_insert(filter_info,
6570 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6574 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6578 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6579 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6580 IXGBE_WRITE_FLUSH(hw);
6586 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6587 struct rte_eth_ethertype_filter *filter)
6589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590 struct ixgbe_filter_info *filter_info =
6591 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592 uint32_t etqf, etqs;
6595 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6597 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6598 filter->ether_type);
6602 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6603 if (etqf & IXGBE_ETQF_FILTER_EN) {
6604 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6605 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6607 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6608 IXGBE_ETQS_RX_QUEUE_SHIFT;
6615 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6616 * @dev: pointer to rte_eth_dev structure
6617 * @filter_op:operation will be taken.
6618 * @arg: a pointer to specific structure corresponding to the filter_op
6621 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6622 enum rte_filter_op filter_op,
6625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6628 MAC_TYPE_FILTER_SUP(hw->mac.type);
6630 if (filter_op == RTE_ETH_FILTER_NOP)
6634 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6639 switch (filter_op) {
6640 case RTE_ETH_FILTER_ADD:
6641 ret = ixgbe_add_del_ethertype_filter(dev,
6642 (struct rte_eth_ethertype_filter *)arg,
6645 case RTE_ETH_FILTER_DELETE:
6646 ret = ixgbe_add_del_ethertype_filter(dev,
6647 (struct rte_eth_ethertype_filter *)arg,
6650 case RTE_ETH_FILTER_GET:
6651 ret = ixgbe_get_ethertype_filter(dev,
6652 (struct rte_eth_ethertype_filter *)arg);
6655 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6663 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6664 enum rte_filter_type filter_type,
6665 enum rte_filter_op filter_op,
6670 switch (filter_type) {
6671 case RTE_ETH_FILTER_NTUPLE:
6672 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6674 case RTE_ETH_FILTER_ETHERTYPE:
6675 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6677 case RTE_ETH_FILTER_SYN:
6678 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6680 case RTE_ETH_FILTER_FDIR:
6681 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6683 case RTE_ETH_FILTER_L2_TUNNEL:
6684 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6686 case RTE_ETH_FILTER_GENERIC:
6687 if (filter_op != RTE_ETH_FILTER_GET)
6689 *(const void **)arg = &ixgbe_flow_ops;
6692 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6702 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6703 u8 **mc_addr_ptr, u32 *vmdq)
6708 mc_addr = *mc_addr_ptr;
6709 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6714 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6715 struct ether_addr *mc_addr_set,
6716 uint32_t nb_mc_addr)
6718 struct ixgbe_hw *hw;
6721 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722 mc_addr_list = (u8 *)mc_addr_set;
6723 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6724 ixgbe_dev_addr_list_itr, TRUE);
6728 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731 uint64_t systime_cycles;
6733 switch (hw->mac.type) {
6734 case ixgbe_mac_X550:
6735 case ixgbe_mac_X550EM_x:
6736 case ixgbe_mac_X550EM_a:
6737 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6738 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6743 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6744 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6748 return systime_cycles;
6752 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6754 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755 uint64_t rx_tstamp_cycles;
6757 switch (hw->mac.type) {
6758 case ixgbe_mac_X550:
6759 case ixgbe_mac_X550EM_x:
6760 case ixgbe_mac_X550EM_a:
6761 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6762 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6763 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6767 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6768 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6769 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6773 return rx_tstamp_cycles;
6777 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780 uint64_t tx_tstamp_cycles;
6782 switch (hw->mac.type) {
6783 case ixgbe_mac_X550:
6784 case ixgbe_mac_X550EM_x:
6785 case ixgbe_mac_X550EM_a:
6786 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6787 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6788 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6792 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6793 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6794 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6798 return tx_tstamp_cycles;
6802 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6804 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805 struct ixgbe_adapter *adapter =
6806 (struct ixgbe_adapter *)dev->data->dev_private;
6807 struct rte_eth_link link;
6808 uint32_t incval = 0;
6811 /* Get current link speed. */
6812 memset(&link, 0, sizeof(link));
6813 ixgbe_dev_link_update(dev, 1);
6814 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6816 switch (link.link_speed) {
6817 case ETH_SPEED_NUM_100M:
6818 incval = IXGBE_INCVAL_100;
6819 shift = IXGBE_INCVAL_SHIFT_100;
6821 case ETH_SPEED_NUM_1G:
6822 incval = IXGBE_INCVAL_1GB;
6823 shift = IXGBE_INCVAL_SHIFT_1GB;
6825 case ETH_SPEED_NUM_10G:
6827 incval = IXGBE_INCVAL_10GB;
6828 shift = IXGBE_INCVAL_SHIFT_10GB;
6832 switch (hw->mac.type) {
6833 case ixgbe_mac_X550:
6834 case ixgbe_mac_X550EM_x:
6835 case ixgbe_mac_X550EM_a:
6836 /* Independent of link speed. */
6838 /* Cycles read will be interpreted as ns. */
6841 case ixgbe_mac_X540:
6842 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6844 case ixgbe_mac_82599EB:
6845 incval >>= IXGBE_INCVAL_SHIFT_82599;
6846 shift -= IXGBE_INCVAL_SHIFT_82599;
6847 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6848 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6851 /* Not supported. */
6855 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6856 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6857 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6859 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6860 adapter->systime_tc.cc_shift = shift;
6861 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6863 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864 adapter->rx_tstamp_tc.cc_shift = shift;
6865 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6867 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6868 adapter->tx_tstamp_tc.cc_shift = shift;
6869 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6873 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6875 struct ixgbe_adapter *adapter =
6876 (struct ixgbe_adapter *)dev->data->dev_private;
6878 adapter->systime_tc.nsec += delta;
6879 adapter->rx_tstamp_tc.nsec += delta;
6880 adapter->tx_tstamp_tc.nsec += delta;
6886 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6889 struct ixgbe_adapter *adapter =
6890 (struct ixgbe_adapter *)dev->data->dev_private;
6892 ns = rte_timespec_to_ns(ts);
6893 /* Set the timecounters to a new value. */
6894 adapter->systime_tc.nsec = ns;
6895 adapter->rx_tstamp_tc.nsec = ns;
6896 adapter->tx_tstamp_tc.nsec = ns;
6902 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6904 uint64_t ns, systime_cycles;
6905 struct ixgbe_adapter *adapter =
6906 (struct ixgbe_adapter *)dev->data->dev_private;
6908 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6909 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6910 *ts = rte_ns_to_timespec(ns);
6916 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922 /* Stop the timesync system time. */
6923 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6924 /* Reset the timesync system time value. */
6925 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6926 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6928 /* Enable system time for platforms where it isn't on by default. */
6929 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6930 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6931 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6933 ixgbe_start_timecounters(dev);
6935 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6936 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6938 IXGBE_ETQF_FILTER_EN |
6941 /* Enable timestamping of received PTP packets. */
6942 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6943 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6944 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6946 /* Enable timestamping of transmitted PTP packets. */
6947 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6948 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6949 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6951 IXGBE_WRITE_FLUSH(hw);
6957 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962 /* Disable timestamping of transmitted PTP packets. */
6963 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6964 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6965 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6967 /* Disable timestamping of received PTP packets. */
6968 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6969 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6970 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6972 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6973 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6975 /* Stop incrementating the System Time registers. */
6976 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6982 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6983 struct timespec *timestamp,
6984 uint32_t flags __rte_unused)
6986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987 struct ixgbe_adapter *adapter =
6988 (struct ixgbe_adapter *)dev->data->dev_private;
6989 uint32_t tsync_rxctl;
6990 uint64_t rx_tstamp_cycles;
6993 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6994 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6997 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6998 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6999 *timestamp = rte_ns_to_timespec(ns);
7005 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7006 struct timespec *timestamp)
7008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009 struct ixgbe_adapter *adapter =
7010 (struct ixgbe_adapter *)dev->data->dev_private;
7011 uint32_t tsync_txctl;
7012 uint64_t tx_tstamp_cycles;
7015 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7016 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7019 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7020 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7021 *timestamp = rte_ns_to_timespec(ns);
7027 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032 const struct reg_info *reg_group;
7033 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7034 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7036 while ((reg_group = reg_set[g_ind++]))
7037 count += ixgbe_regs_group_count(reg_group);
7043 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7047 const struct reg_info *reg_group;
7049 while ((reg_group = ixgbevf_regs[g_ind++]))
7050 count += ixgbe_regs_group_count(reg_group);
7056 ixgbe_get_regs(struct rte_eth_dev *dev,
7057 struct rte_dev_reg_info *regs)
7059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060 uint32_t *data = regs->data;
7063 const struct reg_info *reg_group;
7064 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7065 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7068 regs->length = ixgbe_get_reg_length(dev);
7069 regs->width = sizeof(uint32_t);
7073 /* Support only full register dump */
7074 if ((regs->length == 0) ||
7075 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7076 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7078 while ((reg_group = reg_set[g_ind++]))
7079 count += ixgbe_read_regs_group(dev, &data[count],
7088 ixgbevf_get_regs(struct rte_eth_dev *dev,
7089 struct rte_dev_reg_info *regs)
7091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092 uint32_t *data = regs->data;
7095 const struct reg_info *reg_group;
7098 regs->length = ixgbevf_get_reg_length(dev);
7099 regs->width = sizeof(uint32_t);
7103 /* Support only full register dump */
7104 if ((regs->length == 0) ||
7105 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7106 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7108 while ((reg_group = ixgbevf_regs[g_ind++]))
7109 count += ixgbe_read_regs_group(dev, &data[count],
7118 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 /* Return unit is byte count */
7123 return hw->eeprom.word_size * 2;
7127 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7128 struct rte_dev_eeprom_info *in_eeprom)
7130 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7131 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7132 uint16_t *data = in_eeprom->data;
7135 first = in_eeprom->offset >> 1;
7136 length = in_eeprom->length >> 1;
7137 if ((first > hw->eeprom.word_size) ||
7138 ((first + length) > hw->eeprom.word_size))
7141 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7143 return eeprom->ops.read_buffer(hw, first, length, data);
7147 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7148 struct rte_dev_eeprom_info *in_eeprom)
7150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7152 uint16_t *data = in_eeprom->data;
7155 first = in_eeprom->offset >> 1;
7156 length = in_eeprom->length >> 1;
7157 if ((first > hw->eeprom.word_size) ||
7158 ((first + length) > hw->eeprom.word_size))
7161 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7163 return eeprom->ops.write_buffer(hw, first, length, data);
7167 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7169 case ixgbe_mac_X550:
7170 case ixgbe_mac_X550EM_x:
7171 case ixgbe_mac_X550EM_a:
7172 return ETH_RSS_RETA_SIZE_512;
7173 case ixgbe_mac_X550_vf:
7174 case ixgbe_mac_X550EM_x_vf:
7175 case ixgbe_mac_X550EM_a_vf:
7176 return ETH_RSS_RETA_SIZE_64;
7178 return ETH_RSS_RETA_SIZE_128;
7183 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7185 case ixgbe_mac_X550:
7186 case ixgbe_mac_X550EM_x:
7187 case ixgbe_mac_X550EM_a:
7188 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7189 return IXGBE_RETA(reta_idx >> 2);
7191 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7192 case ixgbe_mac_X550_vf:
7193 case ixgbe_mac_X550EM_x_vf:
7194 case ixgbe_mac_X550EM_a_vf:
7195 return IXGBE_VFRETA(reta_idx >> 2);
7197 return IXGBE_RETA(reta_idx >> 2);
7202 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7204 case ixgbe_mac_X550_vf:
7205 case ixgbe_mac_X550EM_x_vf:
7206 case ixgbe_mac_X550EM_a_vf:
7207 return IXGBE_VFMRQC;
7214 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7216 case ixgbe_mac_X550_vf:
7217 case ixgbe_mac_X550EM_x_vf:
7218 case ixgbe_mac_X550EM_a_vf:
7219 return IXGBE_VFRSSRK(i);
7221 return IXGBE_RSSRK(i);
7226 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7228 case ixgbe_mac_82599_vf:
7229 case ixgbe_mac_X540_vf:
7237 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7238 struct rte_eth_dcb_info *dcb_info)
7240 struct ixgbe_dcb_config *dcb_config =
7241 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7242 struct ixgbe_dcb_tc_config *tc;
7245 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7246 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7248 dcb_info->nb_tcs = 1;
7250 if (dcb_config->vt_mode) { /* vt is enabled*/
7251 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7252 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7253 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7254 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7255 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7256 for (j = 0; j < dcb_info->nb_tcs; j++) {
7257 dcb_info->tc_queue.tc_rxq[i][j].base =
7258 i * dcb_info->nb_tcs + j;
7259 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7260 dcb_info->tc_queue.tc_txq[i][j].base =
7261 i * dcb_info->nb_tcs + j;
7262 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7265 } else { /* vt is disabled*/
7266 struct rte_eth_dcb_rx_conf *rx_conf =
7267 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7268 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7269 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7270 if (dcb_info->nb_tcs == ETH_4_TCS) {
7271 for (i = 0; i < dcb_info->nb_tcs; i++) {
7272 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7273 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7275 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7276 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7277 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7278 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7279 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7280 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7281 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7282 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7283 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7284 for (i = 0; i < dcb_info->nb_tcs; i++) {
7285 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7286 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7288 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7289 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7290 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7291 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7292 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7293 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7294 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7295 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7296 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7297 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7298 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7299 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7300 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7301 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7302 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7303 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7306 for (i = 0; i < dcb_info->nb_tcs; i++) {
7307 tc = &dcb_config->tc_config[i];
7308 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7313 /* Update e-tag ether type */
7315 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7316 uint16_t ether_type)
7318 uint32_t etag_etype;
7320 if (hw->mac.type != ixgbe_mac_X550 &&
7321 hw->mac.type != ixgbe_mac_X550EM_x &&
7322 hw->mac.type != ixgbe_mac_X550EM_a) {
7326 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7327 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7328 etag_etype |= ether_type;
7329 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7330 IXGBE_WRITE_FLUSH(hw);
7335 /* Config l2 tunnel ether type */
7337 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7338 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7342 struct ixgbe_l2_tn_info *l2_tn_info =
7343 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7345 if (l2_tunnel == NULL)
7348 switch (l2_tunnel->l2_tunnel_type) {
7349 case RTE_L2_TUNNEL_TYPE_E_TAG:
7350 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7351 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7354 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7362 /* Enable e-tag tunnel */
7364 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7366 uint32_t etag_etype;
7368 if (hw->mac.type != ixgbe_mac_X550 &&
7369 hw->mac.type != ixgbe_mac_X550EM_x &&
7370 hw->mac.type != ixgbe_mac_X550EM_a) {
7374 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7375 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7376 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7377 IXGBE_WRITE_FLUSH(hw);
7382 /* Enable l2 tunnel */
7384 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7385 enum rte_eth_tunnel_type l2_tunnel_type)
7388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389 struct ixgbe_l2_tn_info *l2_tn_info =
7390 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7392 switch (l2_tunnel_type) {
7393 case RTE_L2_TUNNEL_TYPE_E_TAG:
7394 l2_tn_info->e_tag_en = TRUE;
7395 ret = ixgbe_e_tag_enable(hw);
7398 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7406 /* Disable e-tag tunnel */
7408 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7410 uint32_t etag_etype;
7412 if (hw->mac.type != ixgbe_mac_X550 &&
7413 hw->mac.type != ixgbe_mac_X550EM_x &&
7414 hw->mac.type != ixgbe_mac_X550EM_a) {
7418 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7419 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7420 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7421 IXGBE_WRITE_FLUSH(hw);
7426 /* Disable l2 tunnel */
7428 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7429 enum rte_eth_tunnel_type l2_tunnel_type)
7432 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7433 struct ixgbe_l2_tn_info *l2_tn_info =
7434 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7436 switch (l2_tunnel_type) {
7437 case RTE_L2_TUNNEL_TYPE_E_TAG:
7438 l2_tn_info->e_tag_en = FALSE;
7439 ret = ixgbe_e_tag_disable(hw);
7442 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7451 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7452 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7455 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7456 uint32_t i, rar_entries;
7457 uint32_t rar_low, rar_high;
7459 if (hw->mac.type != ixgbe_mac_X550 &&
7460 hw->mac.type != ixgbe_mac_X550EM_x &&
7461 hw->mac.type != ixgbe_mac_X550EM_a) {
7465 rar_entries = ixgbe_get_num_rx_addrs(hw);
7467 for (i = 1; i < rar_entries; i++) {
7468 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7469 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7470 if ((rar_high & IXGBE_RAH_AV) &&
7471 (rar_high & IXGBE_RAH_ADTYPE) &&
7472 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7473 l2_tunnel->tunnel_id)) {
7474 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7475 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7477 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7487 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7488 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492 uint32_t i, rar_entries;
7493 uint32_t rar_low, rar_high;
7495 if (hw->mac.type != ixgbe_mac_X550 &&
7496 hw->mac.type != ixgbe_mac_X550EM_x &&
7497 hw->mac.type != ixgbe_mac_X550EM_a) {
7501 /* One entry for one tunnel. Try to remove potential existing entry. */
7502 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7504 rar_entries = ixgbe_get_num_rx_addrs(hw);
7506 for (i = 1; i < rar_entries; i++) {
7507 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7508 if (rar_high & IXGBE_RAH_AV) {
7511 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7512 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7513 rar_low = l2_tunnel->tunnel_id;
7515 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7516 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7522 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7523 " Please remove a rule before adding a new one.");
7527 static inline struct ixgbe_l2_tn_filter *
7528 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7529 struct ixgbe_l2_tn_key *key)
7533 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7537 return l2_tn_info->hash_map[ret];
7541 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7542 struct ixgbe_l2_tn_filter *l2_tn_filter)
7546 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7547 &l2_tn_filter->key);
7551 "Failed to insert L2 tunnel filter"
7552 " to hash table %d!",
7557 l2_tn_info->hash_map[ret] = l2_tn_filter;
7559 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7565 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7566 struct ixgbe_l2_tn_key *key)
7569 struct ixgbe_l2_tn_filter *l2_tn_filter;
7571 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7575 "No such L2 tunnel filter to delete %d!",
7580 l2_tn_filter = l2_tn_info->hash_map[ret];
7581 l2_tn_info->hash_map[ret] = NULL;
7583 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7584 rte_free(l2_tn_filter);
7589 /* Add l2 tunnel filter */
7591 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7592 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7596 struct ixgbe_l2_tn_info *l2_tn_info =
7597 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7598 struct ixgbe_l2_tn_key key;
7599 struct ixgbe_l2_tn_filter *node;
7602 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7603 key.tn_id = l2_tunnel->tunnel_id;
7605 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7609 "The L2 tunnel filter already exists!");
7613 node = rte_zmalloc("ixgbe_l2_tn",
7614 sizeof(struct ixgbe_l2_tn_filter),
7619 rte_memcpy(&node->key,
7621 sizeof(struct ixgbe_l2_tn_key));
7622 node->pool = l2_tunnel->pool;
7623 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7630 switch (l2_tunnel->l2_tunnel_type) {
7631 case RTE_L2_TUNNEL_TYPE_E_TAG:
7632 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7635 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7640 if ((!restore) && (ret < 0))
7641 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7646 /* Delete l2 tunnel filter */
7648 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7649 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7652 struct ixgbe_l2_tn_info *l2_tn_info =
7653 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7654 struct ixgbe_l2_tn_key key;
7656 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7657 key.tn_id = l2_tunnel->tunnel_id;
7658 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7662 switch (l2_tunnel->l2_tunnel_type) {
7663 case RTE_L2_TUNNEL_TYPE_E_TAG:
7664 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7667 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7676 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7677 * @dev: pointer to rte_eth_dev structure
7678 * @filter_op:operation will be taken.
7679 * @arg: a pointer to specific structure corresponding to the filter_op
7682 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7683 enum rte_filter_op filter_op,
7688 if (filter_op == RTE_ETH_FILTER_NOP)
7692 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7697 switch (filter_op) {
7698 case RTE_ETH_FILTER_ADD:
7699 ret = ixgbe_dev_l2_tunnel_filter_add
7701 (struct rte_eth_l2_tunnel_conf *)arg,
7704 case RTE_ETH_FILTER_DELETE:
7705 ret = ixgbe_dev_l2_tunnel_filter_del
7707 (struct rte_eth_l2_tunnel_conf *)arg);
7710 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7718 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7722 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7724 if (hw->mac.type != ixgbe_mac_X550 &&
7725 hw->mac.type != ixgbe_mac_X550EM_x &&
7726 hw->mac.type != ixgbe_mac_X550EM_a) {
7730 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7731 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7733 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7734 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7739 /* Enable l2 tunnel forwarding */
7741 ixgbe_dev_l2_tunnel_forwarding_enable
7742 (struct rte_eth_dev *dev,
7743 enum rte_eth_tunnel_type l2_tunnel_type)
7745 struct ixgbe_l2_tn_info *l2_tn_info =
7746 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7749 switch (l2_tunnel_type) {
7750 case RTE_L2_TUNNEL_TYPE_E_TAG:
7751 l2_tn_info->e_tag_fwd_en = TRUE;
7752 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7755 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7763 /* Disable l2 tunnel forwarding */
7765 ixgbe_dev_l2_tunnel_forwarding_disable
7766 (struct rte_eth_dev *dev,
7767 enum rte_eth_tunnel_type l2_tunnel_type)
7769 struct ixgbe_l2_tn_info *l2_tn_info =
7770 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7773 switch (l2_tunnel_type) {
7774 case RTE_L2_TUNNEL_TYPE_E_TAG:
7775 l2_tn_info->e_tag_fwd_en = FALSE;
7776 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7779 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7788 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7789 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7794 uint32_t vmtir, vmvir;
7795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7799 "VF id %u should be less than %u",
7805 if (hw->mac.type != ixgbe_mac_X550 &&
7806 hw->mac.type != ixgbe_mac_X550EM_x &&
7807 hw->mac.type != ixgbe_mac_X550EM_a) {
7812 vmtir = l2_tunnel->tunnel_id;
7816 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7818 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7819 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7821 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7822 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7827 /* Enable l2 tunnel tag insertion */
7829 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7830 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7834 switch (l2_tunnel->l2_tunnel_type) {
7835 case RTE_L2_TUNNEL_TYPE_E_TAG:
7836 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7839 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7847 /* Disable l2 tunnel tag insertion */
7849 ixgbe_dev_l2_tunnel_insertion_disable
7850 (struct rte_eth_dev *dev,
7851 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7855 switch (l2_tunnel->l2_tunnel_type) {
7856 case RTE_L2_TUNNEL_TYPE_E_TAG:
7857 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7860 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7869 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7876 if (hw->mac.type != ixgbe_mac_X550 &&
7877 hw->mac.type != ixgbe_mac_X550EM_x &&
7878 hw->mac.type != ixgbe_mac_X550EM_a) {
7882 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7884 qde |= IXGBE_QDE_STRIP_TAG;
7886 qde &= ~IXGBE_QDE_STRIP_TAG;
7887 qde &= ~IXGBE_QDE_READ;
7888 qde |= IXGBE_QDE_WRITE;
7889 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7894 /* Enable l2 tunnel tag stripping */
7896 ixgbe_dev_l2_tunnel_stripping_enable
7897 (struct rte_eth_dev *dev,
7898 enum rte_eth_tunnel_type l2_tunnel_type)
7902 switch (l2_tunnel_type) {
7903 case RTE_L2_TUNNEL_TYPE_E_TAG:
7904 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7907 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7915 /* Disable l2 tunnel tag stripping */
7917 ixgbe_dev_l2_tunnel_stripping_disable
7918 (struct rte_eth_dev *dev,
7919 enum rte_eth_tunnel_type l2_tunnel_type)
7923 switch (l2_tunnel_type) {
7924 case RTE_L2_TUNNEL_TYPE_E_TAG:
7925 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7928 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7936 /* Enable/disable l2 tunnel offload functions */
7938 ixgbe_dev_l2_tunnel_offload_set
7939 (struct rte_eth_dev *dev,
7940 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7946 if (l2_tunnel == NULL)
7950 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7952 ret = ixgbe_dev_l2_tunnel_enable(
7954 l2_tunnel->l2_tunnel_type);
7956 ret = ixgbe_dev_l2_tunnel_disable(
7958 l2_tunnel->l2_tunnel_type);
7961 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7963 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7967 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7972 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7974 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7976 l2_tunnel->l2_tunnel_type);
7978 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7980 l2_tunnel->l2_tunnel_type);
7983 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7985 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7987 l2_tunnel->l2_tunnel_type);
7989 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7991 l2_tunnel->l2_tunnel_type);
7998 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8001 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8002 IXGBE_WRITE_FLUSH(hw);
8007 /* There's only one register for VxLAN UDP port.
8008 * So, we cannot add several ports. Will update it.
8011 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8015 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8019 return ixgbe_update_vxlan_port(hw, port);
8022 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8023 * UDP port, it must have a value.
8024 * So, will reset it to the original value 0.
8027 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8032 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8034 if (cur_port != port) {
8035 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8039 return ixgbe_update_vxlan_port(hw, 0);
8042 /* Add UDP tunneling port */
8044 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8045 struct rte_eth_udp_tunnel *udp_tunnel)
8048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8050 if (hw->mac.type != ixgbe_mac_X550 &&
8051 hw->mac.type != ixgbe_mac_X550EM_x &&
8052 hw->mac.type != ixgbe_mac_X550EM_a) {
8056 if (udp_tunnel == NULL)
8059 switch (udp_tunnel->prot_type) {
8060 case RTE_TUNNEL_TYPE_VXLAN:
8061 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8064 case RTE_TUNNEL_TYPE_GENEVE:
8065 case RTE_TUNNEL_TYPE_TEREDO:
8066 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8071 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079 /* Remove UDP tunneling port */
8081 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8082 struct rte_eth_udp_tunnel *udp_tunnel)
8085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087 if (hw->mac.type != ixgbe_mac_X550 &&
8088 hw->mac.type != ixgbe_mac_X550EM_x &&
8089 hw->mac.type != ixgbe_mac_X550EM_a) {
8093 if (udp_tunnel == NULL)
8096 switch (udp_tunnel->prot_type) {
8097 case RTE_TUNNEL_TYPE_VXLAN:
8098 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8100 case RTE_TUNNEL_TYPE_GENEVE:
8101 case RTE_TUNNEL_TYPE_TEREDO:
8102 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8106 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8115 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8123 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8127 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8130 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8138 /* PF reset VF event */
8139 if (in_msg == IXGBE_PF_CONTROL_MSG)
8140 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8145 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8148 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8149 struct ixgbe_interrupt *intr =
8150 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8151 ixgbevf_intr_disable(hw);
8153 /* read-on-clear nic registers here */
8154 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8157 /* only one misc vector supported - mailbox */
8158 eicr &= IXGBE_VTEICR_MASK;
8159 if (eicr == IXGBE_MISC_VEC_ID)
8160 intr->flags |= IXGBE_FLAG_MAILBOX;
8166 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8169 struct ixgbe_interrupt *intr =
8170 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8172 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8173 ixgbevf_mbx_process(dev);
8174 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8177 ixgbevf_intr_enable(hw);
8183 ixgbevf_dev_interrupt_handler(void *param)
8185 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8187 ixgbevf_dev_interrupt_get_status(dev);
8188 ixgbevf_dev_interrupt_action(dev);
8192 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8193 * @hw: pointer to hardware structure
8195 * Stops the transmit data path and waits for the HW to internally empty
8196 * the Tx security block
8198 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8200 #define IXGBE_MAX_SECTX_POLL 40
8205 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8206 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8207 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8208 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8209 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8210 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8212 /* Use interrupt-safe sleep just in case */
8216 /* For informational purposes only */
8217 if (i >= IXGBE_MAX_SECTX_POLL)
8218 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8219 "path fully disabled. Continuing with init.");
8221 return IXGBE_SUCCESS;
8225 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8226 * @hw: pointer to hardware structure
8228 * Enables the transmit data path.
8230 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8234 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8235 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8236 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8237 IXGBE_WRITE_FLUSH(hw);
8239 return IXGBE_SUCCESS;
8242 /* restore n-tuple filter */
8244 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8246 struct ixgbe_filter_info *filter_info =
8247 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8248 struct ixgbe_5tuple_filter *node;
8250 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8251 ixgbe_inject_5tuple_filter(dev, node);
8255 /* restore ethernet type filter */
8257 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260 struct ixgbe_filter_info *filter_info =
8261 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8264 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8265 if (filter_info->ethertype_mask & (1 << i)) {
8266 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8267 filter_info->ethertype_filters[i].etqf);
8268 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8269 filter_info->ethertype_filters[i].etqs);
8270 IXGBE_WRITE_FLUSH(hw);
8275 /* restore SYN filter */
8277 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8279 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8280 struct ixgbe_filter_info *filter_info =
8281 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8284 synqf = filter_info->syn_info;
8286 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8287 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8288 IXGBE_WRITE_FLUSH(hw);
8292 /* restore L2 tunnel filter */
8294 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8296 struct ixgbe_l2_tn_info *l2_tn_info =
8297 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8298 struct ixgbe_l2_tn_filter *node;
8299 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8301 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8302 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8303 l2_tn_conf.tunnel_id = node->key.tn_id;
8304 l2_tn_conf.pool = node->pool;
8305 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8310 ixgbe_filter_restore(struct rte_eth_dev *dev)
8312 ixgbe_ntuple_filter_restore(dev);
8313 ixgbe_ethertype_filter_restore(dev);
8314 ixgbe_syn_filter_restore(dev);
8315 ixgbe_fdir_filter_restore(dev);
8316 ixgbe_l2_tn_filter_restore(dev);
8322 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8324 struct ixgbe_l2_tn_info *l2_tn_info =
8325 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8328 if (l2_tn_info->e_tag_en)
8329 (void)ixgbe_e_tag_enable(hw);
8331 if (l2_tn_info->e_tag_fwd_en)
8332 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8334 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8337 /* remove all the n-tuple filters */
8339 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8341 struct ixgbe_filter_info *filter_info =
8342 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8343 struct ixgbe_5tuple_filter *p_5tuple;
8345 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8346 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8349 /* remove all the ether type filters */
8351 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8354 struct ixgbe_filter_info *filter_info =
8355 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8358 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8359 if (filter_info->ethertype_mask & (1 << i) &&
8360 !filter_info->ethertype_filters[i].conf) {
8361 (void)ixgbe_ethertype_filter_remove(filter_info,
8363 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8364 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8365 IXGBE_WRITE_FLUSH(hw);
8370 /* remove the SYN filter */
8372 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8375 struct ixgbe_filter_info *filter_info =
8376 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8378 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8379 filter_info->syn_info = 0;
8381 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8382 IXGBE_WRITE_FLUSH(hw);
8386 /* remove all the L2 tunnel filters */
8388 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8390 struct ixgbe_l2_tn_info *l2_tn_info =
8391 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8392 struct ixgbe_l2_tn_filter *l2_tn_filter;
8393 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8396 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8397 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8398 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8399 l2_tn_conf.pool = l2_tn_filter->pool;
8400 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8408 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8409 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8410 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8411 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8412 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8413 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");