4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
164 #define IXGBE_EXVET_VET_EXT_SHIFT 16
165 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
174 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
175 static int ixgbe_dev_start(struct rte_eth_dev *dev);
176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
177 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
178 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
185 int wait_to_complete);
186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
187 struct rte_eth_stats *stats);
188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
189 struct rte_eth_xstat *xstats, unsigned n);
190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
191 struct rte_eth_xstat *xstats, unsigned n);
192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
205 struct rte_eth_dev_info *dev_info);
206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
212 uint16_t vlan_id, int on);
213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
214 enum rte_vlan_type vlan_type,
216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
217 uint16_t queue, bool on);
218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
229 struct rte_eth_fc_conf *fc_conf);
230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_pfc_conf *pfc_conf);
234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
246 struct rte_intr_handle *handle);
247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static bool is_device_supported(struct rte_eth_dev *dev,
257 struct eth_driver *drv);
259 /* For Virtual Function support */
260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
262 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
263 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
266 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
267 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
268 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
269 struct rte_eth_stats *stats);
270 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
271 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
272 uint16_t vlan_id, int on);
273 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
274 uint16_t queue, int on);
275 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
276 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
277 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
279 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
281 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
282 uint8_t queue, uint8_t msix_vector);
283 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
284 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
285 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
287 /* For Eth VMDQ APIs support */
288 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
289 ether_addr * mac_addr, uint8_t on);
290 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
291 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
292 struct rte_eth_mirror_conf *mirror_conf,
293 uint8_t rule_id, uint8_t on);
294 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
296 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
298 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
300 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
301 uint8_t queue, uint8_t msix_vector);
302 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
304 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
305 uint16_t queue_idx, uint16_t tx_rate);
307 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
308 struct ether_addr *mac_addr,
309 uint32_t index, uint32_t pool);
310 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
311 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
312 struct ether_addr *mac_addr);
313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
314 struct rte_eth_syn_filter *filter);
315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
319 struct ixgbe_5tuple_filter *filter);
320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ntuple_filter *filter);
327 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
328 enum rte_filter_op filter_op,
330 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
331 struct rte_eth_ethertype_filter *filter);
332 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
333 enum rte_filter_type filter_type,
334 enum rte_filter_op filter_op,
336 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
338 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
339 struct ether_addr *mc_addr_set,
340 uint32_t nb_mc_addr);
341 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
342 struct rte_eth_dcb_info *dcb_info);
344 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
345 static int ixgbe_get_regs(struct rte_eth_dev *dev,
346 struct rte_dev_reg_info *regs);
347 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
348 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
349 struct rte_dev_eeprom_info *eeprom);
350 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
351 struct rte_dev_eeprom_info *eeprom);
353 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
354 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
355 struct rte_dev_reg_info *regs);
357 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
358 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
360 struct timespec *timestamp,
362 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
363 struct timespec *timestamp);
364 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
365 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
366 struct timespec *timestamp);
367 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
368 const struct timespec *timestamp);
369 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
372 static int ixgbe_dev_l2_tunnel_eth_type_conf
373 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
374 static int ixgbe_dev_l2_tunnel_offload_set
375 (struct rte_eth_dev *dev,
376 struct rte_eth_l2_tunnel_conf *l2_tunnel,
379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
391 * Define VF Stats MACRO for Non "cleared on read" register
393 #define UPDATE_VF_STAT(reg, last, cur) \
395 uint32_t latest = IXGBE_READ_REG(hw, reg); \
396 cur += (latest - last) & UINT_MAX; \
400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
402 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
403 u64 new_msb = IXGBE_READ_REG(hw, msb); \
404 u64 latest = ((new_msb << 32) | new_lsb); \
405 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 #define IXGBE_SET_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] |= 1 << bit;\
415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (h)->bitmap[idx] &= ~(1 << bit);\
421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
422 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
423 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
424 (r) = (h)->bitmap[idx] >> bit & 1;\
428 * The set of PCI devices this driver supports
430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
484 #ifdef RTE_NIC_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
529 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
530 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
531 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
532 .link_update = ixgbe_dev_link_update,
533 .stats_get = ixgbe_dev_stats_get,
534 .xstats_get = ixgbe_dev_xstats_get,
535 .stats_reset = ixgbe_dev_stats_reset,
536 .xstats_reset = ixgbe_dev_xstats_reset,
537 .xstats_get_names = ixgbe_dev_xstats_get_names,
538 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
539 .fw_version_get = ixgbe_fw_version_get,
540 .dev_infos_get = ixgbe_dev_info_get,
541 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
542 .mtu_set = ixgbe_dev_mtu_set,
543 .vlan_filter_set = ixgbe_vlan_filter_set,
544 .vlan_tpid_set = ixgbe_vlan_tpid_set,
545 .vlan_offload_set = ixgbe_vlan_offload_set,
546 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
547 .rx_queue_start = ixgbe_dev_rx_queue_start,
548 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
549 .tx_queue_start = ixgbe_dev_tx_queue_start,
550 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
551 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
552 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
553 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
554 .rx_queue_release = ixgbe_dev_rx_queue_release,
555 .rx_queue_count = ixgbe_dev_rx_queue_count,
556 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
557 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
558 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
559 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
560 .tx_queue_release = ixgbe_dev_tx_queue_release,
561 .dev_led_on = ixgbe_dev_led_on,
562 .dev_led_off = ixgbe_dev_led_off,
563 .flow_ctrl_get = ixgbe_flow_ctrl_get,
564 .flow_ctrl_set = ixgbe_flow_ctrl_set,
565 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
566 .mac_addr_add = ixgbe_add_rar,
567 .mac_addr_remove = ixgbe_remove_rar,
568 .mac_addr_set = ixgbe_set_default_mac_addr,
569 .uc_hash_table_set = ixgbe_uc_hash_table_set,
570 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
571 .mirror_rule_set = ixgbe_mirror_rule_set,
572 .mirror_rule_reset = ixgbe_mirror_rule_reset,
573 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
574 .reta_update = ixgbe_dev_rss_reta_update,
575 .reta_query = ixgbe_dev_rss_reta_query,
576 #ifdef RTE_NIC_BYPASS
577 .bypass_init = ixgbe_bypass_init,
578 .bypass_state_set = ixgbe_bypass_state_store,
579 .bypass_state_show = ixgbe_bypass_state_show,
580 .bypass_event_set = ixgbe_bypass_event_store,
581 .bypass_event_show = ixgbe_bypass_event_show,
582 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
583 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
584 .bypass_ver_show = ixgbe_bypass_ver_show,
585 .bypass_wd_reset = ixgbe_bypass_wd_reset,
586 #endif /* RTE_NIC_BYPASS */
587 .rss_hash_update = ixgbe_dev_rss_hash_update,
588 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
589 .filter_ctrl = ixgbe_dev_filter_ctrl,
590 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
591 .rxq_info_get = ixgbe_rxq_info_get,
592 .txq_info_get = ixgbe_txq_info_get,
593 .timesync_enable = ixgbe_timesync_enable,
594 .timesync_disable = ixgbe_timesync_disable,
595 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
596 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
597 .get_reg = ixgbe_get_regs,
598 .get_eeprom_length = ixgbe_get_eeprom_length,
599 .get_eeprom = ixgbe_get_eeprom,
600 .set_eeprom = ixgbe_set_eeprom,
601 .get_dcb_info = ixgbe_dev_get_dcb_info,
602 .timesync_adjust_time = ixgbe_timesync_adjust_time,
603 .timesync_read_time = ixgbe_timesync_read_time,
604 .timesync_write_time = ixgbe_timesync_write_time,
605 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
606 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
607 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
608 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
612 * dev_ops for virtual function, bare necessities for basic vf
613 * operation have been implemented
615 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
616 .dev_configure = ixgbevf_dev_configure,
617 .dev_start = ixgbevf_dev_start,
618 .dev_stop = ixgbevf_dev_stop,
619 .link_update = ixgbe_dev_link_update,
620 .stats_get = ixgbevf_dev_stats_get,
621 .xstats_get = ixgbevf_dev_xstats_get,
622 .stats_reset = ixgbevf_dev_stats_reset,
623 .xstats_reset = ixgbevf_dev_stats_reset,
624 .xstats_get_names = ixgbevf_dev_xstats_get_names,
625 .dev_close = ixgbevf_dev_close,
626 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
627 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
628 .dev_infos_get = ixgbevf_dev_info_get,
629 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
630 .mtu_set = ixgbevf_dev_set_mtu,
631 .vlan_filter_set = ixgbevf_vlan_filter_set,
632 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
633 .vlan_offload_set = ixgbevf_vlan_offload_set,
634 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
635 .rx_queue_release = ixgbe_dev_rx_queue_release,
636 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
637 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
638 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
639 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
640 .tx_queue_release = ixgbe_dev_tx_queue_release,
641 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
642 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
643 .mac_addr_add = ixgbevf_add_mac_addr,
644 .mac_addr_remove = ixgbevf_remove_mac_addr,
645 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
646 .rxq_info_get = ixgbe_rxq_info_get,
647 .txq_info_get = ixgbe_txq_info_get,
648 .mac_addr_set = ixgbevf_set_default_mac_addr,
649 .get_reg = ixgbevf_get_regs,
650 .reta_update = ixgbe_dev_rss_reta_update,
651 .reta_query = ixgbe_dev_rss_reta_query,
652 .rss_hash_update = ixgbe_dev_rss_hash_update,
653 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
656 /* store statistics names and its offset in stats structure */
657 struct rte_ixgbe_xstats_name_off {
658 char name[RTE_ETH_XSTATS_NAME_SIZE];
662 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
663 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
664 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
665 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
666 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
667 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
668 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
669 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
670 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
671 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
672 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
673 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
674 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
675 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
676 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
677 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
679 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
681 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
682 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
683 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
684 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
685 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
686 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
687 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
688 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
689 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
690 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
691 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
692 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
693 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
694 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
695 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
696 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
697 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
699 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
701 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
702 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
703 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
704 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
706 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
716 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
719 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
720 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
721 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
723 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
724 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
725 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
726 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
727 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
729 {"rx_fcoe_no_direct_data_placement_ext_buff",
730 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
732 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
734 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
736 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
738 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
740 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
743 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
744 sizeof(rte_ixgbe_stats_strings[0]))
746 /* MACsec statistics */
747 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
748 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
750 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
751 out_pkts_encrypted)},
752 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
753 out_pkts_protected)},
754 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
755 out_octets_encrypted)},
756 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
757 out_octets_protected)},
758 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
765 in_pkts_unknownsci)},
766 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
767 in_octets_decrypted)},
768 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
769 in_octets_validated)},
770 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
784 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
785 in_pkts_notusingsa)},
788 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
789 sizeof(rte_ixgbe_macsec_strings[0]))
791 /* Per-queue statistics */
792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
793 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
794 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
795 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
796 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
799 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
800 sizeof(rte_ixgbe_rxq_strings[0]))
801 #define IXGBE_NB_RXQ_PRIO_VALUES 8
803 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
804 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
805 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
806 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
810 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
811 sizeof(rte_ixgbe_txq_strings[0]))
812 #define IXGBE_NB_TXQ_PRIO_VALUES 8
814 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
815 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
818 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
819 sizeof(rte_ixgbevf_stats_strings[0]))
822 * Atomically reads the link status information from global
823 * structure rte_eth_dev.
826 * - Pointer to the structure rte_eth_dev to read from.
827 * - Pointer to the buffer to be saved with the link status.
830 * - On success, zero.
831 * - On failure, negative value.
834 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
835 struct rte_eth_link *link)
837 struct rte_eth_link *dst = link;
838 struct rte_eth_link *src = &(dev->data->dev_link);
840 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
841 *(uint64_t *)src) == 0)
848 * Atomically writes the link status information into global
849 * structure rte_eth_dev.
852 * - Pointer to the structure rte_eth_dev to read from.
853 * - Pointer to the buffer to be saved with the link status.
856 * - On success, zero.
857 * - On failure, negative value.
860 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
861 struct rte_eth_link *link)
863 struct rte_eth_link *dst = &(dev->data->dev_link);
864 struct rte_eth_link *src = link;
866 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
867 *(uint64_t *)src) == 0)
874 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
877 ixgbe_is_sfp(struct ixgbe_hw *hw)
879 switch (hw->phy.type) {
880 case ixgbe_phy_sfp_avago:
881 case ixgbe_phy_sfp_ftl:
882 case ixgbe_phy_sfp_intel:
883 case ixgbe_phy_sfp_unknown:
884 case ixgbe_phy_sfp_passive_tyco:
885 case ixgbe_phy_sfp_passive_unknown:
892 static inline int32_t
893 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
898 status = ixgbe_reset_hw(hw);
900 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
901 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
902 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
903 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
904 IXGBE_WRITE_FLUSH(hw);
906 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
907 status = IXGBE_SUCCESS;
912 ixgbe_enable_intr(struct rte_eth_dev *dev)
914 struct ixgbe_interrupt *intr =
915 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
916 struct ixgbe_hw *hw =
917 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
919 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
920 IXGBE_WRITE_FLUSH(hw);
924 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
927 ixgbe_disable_intr(struct ixgbe_hw *hw)
929 PMD_INIT_FUNC_TRACE();
931 if (hw->mac.type == ixgbe_mac_82598EB) {
932 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
934 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
935 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
936 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
938 IXGBE_WRITE_FLUSH(hw);
942 * This function resets queue statistics mapping registers.
943 * From Niantic datasheet, Initialization of Statistics section:
944 * "...if software requires the queue counters, the RQSMR and TQSM registers
945 * must be re-programmed following a device reset.
948 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
952 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
953 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
954 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
960 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
965 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
966 #define NB_QMAP_FIELDS_PER_QSM_REG 4
967 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
970 struct ixgbe_stat_mapping_registers *stat_mappings =
971 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
972 uint32_t qsmr_mask = 0;
973 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
977 if ((hw->mac.type != ixgbe_mac_82599EB) &&
978 (hw->mac.type != ixgbe_mac_X540) &&
979 (hw->mac.type != ixgbe_mac_X550) &&
980 (hw->mac.type != ixgbe_mac_X550EM_x) &&
981 (hw->mac.type != ixgbe_mac_X550EM_a))
984 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
985 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
988 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
989 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
990 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
993 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
995 /* Now clear any previous stat_idx set */
996 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
998 stat_mappings->tqsm[n] &= ~clearing_mask;
1000 stat_mappings->rqsmr[n] &= ~clearing_mask;
1002 q_map = (uint32_t)stat_idx;
1003 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1004 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1006 stat_mappings->tqsm[n] |= qsmr_mask;
1008 stat_mappings->rqsmr[n] |= qsmr_mask;
1010 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1011 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1012 queue_id, stat_idx);
1013 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1014 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1016 /* Now write the mapping in the appropriate register */
1018 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1019 stat_mappings->rqsmr[n], n);
1020 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1022 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1023 stat_mappings->tqsm[n], n);
1024 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1030 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1032 struct ixgbe_stat_mapping_registers *stat_mappings =
1033 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1034 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 /* write whatever was in stat mapping table to the NIC */
1038 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1040 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1048 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 struct ixgbe_dcb_tc_config *tc;
1052 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1054 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1055 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1056 for (i = 0; i < dcb_max_tc; i++) {
1057 tc = &dcb_config->tc_config[i];
1058 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1059 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1060 (uint8_t)(100/dcb_max_tc + (i & 1));
1061 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1062 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1063 (uint8_t)(100/dcb_max_tc + (i & 1));
1064 tc->pfc = ixgbe_dcb_pfc_disabled;
1067 /* Initialize default user to priority mapping, UPx->TC0 */
1068 tc = &dcb_config->tc_config[0];
1069 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1070 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1071 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1072 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1073 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1075 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1076 dcb_config->pfc_mode_enable = false;
1077 dcb_config->vt_mode = true;
1078 dcb_config->round_robin_enable = false;
1079 /* support all DCB capabilities in 82599 */
1080 dcb_config->support.capabilities = 0xFF;
1082 /*we only support 4 Tcs for X540, X550 */
1083 if (hw->mac.type == ixgbe_mac_X540 ||
1084 hw->mac.type == ixgbe_mac_X550 ||
1085 hw->mac.type == ixgbe_mac_X550EM_x ||
1086 hw->mac.type == ixgbe_mac_X550EM_a) {
1087 dcb_config->num_tcs.pg_tcs = 4;
1088 dcb_config->num_tcs.pfc_tcs = 4;
1093 * Ensure that all locks are released before first NVM or PHY access
1096 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1101 * Phy lock should not fail in this early stage. If this is the case,
1102 * it is due to an improper exit of the application.
1103 * So force the release of the faulty lock. Release of common lock
1104 * is done automatically by swfw_sync function.
1106 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1107 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1108 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1110 ixgbe_release_swfw_semaphore(hw, mask);
1113 * These ones are more tricky since they are common to all ports; but
1114 * swfw_sync retries last long enough (1s) to be almost sure that if
1115 * lock can not be taken it is due to an improper lock of the
1118 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1119 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1120 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1122 ixgbe_release_swfw_semaphore(hw, mask);
1126 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1127 * It returns 0 on success.
1130 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1132 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1133 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1134 struct ixgbe_hw *hw =
1135 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1136 struct ixgbe_vfta *shadow_vfta =
1137 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1138 struct ixgbe_hwstrip *hwstrip =
1139 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1140 struct ixgbe_dcb_config *dcb_config =
1141 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1142 struct ixgbe_filter_info *filter_info =
1143 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1148 PMD_INIT_FUNC_TRACE();
1150 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1151 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1152 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1153 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1156 * For secondary processes, we don't initialise any further as primary
1157 * has already done this work. Only check we don't need a different
1158 * RX and TX function.
1160 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1161 struct ixgbe_tx_queue *txq;
1162 /* TX queue function in primary, set by last queue initialized
1163 * Tx queue may not initialized by primary process
1165 if (eth_dev->data->tx_queues) {
1166 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1167 ixgbe_set_tx_function(eth_dev, txq);
1169 /* Use default TX function if we get here */
1170 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1171 "Using default TX function.");
1174 ixgbe_set_rx_function(eth_dev);
1179 rte_eth_copy_pci_info(eth_dev, pci_dev);
1180 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1182 /* Vendor and Device ID need to be set before init of shared code */
1183 hw->device_id = pci_dev->id.device_id;
1184 hw->vendor_id = pci_dev->id.vendor_id;
1185 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1186 hw->allow_unsupported_sfp = 1;
1188 /* Initialize the shared code (base driver) */
1189 #ifdef RTE_NIC_BYPASS
1190 diag = ixgbe_bypass_init_shared_code(hw);
1192 diag = ixgbe_init_shared_code(hw);
1193 #endif /* RTE_NIC_BYPASS */
1195 if (diag != IXGBE_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1200 /* pick up the PCI bus settings for reporting later */
1201 ixgbe_get_bus_info(hw);
1203 /* Unlock any pending hardware semaphore */
1204 ixgbe_swfw_lock_reset(hw);
1206 /* Initialize DCB configuration*/
1207 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1208 ixgbe_dcb_init(hw, dcb_config);
1209 /* Get Hardware Flow Control setting */
1210 hw->fc.requested_mode = ixgbe_fc_full;
1211 hw->fc.current_mode = ixgbe_fc_full;
1212 hw->fc.pause_time = IXGBE_FC_PAUSE;
1213 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1214 hw->fc.low_water[i] = IXGBE_FC_LO;
1215 hw->fc.high_water[i] = IXGBE_FC_HI;
1217 hw->fc.send_xon = 1;
1219 /* Make sure we have a good EEPROM before we read from it */
1220 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1221 if (diag != IXGBE_SUCCESS) {
1222 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1226 #ifdef RTE_NIC_BYPASS
1227 diag = ixgbe_bypass_init_hw(hw);
1229 diag = ixgbe_init_hw(hw);
1230 #endif /* RTE_NIC_BYPASS */
1233 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1234 * is called too soon after the kernel driver unbinding/binding occurs.
1235 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1236 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1237 * also called. See ixgbe_identify_phy_82599(). The reason for the
1238 * failure is not known, and only occuts when virtualisation features
1239 * are disabled in the bios. A delay of 100ms was found to be enough by
1240 * trial-and-error, and is doubled to be safe.
1242 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1244 diag = ixgbe_init_hw(hw);
1247 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1248 diag = IXGBE_SUCCESS;
1250 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1251 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1252 "LOM. Please be aware there may be issues associated "
1253 "with your hardware.");
1254 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1255 "please contact your Intel or hardware representative "
1256 "who provided you with this hardware.");
1257 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1258 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1260 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1264 /* Reset the hw statistics */
1265 ixgbe_dev_stats_reset(eth_dev);
1267 /* disable interrupt */
1268 ixgbe_disable_intr(hw);
1270 /* reset mappings for queue statistics hw counters*/
1271 ixgbe_reset_qstat_mappings(hw);
1273 /* Allocate memory for storing MAC addresses */
1274 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1275 hw->mac.num_rar_entries, 0);
1276 if (eth_dev->data->mac_addrs == NULL) {
1278 "Failed to allocate %u bytes needed to store "
1280 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1283 /* Copy the permanent MAC address */
1284 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1285 ð_dev->data->mac_addrs[0]);
1287 /* Allocate memory for storing hash filter MAC addresses */
1288 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1289 IXGBE_VMDQ_NUM_UC_MAC, 0);
1290 if (eth_dev->data->hash_mac_addrs == NULL) {
1292 "Failed to allocate %d bytes needed to store MAC addresses",
1293 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1297 /* initialize the vfta */
1298 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1300 /* initialize the hw strip bitmap*/
1301 memset(hwstrip, 0, sizeof(*hwstrip));
1303 /* initialize PF if max_vfs not zero */
1304 ixgbe_pf_host_init(eth_dev);
1306 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1307 /* let hardware know driver is loaded */
1308 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1309 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1310 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1311 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1312 IXGBE_WRITE_FLUSH(hw);
1314 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1315 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1316 (int) hw->mac.type, (int) hw->phy.type,
1317 (int) hw->phy.sfp_type);
1319 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1320 (int) hw->mac.type, (int) hw->phy.type);
1322 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1323 eth_dev->data->port_id, pci_dev->id.vendor_id,
1324 pci_dev->id.device_id);
1326 rte_intr_callback_register(intr_handle,
1327 ixgbe_dev_interrupt_handler, eth_dev);
1329 /* enable uio/vfio intr/eventfd mapping */
1330 rte_intr_enable(intr_handle);
1332 /* enable support intr */
1333 ixgbe_enable_intr(eth_dev);
1335 /* initialize filter info */
1336 memset(filter_info, 0,
1337 sizeof(struct ixgbe_filter_info));
1339 /* initialize 5tuple filter list */
1340 TAILQ_INIT(&filter_info->fivetuple_list);
1342 /* initialize flow director filter list & hash */
1343 ixgbe_fdir_filter_init(eth_dev);
1345 /* initialize l2 tunnel filter list & hash */
1346 ixgbe_l2_tn_filter_init(eth_dev);
1348 TAILQ_INIT(&filter_ntuple_list);
1349 TAILQ_INIT(&filter_ethertype_list);
1350 TAILQ_INIT(&filter_syn_list);
1351 TAILQ_INIT(&filter_fdir_list);
1352 TAILQ_INIT(&filter_l2_tunnel_list);
1353 TAILQ_INIT(&ixgbe_flow_list);
1359 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1361 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1362 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1363 struct ixgbe_hw *hw;
1365 PMD_INIT_FUNC_TRACE();
1367 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1370 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1372 if (hw->adapter_stopped == 0)
1373 ixgbe_dev_close(eth_dev);
1375 eth_dev->dev_ops = NULL;
1376 eth_dev->rx_pkt_burst = NULL;
1377 eth_dev->tx_pkt_burst = NULL;
1379 /* Unlock any pending hardware semaphore */
1380 ixgbe_swfw_lock_reset(hw);
1382 /* disable uio intr before callback unregister */
1383 rte_intr_disable(intr_handle);
1384 rte_intr_callback_unregister(intr_handle,
1385 ixgbe_dev_interrupt_handler, eth_dev);
1387 /* uninitialize PF if max_vfs not zero */
1388 ixgbe_pf_host_uninit(eth_dev);
1390 rte_free(eth_dev->data->mac_addrs);
1391 eth_dev->data->mac_addrs = NULL;
1393 rte_free(eth_dev->data->hash_mac_addrs);
1394 eth_dev->data->hash_mac_addrs = NULL;
1396 /* remove all the fdir filters & hash */
1397 ixgbe_fdir_filter_uninit(eth_dev);
1399 /* remove all the L2 tunnel filters & hash */
1400 ixgbe_l2_tn_filter_uninit(eth_dev);
1402 /* Remove all ntuple filters of the device */
1403 ixgbe_ntuple_filter_uninit(eth_dev);
1405 /* clear all the filters list */
1406 ixgbe_filterlist_flush();
1411 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1413 struct ixgbe_filter_info *filter_info =
1414 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1415 struct ixgbe_5tuple_filter *p_5tuple;
1417 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1418 TAILQ_REMOVE(&filter_info->fivetuple_list,
1423 memset(filter_info->fivetuple_mask, 0,
1424 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1429 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1431 struct ixgbe_hw_fdir_info *fdir_info =
1432 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1433 struct ixgbe_fdir_filter *fdir_filter;
1435 if (fdir_info->hash_map)
1436 rte_free(fdir_info->hash_map);
1437 if (fdir_info->hash_handle)
1438 rte_hash_free(fdir_info->hash_handle);
1440 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1441 TAILQ_REMOVE(&fdir_info->fdir_list,
1444 rte_free(fdir_filter);
1450 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1452 struct ixgbe_l2_tn_info *l2_tn_info =
1453 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1454 struct ixgbe_l2_tn_filter *l2_tn_filter;
1456 if (l2_tn_info->hash_map)
1457 rte_free(l2_tn_info->hash_map);
1458 if (l2_tn_info->hash_handle)
1459 rte_hash_free(l2_tn_info->hash_handle);
1461 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1462 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1465 rte_free(l2_tn_filter);
1471 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1473 struct ixgbe_hw_fdir_info *fdir_info =
1474 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1475 char fdir_hash_name[RTE_HASH_NAMESIZE];
1476 struct rte_hash_parameters fdir_hash_params = {
1477 .name = fdir_hash_name,
1478 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1479 .key_len = sizeof(union ixgbe_atr_input),
1480 .hash_func = rte_hash_crc,
1481 .hash_func_init_val = 0,
1482 .socket_id = rte_socket_id(),
1485 TAILQ_INIT(&fdir_info->fdir_list);
1486 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1487 "fdir_%s", eth_dev->data->name);
1488 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1489 if (!fdir_info->hash_handle) {
1490 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1493 fdir_info->hash_map = rte_zmalloc("ixgbe",
1494 sizeof(struct ixgbe_fdir_filter *) *
1495 IXGBE_MAX_FDIR_FILTER_NUM,
1497 if (!fdir_info->hash_map) {
1499 "Failed to allocate memory for fdir hash map!");
1502 fdir_info->mask_added = FALSE;
1507 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1509 struct ixgbe_l2_tn_info *l2_tn_info =
1510 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1511 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1512 struct rte_hash_parameters l2_tn_hash_params = {
1513 .name = l2_tn_hash_name,
1514 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1515 .key_len = sizeof(struct ixgbe_l2_tn_key),
1516 .hash_func = rte_hash_crc,
1517 .hash_func_init_val = 0,
1518 .socket_id = rte_socket_id(),
1521 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1522 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1523 "l2_tn_%s", eth_dev->data->name);
1524 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1525 if (!l2_tn_info->hash_handle) {
1526 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1529 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1530 sizeof(struct ixgbe_l2_tn_filter *) *
1531 IXGBE_MAX_L2_TN_FILTER_NUM,
1533 if (!l2_tn_info->hash_map) {
1535 "Failed to allocate memory for L2 TN hash map!");
1538 l2_tn_info->e_tag_en = FALSE;
1539 l2_tn_info->e_tag_fwd_en = FALSE;
1540 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1545 * Negotiate mailbox API version with the PF.
1546 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1547 * Then we try to negotiate starting with the most recent one.
1548 * If all negotiation attempts fail, then we will proceed with
1549 * the default one (ixgbe_mbox_api_10).
1552 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1556 /* start with highest supported, proceed down */
1557 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1564 i != RTE_DIM(sup_ver) &&
1565 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1571 generate_random_mac_addr(struct ether_addr *mac_addr)
1575 /* Set Organizationally Unique Identifier (OUI) prefix. */
1576 mac_addr->addr_bytes[0] = 0x00;
1577 mac_addr->addr_bytes[1] = 0x09;
1578 mac_addr->addr_bytes[2] = 0xC0;
1579 /* Force indication of locally assigned MAC address. */
1580 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1581 /* Generate the last 3 bytes of the MAC address with a random number. */
1582 random = rte_rand();
1583 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1587 * Virtual Function device init
1590 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1594 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1595 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1598 struct ixgbe_vfta *shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1600 struct ixgbe_hwstrip *hwstrip =
1601 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1602 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1604 PMD_INIT_FUNC_TRACE();
1606 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1607 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1608 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1610 /* for secondary processes, we don't initialise any further as primary
1611 * has already done this work. Only check we don't need a different
1614 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1615 struct ixgbe_tx_queue *txq;
1616 /* TX queue function in primary, set by last queue initialized
1617 * Tx queue may not initialized by primary process
1619 if (eth_dev->data->tx_queues) {
1620 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1621 ixgbe_set_tx_function(eth_dev, txq);
1623 /* Use default TX function if we get here */
1624 PMD_INIT_LOG(NOTICE,
1625 "No TX queues configured yet. Using default TX function.");
1628 ixgbe_set_rx_function(eth_dev);
1633 rte_eth_copy_pci_info(eth_dev, pci_dev);
1634 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1636 hw->device_id = pci_dev->id.device_id;
1637 hw->vendor_id = pci_dev->id.vendor_id;
1638 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1640 /* initialize the vfta */
1641 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1643 /* initialize the hw strip bitmap*/
1644 memset(hwstrip, 0, sizeof(*hwstrip));
1646 /* Initialize the shared code (base driver) */
1647 diag = ixgbe_init_shared_code(hw);
1648 if (diag != IXGBE_SUCCESS) {
1649 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1653 /* init_mailbox_params */
1654 hw->mbx.ops.init_params(hw);
1656 /* Reset the hw statistics */
1657 ixgbevf_dev_stats_reset(eth_dev);
1659 /* Disable the interrupts for VF */
1660 ixgbevf_intr_disable(hw);
1662 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1663 diag = hw->mac.ops.reset_hw(hw);
1666 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1667 * the underlying PF driver has not assigned a MAC address to the VF.
1668 * In this case, assign a random MAC address.
1670 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1671 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1675 /* negotiate mailbox API version to use with the PF. */
1676 ixgbevf_negotiate_api(hw);
1678 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1679 ixgbevf_get_queues(hw, &tcs, &tc);
1681 /* Allocate memory for storing MAC addresses */
1682 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1683 hw->mac.num_rar_entries, 0);
1684 if (eth_dev->data->mac_addrs == NULL) {
1686 "Failed to allocate %u bytes needed to store "
1688 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1692 /* Generate a random MAC address, if none was assigned by PF. */
1693 if (is_zero_ether_addr(perm_addr)) {
1694 generate_random_mac_addr(perm_addr);
1695 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1697 rte_free(eth_dev->data->mac_addrs);
1698 eth_dev->data->mac_addrs = NULL;
1701 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1702 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1703 "%02x:%02x:%02x:%02x:%02x:%02x",
1704 perm_addr->addr_bytes[0],
1705 perm_addr->addr_bytes[1],
1706 perm_addr->addr_bytes[2],
1707 perm_addr->addr_bytes[3],
1708 perm_addr->addr_bytes[4],
1709 perm_addr->addr_bytes[5]);
1712 /* Copy the permanent MAC address */
1713 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1715 /* reset the hardware with the new settings */
1716 diag = hw->mac.ops.start_hw(hw);
1722 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1726 rte_intr_callback_register(intr_handle,
1727 ixgbevf_dev_interrupt_handler, eth_dev);
1728 rte_intr_enable(intr_handle);
1729 ixgbevf_intr_enable(hw);
1731 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1732 eth_dev->data->port_id, pci_dev->id.vendor_id,
1733 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1738 /* Virtual Function device uninit */
1741 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1743 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1744 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1745 struct ixgbe_hw *hw;
1747 PMD_INIT_FUNC_TRACE();
1749 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1752 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1754 if (hw->adapter_stopped == 0)
1755 ixgbevf_dev_close(eth_dev);
1757 eth_dev->dev_ops = NULL;
1758 eth_dev->rx_pkt_burst = NULL;
1759 eth_dev->tx_pkt_burst = NULL;
1761 /* Disable the interrupts for VF */
1762 ixgbevf_intr_disable(hw);
1764 rte_free(eth_dev->data->mac_addrs);
1765 eth_dev->data->mac_addrs = NULL;
1767 rte_intr_disable(intr_handle);
1768 rte_intr_callback_unregister(intr_handle,
1769 ixgbevf_dev_interrupt_handler, eth_dev);
1774 static struct eth_driver rte_ixgbe_pmd = {
1776 .id_table = pci_id_ixgbe_map,
1777 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1778 .probe = rte_eth_dev_pci_probe,
1779 .remove = rte_eth_dev_pci_remove,
1781 .eth_dev_init = eth_ixgbe_dev_init,
1782 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1783 .dev_private_size = sizeof(struct ixgbe_adapter),
1787 * virtual function driver struct
1789 static struct eth_driver rte_ixgbevf_pmd = {
1791 .id_table = pci_id_ixgbevf_map,
1792 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1793 .probe = rte_eth_dev_pci_probe,
1794 .remove = rte_eth_dev_pci_remove,
1796 .eth_dev_init = eth_ixgbevf_dev_init,
1797 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1798 .dev_private_size = sizeof(struct ixgbe_adapter),
1802 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1804 struct ixgbe_hw *hw =
1805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 struct ixgbe_vfta *shadow_vfta =
1807 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1812 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1813 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1814 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1819 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1821 /* update local VFTA copy */
1822 shadow_vfta->vfta[vid_idx] = vfta;
1828 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1831 ixgbe_vlan_hw_strip_enable(dev, queue);
1833 ixgbe_vlan_hw_strip_disable(dev, queue);
1837 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1838 enum rte_vlan_type vlan_type,
1841 struct ixgbe_hw *hw =
1842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1848 qinq &= IXGBE_DMATXCTL_GDV;
1850 switch (vlan_type) {
1851 case ETH_VLAN_TYPE_INNER:
1853 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1854 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1855 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1856 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1857 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1858 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1859 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1862 PMD_DRV_LOG(ERR, "Inner type is not supported"
1866 case ETH_VLAN_TYPE_OUTER:
1868 /* Only the high 16-bits is valid */
1869 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1870 IXGBE_EXVET_VET_EXT_SHIFT);
1872 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1884 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1892 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1894 struct ixgbe_hw *hw =
1895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 PMD_INIT_FUNC_TRACE();
1900 /* Filter Table Disable */
1901 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1908 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1910 struct ixgbe_hw *hw =
1911 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912 struct ixgbe_vfta *shadow_vfta =
1913 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1917 PMD_INIT_FUNC_TRACE();
1919 /* Filter Table Enable */
1920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1922 vlnctrl |= IXGBE_VLNCTRL_VFE;
1924 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1926 /* write whatever is in local vfta copy */
1927 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1928 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1932 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1934 struct ixgbe_hwstrip *hwstrip =
1935 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1936 struct ixgbe_rx_queue *rxq;
1938 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1942 IXGBE_SET_HWSTRIP(hwstrip, queue);
1944 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1946 if (queue >= dev->data->nb_rx_queues)
1949 rxq = dev->data->rx_queues[queue];
1952 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1954 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1958 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1960 struct ixgbe_hw *hw =
1961 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 PMD_INIT_FUNC_TRACE();
1966 if (hw->mac.type == ixgbe_mac_82598EB) {
1967 /* No queue level support */
1968 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1972 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1973 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1974 ctrl &= ~IXGBE_RXDCTL_VME;
1975 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1977 /* record those setting for HW strip per queue */
1978 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1982 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1984 struct ixgbe_hw *hw =
1985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988 PMD_INIT_FUNC_TRACE();
1990 if (hw->mac.type == ixgbe_mac_82598EB) {
1991 /* No queue level supported */
1992 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1996 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1997 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1998 ctrl |= IXGBE_RXDCTL_VME;
1999 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2001 /* record those setting for HW strip per queue */
2002 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2006 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2008 struct ixgbe_hw *hw =
2009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012 struct ixgbe_rx_queue *rxq;
2014 PMD_INIT_FUNC_TRACE();
2016 if (hw->mac.type == ixgbe_mac_82598EB) {
2017 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2018 ctrl &= ~IXGBE_VLNCTRL_VME;
2019 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2021 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2023 rxq = dev->data->rx_queues[i];
2024 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2025 ctrl &= ~IXGBE_RXDCTL_VME;
2026 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2028 /* record those setting for HW strip per queue */
2029 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2035 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2037 struct ixgbe_hw *hw =
2038 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041 struct ixgbe_rx_queue *rxq;
2043 PMD_INIT_FUNC_TRACE();
2045 if (hw->mac.type == ixgbe_mac_82598EB) {
2046 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047 ctrl |= IXGBE_VLNCTRL_VME;
2048 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2050 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2051 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2052 rxq = dev->data->rx_queues[i];
2053 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2054 ctrl |= IXGBE_RXDCTL_VME;
2055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2057 /* record those setting for HW strip per queue */
2058 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2064 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2066 struct ixgbe_hw *hw =
2067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 PMD_INIT_FUNC_TRACE();
2072 /* DMATXCTRL: Geric Double VLAN Disable */
2073 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074 ctrl &= ~IXGBE_DMATXCTL_GDV;
2075 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2077 /* CTRL_EXT: Global Double VLAN Disable */
2078 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079 ctrl &= ~IXGBE_EXTENDED_VLAN;
2080 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2085 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2087 struct ixgbe_hw *hw =
2088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 PMD_INIT_FUNC_TRACE();
2093 /* DMATXCTRL: Geric Double VLAN Enable */
2094 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095 ctrl |= IXGBE_DMATXCTL_GDV;
2096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2098 /* CTRL_EXT: Global Double VLAN Enable */
2099 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100 ctrl |= IXGBE_EXTENDED_VLAN;
2101 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2103 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2104 if (hw->mac.type == ixgbe_mac_X550 ||
2105 hw->mac.type == ixgbe_mac_X550EM_x ||
2106 hw->mac.type == ixgbe_mac_X550EM_a) {
2107 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2108 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2109 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2113 * VET EXT field in the EXVET register = 0x8100 by default
2114 * So no need to change. Same to VT field of DMATXCTL register
2119 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2121 if (mask & ETH_VLAN_STRIP_MASK) {
2122 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2123 ixgbe_vlan_hw_strip_enable_all(dev);
2125 ixgbe_vlan_hw_strip_disable_all(dev);
2128 if (mask & ETH_VLAN_FILTER_MASK) {
2129 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2130 ixgbe_vlan_hw_filter_enable(dev);
2132 ixgbe_vlan_hw_filter_disable(dev);
2135 if (mask & ETH_VLAN_EXTEND_MASK) {
2136 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2137 ixgbe_vlan_hw_extend_enable(dev);
2139 ixgbe_vlan_hw_extend_disable(dev);
2144 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2146 struct ixgbe_hw *hw =
2147 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2149 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2151 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2152 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2156 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2158 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2163 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2166 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2172 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2173 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2179 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2181 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2182 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2184 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2186 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2187 /* check multi-queue mode */
2188 switch (dev_conf->rxmode.mq_mode) {
2189 case ETH_MQ_RX_VMDQ_DCB:
2190 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2192 case ETH_MQ_RX_VMDQ_DCB_RSS:
2193 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2194 PMD_INIT_LOG(ERR, "SRIOV active,"
2195 " unsupported mq_mode rx %d.",
2196 dev_conf->rxmode.mq_mode);
2199 case ETH_MQ_RX_VMDQ_RSS:
2200 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2201 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2202 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2203 PMD_INIT_LOG(ERR, "SRIOV is active,"
2204 " invalid queue number"
2205 " for VMDQ RSS, allowed"
2206 " value are 1, 2 or 4.");
2210 case ETH_MQ_RX_VMDQ_ONLY:
2211 case ETH_MQ_RX_NONE:
2212 /* if nothing mq mode configure, use default scheme */
2213 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2214 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2215 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2217 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2218 /* SRIOV only works in VMDq enable mode */
2219 PMD_INIT_LOG(ERR, "SRIOV is active,"
2220 " wrong mq_mode rx %d.",
2221 dev_conf->rxmode.mq_mode);
2225 switch (dev_conf->txmode.mq_mode) {
2226 case ETH_MQ_TX_VMDQ_DCB:
2227 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2228 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2230 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2231 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2235 /* check valid queue number */
2236 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2237 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2238 PMD_INIT_LOG(ERR, "SRIOV is active,"
2239 " nb_rx_q=%d nb_tx_q=%d queue number"
2240 " must be less than or equal to %d.",
2242 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2246 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2247 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2251 /* check configuration for vmdb+dcb mode */
2252 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2253 const struct rte_eth_vmdq_dcb_conf *conf;
2255 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2256 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2257 IXGBE_VMDQ_DCB_NB_QUEUES);
2260 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2261 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2262 conf->nb_queue_pools == ETH_32_POOLS)) {
2263 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2264 " nb_queue_pools must be %d or %d.",
2265 ETH_16_POOLS, ETH_32_POOLS);
2269 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2270 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2272 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2274 IXGBE_VMDQ_DCB_NB_QUEUES);
2277 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2278 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2279 conf->nb_queue_pools == ETH_32_POOLS)) {
2280 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2281 " nb_queue_pools != %d and"
2282 " nb_queue_pools != %d.",
2283 ETH_16_POOLS, ETH_32_POOLS);
2288 /* For DCB mode check our configuration before we go further */
2289 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2290 const struct rte_eth_dcb_rx_conf *conf;
2292 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2293 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2294 IXGBE_DCB_NB_QUEUES);
2297 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2298 if (!(conf->nb_tcs == ETH_4_TCS ||
2299 conf->nb_tcs == ETH_8_TCS)) {
2300 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2301 " and nb_tcs != %d.",
2302 ETH_4_TCS, ETH_8_TCS);
2307 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2308 const struct rte_eth_dcb_tx_conf *conf;
2310 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2311 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2312 IXGBE_DCB_NB_QUEUES);
2315 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2316 if (!(conf->nb_tcs == ETH_4_TCS ||
2317 conf->nb_tcs == ETH_8_TCS)) {
2318 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2319 " and nb_tcs != %d.",
2320 ETH_4_TCS, ETH_8_TCS);
2326 * When DCB/VT is off, maximum number of queues changes,
2327 * except for 82598EB, which remains constant.
2329 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2330 hw->mac.type != ixgbe_mac_82598EB) {
2331 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2333 "Neither VT nor DCB are enabled, "
2335 IXGBE_NONE_MODE_TX_NB_QUEUES);
2344 ixgbe_dev_configure(struct rte_eth_dev *dev)
2346 struct ixgbe_interrupt *intr =
2347 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2348 struct ixgbe_adapter *adapter =
2349 (struct ixgbe_adapter *)dev->data->dev_private;
2352 PMD_INIT_FUNC_TRACE();
2353 /* multipe queue mode checking */
2354 ret = ixgbe_check_mq_mode(dev);
2356 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2361 /* set flag to update link status after init */
2362 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2365 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2366 * allocation or vector Rx preconditions we will reset it.
2368 adapter->rx_bulk_alloc_allowed = true;
2369 adapter->rx_vec_allowed = true;
2375 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw =
2378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 struct ixgbe_interrupt *intr =
2380 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2383 /* only set up it on X550EM_X */
2384 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2385 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2387 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2388 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2389 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2394 * Configure device link speed and setup link.
2395 * It returns 0 on success.
2398 ixgbe_dev_start(struct rte_eth_dev *dev)
2400 struct ixgbe_hw *hw =
2401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402 struct ixgbe_vf_info *vfinfo =
2403 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2404 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2405 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2406 uint32_t intr_vector = 0;
2407 int err, link_up = 0, negotiate = 0;
2412 uint32_t *link_speeds;
2414 PMD_INIT_FUNC_TRACE();
2416 /* IXGBE devices don't support:
2417 * - half duplex (checked afterwards for valid speeds)
2418 * - fixed speed: TODO implement
2420 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2421 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2422 dev->data->port_id);
2426 /* disable uio/vfio intr/eventfd mapping */
2427 rte_intr_disable(intr_handle);
2430 hw->adapter_stopped = 0;
2431 ixgbe_stop_adapter(hw);
2433 /* reinitialize adapter
2434 * this calls reset and start
2436 status = ixgbe_pf_reset_hw(hw);
2439 hw->mac.ops.start_hw(hw);
2440 hw->mac.get_link_status = true;
2442 /* configure PF module if SRIOV enabled */
2443 ixgbe_pf_host_configure(dev);
2445 ixgbe_dev_phy_intr_setup(dev);
2447 /* check and configure queue intr-vector mapping */
2448 if ((rte_intr_cap_multiple(intr_handle) ||
2449 !RTE_ETH_DEV_SRIOV(dev).active) &&
2450 dev->data->dev_conf.intr_conf.rxq != 0) {
2451 intr_vector = dev->data->nb_rx_queues;
2452 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2453 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2454 IXGBE_MAX_INTR_QUEUE_NUM);
2457 if (rte_intr_efd_enable(intr_handle, intr_vector))
2461 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2462 intr_handle->intr_vec =
2463 rte_zmalloc("intr_vec",
2464 dev->data->nb_rx_queues * sizeof(int), 0);
2465 if (intr_handle->intr_vec == NULL) {
2466 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2467 " intr_vec", dev->data->nb_rx_queues);
2472 /* confiugre msix for sleep until rx interrupt */
2473 ixgbe_configure_msix(dev);
2475 /* initialize transmission unit */
2476 ixgbe_dev_tx_init(dev);
2478 /* This can fail when allocating mbufs for descriptor rings */
2479 err = ixgbe_dev_rx_init(dev);
2481 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2485 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2486 ETH_VLAN_EXTEND_MASK;
2487 ixgbe_vlan_offload_set(dev, mask);
2489 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2490 /* Enable vlan filtering for VMDq */
2491 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2494 /* Configure DCB hw */
2495 ixgbe_configure_dcb(dev);
2497 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2498 err = ixgbe_fdir_configure(dev);
2503 /* Restore vf rate limit */
2504 if (vfinfo != NULL) {
2505 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2506 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2507 if (vfinfo[vf].tx_rate[idx] != 0)
2508 rte_pmd_ixgbe_set_vf_rate_limit(
2509 dev->data->port_id, vf,
2510 vfinfo[vf].tx_rate[idx],
2514 ixgbe_restore_statistics_mapping(dev);
2516 err = ixgbe_dev_rxtx_start(dev);
2518 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2522 /* Skip link setup if loopback mode is enabled for 82599. */
2523 if (hw->mac.type == ixgbe_mac_82599EB &&
2524 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2525 goto skip_link_setup;
2527 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2528 err = hw->mac.ops.setup_sfp(hw);
2533 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2534 /* Turn on the copper */
2535 ixgbe_set_phy_power(hw, true);
2537 /* Turn on the laser */
2538 ixgbe_enable_tx_laser(hw);
2541 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2544 dev->data->dev_link.link_status = link_up;
2546 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2550 link_speeds = &dev->data->dev_conf.link_speeds;
2551 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2552 ETH_LINK_SPEED_10G)) {
2553 PMD_INIT_LOG(ERR, "Invalid link setting");
2558 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2559 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2560 IXGBE_LINK_SPEED_82599_AUTONEG :
2561 IXGBE_LINK_SPEED_82598_AUTONEG;
2563 if (*link_speeds & ETH_LINK_SPEED_10G)
2564 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2565 if (*link_speeds & ETH_LINK_SPEED_1G)
2566 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2567 if (*link_speeds & ETH_LINK_SPEED_100M)
2568 speed |= IXGBE_LINK_SPEED_100_FULL;
2571 err = ixgbe_setup_link(hw, speed, link_up);
2577 if (rte_intr_allow_others(intr_handle)) {
2578 /* check if lsc interrupt is enabled */
2579 if (dev->data->dev_conf.intr_conf.lsc != 0)
2580 ixgbe_dev_lsc_interrupt_setup(dev);
2581 ixgbe_dev_macsec_interrupt_setup(dev);
2583 rte_intr_callback_unregister(intr_handle,
2584 ixgbe_dev_interrupt_handler, dev);
2585 if (dev->data->dev_conf.intr_conf.lsc != 0)
2586 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2587 " no intr multiplex");
2590 /* check if rxq interrupt is enabled */
2591 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2592 rte_intr_dp_is_en(intr_handle))
2593 ixgbe_dev_rxq_interrupt_setup(dev);
2595 /* enable uio/vfio intr/eventfd mapping */
2596 rte_intr_enable(intr_handle);
2598 /* resume enabled intr since hw reset */
2599 ixgbe_enable_intr(dev);
2600 ixgbe_l2_tunnel_conf(dev);
2601 ixgbe_filter_restore(dev);
2606 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2607 ixgbe_dev_clear_queues(dev);
2612 * Stop device: disable rx and tx functions to allow for reconfiguring.
2615 ixgbe_dev_stop(struct rte_eth_dev *dev)
2617 struct rte_eth_link link;
2618 struct ixgbe_hw *hw =
2619 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620 struct ixgbe_vf_info *vfinfo =
2621 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2622 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2623 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2626 PMD_INIT_FUNC_TRACE();
2628 /* disable interrupts */
2629 ixgbe_disable_intr(hw);
2632 ixgbe_pf_reset_hw(hw);
2633 hw->adapter_stopped = 0;
2636 ixgbe_stop_adapter(hw);
2638 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2639 vfinfo[vf].clear_to_send = false;
2641 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2642 /* Turn off the copper */
2643 ixgbe_set_phy_power(hw, false);
2645 /* Turn off the laser */
2646 ixgbe_disable_tx_laser(hw);
2649 ixgbe_dev_clear_queues(dev);
2651 /* Clear stored conf */
2652 dev->data->scattered_rx = 0;
2655 /* Clear recorded link status */
2656 memset(&link, 0, sizeof(link));
2657 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2659 if (!rte_intr_allow_others(intr_handle))
2660 /* resume to the default handler */
2661 rte_intr_callback_register(intr_handle,
2662 ixgbe_dev_interrupt_handler,
2665 /* Clean datapath event and queue/vec mapping */
2666 rte_intr_efd_disable(intr_handle);
2667 if (intr_handle->intr_vec != NULL) {
2668 rte_free(intr_handle->intr_vec);
2669 intr_handle->intr_vec = NULL;
2674 * Set device link up: enable tx.
2677 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2679 struct ixgbe_hw *hw =
2680 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 if (hw->mac.type == ixgbe_mac_82599EB) {
2682 #ifdef RTE_NIC_BYPASS
2683 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2684 /* Not suported in bypass mode */
2685 PMD_INIT_LOG(ERR, "Set link up is not supported "
2686 "by device id 0x%x", hw->device_id);
2692 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2693 /* Turn on the copper */
2694 ixgbe_set_phy_power(hw, true);
2696 /* Turn on the laser */
2697 ixgbe_enable_tx_laser(hw);
2704 * Set device link down: disable tx.
2707 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2709 struct ixgbe_hw *hw =
2710 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711 if (hw->mac.type == ixgbe_mac_82599EB) {
2712 #ifdef RTE_NIC_BYPASS
2713 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2714 /* Not suported in bypass mode */
2715 PMD_INIT_LOG(ERR, "Set link down is not supported "
2716 "by device id 0x%x", hw->device_id);
2722 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2723 /* Turn off the copper */
2724 ixgbe_set_phy_power(hw, false);
2726 /* Turn off the laser */
2727 ixgbe_disable_tx_laser(hw);
2734 * Reest and stop device.
2737 ixgbe_dev_close(struct rte_eth_dev *dev)
2739 struct ixgbe_hw *hw =
2740 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2742 PMD_INIT_FUNC_TRACE();
2744 ixgbe_pf_reset_hw(hw);
2746 ixgbe_dev_stop(dev);
2747 hw->adapter_stopped = 1;
2749 ixgbe_dev_free_queues(dev);
2751 ixgbe_disable_pcie_master(hw);
2753 /* reprogram the RAR[0] in case user changed it. */
2754 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2758 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2759 struct ixgbe_hw_stats *hw_stats,
2760 struct ixgbe_macsec_stats *macsec_stats,
2761 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2762 uint64_t *total_qprc, uint64_t *total_qprdc)
2764 uint32_t bprc, lxon, lxoff, total;
2765 uint32_t delta_gprc = 0;
2767 /* Workaround for RX byte count not including CRC bytes when CRC
2768 * strip is enabled. CRC bytes are removed from counters when crc_strip
2771 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2772 IXGBE_HLREG0_RXCRCSTRP);
2774 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2775 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2776 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2777 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2779 for (i = 0; i < 8; i++) {
2780 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2782 /* global total per queue */
2783 hw_stats->mpc[i] += mp;
2784 /* Running comprehensive total for stats display */
2785 *total_missed_rx += hw_stats->mpc[i];
2786 if (hw->mac.type == ixgbe_mac_82598EB) {
2787 hw_stats->rnbc[i] +=
2788 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2789 hw_stats->pxonrxc[i] +=
2790 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2791 hw_stats->pxoffrxc[i] +=
2792 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2794 hw_stats->pxonrxc[i] +=
2795 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2796 hw_stats->pxoffrxc[i] +=
2797 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2798 hw_stats->pxon2offc[i] +=
2799 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2801 hw_stats->pxontxc[i] +=
2802 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2803 hw_stats->pxofftxc[i] +=
2804 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2806 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2807 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2808 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2809 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2811 delta_gprc += delta_qprc;
2813 hw_stats->qprc[i] += delta_qprc;
2814 hw_stats->qptc[i] += delta_qptc;
2816 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2817 hw_stats->qbrc[i] +=
2818 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2820 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2822 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2823 hw_stats->qbtc[i] +=
2824 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2826 hw_stats->qprdc[i] += delta_qprdc;
2827 *total_qprdc += hw_stats->qprdc[i];
2829 *total_qprc += hw_stats->qprc[i];
2830 *total_qbrc += hw_stats->qbrc[i];
2832 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2833 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2834 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2837 * An errata states that gprc actually counts good + missed packets:
2838 * Workaround to set gprc to summated queue packet receives
2840 hw_stats->gprc = *total_qprc;
2842 if (hw->mac.type != ixgbe_mac_82598EB) {
2843 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2844 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2845 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2846 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2847 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2848 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2849 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2850 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2852 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2853 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2854 /* 82598 only has a counter in the high register */
2855 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2856 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2857 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2859 uint64_t old_tpr = hw_stats->tpr;
2861 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2862 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2865 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2867 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2868 hw_stats->gptc += delta_gptc;
2869 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2870 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2873 * Workaround: mprc hardware is incorrectly counting
2874 * broadcasts, so for now we subtract those.
2876 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2877 hw_stats->bprc += bprc;
2878 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2879 if (hw->mac.type == ixgbe_mac_82598EB)
2880 hw_stats->mprc -= bprc;
2882 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2883 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2884 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2885 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2886 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2887 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2889 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2890 hw_stats->lxontxc += lxon;
2891 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2892 hw_stats->lxofftxc += lxoff;
2893 total = lxon + lxoff;
2895 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2896 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2897 hw_stats->gptc -= total;
2898 hw_stats->mptc -= total;
2899 hw_stats->ptc64 -= total;
2900 hw_stats->gotc -= total * ETHER_MIN_LEN;
2902 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2903 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2904 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2905 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2906 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2907 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2908 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2909 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2910 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2911 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2912 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2913 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2914 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2915 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2916 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2917 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2918 /* Only read FCOE on 82599 */
2919 if (hw->mac.type != ixgbe_mac_82598EB) {
2920 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2921 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2922 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2923 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2924 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2927 /* Flow Director Stats registers */
2928 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2929 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2931 /* MACsec Stats registers */
2932 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2933 macsec_stats->out_pkts_encrypted +=
2934 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2935 macsec_stats->out_pkts_protected +=
2936 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2937 macsec_stats->out_octets_encrypted +=
2938 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2939 macsec_stats->out_octets_protected +=
2940 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2941 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2942 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2943 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2944 macsec_stats->in_pkts_unknownsci +=
2945 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2946 macsec_stats->in_octets_decrypted +=
2947 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2948 macsec_stats->in_octets_validated +=
2949 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2950 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2951 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2952 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2953 for (i = 0; i < 2; i++) {
2954 macsec_stats->in_pkts_ok +=
2955 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2956 macsec_stats->in_pkts_invalid +=
2957 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2958 macsec_stats->in_pkts_notvalid +=
2959 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2961 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2962 macsec_stats->in_pkts_notusingsa +=
2963 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2967 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2970 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2972 struct ixgbe_hw *hw =
2973 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974 struct ixgbe_hw_stats *hw_stats =
2975 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2976 struct ixgbe_macsec_stats *macsec_stats =
2977 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2978 dev->data->dev_private);
2979 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2982 total_missed_rx = 0;
2987 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2988 &total_qbrc, &total_qprc, &total_qprdc);
2993 /* Fill out the rte_eth_stats statistics structure */
2994 stats->ipackets = total_qprc;
2995 stats->ibytes = total_qbrc;
2996 stats->opackets = hw_stats->gptc;
2997 stats->obytes = hw_stats->gotc;
2999 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3000 stats->q_ipackets[i] = hw_stats->qprc[i];
3001 stats->q_opackets[i] = hw_stats->qptc[i];
3002 stats->q_ibytes[i] = hw_stats->qbrc[i];
3003 stats->q_obytes[i] = hw_stats->qbtc[i];
3004 stats->q_errors[i] = hw_stats->qprdc[i];
3008 stats->imissed = total_missed_rx;
3009 stats->ierrors = hw_stats->crcerrs +
3025 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3027 struct ixgbe_hw_stats *stats =
3028 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3030 /* HW registers are cleared on read */
3031 ixgbe_dev_stats_get(dev, NULL);
3033 /* Reset software totals */
3034 memset(stats, 0, sizeof(*stats));
3037 /* This function calculates the number of xstats based on the current config */
3039 ixgbe_xstats_calc_num(void) {
3040 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3041 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3042 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3045 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3046 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3048 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3049 unsigned stat, i, count;
3051 if (xstats_names != NULL) {
3054 /* Note: limit >= cnt_stats checked upstream
3055 * in rte_eth_xstats_names()
3058 /* Extended stats from ixgbe_hw_stats */
3059 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3060 snprintf(xstats_names[count].name,
3061 sizeof(xstats_names[count].name),
3063 rte_ixgbe_stats_strings[i].name);
3068 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3069 snprintf(xstats_names[count].name,
3070 sizeof(xstats_names[count].name),
3072 rte_ixgbe_macsec_strings[i].name);
3076 /* RX Priority Stats */
3077 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3078 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3079 snprintf(xstats_names[count].name,
3080 sizeof(xstats_names[count].name),
3081 "rx_priority%u_%s", i,
3082 rte_ixgbe_rxq_strings[stat].name);
3087 /* TX Priority Stats */
3088 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3089 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3090 snprintf(xstats_names[count].name,
3091 sizeof(xstats_names[count].name),
3092 "tx_priority%u_%s", i,
3093 rte_ixgbe_txq_strings[stat].name);
3101 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3102 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3106 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3109 if (xstats_names != NULL)
3110 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3111 snprintf(xstats_names[i].name,
3112 sizeof(xstats_names[i].name),
3113 "%s", rte_ixgbevf_stats_strings[i].name);
3114 return IXGBEVF_NB_XSTATS;
3118 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3121 struct ixgbe_hw *hw =
3122 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123 struct ixgbe_hw_stats *hw_stats =
3124 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3125 struct ixgbe_macsec_stats *macsec_stats =
3126 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3127 dev->data->dev_private);
3128 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3129 unsigned i, stat, count = 0;
3131 count = ixgbe_xstats_calc_num();
3136 total_missed_rx = 0;
3141 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3142 &total_qbrc, &total_qprc, &total_qprdc);
3144 /* If this is a reset xstats is NULL, and we have cleared the
3145 * registers by reading them.
3150 /* Extended stats from ixgbe_hw_stats */
3152 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3153 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3154 rte_ixgbe_stats_strings[i].offset);
3155 xstats[count].id = count;
3160 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3161 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3162 rte_ixgbe_macsec_strings[i].offset);
3163 xstats[count].id = count;
3167 /* RX Priority Stats */
3168 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3169 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3170 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3171 rte_ixgbe_rxq_strings[stat].offset +
3172 (sizeof(uint64_t) * i));
3173 xstats[count].id = count;
3178 /* TX Priority Stats */
3179 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3180 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3181 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3182 rte_ixgbe_txq_strings[stat].offset +
3183 (sizeof(uint64_t) * i));
3184 xstats[count].id = count;
3192 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3194 struct ixgbe_hw_stats *stats =
3195 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3196 struct ixgbe_macsec_stats *macsec_stats =
3197 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3198 dev->data->dev_private);
3200 unsigned count = ixgbe_xstats_calc_num();
3202 /* HW registers are cleared on read */
3203 ixgbe_dev_xstats_get(dev, NULL, count);
3205 /* Reset software totals */
3206 memset(stats, 0, sizeof(*stats));
3207 memset(macsec_stats, 0, sizeof(*macsec_stats));
3211 ixgbevf_update_stats(struct rte_eth_dev *dev)
3213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3215 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3217 /* Good Rx packet, include VF loopback */
3218 UPDATE_VF_STAT(IXGBE_VFGPRC,
3219 hw_stats->last_vfgprc, hw_stats->vfgprc);
3221 /* Good Rx octets, include VF loopback */
3222 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3223 hw_stats->last_vfgorc, hw_stats->vfgorc);
3225 /* Good Tx packet, include VF loopback */
3226 UPDATE_VF_STAT(IXGBE_VFGPTC,
3227 hw_stats->last_vfgptc, hw_stats->vfgptc);
3229 /* Good Tx octets, include VF loopback */
3230 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3231 hw_stats->last_vfgotc, hw_stats->vfgotc);
3233 /* Rx Multicst Packet */
3234 UPDATE_VF_STAT(IXGBE_VFMPRC,
3235 hw_stats->last_vfmprc, hw_stats->vfmprc);
3239 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3242 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3243 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3246 if (n < IXGBEVF_NB_XSTATS)
3247 return IXGBEVF_NB_XSTATS;
3249 ixgbevf_update_stats(dev);
3254 /* Extended stats */
3255 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3256 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3257 rte_ixgbevf_stats_strings[i].offset);
3260 return IXGBEVF_NB_XSTATS;
3264 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3266 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3267 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3269 ixgbevf_update_stats(dev);
3274 stats->ipackets = hw_stats->vfgprc;
3275 stats->ibytes = hw_stats->vfgorc;
3276 stats->opackets = hw_stats->vfgptc;
3277 stats->obytes = hw_stats->vfgotc;
3281 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3283 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3284 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3286 /* Sync HW register to the last stats */
3287 ixgbevf_dev_stats_get(dev, NULL);
3289 /* reset HW current stats*/
3290 hw_stats->vfgprc = 0;
3291 hw_stats->vfgorc = 0;
3292 hw_stats->vfgptc = 0;
3293 hw_stats->vfgotc = 0;
3297 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3299 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 u16 eeprom_verh, eeprom_verl;
3304 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3305 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3307 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3308 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3310 ret += 1; /* add the size of '\0' */
3311 if (fw_size < (u32)ret)
3318 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3320 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3324 dev_info->pci_dev = pci_dev;
3325 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3326 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3327 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3329 * When DCB/VT is off, maximum number of queues changes,
3330 * except for 82598EB, which remains constant.
3332 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3333 hw->mac.type != ixgbe_mac_82598EB)
3334 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3336 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3337 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3338 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3339 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3340 dev_info->max_vfs = pci_dev->max_vfs;
3341 if (hw->mac.type == ixgbe_mac_82598EB)
3342 dev_info->max_vmdq_pools = ETH_16_POOLS;
3344 dev_info->max_vmdq_pools = ETH_64_POOLS;
3345 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3346 dev_info->rx_offload_capa =
3347 DEV_RX_OFFLOAD_VLAN_STRIP |
3348 DEV_RX_OFFLOAD_IPV4_CKSUM |
3349 DEV_RX_OFFLOAD_UDP_CKSUM |
3350 DEV_RX_OFFLOAD_TCP_CKSUM;
3353 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3356 if ((hw->mac.type == ixgbe_mac_82599EB ||
3357 hw->mac.type == ixgbe_mac_X540) &&
3358 !RTE_ETH_DEV_SRIOV(dev).active)
3359 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3361 if (hw->mac.type == ixgbe_mac_82599EB ||
3362 hw->mac.type == ixgbe_mac_X540)
3363 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3365 if (hw->mac.type == ixgbe_mac_X550 ||
3366 hw->mac.type == ixgbe_mac_X550EM_x ||
3367 hw->mac.type == ixgbe_mac_X550EM_a)
3368 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3370 dev_info->tx_offload_capa =
3371 DEV_TX_OFFLOAD_VLAN_INSERT |
3372 DEV_TX_OFFLOAD_IPV4_CKSUM |
3373 DEV_TX_OFFLOAD_UDP_CKSUM |
3374 DEV_TX_OFFLOAD_TCP_CKSUM |
3375 DEV_TX_OFFLOAD_SCTP_CKSUM |
3376 DEV_TX_OFFLOAD_TCP_TSO;
3378 if (hw->mac.type == ixgbe_mac_82599EB ||
3379 hw->mac.type == ixgbe_mac_X540)
3380 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3382 if (hw->mac.type == ixgbe_mac_X550 ||
3383 hw->mac.type == ixgbe_mac_X550EM_x ||
3384 hw->mac.type == ixgbe_mac_X550EM_a)
3385 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3387 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3389 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3390 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3391 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3393 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3397 dev_info->default_txconf = (struct rte_eth_txconf) {
3399 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3400 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3401 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3403 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3404 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3405 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3406 ETH_TXQ_FLAGS_NOOFFLOADS,
3409 dev_info->rx_desc_lim = rx_desc_lim;
3410 dev_info->tx_desc_lim = tx_desc_lim;
3412 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3413 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3414 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3416 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3417 if (hw->mac.type == ixgbe_mac_X540 ||
3418 hw->mac.type == ixgbe_mac_X540_vf ||
3419 hw->mac.type == ixgbe_mac_X550 ||
3420 hw->mac.type == ixgbe_mac_X550_vf) {
3421 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3425 static const uint32_t *
3426 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3428 static const uint32_t ptypes[] = {
3429 /* For non-vec functions,
3430 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3431 * for vec functions,
3432 * refers to _recv_raw_pkts_vec().
3436 RTE_PTYPE_L3_IPV4_EXT,
3438 RTE_PTYPE_L3_IPV6_EXT,
3442 RTE_PTYPE_TUNNEL_IP,
3443 RTE_PTYPE_INNER_L3_IPV6,
3444 RTE_PTYPE_INNER_L3_IPV6_EXT,
3445 RTE_PTYPE_INNER_L4_TCP,
3446 RTE_PTYPE_INNER_L4_UDP,
3450 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3451 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3452 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3453 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3459 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3460 struct rte_eth_dev_info *dev_info)
3462 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3463 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465 dev_info->pci_dev = pci_dev;
3466 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3467 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3468 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3469 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3470 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3471 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3472 dev_info->max_vfs = pci_dev->max_vfs;
3473 if (hw->mac.type == ixgbe_mac_82598EB)
3474 dev_info->max_vmdq_pools = ETH_16_POOLS;
3476 dev_info->max_vmdq_pools = ETH_64_POOLS;
3477 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3478 DEV_RX_OFFLOAD_IPV4_CKSUM |
3479 DEV_RX_OFFLOAD_UDP_CKSUM |
3480 DEV_RX_OFFLOAD_TCP_CKSUM;
3481 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3482 DEV_TX_OFFLOAD_IPV4_CKSUM |
3483 DEV_TX_OFFLOAD_UDP_CKSUM |
3484 DEV_TX_OFFLOAD_TCP_CKSUM |
3485 DEV_TX_OFFLOAD_SCTP_CKSUM |
3486 DEV_TX_OFFLOAD_TCP_TSO;
3488 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3490 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3491 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3492 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3494 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3498 dev_info->default_txconf = (struct rte_eth_txconf) {
3500 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3501 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3502 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3504 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3505 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3506 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3507 ETH_TXQ_FLAGS_NOOFFLOADS,
3510 dev_info->rx_desc_lim = rx_desc_lim;
3511 dev_info->tx_desc_lim = tx_desc_lim;
3514 /* return 0 means link status changed, -1 means not changed */
3516 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3518 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519 struct rte_eth_link link, old;
3520 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3524 link.link_status = ETH_LINK_DOWN;
3525 link.link_speed = 0;
3526 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3527 memset(&old, 0, sizeof(old));
3528 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3530 hw->mac.get_link_status = true;
3532 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3533 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3534 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3536 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3539 link.link_speed = ETH_SPEED_NUM_100M;
3540 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3541 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3542 if (link.link_status == old.link_status)
3548 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3549 if (link.link_status == old.link_status)
3553 link.link_status = ETH_LINK_UP;
3554 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3556 switch (link_speed) {
3558 case IXGBE_LINK_SPEED_UNKNOWN:
3559 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3560 link.link_speed = ETH_SPEED_NUM_100M;
3563 case IXGBE_LINK_SPEED_100_FULL:
3564 link.link_speed = ETH_SPEED_NUM_100M;
3567 case IXGBE_LINK_SPEED_1GB_FULL:
3568 link.link_speed = ETH_SPEED_NUM_1G;
3571 case IXGBE_LINK_SPEED_10GB_FULL:
3572 link.link_speed = ETH_SPEED_NUM_10G;
3575 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3577 if (link.link_status == old.link_status)
3584 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3590 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3591 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3595 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3601 fctrl &= (~IXGBE_FCTRL_UPE);
3602 if (dev->data->all_multicast == 1)
3603 fctrl |= IXGBE_FCTRL_MPE;
3605 fctrl &= (~IXGBE_FCTRL_MPE);
3606 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3610 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3616 fctrl |= IXGBE_FCTRL_MPE;
3617 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3621 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3623 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626 if (dev->data->promiscuous == 1)
3627 return; /* must remain in all_multicast mode */
3629 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3630 fctrl &= (~IXGBE_FCTRL_MPE);
3631 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3635 * It clears the interrupt causes and enables the interrupt.
3636 * It will be called once only during nic initialized.
3639 * Pointer to struct rte_eth_dev.
3642 * - On success, zero.
3643 * - On failure, a negative value.
3646 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3648 struct ixgbe_interrupt *intr =
3649 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3651 ixgbe_dev_link_status_print(dev);
3652 intr->mask |= IXGBE_EICR_LSC;
3658 * It clears the interrupt causes and enables the interrupt.
3659 * It will be called once only during nic initialized.
3662 * Pointer to struct rte_eth_dev.
3665 * - On success, zero.
3666 * - On failure, a negative value.
3669 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3671 struct ixgbe_interrupt *intr =
3672 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3674 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3680 * It clears the interrupt causes and enables the interrupt.
3681 * It will be called once only during nic initialized.
3684 * Pointer to struct rte_eth_dev.
3687 * - On success, zero.
3688 * - On failure, a negative value.
3691 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3693 struct ixgbe_interrupt *intr =
3694 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3696 intr->mask |= IXGBE_EICR_LINKSEC;
3702 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3705 * Pointer to struct rte_eth_dev.
3708 * - On success, zero.
3709 * - On failure, a negative value.
3712 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3715 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 struct ixgbe_interrupt *intr =
3717 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3719 /* clear all cause mask */
3720 ixgbe_disable_intr(hw);
3722 /* read-on-clear nic registers here */
3723 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3724 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3728 /* set flag for async link update */
3729 if (eicr & IXGBE_EICR_LSC)
3730 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3732 if (eicr & IXGBE_EICR_MAILBOX)
3733 intr->flags |= IXGBE_FLAG_MAILBOX;
3735 if (eicr & IXGBE_EICR_LINKSEC)
3736 intr->flags |= IXGBE_FLAG_MACSEC;
3738 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3739 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3740 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3741 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3747 * It gets and then prints the link status.
3750 * Pointer to struct rte_eth_dev.
3753 * - On success, zero.
3754 * - On failure, a negative value.
3757 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3759 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3760 struct rte_eth_link link;
3762 memset(&link, 0, sizeof(link));
3763 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3764 if (link.link_status) {
3765 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3766 (int)(dev->data->port_id),
3767 (unsigned)link.link_speed,
3768 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3769 "full-duplex" : "half-duplex");
3771 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3772 (int)(dev->data->port_id));
3774 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3775 pci_dev->addr.domain,
3777 pci_dev->addr.devid,
3778 pci_dev->addr.function);
3782 * It executes link_update after knowing an interrupt occurred.
3785 * Pointer to struct rte_eth_dev.
3788 * - On success, zero.
3789 * - On failure, a negative value.
3792 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3793 struct rte_intr_handle *intr_handle)
3795 struct ixgbe_interrupt *intr =
3796 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3798 struct rte_eth_link link;
3799 struct ixgbe_hw *hw =
3800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3804 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3805 ixgbe_pf_mbx_process(dev);
3806 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3809 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3810 ixgbe_handle_lasi(hw);
3811 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3814 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3815 /* get the link status before link update, for predicting later */
3816 memset(&link, 0, sizeof(link));
3817 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3819 ixgbe_dev_link_update(dev, 0);
3822 if (!link.link_status)
3823 /* handle it 1 sec later, wait it being stable */
3824 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3825 /* likely to down */
3827 /* handle it 4 sec later, wait it being stable */
3828 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3830 ixgbe_dev_link_status_print(dev);
3831 intr->mask_original = intr->mask;
3832 /* only disable lsc interrupt */
3833 intr->mask &= ~IXGBE_EIMS_LSC;
3834 if (rte_eal_alarm_set(timeout * 1000,
3835 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3836 PMD_DRV_LOG(ERR, "Error setting alarm");
3838 intr->mask = intr->mask_original;
3841 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3842 ixgbe_enable_intr(dev);
3843 rte_intr_enable(intr_handle);
3849 * Interrupt handler which shall be registered for alarm callback for delayed
3850 * handling specific interrupt to wait for the stable nic state. As the
3851 * NIC interrupt state is not stable for ixgbe after link is just down,
3852 * it needs to wait 4 seconds to get the stable status.
3855 * Pointer to interrupt handle.
3857 * The address of parameter (struct rte_eth_dev *) regsitered before.
3863 ixgbe_dev_interrupt_delayed_handler(void *param)
3865 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3866 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3867 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3868 struct ixgbe_interrupt *intr =
3869 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3870 struct ixgbe_hw *hw =
3871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874 ixgbe_disable_intr(hw);
3876 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3877 if (eicr & IXGBE_EICR_MAILBOX)
3878 ixgbe_pf_mbx_process(dev);
3880 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3881 ixgbe_handle_lasi(hw);
3882 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3885 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3886 ixgbe_dev_link_update(dev, 0);
3887 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3888 ixgbe_dev_link_status_print(dev);
3889 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3892 if (intr->flags & IXGBE_FLAG_MACSEC) {
3893 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3895 intr->flags &= ~IXGBE_FLAG_MACSEC;
3898 /* restore original mask */
3899 intr->mask = intr->mask_original;
3900 intr->mask_original = 0;
3902 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3903 ixgbe_enable_intr(dev);
3904 rte_intr_enable(intr_handle);
3908 * Interrupt handler triggered by NIC for handling
3909 * specific interrupt.
3912 * Pointer to interrupt handle.
3914 * The address of parameter (struct rte_eth_dev *) regsitered before.
3920 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3923 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3925 ixgbe_dev_interrupt_get_status(dev);
3926 ixgbe_dev_interrupt_action(dev, handle);
3930 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3932 struct ixgbe_hw *hw;
3934 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3939 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3941 struct ixgbe_hw *hw;
3943 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3948 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3950 struct ixgbe_hw *hw;
3956 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958 fc_conf->pause_time = hw->fc.pause_time;
3959 fc_conf->high_water = hw->fc.high_water[0];
3960 fc_conf->low_water = hw->fc.low_water[0];
3961 fc_conf->send_xon = hw->fc.send_xon;
3962 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3965 * Return rx_pause status according to actual setting of
3968 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3969 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3975 * Return tx_pause status according to actual setting of
3978 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3979 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3984 if (rx_pause && tx_pause)
3985 fc_conf->mode = RTE_FC_FULL;
3987 fc_conf->mode = RTE_FC_RX_PAUSE;
3989 fc_conf->mode = RTE_FC_TX_PAUSE;
3991 fc_conf->mode = RTE_FC_NONE;
3997 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3999 struct ixgbe_hw *hw;
4001 uint32_t rx_buf_size;
4002 uint32_t max_high_water;
4004 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4011 PMD_INIT_FUNC_TRACE();
4013 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4015 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4018 * At least reserve one Ethernet frame for watermark
4019 * high_water/low_water in kilo bytes for ixgbe
4021 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4022 if ((fc_conf->high_water > max_high_water) ||
4023 (fc_conf->high_water < fc_conf->low_water)) {
4024 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4025 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4029 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4030 hw->fc.pause_time = fc_conf->pause_time;
4031 hw->fc.high_water[0] = fc_conf->high_water;
4032 hw->fc.low_water[0] = fc_conf->low_water;
4033 hw->fc.send_xon = fc_conf->send_xon;
4034 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4036 err = ixgbe_fc_enable(hw);
4038 /* Not negotiated is not an error case */
4039 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4041 /* check if we want to forward MAC frames - driver doesn't have native
4042 * capability to do that, so we'll write the registers ourselves */
4044 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4046 /* set or clear MFLCN.PMCF bit depending on configuration */
4047 if (fc_conf->mac_ctrl_frame_fwd != 0)
4048 mflcn |= IXGBE_MFLCN_PMCF;
4050 mflcn &= ~IXGBE_MFLCN_PMCF;
4052 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4053 IXGBE_WRITE_FLUSH(hw);
4058 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4063 * ixgbe_pfc_enable_generic - Enable flow control
4064 * @hw: pointer to hardware structure
4065 * @tc_num: traffic class number
4066 * Enable flow control according to the current settings.
4069 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4072 uint32_t mflcn_reg, fccfg_reg;
4074 uint32_t fcrtl, fcrth;
4078 /* Validate the water mark configuration */
4079 if (!hw->fc.pause_time) {
4080 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4084 /* Low water mark of zero causes XOFF floods */
4085 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4086 /* High/Low water can not be 0 */
4087 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4088 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4089 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4093 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4094 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4095 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4099 /* Negotiate the fc mode to use */
4100 ixgbe_fc_autoneg(hw);
4102 /* Disable any previous flow control settings */
4103 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4104 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4106 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4107 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4109 switch (hw->fc.current_mode) {
4112 * If the count of enabled RX Priority Flow control >1,
4113 * and the TX pause can not be disabled
4116 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4117 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4118 if (reg & IXGBE_FCRTH_FCEN)
4122 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4124 case ixgbe_fc_rx_pause:
4126 * Rx Flow control is enabled and Tx Flow control is
4127 * disabled by software override. Since there really
4128 * isn't a way to advertise that we are capable of RX
4129 * Pause ONLY, we will advertise that we support both
4130 * symmetric and asymmetric Rx PAUSE. Later, we will
4131 * disable the adapter's ability to send PAUSE frames.
4133 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4135 * If the count of enabled RX Priority Flow control >1,
4136 * and the TX pause can not be disabled
4139 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4140 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4141 if (reg & IXGBE_FCRTH_FCEN)
4145 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4147 case ixgbe_fc_tx_pause:
4149 * Tx Flow control is enabled, and Rx Flow control is
4150 * disabled by software override.
4152 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4155 /* Flow control (both Rx and Tx) is enabled by SW override. */
4156 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4157 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4160 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4161 ret_val = IXGBE_ERR_CONFIG;
4165 /* Set 802.3x based flow control settings. */
4166 mflcn_reg |= IXGBE_MFLCN_DPF;
4167 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4168 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4170 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4171 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4172 hw->fc.high_water[tc_num]) {
4173 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4174 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4175 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4177 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4179 * In order to prevent Tx hangs when the internal Tx
4180 * switch is enabled we must set the high water mark
4181 * to the maximum FCRTH value. This allows the Tx
4182 * switch to function even under heavy Rx workloads.
4184 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4186 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4188 /* Configure pause time (2 TCs per register) */
4189 reg = hw->fc.pause_time * 0x00010001;
4190 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4191 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4193 /* Configure flow control refresh threshold value */
4194 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4201 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4206 if (hw->mac.type != ixgbe_mac_82598EB) {
4207 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4213 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4216 uint32_t rx_buf_size;
4217 uint32_t max_high_water;
4219 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4220 struct ixgbe_hw *hw =
4221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222 struct ixgbe_dcb_config *dcb_config =
4223 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4225 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4232 PMD_INIT_FUNC_TRACE();
4234 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4235 tc_num = map[pfc_conf->priority];
4236 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4237 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4239 * At least reserve one Ethernet frame for watermark
4240 * high_water/low_water in kilo bytes for ixgbe
4242 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4243 if ((pfc_conf->fc.high_water > max_high_water) ||
4244 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4245 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4246 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4250 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4251 hw->fc.pause_time = pfc_conf->fc.pause_time;
4252 hw->fc.send_xon = pfc_conf->fc.send_xon;
4253 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4254 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4256 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4258 /* Not negotiated is not an error case */
4259 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4262 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4267 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4268 struct rte_eth_rss_reta_entry64 *reta_conf,
4271 uint16_t i, sp_reta_size;
4274 uint16_t idx, shift;
4275 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278 PMD_INIT_FUNC_TRACE();
4280 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4281 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4286 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4287 if (reta_size != sp_reta_size) {
4288 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4289 "(%d) doesn't match the number hardware can supported "
4290 "(%d)", reta_size, sp_reta_size);
4294 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4295 idx = i / RTE_RETA_GROUP_SIZE;
4296 shift = i % RTE_RETA_GROUP_SIZE;
4297 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4301 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4302 if (mask == IXGBE_4_BIT_MASK)
4305 r = IXGBE_READ_REG(hw, reta_reg);
4306 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4307 if (mask & (0x1 << j))
4308 reta |= reta_conf[idx].reta[shift + j] <<
4311 reta |= r & (IXGBE_8_BIT_MASK <<
4314 IXGBE_WRITE_REG(hw, reta_reg, reta);
4321 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4322 struct rte_eth_rss_reta_entry64 *reta_conf,
4325 uint16_t i, sp_reta_size;
4328 uint16_t idx, shift;
4329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332 PMD_INIT_FUNC_TRACE();
4333 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4334 if (reta_size != sp_reta_size) {
4335 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4336 "(%d) doesn't match the number hardware can supported "
4337 "(%d)", reta_size, sp_reta_size);
4341 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4342 idx = i / RTE_RETA_GROUP_SIZE;
4343 shift = i % RTE_RETA_GROUP_SIZE;
4344 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4349 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4350 reta = IXGBE_READ_REG(hw, reta_reg);
4351 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4352 if (mask & (0x1 << j))
4353 reta_conf[idx].reta[shift + j] =
4354 ((reta >> (CHAR_BIT * j)) &
4363 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4364 uint32_t index, uint32_t pool)
4366 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367 uint32_t enable_addr = 1;
4369 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4373 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4375 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377 ixgbe_clear_rar(hw, index);
4381 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4383 ixgbe_remove_rar(dev, 0);
4385 ixgbe_add_rar(dev, addr, 0, 0);
4389 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4391 if (strcmp(dev->driver->pci_drv.driver.name,
4392 drv->pci_drv.driver.name))
4399 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4400 struct ether_addr *mac_addr)
4402 struct ixgbe_hw *hw;
4403 struct ixgbe_vf_info *vfinfo;
4405 uint8_t *new_mac = (uint8_t *)(mac_addr);
4406 struct rte_eth_dev *dev;
4407 struct rte_pci_device *pci_dev;
4409 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4411 dev = &rte_eth_devices[port];
4412 pci_dev = IXGBE_DEV_TO_PCI(dev);
4414 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4417 if (vf >= pci_dev->max_vfs)
4420 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4422 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4424 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4425 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4427 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4434 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4438 struct ixgbe_hw *hw;
4439 struct rte_eth_dev_info dev_info;
4440 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4442 ixgbe_dev_info_get(dev, &dev_info);
4444 /* check that mtu is within the allowed range */
4445 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4448 /* refuse mtu that requires the support of scattered packets when this
4449 * feature has not been enabled before.
4451 if (!dev->data->scattered_rx &&
4452 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4453 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4456 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4459 /* switch to jumbo mode if needed */
4460 if (frame_size > ETHER_MAX_LEN) {
4461 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4462 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4464 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4465 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4467 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4469 /* update max frame size */
4470 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4472 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4473 maxfrs &= 0x0000FFFF;
4474 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4475 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4481 * Virtual Function operations
4484 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4486 PMD_INIT_FUNC_TRACE();
4488 /* Clear interrupt mask to stop from interrupts being generated */
4489 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4491 IXGBE_WRITE_FLUSH(hw);
4495 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4497 PMD_INIT_FUNC_TRACE();
4499 /* VF enable interrupt autoclean */
4500 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4501 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4502 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4504 IXGBE_WRITE_FLUSH(hw);
4508 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4510 struct rte_eth_conf *conf = &dev->data->dev_conf;
4511 struct ixgbe_adapter *adapter =
4512 (struct ixgbe_adapter *)dev->data->dev_private;
4514 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4515 dev->data->port_id);
4518 * VF has no ability to enable/disable HW CRC
4519 * Keep the persistent behavior the same as Host PF
4521 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4522 if (!conf->rxmode.hw_strip_crc) {
4523 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4524 conf->rxmode.hw_strip_crc = 1;
4527 if (conf->rxmode.hw_strip_crc) {
4528 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4529 conf->rxmode.hw_strip_crc = 0;
4534 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4535 * allocation or vector Rx preconditions we will reset it.
4537 adapter->rx_bulk_alloc_allowed = true;
4538 adapter->rx_vec_allowed = true;
4544 ixgbevf_dev_start(struct rte_eth_dev *dev)
4546 struct ixgbe_hw *hw =
4547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548 uint32_t intr_vector = 0;
4549 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4550 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4554 PMD_INIT_FUNC_TRACE();
4556 hw->mac.ops.reset_hw(hw);
4557 hw->mac.get_link_status = true;
4559 /* negotiate mailbox API version to use with the PF. */
4560 ixgbevf_negotiate_api(hw);
4562 ixgbevf_dev_tx_init(dev);
4564 /* This can fail when allocating mbufs for descriptor rings */
4565 err = ixgbevf_dev_rx_init(dev);
4567 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4568 ixgbe_dev_clear_queues(dev);
4573 ixgbevf_set_vfta_all(dev, 1);
4576 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4577 ETH_VLAN_EXTEND_MASK;
4578 ixgbevf_vlan_offload_set(dev, mask);
4580 ixgbevf_dev_rxtx_start(dev);
4582 /* check and configure queue intr-vector mapping */
4583 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4584 intr_vector = dev->data->nb_rx_queues;
4585 if (rte_intr_efd_enable(intr_handle, intr_vector))
4589 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4590 intr_handle->intr_vec =
4591 rte_zmalloc("intr_vec",
4592 dev->data->nb_rx_queues * sizeof(int), 0);
4593 if (intr_handle->intr_vec == NULL) {
4594 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4595 " intr_vec", dev->data->nb_rx_queues);
4599 ixgbevf_configure_msix(dev);
4601 rte_intr_enable(intr_handle);
4603 /* Re-enable interrupt for VF */
4604 ixgbevf_intr_enable(hw);
4610 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4613 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4614 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4616 PMD_INIT_FUNC_TRACE();
4618 ixgbevf_intr_disable(hw);
4620 hw->adapter_stopped = 1;
4621 ixgbe_stop_adapter(hw);
4624 * Clear what we set, but we still keep shadow_vfta to
4625 * restore after device starts
4627 ixgbevf_set_vfta_all(dev, 0);
4629 /* Clear stored conf */
4630 dev->data->scattered_rx = 0;
4632 ixgbe_dev_clear_queues(dev);
4634 /* Clean datapath event and queue/vec mapping */
4635 rte_intr_efd_disable(intr_handle);
4636 if (intr_handle->intr_vec != NULL) {
4637 rte_free(intr_handle->intr_vec);
4638 intr_handle->intr_vec = NULL;
4643 ixgbevf_dev_close(struct rte_eth_dev *dev)
4645 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647 PMD_INIT_FUNC_TRACE();
4651 ixgbevf_dev_stop(dev);
4653 ixgbe_dev_free_queues(dev);
4656 * Remove the VF MAC address ro ensure
4657 * that the VF traffic goes to the PF
4658 * after stop, close and detach of the VF
4660 ixgbevf_remove_mac_addr(dev, 0);
4663 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4665 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666 struct ixgbe_vfta *shadow_vfta =
4667 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4668 int i = 0, j = 0, vfta = 0, mask = 1;
4670 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4671 vfta = shadow_vfta->vfta[i];
4674 for (j = 0; j < 32; j++) {
4676 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4686 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4688 struct ixgbe_hw *hw =
4689 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690 struct ixgbe_vfta *shadow_vfta =
4691 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4692 uint32_t vid_idx = 0;
4693 uint32_t vid_bit = 0;
4696 PMD_INIT_FUNC_TRACE();
4698 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4699 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4701 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4704 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4705 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4707 /* Save what we set and retore it after device reset */
4709 shadow_vfta->vfta[vid_idx] |= vid_bit;
4711 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4717 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4719 struct ixgbe_hw *hw =
4720 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723 PMD_INIT_FUNC_TRACE();
4725 if (queue >= hw->mac.max_rx_queues)
4728 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4730 ctrl |= IXGBE_RXDCTL_VME;
4732 ctrl &= ~IXGBE_RXDCTL_VME;
4733 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4735 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4739 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4741 struct ixgbe_hw *hw =
4742 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746 /* VF function only support hw strip feature, others are not support */
4747 if (mask & ETH_VLAN_STRIP_MASK) {
4748 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4750 for (i = 0; i < hw->mac.max_rx_queues; i++)
4751 ixgbevf_vlan_strip_queue_set(dev, i, on);
4756 ixgbe_vt_check(struct ixgbe_hw *hw)
4760 /* if Virtualization Technology is enabled */
4761 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4762 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4763 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4771 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4773 uint32_t vector = 0;
4775 switch (hw->mac.mc_filter_type) {
4776 case 0: /* use bits [47:36] of the address */
4777 vector = ((uc_addr->addr_bytes[4] >> 4) |
4778 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4780 case 1: /* use bits [46:35] of the address */
4781 vector = ((uc_addr->addr_bytes[4] >> 3) |
4782 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4784 case 2: /* use bits [45:34] of the address */
4785 vector = ((uc_addr->addr_bytes[4] >> 2) |
4786 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4788 case 3: /* use bits [43:32] of the address */
4789 vector = ((uc_addr->addr_bytes[4]) |
4790 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4792 default: /* Invalid mc_filter_type */
4796 /* vector can only be 12-bits or boundary will be exceeded */
4802 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4810 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4811 const uint32_t ixgbe_uta_bit_shift = 5;
4812 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4813 const uint32_t bit1 = 0x1;
4815 struct ixgbe_hw *hw =
4816 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4817 struct ixgbe_uta_info *uta_info =
4818 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4820 /* The UTA table only exists on 82599 hardware and newer */
4821 if (hw->mac.type < ixgbe_mac_82599EB)
4824 vector = ixgbe_uta_vector(hw, mac_addr);
4825 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4826 uta_shift = vector & ixgbe_uta_bit_mask;
4828 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4832 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4834 uta_info->uta_in_use++;
4835 reg_val |= (bit1 << uta_shift);
4836 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4838 uta_info->uta_in_use--;
4839 reg_val &= ~(bit1 << uta_shift);
4840 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4843 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4845 if (uta_info->uta_in_use > 0)
4846 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4847 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4849 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4855 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4858 struct ixgbe_hw *hw =
4859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 struct ixgbe_uta_info *uta_info =
4861 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4863 /* The UTA table only exists on 82599 hardware and newer */
4864 if (hw->mac.type < ixgbe_mac_82599EB)
4868 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4869 uta_info->uta_shadow[i] = ~0;
4870 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4873 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4874 uta_info->uta_shadow[i] = 0;
4875 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4883 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4885 uint32_t new_val = orig_val;
4887 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4888 new_val |= IXGBE_VMOLR_AUPE;
4889 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4890 new_val |= IXGBE_VMOLR_ROMPE;
4891 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4892 new_val |= IXGBE_VMOLR_ROPE;
4893 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4894 new_val |= IXGBE_VMOLR_BAM;
4895 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4896 new_val |= IXGBE_VMOLR_MPE;
4903 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4905 struct ixgbe_hw *hw;
4906 struct ixgbe_mac_info *mac;
4907 struct rte_eth_dev *dev;
4908 struct rte_pci_device *pci_dev;
4910 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4912 dev = &rte_eth_devices[port];
4913 pci_dev = IXGBE_DEV_TO_PCI(dev);
4915 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4918 if (vf >= pci_dev->max_vfs)
4924 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4927 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4933 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4935 struct ixgbe_hw *hw;
4936 struct ixgbe_mac_info *mac;
4937 struct rte_eth_dev *dev;
4938 struct rte_pci_device *pci_dev;
4940 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4942 dev = &rte_eth_devices[port];
4943 pci_dev = IXGBE_DEV_TO_PCI(dev);
4945 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4948 if (vf >= pci_dev->max_vfs)
4954 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4956 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4962 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4964 struct ixgbe_hw *hw;
4966 struct rte_eth_dev *dev;
4967 struct rte_pci_device *pci_dev;
4969 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4971 dev = &rte_eth_devices[port];
4972 pci_dev = IXGBE_DEV_TO_PCI(dev);
4974 if (!is_device_supported(dev, &rte_ixgbe_pmd))
4977 if (vf >= pci_dev->max_vfs)
4980 if (vlan_id > ETHER_MAX_VLAN_ID)
4983 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4987 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4992 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4998 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5000 struct ixgbe_hw *hw;
5002 struct rte_eth_dev *dev;
5004 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5006 dev = &rte_eth_devices[port];
5008 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5014 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5016 /* enable or disable VMDQ loopback */
5018 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5020 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5022 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5028 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5030 struct ixgbe_hw *hw;
5033 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5034 struct rte_eth_dev *dev;
5036 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5038 dev = &rte_eth_devices[port];
5040 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5046 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047 for (i = 0; i <= num_queues; i++) {
5048 reg_value = IXGBE_QDE_WRITE |
5049 (i << IXGBE_QDE_IDX_SHIFT) |
5050 (on & IXGBE_QDE_ENABLE);
5051 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5058 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5060 struct ixgbe_hw *hw;
5062 struct rte_eth_dev *dev;
5063 struct rte_pci_device *pci_dev;
5065 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5067 dev = &rte_eth_devices[port];
5068 pci_dev = IXGBE_DEV_TO_PCI(dev);
5070 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5073 /* only support VF's 0 to 63 */
5074 if ((vf >= pci_dev->max_vfs) || (vf > 63))
5080 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5083 reg_value |= IXGBE_SRRCTL_DROP_EN;
5085 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5087 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5093 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5095 struct rte_eth_dev *dev;
5096 struct rte_pci_device *pci_dev;
5097 struct ixgbe_hw *hw;
5098 uint16_t queues_per_pool;
5101 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5103 dev = &rte_eth_devices[port];
5104 pci_dev = IXGBE_DEV_TO_PCI(dev);
5105 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5110 if (vf >= pci_dev->max_vfs)
5116 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5118 /* The PF has 128 queue pairs and in SRIOV configuration
5119 * those queues will be assigned to VF's, so RXDCTL
5120 * registers will be dealing with queues which will be
5122 * Let's say we have SRIOV configured with 31 VF's then the
5123 * first 124 queues 0-123 will be allocated to VF's and only
5124 * the last 4 queues 123-127 will be assigned to the PF.
5126 if (hw->mac.type == ixgbe_mac_82598EB)
5127 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5130 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5133 for (q = 0; q < queues_per_pool; q++)
5134 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5135 q + vf * queues_per_pool, on);
5140 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5143 struct rte_eth_dev *dev;
5144 struct rte_pci_device *pci_dev;
5145 struct ixgbe_hw *hw;
5148 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5150 dev = &rte_eth_devices[port];
5151 pci_dev = IXGBE_DEV_TO_PCI(dev);
5153 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5156 if (vf >= pci_dev->max_vfs)
5162 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5163 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5165 if (hw->mac.type == ixgbe_mac_82598EB) {
5166 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5167 " on 82599 hardware and newer");
5170 if (ixgbe_vt_check(hw) < 0)
5173 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5180 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5186 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5188 struct rte_eth_dev *dev;
5189 struct rte_pci_device *pci_dev;
5192 const uint8_t bit1 = 0x1;
5193 struct ixgbe_hw *hw;
5195 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5197 dev = &rte_eth_devices[port];
5198 pci_dev = IXGBE_DEV_TO_PCI(dev);
5200 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5203 if (vf >= pci_dev->max_vfs)
5209 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5211 if (ixgbe_vt_check(hw) < 0)
5214 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5216 addr = IXGBE_VFRE(1);
5217 val = bit1 << (vf - 32);
5219 addr = IXGBE_VFRE(0);
5223 reg = IXGBE_READ_REG(hw, addr);
5230 IXGBE_WRITE_REG(hw, addr, reg);
5236 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5238 struct rte_eth_dev *dev;
5239 struct rte_pci_device *pci_dev;
5242 const uint8_t bit1 = 0x1;
5244 struct ixgbe_hw *hw;
5246 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5248 dev = &rte_eth_devices[port];
5249 pci_dev = IXGBE_DEV_TO_PCI(dev);
5251 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5254 if (vf >= pci_dev->max_vfs)
5260 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261 if (ixgbe_vt_check(hw) < 0)
5264 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5266 addr = IXGBE_VFTE(1);
5267 val = bit1 << (vf - 32);
5269 addr = IXGBE_VFTE(0);
5273 reg = IXGBE_READ_REG(hw, addr);
5280 IXGBE_WRITE_REG(hw, addr, reg);
5286 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5287 uint64_t vf_mask, uint8_t vlan_on)
5289 struct rte_eth_dev *dev;
5292 struct ixgbe_hw *hw;
5294 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5296 dev = &rte_eth_devices[port];
5298 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5301 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5304 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5305 if (ixgbe_vt_check(hw) < 0)
5308 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5309 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5310 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5320 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5321 uint16_t tx_rate, uint64_t q_msk)
5323 struct rte_eth_dev *dev;
5324 struct ixgbe_hw *hw;
5325 struct ixgbe_vf_info *vfinfo;
5326 struct rte_eth_link link;
5327 uint8_t nb_q_per_pool;
5328 uint32_t queue_stride;
5329 uint32_t queue_idx, idx = 0, vf_idx;
5331 uint16_t total_rate = 0;
5332 struct rte_pci_device *pci_dev;
5334 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5336 dev = &rte_eth_devices[port];
5337 pci_dev = IXGBE_DEV_TO_PCI(dev);
5338 rte_eth_link_get_nowait(port, &link);
5340 if (!is_device_supported(dev, &rte_ixgbe_pmd))
5343 if (vf >= pci_dev->max_vfs)
5346 if (tx_rate > link.link_speed)
5352 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5353 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5354 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5355 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5356 queue_idx = vf * queue_stride;
5357 queue_end = queue_idx + nb_q_per_pool - 1;
5358 if (queue_end >= hw->mac.max_tx_queues)
5362 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5365 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5367 total_rate += vfinfo[vf_idx].tx_rate[idx];
5373 /* Store tx_rate for this vf. */
5374 for (idx = 0; idx < nb_q_per_pool; idx++) {
5375 if (((uint64_t)0x1 << idx) & q_msk) {
5376 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5377 vfinfo[vf].tx_rate[idx] = tx_rate;
5378 total_rate += tx_rate;
5382 if (total_rate > dev->data->dev_link.link_speed) {
5383 /* Reset stored TX rate of the VF if it causes exceed
5386 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5390 /* Set RTTBCNRC of each queue/pool for vf X */
5391 for (; queue_idx <= queue_end; queue_idx++) {
5393 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5400 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5401 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5402 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5403 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5404 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5405 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5406 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5409 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5410 struct rte_eth_mirror_conf *mirror_conf,
5411 uint8_t rule_id, uint8_t on)
5413 uint32_t mr_ctl, vlvf;
5414 uint32_t mp_lsb = 0;
5415 uint32_t mv_msb = 0;
5416 uint32_t mv_lsb = 0;
5417 uint32_t mp_msb = 0;
5420 uint64_t vlan_mask = 0;
5422 const uint8_t pool_mask_offset = 32;
5423 const uint8_t vlan_mask_offset = 32;
5424 const uint8_t dst_pool_offset = 8;
5425 const uint8_t rule_mr_offset = 4;
5426 const uint8_t mirror_rule_mask = 0x0F;
5428 struct ixgbe_mirror_info *mr_info =
5429 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5430 struct ixgbe_hw *hw =
5431 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5432 uint8_t mirror_type = 0;
5434 if (ixgbe_vt_check(hw) < 0)
5437 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5440 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5441 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5442 mirror_conf->rule_type);
5446 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5447 mirror_type |= IXGBE_MRCTL_VLME;
5448 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5449 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5450 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5451 /* search vlan id related pool vlan filter index */
5452 reg_index = ixgbe_find_vlvf_slot(hw,
5453 mirror_conf->vlan.vlan_id[i],
5457 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5458 if ((vlvf & IXGBE_VLVF_VIEN) &&
5459 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5460 mirror_conf->vlan.vlan_id[i]))
5461 vlan_mask |= (1ULL << reg_index);
5468 mv_lsb = vlan_mask & 0xFFFFFFFF;
5469 mv_msb = vlan_mask >> vlan_mask_offset;
5471 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5472 mirror_conf->vlan.vlan_mask;
5473 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5474 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5475 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5476 mirror_conf->vlan.vlan_id[i];
5481 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5482 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5483 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5488 * if enable pool mirror, write related pool mask register,if disable
5489 * pool mirror, clear PFMRVM register
5491 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5492 mirror_type |= IXGBE_MRCTL_VPME;
5494 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5495 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5496 mr_info->mr_conf[rule_id].pool_mask =
5497 mirror_conf->pool_mask;
5502 mr_info->mr_conf[rule_id].pool_mask = 0;
5505 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5506 mirror_type |= IXGBE_MRCTL_UPME;
5507 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5508 mirror_type |= IXGBE_MRCTL_DPME;
5510 /* read mirror control register and recalculate it */
5511 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5514 mr_ctl |= mirror_type;
5515 mr_ctl &= mirror_rule_mask;
5516 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5518 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5520 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5521 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5523 /* write mirrror control register */
5524 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5526 /* write pool mirrror control register */
5527 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5528 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5529 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5532 /* write VLAN mirrror control register */
5533 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5534 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5535 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5543 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5546 uint32_t lsb_val = 0;
5547 uint32_t msb_val = 0;
5548 const uint8_t rule_mr_offset = 4;
5550 struct ixgbe_hw *hw =
5551 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5552 struct ixgbe_mirror_info *mr_info =
5553 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5555 if (ixgbe_vt_check(hw) < 0)
5558 memset(&mr_info->mr_conf[rule_id], 0,
5559 sizeof(struct rte_eth_mirror_conf));
5561 /* clear PFVMCTL register */
5562 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5564 /* clear pool mask register */
5565 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5566 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5568 /* clear vlan mask register */
5569 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5570 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5576 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5578 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5579 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5581 struct ixgbe_hw *hw =
5582 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5585 mask |= (1 << IXGBE_MISC_VEC_ID);
5586 RTE_SET_USED(queue_id);
5587 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5589 rte_intr_enable(intr_handle);
5595 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5598 struct ixgbe_hw *hw =
5599 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5601 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5602 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5603 RTE_SET_USED(queue_id);
5604 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5610 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5612 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5615 struct ixgbe_hw *hw =
5616 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5617 struct ixgbe_interrupt *intr =
5618 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5620 if (queue_id < 16) {
5621 ixgbe_disable_intr(hw);
5622 intr->mask |= (1 << queue_id);
5623 ixgbe_enable_intr(dev);
5624 } else if (queue_id < 32) {
5625 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5626 mask &= (1 << queue_id);
5627 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5628 } else if (queue_id < 64) {
5629 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5630 mask &= (1 << (queue_id - 32));
5631 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5633 rte_intr_enable(intr_handle);
5639 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5642 struct ixgbe_hw *hw =
5643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644 struct ixgbe_interrupt *intr =
5645 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5647 if (queue_id < 16) {
5648 ixgbe_disable_intr(hw);
5649 intr->mask &= ~(1 << queue_id);
5650 ixgbe_enable_intr(dev);
5651 } else if (queue_id < 32) {
5652 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5653 mask &= ~(1 << queue_id);
5654 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5655 } else if (queue_id < 64) {
5656 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5657 mask &= ~(1 << (queue_id - 32));
5658 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5665 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5666 uint8_t queue, uint8_t msix_vector)
5670 if (direction == -1) {
5672 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5673 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5676 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5678 /* rx or tx cause */
5679 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5680 idx = ((16 * (queue & 1)) + (8 * direction));
5681 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5682 tmp &= ~(0xFF << idx);
5683 tmp |= (msix_vector << idx);
5684 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5689 * set the IVAR registers, mapping interrupt causes to vectors
5691 * pointer to ixgbe_hw struct
5693 * 0 for Rx, 1 for Tx, -1 for other causes
5695 * queue to map the corresponding interrupt to
5697 * the vector to map to the corresponding queue
5700 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5701 uint8_t queue, uint8_t msix_vector)
5705 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5706 if (hw->mac.type == ixgbe_mac_82598EB) {
5707 if (direction == -1)
5709 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5710 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5711 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5712 tmp |= (msix_vector << (8 * (queue & 0x3)));
5713 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5714 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5715 (hw->mac.type == ixgbe_mac_X540)) {
5716 if (direction == -1) {
5718 idx = ((queue & 1) * 8);
5719 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5720 tmp &= ~(0xFF << idx);
5721 tmp |= (msix_vector << idx);
5722 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5724 /* rx or tx causes */
5725 idx = ((16 * (queue & 1)) + (8 * direction));
5726 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5727 tmp &= ~(0xFF << idx);
5728 tmp |= (msix_vector << idx);
5729 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5735 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5737 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5738 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5739 struct ixgbe_hw *hw =
5740 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5744 /* Configure VF other cause ivar */
5745 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5747 /* won't configure msix register if no mapping is done
5748 * between intr vector and event fd.
5750 if (!rte_intr_dp_is_en(intr_handle))
5753 /* Configure all RX queues of VF */
5754 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5755 /* Force all queue use vector 0,
5756 * as IXGBE_VF_MAXMSIVECOTR = 1
5758 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5759 intr_handle->intr_vec[q_idx] = vector_idx;
5764 * Sets up the hardware to properly generate MSI-X interrupts
5766 * board private structure
5769 ixgbe_configure_msix(struct rte_eth_dev *dev)
5771 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5772 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5773 struct ixgbe_hw *hw =
5774 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5776 uint32_t vec = IXGBE_MISC_VEC_ID;
5780 /* won't configure msix register if no mapping is done
5781 * between intr vector and event fd
5783 if (!rte_intr_dp_is_en(intr_handle))
5786 if (rte_intr_allow_others(intr_handle))
5787 vec = base = IXGBE_RX_VEC_START;
5789 /* setup GPIE for MSI-x mode */
5790 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5791 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5792 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5793 /* auto clearing and auto setting corresponding bits in EIMS
5794 * when MSI-X interrupt is triggered
5796 if (hw->mac.type == ixgbe_mac_82598EB) {
5797 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5799 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5800 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5802 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5804 /* Populate the IVAR table and set the ITR values to the
5805 * corresponding register.
5807 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5809 /* by default, 1:1 mapping */
5810 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5811 intr_handle->intr_vec[queue_id] = vec;
5812 if (vec < base + intr_handle->nb_efd - 1)
5816 switch (hw->mac.type) {
5817 case ixgbe_mac_82598EB:
5818 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5821 case ixgbe_mac_82599EB:
5822 case ixgbe_mac_X540:
5823 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5828 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5829 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5831 /* set up to autoclear timer, and the vectors */
5832 mask = IXGBE_EIMS_ENABLE_MASK;
5833 mask &= ~(IXGBE_EIMS_OTHER |
5834 IXGBE_EIMS_MAILBOX |
5837 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5840 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5841 uint16_t queue_idx, uint16_t tx_rate)
5843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5844 uint32_t rf_dec, rf_int;
5846 uint16_t link_speed = dev->data->dev_link.link_speed;
5848 if (queue_idx >= hw->mac.max_tx_queues)
5852 /* Calculate the rate factor values to set */
5853 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5854 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5855 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5857 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5858 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5859 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5860 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5866 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5867 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5870 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5871 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5872 IXGBE_MAX_JUMBO_FRAME_SIZE))
5873 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5874 IXGBE_MMW_SIZE_JUMBO_FRAME);
5876 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5877 IXGBE_MMW_SIZE_DEFAULT);
5879 /* Set RTTBCNRC of queue X */
5880 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5881 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5882 IXGBE_WRITE_FLUSH(hw);
5888 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5889 __attribute__((unused)) uint32_t index,
5890 __attribute__((unused)) uint32_t pool)
5892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5896 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5897 * operation. Trap this case to avoid exhausting the [very limited]
5898 * set of PF resources used to store VF MAC addresses.
5900 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5902 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5905 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5909 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5913 struct ether_addr *mac_addr;
5918 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5919 * not support the deletion of a given MAC address.
5920 * Instead, it imposes to delete all MAC addresses, then to add again
5921 * all MAC addresses with the exception of the one to be deleted.
5923 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5926 * Add again all MAC addresses, with the exception of the deleted one
5927 * and of the permanent MAC address.
5929 for (i = 0, mac_addr = dev->data->mac_addrs;
5930 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5931 /* Skip the deleted MAC address */
5934 /* Skip NULL MAC addresses */
5935 if (is_zero_ether_addr(mac_addr))
5937 /* Skip the permanent MAC address */
5938 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5940 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5943 "Adding again MAC address "
5944 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5946 mac_addr->addr_bytes[0],
5947 mac_addr->addr_bytes[1],
5948 mac_addr->addr_bytes[2],
5949 mac_addr->addr_bytes[3],
5950 mac_addr->addr_bytes[4],
5951 mac_addr->addr_bytes[5],
5957 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5961 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5964 #define MAC_TYPE_FILTER_SUP(type) do {\
5965 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5966 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5967 (type) != ixgbe_mac_X550EM_a)\
5972 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5973 struct rte_eth_syn_filter *filter,
5976 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977 struct ixgbe_filter_info *filter_info =
5978 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5982 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5985 syn_info = filter_info->syn_info;
5988 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5990 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5991 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5993 if (filter->hig_pri)
5994 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5996 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5998 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5999 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6001 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6004 filter_info->syn_info = synqf;
6005 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6006 IXGBE_WRITE_FLUSH(hw);
6011 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6012 struct rte_eth_syn_filter *filter)
6014 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6015 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6017 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6018 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6019 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6026 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6027 enum rte_filter_op filter_op,
6030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6033 MAC_TYPE_FILTER_SUP(hw->mac.type);
6035 if (filter_op == RTE_ETH_FILTER_NOP)
6039 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6044 switch (filter_op) {
6045 case RTE_ETH_FILTER_ADD:
6046 ret = ixgbe_syn_filter_set(dev,
6047 (struct rte_eth_syn_filter *)arg,
6050 case RTE_ETH_FILTER_DELETE:
6051 ret = ixgbe_syn_filter_set(dev,
6052 (struct rte_eth_syn_filter *)arg,
6055 case RTE_ETH_FILTER_GET:
6056 ret = ixgbe_syn_filter_get(dev,
6057 (struct rte_eth_syn_filter *)arg);
6060 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6069 static inline enum ixgbe_5tuple_protocol
6070 convert_protocol_type(uint8_t protocol_value)
6072 if (protocol_value == IPPROTO_TCP)
6073 return IXGBE_FILTER_PROTOCOL_TCP;
6074 else if (protocol_value == IPPROTO_UDP)
6075 return IXGBE_FILTER_PROTOCOL_UDP;
6076 else if (protocol_value == IPPROTO_SCTP)
6077 return IXGBE_FILTER_PROTOCOL_SCTP;
6079 return IXGBE_FILTER_PROTOCOL_NONE;
6082 /* inject a 5-tuple filter to HW */
6084 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6085 struct ixgbe_5tuple_filter *filter)
6087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089 uint32_t ftqf, sdpqf;
6090 uint32_t l34timir = 0;
6091 uint8_t mask = 0xff;
6095 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6096 IXGBE_SDPQF_DSTPORT_SHIFT);
6097 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6099 ftqf = (uint32_t)(filter->filter_info.proto &
6100 IXGBE_FTQF_PROTOCOL_MASK);
6101 ftqf |= (uint32_t)((filter->filter_info.priority &
6102 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6103 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6104 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6105 if (filter->filter_info.dst_ip_mask == 0)
6106 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6107 if (filter->filter_info.src_port_mask == 0)
6108 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6109 if (filter->filter_info.dst_port_mask == 0)
6110 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6111 if (filter->filter_info.proto_mask == 0)
6112 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6113 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6114 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6115 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6117 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6118 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6119 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6120 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6122 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6123 l34timir |= (uint32_t)(filter->queue <<
6124 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6125 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6129 * add a 5tuple filter
6132 * dev: Pointer to struct rte_eth_dev.
6133 * index: the index the filter allocates.
6134 * filter: ponter to the filter that will be added.
6135 * rx_queue: the queue id the filter assigned to.
6138 * - On success, zero.
6139 * - On failure, a negative value.
6142 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6143 struct ixgbe_5tuple_filter *filter)
6145 struct ixgbe_filter_info *filter_info =
6146 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6150 * look for an unused 5tuple filter index,
6151 * and insert the filter to list.
6153 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6154 idx = i / (sizeof(uint32_t) * NBBY);
6155 shift = i % (sizeof(uint32_t) * NBBY);
6156 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6157 filter_info->fivetuple_mask[idx] |= 1 << shift;
6159 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6165 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6166 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6170 ixgbe_inject_5tuple_filter(dev, filter);
6176 * remove a 5tuple filter
6179 * dev: Pointer to struct rte_eth_dev.
6180 * filter: the pointer of the filter will be removed.
6183 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6184 struct ixgbe_5tuple_filter *filter)
6186 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6187 struct ixgbe_filter_info *filter_info =
6188 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6189 uint16_t index = filter->index;
6191 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6192 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6193 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6196 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6197 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6198 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6199 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6200 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6204 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6206 struct ixgbe_hw *hw;
6207 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6209 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6214 /* refuse mtu that requires the support of scattered packets when this
6215 * feature has not been enabled before.
6217 if (!dev->data->scattered_rx &&
6218 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6219 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6223 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6224 * request of the version 2.0 of the mailbox API.
6225 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6226 * of the mailbox API.
6227 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6228 * prior to 3.11.33 which contains the following change:
6229 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6231 ixgbevf_rlpml_set_vf(hw, max_frame);
6233 /* update max frame size */
6234 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6238 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6239 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6243 static inline struct ixgbe_5tuple_filter *
6244 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6245 struct ixgbe_5tuple_filter_info *key)
6247 struct ixgbe_5tuple_filter *it;
6249 TAILQ_FOREACH(it, filter_list, entries) {
6250 if (memcmp(key, &it->filter_info,
6251 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6258 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6260 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6261 struct ixgbe_5tuple_filter_info *filter_info)
6263 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6264 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6265 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6268 switch (filter->dst_ip_mask) {
6270 filter_info->dst_ip_mask = 0;
6271 filter_info->dst_ip = filter->dst_ip;
6274 filter_info->dst_ip_mask = 1;
6277 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6281 switch (filter->src_ip_mask) {
6283 filter_info->src_ip_mask = 0;
6284 filter_info->src_ip = filter->src_ip;
6287 filter_info->src_ip_mask = 1;
6290 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6294 switch (filter->dst_port_mask) {
6296 filter_info->dst_port_mask = 0;
6297 filter_info->dst_port = filter->dst_port;
6300 filter_info->dst_port_mask = 1;
6303 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6307 switch (filter->src_port_mask) {
6309 filter_info->src_port_mask = 0;
6310 filter_info->src_port = filter->src_port;
6313 filter_info->src_port_mask = 1;
6316 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6320 switch (filter->proto_mask) {
6322 filter_info->proto_mask = 0;
6323 filter_info->proto =
6324 convert_protocol_type(filter->proto);
6327 filter_info->proto_mask = 1;
6330 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6334 filter_info->priority = (uint8_t)filter->priority;
6339 * add or delete a ntuple filter
6342 * dev: Pointer to struct rte_eth_dev.
6343 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6344 * add: if true, add filter, if false, remove filter
6347 * - On success, zero.
6348 * - On failure, a negative value.
6351 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6352 struct rte_eth_ntuple_filter *ntuple_filter,
6355 struct ixgbe_filter_info *filter_info =
6356 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6357 struct ixgbe_5tuple_filter_info filter_5tuple;
6358 struct ixgbe_5tuple_filter *filter;
6361 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6362 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6366 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6367 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6371 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6373 if (filter != NULL && add) {
6374 PMD_DRV_LOG(ERR, "filter exists.");
6377 if (filter == NULL && !add) {
6378 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6383 filter = rte_zmalloc("ixgbe_5tuple_filter",
6384 sizeof(struct ixgbe_5tuple_filter), 0);
6387 (void)rte_memcpy(&filter->filter_info,
6389 sizeof(struct ixgbe_5tuple_filter_info));
6390 filter->queue = ntuple_filter->queue;
6391 ret = ixgbe_add_5tuple_filter(dev, filter);
6397 ixgbe_remove_5tuple_filter(dev, filter);
6403 * get a ntuple filter
6406 * dev: Pointer to struct rte_eth_dev.
6407 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6410 * - On success, zero.
6411 * - On failure, a negative value.
6414 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6415 struct rte_eth_ntuple_filter *ntuple_filter)
6417 struct ixgbe_filter_info *filter_info =
6418 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6419 struct ixgbe_5tuple_filter_info filter_5tuple;
6420 struct ixgbe_5tuple_filter *filter;
6423 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6424 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6428 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6429 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6433 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6435 if (filter == NULL) {
6436 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6439 ntuple_filter->queue = filter->queue;
6444 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6445 * @dev: pointer to rte_eth_dev structure
6446 * @filter_op:operation will be taken.
6447 * @arg: a pointer to specific structure corresponding to the filter_op
6450 * - On success, zero.
6451 * - On failure, a negative value.
6454 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6455 enum rte_filter_op filter_op,
6458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6461 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6463 if (filter_op == RTE_ETH_FILTER_NOP)
6467 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6472 switch (filter_op) {
6473 case RTE_ETH_FILTER_ADD:
6474 ret = ixgbe_add_del_ntuple_filter(dev,
6475 (struct rte_eth_ntuple_filter *)arg,
6478 case RTE_ETH_FILTER_DELETE:
6479 ret = ixgbe_add_del_ntuple_filter(dev,
6480 (struct rte_eth_ntuple_filter *)arg,
6483 case RTE_ETH_FILTER_GET:
6484 ret = ixgbe_get_ntuple_filter(dev,
6485 (struct rte_eth_ntuple_filter *)arg);
6488 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6496 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6497 struct rte_eth_ethertype_filter *filter,
6500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6501 struct ixgbe_filter_info *filter_info =
6502 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6506 struct ixgbe_ethertype_filter ethertype_filter;
6508 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6511 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6512 filter->ether_type == ETHER_TYPE_IPv6) {
6513 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6514 " ethertype filter.", filter->ether_type);
6518 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6519 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6522 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6523 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6527 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6528 if (ret >= 0 && add) {
6529 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6530 filter->ether_type);
6533 if (ret < 0 && !add) {
6534 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6535 filter->ether_type);
6540 etqf = IXGBE_ETQF_FILTER_EN;
6541 etqf |= (uint32_t)filter->ether_type;
6542 etqs |= (uint32_t)((filter->queue <<
6543 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6544 IXGBE_ETQS_RX_QUEUE);
6545 etqs |= IXGBE_ETQS_QUEUE_EN;
6547 ethertype_filter.ethertype = filter->ether_type;
6548 ethertype_filter.etqf = etqf;
6549 ethertype_filter.etqs = etqs;
6550 ethertype_filter.conf = FALSE;
6551 ret = ixgbe_ethertype_filter_insert(filter_info,
6554 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6558 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6562 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6563 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6564 IXGBE_WRITE_FLUSH(hw);
6570 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6571 struct rte_eth_ethertype_filter *filter)
6573 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6574 struct ixgbe_filter_info *filter_info =
6575 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6576 uint32_t etqf, etqs;
6579 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6581 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6582 filter->ether_type);
6586 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6587 if (etqf & IXGBE_ETQF_FILTER_EN) {
6588 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6589 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6591 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6592 IXGBE_ETQS_RX_QUEUE_SHIFT;
6599 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6600 * @dev: pointer to rte_eth_dev structure
6601 * @filter_op:operation will be taken.
6602 * @arg: a pointer to specific structure corresponding to the filter_op
6605 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6606 enum rte_filter_op filter_op,
6609 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612 MAC_TYPE_FILTER_SUP(hw->mac.type);
6614 if (filter_op == RTE_ETH_FILTER_NOP)
6618 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6623 switch (filter_op) {
6624 case RTE_ETH_FILTER_ADD:
6625 ret = ixgbe_add_del_ethertype_filter(dev,
6626 (struct rte_eth_ethertype_filter *)arg,
6629 case RTE_ETH_FILTER_DELETE:
6630 ret = ixgbe_add_del_ethertype_filter(dev,
6631 (struct rte_eth_ethertype_filter *)arg,
6634 case RTE_ETH_FILTER_GET:
6635 ret = ixgbe_get_ethertype_filter(dev,
6636 (struct rte_eth_ethertype_filter *)arg);
6639 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6647 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6648 enum rte_filter_type filter_type,
6649 enum rte_filter_op filter_op,
6654 switch (filter_type) {
6655 case RTE_ETH_FILTER_NTUPLE:
6656 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6658 case RTE_ETH_FILTER_ETHERTYPE:
6659 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6661 case RTE_ETH_FILTER_SYN:
6662 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6664 case RTE_ETH_FILTER_FDIR:
6665 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6667 case RTE_ETH_FILTER_L2_TUNNEL:
6668 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6670 case RTE_ETH_FILTER_GENERIC:
6671 if (filter_op != RTE_ETH_FILTER_GET)
6673 *(const void **)arg = &ixgbe_flow_ops;
6676 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6686 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6687 u8 **mc_addr_ptr, u32 *vmdq)
6692 mc_addr = *mc_addr_ptr;
6693 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6698 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6699 struct ether_addr *mc_addr_set,
6700 uint32_t nb_mc_addr)
6702 struct ixgbe_hw *hw;
6705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6706 mc_addr_list = (u8 *)mc_addr_set;
6707 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6708 ixgbe_dev_addr_list_itr, TRUE);
6712 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6714 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715 uint64_t systime_cycles;
6717 switch (hw->mac.type) {
6718 case ixgbe_mac_X550:
6719 case ixgbe_mac_X550EM_x:
6720 case ixgbe_mac_X550EM_a:
6721 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6722 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6723 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6727 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6728 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6732 return systime_cycles;
6736 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739 uint64_t rx_tstamp_cycles;
6741 switch (hw->mac.type) {
6742 case ixgbe_mac_X550:
6743 case ixgbe_mac_X550EM_x:
6744 case ixgbe_mac_X550EM_a:
6745 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6746 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6747 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6751 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6752 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6753 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6757 return rx_tstamp_cycles;
6761 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764 uint64_t tx_tstamp_cycles;
6766 switch (hw->mac.type) {
6767 case ixgbe_mac_X550:
6768 case ixgbe_mac_X550EM_x:
6769 case ixgbe_mac_X550EM_a:
6770 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6771 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6772 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6776 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6777 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6778 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6782 return tx_tstamp_cycles;
6786 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6789 struct ixgbe_adapter *adapter =
6790 (struct ixgbe_adapter *)dev->data->dev_private;
6791 struct rte_eth_link link;
6792 uint32_t incval = 0;
6795 /* Get current link speed. */
6796 memset(&link, 0, sizeof(link));
6797 ixgbe_dev_link_update(dev, 1);
6798 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6800 switch (link.link_speed) {
6801 case ETH_SPEED_NUM_100M:
6802 incval = IXGBE_INCVAL_100;
6803 shift = IXGBE_INCVAL_SHIFT_100;
6805 case ETH_SPEED_NUM_1G:
6806 incval = IXGBE_INCVAL_1GB;
6807 shift = IXGBE_INCVAL_SHIFT_1GB;
6809 case ETH_SPEED_NUM_10G:
6811 incval = IXGBE_INCVAL_10GB;
6812 shift = IXGBE_INCVAL_SHIFT_10GB;
6816 switch (hw->mac.type) {
6817 case ixgbe_mac_X550:
6818 case ixgbe_mac_X550EM_x:
6819 case ixgbe_mac_X550EM_a:
6820 /* Independent of link speed. */
6822 /* Cycles read will be interpreted as ns. */
6825 case ixgbe_mac_X540:
6826 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6828 case ixgbe_mac_82599EB:
6829 incval >>= IXGBE_INCVAL_SHIFT_82599;
6830 shift -= IXGBE_INCVAL_SHIFT_82599;
6831 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6832 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6835 /* Not supported. */
6839 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6840 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6841 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6843 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6844 adapter->systime_tc.cc_shift = shift;
6845 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6847 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6848 adapter->rx_tstamp_tc.cc_shift = shift;
6849 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6851 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6852 adapter->tx_tstamp_tc.cc_shift = shift;
6853 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6857 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6859 struct ixgbe_adapter *adapter =
6860 (struct ixgbe_adapter *)dev->data->dev_private;
6862 adapter->systime_tc.nsec += delta;
6863 adapter->rx_tstamp_tc.nsec += delta;
6864 adapter->tx_tstamp_tc.nsec += delta;
6870 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6873 struct ixgbe_adapter *adapter =
6874 (struct ixgbe_adapter *)dev->data->dev_private;
6876 ns = rte_timespec_to_ns(ts);
6877 /* Set the timecounters to a new value. */
6878 adapter->systime_tc.nsec = ns;
6879 adapter->rx_tstamp_tc.nsec = ns;
6880 adapter->tx_tstamp_tc.nsec = ns;
6886 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6888 uint64_t ns, systime_cycles;
6889 struct ixgbe_adapter *adapter =
6890 (struct ixgbe_adapter *)dev->data->dev_private;
6892 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6893 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6894 *ts = rte_ns_to_timespec(ns);
6900 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6906 /* Stop the timesync system time. */
6907 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6908 /* Reset the timesync system time value. */
6909 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6910 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6912 /* Enable system time for platforms where it isn't on by default. */
6913 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6914 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6915 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6917 ixgbe_start_timecounters(dev);
6919 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6920 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6922 IXGBE_ETQF_FILTER_EN |
6925 /* Enable timestamping of received PTP packets. */
6926 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6927 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6928 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6930 /* Enable timestamping of transmitted PTP packets. */
6931 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6932 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6933 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6935 IXGBE_WRITE_FLUSH(hw);
6941 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6943 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6946 /* Disable timestamping of transmitted PTP packets. */
6947 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6948 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6949 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6951 /* Disable timestamping of received PTP packets. */
6952 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6953 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6954 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6956 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6957 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6959 /* Stop incrementating the System Time registers. */
6960 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6966 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6967 struct timespec *timestamp,
6968 uint32_t flags __rte_unused)
6970 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6971 struct ixgbe_adapter *adapter =
6972 (struct ixgbe_adapter *)dev->data->dev_private;
6973 uint32_t tsync_rxctl;
6974 uint64_t rx_tstamp_cycles;
6977 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6978 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6981 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6982 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6983 *timestamp = rte_ns_to_timespec(ns);
6989 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6990 struct timespec *timestamp)
6992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6993 struct ixgbe_adapter *adapter =
6994 (struct ixgbe_adapter *)dev->data->dev_private;
6995 uint32_t tsync_txctl;
6996 uint64_t tx_tstamp_cycles;
6999 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7000 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7003 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7004 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7005 *timestamp = rte_ns_to_timespec(ns);
7011 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7016 const struct reg_info *reg_group;
7017 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7018 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7020 while ((reg_group = reg_set[g_ind++]))
7021 count += ixgbe_regs_group_count(reg_group);
7027 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7031 const struct reg_info *reg_group;
7033 while ((reg_group = ixgbevf_regs[g_ind++]))
7034 count += ixgbe_regs_group_count(reg_group);
7040 ixgbe_get_regs(struct rte_eth_dev *dev,
7041 struct rte_dev_reg_info *regs)
7043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7044 uint32_t *data = regs->data;
7047 const struct reg_info *reg_group;
7048 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7049 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7052 regs->length = ixgbe_get_reg_length(dev);
7053 regs->width = sizeof(uint32_t);
7057 /* Support only full register dump */
7058 if ((regs->length == 0) ||
7059 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7060 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7062 while ((reg_group = reg_set[g_ind++]))
7063 count += ixgbe_read_regs_group(dev, &data[count],
7072 ixgbevf_get_regs(struct rte_eth_dev *dev,
7073 struct rte_dev_reg_info *regs)
7075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076 uint32_t *data = regs->data;
7079 const struct reg_info *reg_group;
7082 regs->length = ixgbevf_get_reg_length(dev);
7083 regs->width = sizeof(uint32_t);
7087 /* Support only full register dump */
7088 if ((regs->length == 0) ||
7089 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7090 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7092 while ((reg_group = ixgbevf_regs[g_ind++]))
7093 count += ixgbe_read_regs_group(dev, &data[count],
7102 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7106 /* Return unit is byte count */
7107 return hw->eeprom.word_size * 2;
7111 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7112 struct rte_dev_eeprom_info *in_eeprom)
7114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7115 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7116 uint16_t *data = in_eeprom->data;
7119 first = in_eeprom->offset >> 1;
7120 length = in_eeprom->length >> 1;
7121 if ((first > hw->eeprom.word_size) ||
7122 ((first + length) > hw->eeprom.word_size))
7125 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7127 return eeprom->ops.read_buffer(hw, first, length, data);
7131 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7132 struct rte_dev_eeprom_info *in_eeprom)
7134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7136 uint16_t *data = in_eeprom->data;
7139 first = in_eeprom->offset >> 1;
7140 length = in_eeprom->length >> 1;
7141 if ((first > hw->eeprom.word_size) ||
7142 ((first + length) > hw->eeprom.word_size))
7145 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7147 return eeprom->ops.write_buffer(hw, first, length, data);
7151 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7153 case ixgbe_mac_X550:
7154 case ixgbe_mac_X550EM_x:
7155 case ixgbe_mac_X550EM_a:
7156 return ETH_RSS_RETA_SIZE_512;
7157 case ixgbe_mac_X550_vf:
7158 case ixgbe_mac_X550EM_x_vf:
7159 case ixgbe_mac_X550EM_a_vf:
7160 return ETH_RSS_RETA_SIZE_64;
7162 return ETH_RSS_RETA_SIZE_128;
7167 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7169 case ixgbe_mac_X550:
7170 case ixgbe_mac_X550EM_x:
7171 case ixgbe_mac_X550EM_a:
7172 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7173 return IXGBE_RETA(reta_idx >> 2);
7175 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7176 case ixgbe_mac_X550_vf:
7177 case ixgbe_mac_X550EM_x_vf:
7178 case ixgbe_mac_X550EM_a_vf:
7179 return IXGBE_VFRETA(reta_idx >> 2);
7181 return IXGBE_RETA(reta_idx >> 2);
7186 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7188 case ixgbe_mac_X550_vf:
7189 case ixgbe_mac_X550EM_x_vf:
7190 case ixgbe_mac_X550EM_a_vf:
7191 return IXGBE_VFMRQC;
7198 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7200 case ixgbe_mac_X550_vf:
7201 case ixgbe_mac_X550EM_x_vf:
7202 case ixgbe_mac_X550EM_a_vf:
7203 return IXGBE_VFRSSRK(i);
7205 return IXGBE_RSSRK(i);
7210 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7212 case ixgbe_mac_82599_vf:
7213 case ixgbe_mac_X540_vf:
7221 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7222 struct rte_eth_dcb_info *dcb_info)
7224 struct ixgbe_dcb_config *dcb_config =
7225 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7226 struct ixgbe_dcb_tc_config *tc;
7229 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7230 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7232 dcb_info->nb_tcs = 1;
7234 if (dcb_config->vt_mode) { /* vt is enabled*/
7235 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7236 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7237 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7238 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7239 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7240 for (j = 0; j < dcb_info->nb_tcs; j++) {
7241 dcb_info->tc_queue.tc_rxq[i][j].base =
7242 i * dcb_info->nb_tcs + j;
7243 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7244 dcb_info->tc_queue.tc_txq[i][j].base =
7245 i * dcb_info->nb_tcs + j;
7246 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7249 } else { /* vt is disabled*/
7250 struct rte_eth_dcb_rx_conf *rx_conf =
7251 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7252 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7253 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7254 if (dcb_info->nb_tcs == ETH_4_TCS) {
7255 for (i = 0; i < dcb_info->nb_tcs; i++) {
7256 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7257 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7259 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7260 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7261 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7262 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7263 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7264 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7265 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7266 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7267 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7268 for (i = 0; i < dcb_info->nb_tcs; i++) {
7269 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7270 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7272 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7273 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7274 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7275 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7276 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7277 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7278 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7279 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7280 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7281 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7282 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7283 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7284 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7285 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7286 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7287 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7290 for (i = 0; i < dcb_info->nb_tcs; i++) {
7291 tc = &dcb_config->tc_config[i];
7292 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7297 /* Update e-tag ether type */
7299 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7300 uint16_t ether_type)
7302 uint32_t etag_etype;
7304 if (hw->mac.type != ixgbe_mac_X550 &&
7305 hw->mac.type != ixgbe_mac_X550EM_x &&
7306 hw->mac.type != ixgbe_mac_X550EM_a) {
7310 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7311 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7312 etag_etype |= ether_type;
7313 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7314 IXGBE_WRITE_FLUSH(hw);
7319 /* Config l2 tunnel ether type */
7321 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7322 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7326 struct ixgbe_l2_tn_info *l2_tn_info =
7327 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7329 if (l2_tunnel == NULL)
7332 switch (l2_tunnel->l2_tunnel_type) {
7333 case RTE_L2_TUNNEL_TYPE_E_TAG:
7334 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7335 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7338 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7346 /* Enable e-tag tunnel */
7348 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7350 uint32_t etag_etype;
7352 if (hw->mac.type != ixgbe_mac_X550 &&
7353 hw->mac.type != ixgbe_mac_X550EM_x &&
7354 hw->mac.type != ixgbe_mac_X550EM_a) {
7358 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7359 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7360 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7361 IXGBE_WRITE_FLUSH(hw);
7366 /* Enable l2 tunnel */
7368 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7369 enum rte_eth_tunnel_type l2_tunnel_type)
7372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373 struct ixgbe_l2_tn_info *l2_tn_info =
7374 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7376 switch (l2_tunnel_type) {
7377 case RTE_L2_TUNNEL_TYPE_E_TAG:
7378 l2_tn_info->e_tag_en = TRUE;
7379 ret = ixgbe_e_tag_enable(hw);
7382 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7390 /* Disable e-tag tunnel */
7392 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7394 uint32_t etag_etype;
7396 if (hw->mac.type != ixgbe_mac_X550 &&
7397 hw->mac.type != ixgbe_mac_X550EM_x &&
7398 hw->mac.type != ixgbe_mac_X550EM_a) {
7402 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7403 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7404 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7405 IXGBE_WRITE_FLUSH(hw);
7410 /* Disable l2 tunnel */
7412 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7413 enum rte_eth_tunnel_type l2_tunnel_type)
7416 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7417 struct ixgbe_l2_tn_info *l2_tn_info =
7418 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7420 switch (l2_tunnel_type) {
7421 case RTE_L2_TUNNEL_TYPE_E_TAG:
7422 l2_tn_info->e_tag_en = FALSE;
7423 ret = ixgbe_e_tag_disable(hw);
7426 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7435 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7436 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440 uint32_t i, rar_entries;
7441 uint32_t rar_low, rar_high;
7443 if (hw->mac.type != ixgbe_mac_X550 &&
7444 hw->mac.type != ixgbe_mac_X550EM_x &&
7445 hw->mac.type != ixgbe_mac_X550EM_a) {
7449 rar_entries = ixgbe_get_num_rx_addrs(hw);
7451 for (i = 1; i < rar_entries; i++) {
7452 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7453 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7454 if ((rar_high & IXGBE_RAH_AV) &&
7455 (rar_high & IXGBE_RAH_ADTYPE) &&
7456 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7457 l2_tunnel->tunnel_id)) {
7458 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7459 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7461 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7471 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7472 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7476 uint32_t i, rar_entries;
7477 uint32_t rar_low, rar_high;
7479 if (hw->mac.type != ixgbe_mac_X550 &&
7480 hw->mac.type != ixgbe_mac_X550EM_x &&
7481 hw->mac.type != ixgbe_mac_X550EM_a) {
7485 /* One entry for one tunnel. Try to remove potential existing entry. */
7486 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7488 rar_entries = ixgbe_get_num_rx_addrs(hw);
7490 for (i = 1; i < rar_entries; i++) {
7491 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7492 if (rar_high & IXGBE_RAH_AV) {
7495 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7496 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7497 rar_low = l2_tunnel->tunnel_id;
7499 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7500 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7506 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7507 " Please remove a rule before adding a new one.");
7511 static inline struct ixgbe_l2_tn_filter *
7512 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7513 struct ixgbe_l2_tn_key *key)
7517 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7521 return l2_tn_info->hash_map[ret];
7525 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7526 struct ixgbe_l2_tn_filter *l2_tn_filter)
7530 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7531 &l2_tn_filter->key);
7535 "Failed to insert L2 tunnel filter"
7536 " to hash table %d!",
7541 l2_tn_info->hash_map[ret] = l2_tn_filter;
7543 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7549 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7550 struct ixgbe_l2_tn_key *key)
7553 struct ixgbe_l2_tn_filter *l2_tn_filter;
7555 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7559 "No such L2 tunnel filter to delete %d!",
7564 l2_tn_filter = l2_tn_info->hash_map[ret];
7565 l2_tn_info->hash_map[ret] = NULL;
7567 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7568 rte_free(l2_tn_filter);
7573 /* Add l2 tunnel filter */
7575 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7576 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7580 struct ixgbe_l2_tn_info *l2_tn_info =
7581 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7582 struct ixgbe_l2_tn_key key;
7583 struct ixgbe_l2_tn_filter *node;
7586 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7587 key.tn_id = l2_tunnel->tunnel_id;
7589 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7593 "The L2 tunnel filter already exists!");
7597 node = rte_zmalloc("ixgbe_l2_tn",
7598 sizeof(struct ixgbe_l2_tn_filter),
7603 (void)rte_memcpy(&node->key,
7605 sizeof(struct ixgbe_l2_tn_key));
7606 node->pool = l2_tunnel->pool;
7607 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7614 switch (l2_tunnel->l2_tunnel_type) {
7615 case RTE_L2_TUNNEL_TYPE_E_TAG:
7616 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7619 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7624 if ((!restore) && (ret < 0))
7625 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7630 /* Delete l2 tunnel filter */
7632 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7633 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7636 struct ixgbe_l2_tn_info *l2_tn_info =
7637 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7638 struct ixgbe_l2_tn_key key;
7640 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7641 key.tn_id = l2_tunnel->tunnel_id;
7642 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7646 switch (l2_tunnel->l2_tunnel_type) {
7647 case RTE_L2_TUNNEL_TYPE_E_TAG:
7648 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7651 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7660 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7661 * @dev: pointer to rte_eth_dev structure
7662 * @filter_op:operation will be taken.
7663 * @arg: a pointer to specific structure corresponding to the filter_op
7666 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7667 enum rte_filter_op filter_op,
7672 if (filter_op == RTE_ETH_FILTER_NOP)
7676 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7681 switch (filter_op) {
7682 case RTE_ETH_FILTER_ADD:
7683 ret = ixgbe_dev_l2_tunnel_filter_add
7685 (struct rte_eth_l2_tunnel_conf *)arg,
7688 case RTE_ETH_FILTER_DELETE:
7689 ret = ixgbe_dev_l2_tunnel_filter_del
7691 (struct rte_eth_l2_tunnel_conf *)arg);
7694 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7702 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7706 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7708 if (hw->mac.type != ixgbe_mac_X550 &&
7709 hw->mac.type != ixgbe_mac_X550EM_x &&
7710 hw->mac.type != ixgbe_mac_X550EM_a) {
7714 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7715 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7717 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7718 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7723 /* Enable l2 tunnel forwarding */
7725 ixgbe_dev_l2_tunnel_forwarding_enable
7726 (struct rte_eth_dev *dev,
7727 enum rte_eth_tunnel_type l2_tunnel_type)
7729 struct ixgbe_l2_tn_info *l2_tn_info =
7730 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7733 switch (l2_tunnel_type) {
7734 case RTE_L2_TUNNEL_TYPE_E_TAG:
7735 l2_tn_info->e_tag_fwd_en = TRUE;
7736 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7739 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7747 /* Disable l2 tunnel forwarding */
7749 ixgbe_dev_l2_tunnel_forwarding_disable
7750 (struct rte_eth_dev *dev,
7751 enum rte_eth_tunnel_type l2_tunnel_type)
7753 struct ixgbe_l2_tn_info *l2_tn_info =
7754 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7757 switch (l2_tunnel_type) {
7758 case RTE_L2_TUNNEL_TYPE_E_TAG:
7759 l2_tn_info->e_tag_fwd_en = FALSE;
7760 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7763 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7772 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7773 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7776 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7778 uint32_t vmtir, vmvir;
7779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7781 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7783 "VF id %u should be less than %u",
7789 if (hw->mac.type != ixgbe_mac_X550 &&
7790 hw->mac.type != ixgbe_mac_X550EM_x &&
7791 hw->mac.type != ixgbe_mac_X550EM_a) {
7796 vmtir = l2_tunnel->tunnel_id;
7800 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7802 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7803 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7805 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7806 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7811 /* Enable l2 tunnel tag insertion */
7813 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7814 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7818 switch (l2_tunnel->l2_tunnel_type) {
7819 case RTE_L2_TUNNEL_TYPE_E_TAG:
7820 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7823 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7831 /* Disable l2 tunnel tag insertion */
7833 ixgbe_dev_l2_tunnel_insertion_disable
7834 (struct rte_eth_dev *dev,
7835 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7839 switch (l2_tunnel->l2_tunnel_type) {
7840 case RTE_L2_TUNNEL_TYPE_E_TAG:
7841 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7844 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7853 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7860 if (hw->mac.type != ixgbe_mac_X550 &&
7861 hw->mac.type != ixgbe_mac_X550EM_x &&
7862 hw->mac.type != ixgbe_mac_X550EM_a) {
7866 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7868 qde |= IXGBE_QDE_STRIP_TAG;
7870 qde &= ~IXGBE_QDE_STRIP_TAG;
7871 qde &= ~IXGBE_QDE_READ;
7872 qde |= IXGBE_QDE_WRITE;
7873 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7878 /* Enable l2 tunnel tag stripping */
7880 ixgbe_dev_l2_tunnel_stripping_enable
7881 (struct rte_eth_dev *dev,
7882 enum rte_eth_tunnel_type l2_tunnel_type)
7886 switch (l2_tunnel_type) {
7887 case RTE_L2_TUNNEL_TYPE_E_TAG:
7888 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7891 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7899 /* Disable l2 tunnel tag stripping */
7901 ixgbe_dev_l2_tunnel_stripping_disable
7902 (struct rte_eth_dev *dev,
7903 enum rte_eth_tunnel_type l2_tunnel_type)
7907 switch (l2_tunnel_type) {
7908 case RTE_L2_TUNNEL_TYPE_E_TAG:
7909 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7912 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7920 /* Enable/disable l2 tunnel offload functions */
7922 ixgbe_dev_l2_tunnel_offload_set
7923 (struct rte_eth_dev *dev,
7924 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7930 if (l2_tunnel == NULL)
7934 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7936 ret = ixgbe_dev_l2_tunnel_enable(
7938 l2_tunnel->l2_tunnel_type);
7940 ret = ixgbe_dev_l2_tunnel_disable(
7942 l2_tunnel->l2_tunnel_type);
7945 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7947 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7951 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7956 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7958 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7960 l2_tunnel->l2_tunnel_type);
7962 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7964 l2_tunnel->l2_tunnel_type);
7967 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7969 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7971 l2_tunnel->l2_tunnel_type);
7973 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7975 l2_tunnel->l2_tunnel_type);
7982 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7985 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7986 IXGBE_WRITE_FLUSH(hw);
7991 /* There's only one register for VxLAN UDP port.
7992 * So, we cannot add several ports. Will update it.
7995 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7999 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8003 return ixgbe_update_vxlan_port(hw, port);
8006 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8007 * UDP port, it must have a value.
8008 * So, will reset it to the original value 0.
8011 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8016 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8018 if (cur_port != port) {
8019 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8023 return ixgbe_update_vxlan_port(hw, 0);
8026 /* Add UDP tunneling port */
8028 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8029 struct rte_eth_udp_tunnel *udp_tunnel)
8032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8034 if (hw->mac.type != ixgbe_mac_X550 &&
8035 hw->mac.type != ixgbe_mac_X550EM_x &&
8036 hw->mac.type != ixgbe_mac_X550EM_a) {
8040 if (udp_tunnel == NULL)
8043 switch (udp_tunnel->prot_type) {
8044 case RTE_TUNNEL_TYPE_VXLAN:
8045 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8048 case RTE_TUNNEL_TYPE_GENEVE:
8049 case RTE_TUNNEL_TYPE_TEREDO:
8050 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8055 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8063 /* Remove UDP tunneling port */
8065 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8066 struct rte_eth_udp_tunnel *udp_tunnel)
8069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8071 if (hw->mac.type != ixgbe_mac_X550 &&
8072 hw->mac.type != ixgbe_mac_X550EM_x &&
8073 hw->mac.type != ixgbe_mac_X550EM_a) {
8077 if (udp_tunnel == NULL)
8080 switch (udp_tunnel->prot_type) {
8081 case RTE_TUNNEL_TYPE_VXLAN:
8082 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8084 case RTE_TUNNEL_TYPE_GENEVE:
8085 case RTE_TUNNEL_TYPE_TEREDO:
8086 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8090 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8099 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8103 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8107 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8109 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8111 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8114 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8122 /* PF reset VF event */
8123 if (in_msg == IXGBE_PF_CONTROL_MSG)
8124 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8128 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132 struct ixgbe_interrupt *intr =
8133 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8134 ixgbevf_intr_disable(hw);
8136 /* read-on-clear nic registers here */
8137 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8140 /* only one misc vector supported - mailbox */
8141 eicr &= IXGBE_VTEICR_MASK;
8142 if (eicr == IXGBE_MISC_VEC_ID)
8143 intr->flags |= IXGBE_FLAG_MAILBOX;
8149 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8151 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8152 struct ixgbe_interrupt *intr =
8153 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8155 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8156 ixgbevf_mbx_process(dev);
8157 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8160 ixgbevf_intr_enable(hw);
8166 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8169 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8171 ixgbevf_dev_interrupt_get_status(dev);
8172 ixgbevf_dev_interrupt_action(dev);
8176 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8177 * @hw: pointer to hardware structure
8179 * Stops the transmit data path and waits for the HW to internally empty
8180 * the Tx security block
8182 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8184 #define IXGBE_MAX_SECTX_POLL 40
8189 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8190 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8191 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8192 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8193 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8194 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8196 /* Use interrupt-safe sleep just in case */
8200 /* For informational purposes only */
8201 if (i >= IXGBE_MAX_SECTX_POLL)
8202 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8203 "path fully disabled. Continuing with init.");
8205 return IXGBE_SUCCESS;
8209 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8210 * @hw: pointer to hardware structure
8212 * Enables the transmit data path.
8214 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8218 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8219 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8220 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8221 IXGBE_WRITE_FLUSH(hw);
8223 return IXGBE_SUCCESS;
8227 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8229 struct ixgbe_hw *hw;
8230 struct rte_eth_dev *dev;
8233 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8235 dev = &rte_eth_devices[port];
8237 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8240 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8242 /* Stop the data paths */
8243 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8247 * As no ixgbe_disable_sec_rx_path equivalent is
8248 * implemented for tx in the base code, and we are
8249 * not allowed to modify the base code in DPDK, so
8250 * just call the hand-written one directly for now.
8251 * The hardware support has been checked by
8252 * ixgbe_disable_sec_rx_path().
8254 ixgbe_disable_sec_tx_path_generic(hw);
8256 /* Enable Ethernet CRC (required by MACsec offload) */
8257 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8258 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8259 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8261 /* Enable the TX and RX crypto engines */
8262 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8263 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8264 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8266 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8267 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8268 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8270 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8271 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8273 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8275 /* Enable SA lookup */
8276 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8277 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8278 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8279 IXGBE_LSECTXCTRL_AUTH;
8280 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8281 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8282 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8283 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8285 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8286 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8287 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8288 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8290 ctrl |= IXGBE_LSECRXCTRL_RP;
8292 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8293 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8295 /* Start the data paths */
8296 ixgbe_enable_sec_rx_path(hw);
8299 * As no ixgbe_enable_sec_rx_path equivalent is
8300 * implemented for tx in the base code, and we are
8301 * not allowed to modify the base code in DPDK, so
8302 * just call the hand-written one directly for now.
8304 ixgbe_enable_sec_tx_path_generic(hw);
8310 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8312 struct ixgbe_hw *hw;
8313 struct rte_eth_dev *dev;
8316 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8318 dev = &rte_eth_devices[port];
8320 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8323 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8325 /* Stop the data paths */
8326 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8330 * As no ixgbe_disable_sec_rx_path equivalent is
8331 * implemented for tx in the base code, and we are
8332 * not allowed to modify the base code in DPDK, so
8333 * just call the hand-written one directly for now.
8334 * The hardware support has been checked by
8335 * ixgbe_disable_sec_rx_path().
8337 ixgbe_disable_sec_tx_path_generic(hw);
8339 /* Disable the TX and RX crypto engines */
8340 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8341 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8342 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8344 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8345 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8346 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8348 /* Disable SA lookup */
8349 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8350 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8351 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8352 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8354 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8355 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8356 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8357 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8359 /* Start the data paths */
8360 ixgbe_enable_sec_rx_path(hw);
8363 * As no ixgbe_enable_sec_rx_path equivalent is
8364 * implemented for tx in the base code, and we are
8365 * not allowed to modify the base code in DPDK, so
8366 * just call the hand-written one directly for now.
8368 ixgbe_enable_sec_tx_path_generic(hw);
8374 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8376 struct ixgbe_hw *hw;
8377 struct rte_eth_dev *dev;
8380 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8382 dev = &rte_eth_devices[port];
8384 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8387 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8389 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8390 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8392 ctrl = mac[4] | (mac[5] << 8);
8393 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8399 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8401 struct ixgbe_hw *hw;
8402 struct rte_eth_dev *dev;
8405 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8407 dev = &rte_eth_devices[port];
8409 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8412 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8414 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8415 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8417 pi = rte_cpu_to_be_16(pi);
8418 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8419 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8425 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8426 uint32_t pn, uint8_t *key)
8428 struct ixgbe_hw *hw;
8429 struct rte_eth_dev *dev;
8432 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8434 dev = &rte_eth_devices[port];
8436 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8441 if (idx != 0 && idx != 1)
8447 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8449 /* Set the PN and key */
8450 pn = rte_cpu_to_be_32(pn);
8452 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8454 for (i = 0; i < 4; i++) {
8455 ctrl = (key[i * 4 + 0] << 0) |
8456 (key[i * 4 + 1] << 8) |
8457 (key[i * 4 + 2] << 16) |
8458 (key[i * 4 + 3] << 24);
8459 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8462 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8464 for (i = 0; i < 4; i++) {
8465 ctrl = (key[i * 4 + 0] << 0) |
8466 (key[i * 4 + 1] << 8) |
8467 (key[i * 4 + 2] << 16) |
8468 (key[i * 4 + 3] << 24);
8469 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8473 /* Set AN and select the SA */
8474 ctrl = (an << idx * 2) | (idx << 4);
8475 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8481 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8482 uint32_t pn, uint8_t *key)
8484 struct ixgbe_hw *hw;
8485 struct rte_eth_dev *dev;
8488 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8490 dev = &rte_eth_devices[port];
8492 if (!is_device_supported(dev, &rte_ixgbe_pmd))
8495 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8497 if (idx != 0 && idx != 1)
8504 pn = rte_cpu_to_be_32(pn);
8505 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8508 for (i = 0; i < 4; i++) {
8509 ctrl = (key[i * 4 + 0] << 0) |
8510 (key[i * 4 + 1] << 8) |
8511 (key[i * 4 + 2] << 16) |
8512 (key[i * 4 + 3] << 24);
8513 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8516 /* Set the AN and validate the SA */
8517 ctrl = an | (1 << 2);
8518 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8523 /* restore n-tuple filter */
8525 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8527 struct ixgbe_filter_info *filter_info =
8528 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8529 struct ixgbe_5tuple_filter *node;
8531 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8532 ixgbe_inject_5tuple_filter(dev, node);
8536 /* restore ethernet type filter */
8538 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8540 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8541 struct ixgbe_filter_info *filter_info =
8542 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8545 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8546 if (filter_info->ethertype_mask & (1 << i)) {
8547 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8548 filter_info->ethertype_filters[i].etqf);
8549 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8550 filter_info->ethertype_filters[i].etqs);
8551 IXGBE_WRITE_FLUSH(hw);
8556 /* restore SYN filter */
8558 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8560 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8561 struct ixgbe_filter_info *filter_info =
8562 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8565 synqf = filter_info->syn_info;
8567 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8568 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8569 IXGBE_WRITE_FLUSH(hw);
8573 /* restore L2 tunnel filter */
8575 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8577 struct ixgbe_l2_tn_info *l2_tn_info =
8578 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8579 struct ixgbe_l2_tn_filter *node;
8580 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8582 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8583 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8584 l2_tn_conf.tunnel_id = node->key.tn_id;
8585 l2_tn_conf.pool = node->pool;
8586 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8591 ixgbe_filter_restore(struct rte_eth_dev *dev)
8593 ixgbe_ntuple_filter_restore(dev);
8594 ixgbe_ethertype_filter_restore(dev);
8595 ixgbe_syn_filter_restore(dev);
8596 ixgbe_fdir_filter_restore(dev);
8597 ixgbe_l2_tn_filter_restore(dev);
8603 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8605 struct ixgbe_l2_tn_info *l2_tn_info =
8606 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8609 if (l2_tn_info->e_tag_en)
8610 (void)ixgbe_e_tag_enable(hw);
8612 if (l2_tn_info->e_tag_fwd_en)
8613 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8615 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8618 /* remove all the n-tuple filters */
8620 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8622 struct ixgbe_filter_info *filter_info =
8623 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8624 struct ixgbe_5tuple_filter *p_5tuple;
8626 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8627 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8630 /* remove all the ether type filters */
8632 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8635 struct ixgbe_filter_info *filter_info =
8636 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8639 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8640 if (filter_info->ethertype_mask & (1 << i) &&
8641 !filter_info->ethertype_filters[i].conf) {
8642 (void)ixgbe_ethertype_filter_remove(filter_info,
8644 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8645 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8646 IXGBE_WRITE_FLUSH(hw);
8651 /* remove the SYN filter */
8653 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8655 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8656 struct ixgbe_filter_info *filter_info =
8657 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8659 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8660 filter_info->syn_info = 0;
8662 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8663 IXGBE_WRITE_FLUSH(hw);
8667 /* remove all the L2 tunnel filters */
8669 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8671 struct ixgbe_l2_tn_info *l2_tn_info =
8672 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8673 struct ixgbe_l2_tn_filter *l2_tn_filter;
8674 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8677 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8678 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8679 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8680 l2_tn_conf.pool = l2_tn_filter->pool;
8681 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8689 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8690 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8691 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8692 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8693 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8694 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");