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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
96 * Default values for RX/TX configuration
98 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
99 #define IXGBE_DEFAULT_RX_PTHRESH 8
100 #define IXGBE_DEFAULT_RX_HTHRESH 8
101 #define IXGBE_DEFAULT_RX_WTHRESH 0
103 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
104 #define IXGBE_DEFAULT_TX_PTHRESH 32
105 #define IXGBE_DEFAULT_TX_HTHRESH 0
106 #define IXGBE_DEFAULT_TX_WTHRESH 0
107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
109 /* Bit shift and mask */
110 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
111 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
112 #define IXGBE_8_BIT_WIDTH CHAR_BIT
113 #define IXGBE_8_BIT_MASK UINT8_MAX
115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
119 #define IXGBE_HKEY_MAX_INDEX 10
121 /* Additional timesync values. */
122 #define IXGBE_TIMINCA_16NS_SHIFT 24
123 #define IXGBE_TIMINCA_INCVALUE 16000000
124 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
125 | IXGBE_TIMINCA_INCVALUE)
127 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
128 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
129 static int ixgbe_dev_start(struct rte_eth_dev *dev);
130 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
131 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
132 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
133 static void ixgbe_dev_close(struct rte_eth_dev *dev);
134 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
135 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
136 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
137 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
138 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
139 int wait_to_complete);
140 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
141 struct rte_eth_stats *stats);
142 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
143 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
147 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
148 struct rte_eth_dev_info *dev_info);
149 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
150 struct rte_eth_dev_info *dev_info);
151 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
153 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
154 uint16_t vlan_id, int on);
155 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
156 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
157 uint16_t queue, bool on);
158 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
160 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
161 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
162 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
163 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
164 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
166 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
167 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
168 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
169 struct rte_eth_fc_conf *fc_conf);
170 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
171 struct rte_eth_fc_conf *fc_conf);
172 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
173 struct rte_eth_pfc_conf *pfc_conf);
174 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
175 struct rte_eth_rss_reta_entry64 *reta_conf,
177 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
178 struct rte_eth_rss_reta_entry64 *reta_conf,
180 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
181 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
182 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
183 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
184 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
186 static void ixgbe_dev_interrupt_delayed_handler(void *param);
187 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
188 uint32_t index, uint32_t pool);
189 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
190 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
191 struct ether_addr *mac_addr);
192 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
194 /* For Virtual Function support */
195 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
196 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
197 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
198 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
199 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
200 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
201 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
202 struct rte_eth_stats *stats);
203 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
204 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
205 uint16_t vlan_id, int on);
206 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
207 uint16_t queue, int on);
208 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
209 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
211 /* For Eth VMDQ APIs support */
212 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
213 ether_addr* mac_addr,uint8_t on);
214 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
215 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
216 uint16_t rx_mask, uint8_t on);
217 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
218 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
219 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
220 uint64_t pool_mask,uint8_t vlan_on);
221 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
222 struct rte_eth_mirror_conf *mirror_conf,
223 uint8_t rule_id, uint8_t on);
224 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
227 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
228 uint16_t queue_idx, uint16_t tx_rate);
229 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
230 uint16_t tx_rate, uint64_t q_msk);
232 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
233 struct ether_addr *mac_addr,
234 uint32_t index, uint32_t pool);
235 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
236 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
237 struct ether_addr *mac_addr);
238 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
239 struct rte_eth_syn_filter *filter,
241 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
242 struct rte_eth_syn_filter *filter);
243 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
244 enum rte_filter_op filter_op,
246 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
247 struct ixgbe_5tuple_filter *filter);
248 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
249 struct ixgbe_5tuple_filter *filter);
250 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
251 struct rte_eth_ntuple_filter *filter,
253 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
254 enum rte_filter_op filter_op,
256 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
257 struct rte_eth_ntuple_filter *filter);
258 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
259 struct rte_eth_ethertype_filter *filter,
261 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
262 enum rte_filter_op filter_op,
264 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
265 struct rte_eth_ethertype_filter *filter);
266 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
267 enum rte_filter_type filter_type,
268 enum rte_filter_op filter_op,
270 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
272 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
273 struct ether_addr *mc_addr_set,
274 uint32_t nb_mc_addr);
276 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
277 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
278 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
279 struct timespec *timestamp,
281 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
282 struct timespec *timestamp);
285 * Define VF Stats MACRO for Non "cleared on read" register
287 #define UPDATE_VF_STAT(reg, last, cur) \
289 u32 latest = IXGBE_READ_REG(hw, reg); \
290 cur += latest - last; \
294 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
296 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
297 u64 new_msb = IXGBE_READ_REG(hw, msb); \
298 u64 latest = ((new_msb << 32) | new_lsb); \
299 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
303 #define IXGBE_SET_HWSTRIP(h, q) do{\
304 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
305 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
306 (h)->bitmap[idx] |= 1 << bit;\
309 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
310 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
311 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
312 (h)->bitmap[idx] &= ~(1 << bit);\
315 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
316 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
317 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
318 (r) = (h)->bitmap[idx] >> bit & 1;\
322 * The set of PCI devices this driver supports
324 static const struct rte_pci_id pci_id_ixgbe_map[] = {
326 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
327 #include "rte_pci_dev_ids.h"
329 { .vendor_id = 0, /* sentinel */ },
334 * The set of PCI devices this driver supports (for 82599 VF)
336 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
338 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
339 #include "rte_pci_dev_ids.h"
340 { .vendor_id = 0, /* sentinel */ },
344 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
345 .dev_configure = ixgbe_dev_configure,
346 .dev_start = ixgbe_dev_start,
347 .dev_stop = ixgbe_dev_stop,
348 .dev_set_link_up = ixgbe_dev_set_link_up,
349 .dev_set_link_down = ixgbe_dev_set_link_down,
350 .dev_close = ixgbe_dev_close,
351 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
352 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
353 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
354 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
355 .link_update = ixgbe_dev_link_update,
356 .stats_get = ixgbe_dev_stats_get,
357 .stats_reset = ixgbe_dev_stats_reset,
358 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
359 .dev_infos_get = ixgbe_dev_info_get,
360 .mtu_set = ixgbe_dev_mtu_set,
361 .vlan_filter_set = ixgbe_vlan_filter_set,
362 .vlan_tpid_set = ixgbe_vlan_tpid_set,
363 .vlan_offload_set = ixgbe_vlan_offload_set,
364 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
365 .rx_queue_start = ixgbe_dev_rx_queue_start,
366 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
367 .tx_queue_start = ixgbe_dev_tx_queue_start,
368 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
369 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
370 .rx_queue_release = ixgbe_dev_rx_queue_release,
371 .rx_queue_count = ixgbe_dev_rx_queue_count,
372 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
373 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
374 .tx_queue_release = ixgbe_dev_tx_queue_release,
375 .dev_led_on = ixgbe_dev_led_on,
376 .dev_led_off = ixgbe_dev_led_off,
377 .flow_ctrl_get = ixgbe_flow_ctrl_get,
378 .flow_ctrl_set = ixgbe_flow_ctrl_set,
379 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
380 .mac_addr_add = ixgbe_add_rar,
381 .mac_addr_remove = ixgbe_remove_rar,
382 .mac_addr_set = ixgbe_set_default_mac_addr,
383 .uc_hash_table_set = ixgbe_uc_hash_table_set,
384 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
385 .mirror_rule_set = ixgbe_mirror_rule_set,
386 .mirror_rule_reset = ixgbe_mirror_rule_reset,
387 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
388 .set_vf_rx = ixgbe_set_pool_rx,
389 .set_vf_tx = ixgbe_set_pool_tx,
390 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
391 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
392 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
393 .reta_update = ixgbe_dev_rss_reta_update,
394 .reta_query = ixgbe_dev_rss_reta_query,
395 #ifdef RTE_NIC_BYPASS
396 .bypass_init = ixgbe_bypass_init,
397 .bypass_state_set = ixgbe_bypass_state_store,
398 .bypass_state_show = ixgbe_bypass_state_show,
399 .bypass_event_set = ixgbe_bypass_event_store,
400 .bypass_event_show = ixgbe_bypass_event_show,
401 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
402 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
403 .bypass_ver_show = ixgbe_bypass_ver_show,
404 .bypass_wd_reset = ixgbe_bypass_wd_reset,
405 #endif /* RTE_NIC_BYPASS */
406 .rss_hash_update = ixgbe_dev_rss_hash_update,
407 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
408 .filter_ctrl = ixgbe_dev_filter_ctrl,
409 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
410 .timesync_enable = ixgbe_timesync_enable,
411 .timesync_disable = ixgbe_timesync_disable,
412 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
413 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
417 * dev_ops for virtual function, bare necessities for basic vf
418 * operation have been implemented
420 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
421 .dev_configure = ixgbevf_dev_configure,
422 .dev_start = ixgbevf_dev_start,
423 .dev_stop = ixgbevf_dev_stop,
424 .link_update = ixgbe_dev_link_update,
425 .stats_get = ixgbevf_dev_stats_get,
426 .stats_reset = ixgbevf_dev_stats_reset,
427 .dev_close = ixgbevf_dev_close,
428 .dev_infos_get = ixgbevf_dev_info_get,
429 .mtu_set = ixgbevf_dev_set_mtu,
430 .vlan_filter_set = ixgbevf_vlan_filter_set,
431 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
432 .vlan_offload_set = ixgbevf_vlan_offload_set,
433 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
434 .rx_queue_release = ixgbe_dev_rx_queue_release,
435 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
436 .tx_queue_release = ixgbe_dev_tx_queue_release,
437 .mac_addr_add = ixgbevf_add_mac_addr,
438 .mac_addr_remove = ixgbevf_remove_mac_addr,
439 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
440 .mac_addr_set = ixgbevf_set_default_mac_addr,
444 * Atomically reads the link status information from global
445 * structure rte_eth_dev.
448 * - Pointer to the structure rte_eth_dev to read from.
449 * - Pointer to the buffer to be saved with the link status.
452 * - On success, zero.
453 * - On failure, negative value.
456 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
457 struct rte_eth_link *link)
459 struct rte_eth_link *dst = link;
460 struct rte_eth_link *src = &(dev->data->dev_link);
462 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
463 *(uint64_t *)src) == 0)
470 * Atomically writes the link status information into global
471 * structure rte_eth_dev.
474 * - Pointer to the structure rte_eth_dev to read from.
475 * - Pointer to the buffer to be saved with the link status.
478 * - On success, zero.
479 * - On failure, negative value.
482 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
483 struct rte_eth_link *link)
485 struct rte_eth_link *dst = &(dev->data->dev_link);
486 struct rte_eth_link *src = link;
488 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
489 *(uint64_t *)src) == 0)
496 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
499 ixgbe_is_sfp(struct ixgbe_hw *hw)
501 switch (hw->phy.type) {
502 case ixgbe_phy_sfp_avago:
503 case ixgbe_phy_sfp_ftl:
504 case ixgbe_phy_sfp_intel:
505 case ixgbe_phy_sfp_unknown:
506 case ixgbe_phy_sfp_passive_tyco:
507 case ixgbe_phy_sfp_passive_unknown:
514 static inline int32_t
515 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
520 status = ixgbe_reset_hw(hw);
522 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
523 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
524 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
525 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
526 IXGBE_WRITE_FLUSH(hw);
532 ixgbe_enable_intr(struct rte_eth_dev *dev)
534 struct ixgbe_interrupt *intr =
535 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
536 struct ixgbe_hw *hw =
537 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
539 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
540 IXGBE_WRITE_FLUSH(hw);
544 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
547 ixgbe_disable_intr(struct ixgbe_hw *hw)
549 PMD_INIT_FUNC_TRACE();
551 if (hw->mac.type == ixgbe_mac_82598EB) {
552 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
554 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
555 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
556 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
558 IXGBE_WRITE_FLUSH(hw);
562 * This function resets queue statistics mapping registers.
563 * From Niantic datasheet, Initialization of Statistics section:
564 * "...if software requires the queue counters, the RQSMR and TQSM registers
565 * must be re-programmed following a device reset.
568 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
572 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
573 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
574 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
580 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
585 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
586 #define NB_QMAP_FIELDS_PER_QSM_REG 4
587 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
590 struct ixgbe_stat_mapping_registers *stat_mappings =
591 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
592 uint32_t qsmr_mask = 0;
593 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
597 if ((hw->mac.type != ixgbe_mac_82599EB) &&
598 (hw->mac.type != ixgbe_mac_X540) &&
599 (hw->mac.type != ixgbe_mac_X550) &&
600 (hw->mac.type != ixgbe_mac_X550EM_x))
603 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
604 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
607 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
608 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
609 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
612 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
614 /* Now clear any previous stat_idx set */
615 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
617 stat_mappings->tqsm[n] &= ~clearing_mask;
619 stat_mappings->rqsmr[n] &= ~clearing_mask;
621 q_map = (uint32_t)stat_idx;
622 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
623 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
625 stat_mappings->tqsm[n] |= qsmr_mask;
627 stat_mappings->rqsmr[n] |= qsmr_mask;
629 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
630 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
632 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
633 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
635 /* Now write the mapping in the appropriate register */
637 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
638 stat_mappings->rqsmr[n], n);
639 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
642 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
643 stat_mappings->tqsm[n], n);
644 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
650 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
652 struct ixgbe_stat_mapping_registers *stat_mappings =
653 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
657 /* write whatever was in stat mapping table to the NIC */
658 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
660 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
663 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
668 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
671 struct ixgbe_dcb_tc_config *tc;
672 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
674 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
675 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
676 for (i = 0; i < dcb_max_tc; i++) {
677 tc = &dcb_config->tc_config[i];
678 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
679 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
680 (uint8_t)(100/dcb_max_tc + (i & 1));
681 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
682 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
683 (uint8_t)(100/dcb_max_tc + (i & 1));
684 tc->pfc = ixgbe_dcb_pfc_disabled;
687 /* Initialize default user to priority mapping, UPx->TC0 */
688 tc = &dcb_config->tc_config[0];
689 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
690 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
691 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
692 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
693 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
695 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
696 dcb_config->pfc_mode_enable = false;
697 dcb_config->vt_mode = true;
698 dcb_config->round_robin_enable = false;
699 /* support all DCB capabilities in 82599 */
700 dcb_config->support.capabilities = 0xFF;
702 /*we only support 4 Tcs for X540, X550 */
703 if (hw->mac.type == ixgbe_mac_X540 ||
704 hw->mac.type == ixgbe_mac_X550 ||
705 hw->mac.type == ixgbe_mac_X550EM_x) {
706 dcb_config->num_tcs.pg_tcs = 4;
707 dcb_config->num_tcs.pfc_tcs = 4;
712 * Ensure that all locks are released before first NVM or PHY access
715 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
720 * Phy lock should not fail in this early stage. If this is the case,
721 * it is due to an improper exit of the application.
722 * So force the release of the faulty lock. Release of common lock
723 * is done automatically by swfw_sync function.
725 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
726 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
727 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
729 ixgbe_release_swfw_semaphore(hw, mask);
732 * These ones are more tricky since they are common to all ports; but
733 * swfw_sync retries last long enough (1s) to be almost sure that if
734 * lock can not be taken it is due to an improper lock of the
737 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
738 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
739 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
741 ixgbe_release_swfw_semaphore(hw, mask);
745 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
746 * It returns 0 on success.
749 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
751 struct rte_pci_device *pci_dev;
752 struct ixgbe_hw *hw =
753 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
754 struct ixgbe_vfta * shadow_vfta =
755 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
756 struct ixgbe_hwstrip *hwstrip =
757 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
758 struct ixgbe_dcb_config *dcb_config =
759 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
760 struct ixgbe_filter_info *filter_info =
761 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
766 PMD_INIT_FUNC_TRACE();
768 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
769 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
770 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
773 * For secondary processes, we don't initialise any further as primary
774 * has already done this work. Only check we don't need a different
775 * RX and TX function.
777 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
778 struct ixgbe_tx_queue *txq;
779 /* TX queue function in primary, set by last queue initialized
780 * Tx queue may not initialized by primary process */
781 if (eth_dev->data->tx_queues) {
782 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
783 ixgbe_set_tx_function(eth_dev, txq);
785 /* Use default TX function if we get here */
786 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
787 "Using default TX function.");
790 ixgbe_set_rx_function(eth_dev);
794 pci_dev = eth_dev->pci_dev;
796 /* Vendor and Device ID need to be set before init of shared code */
797 hw->device_id = pci_dev->id.device_id;
798 hw->vendor_id = pci_dev->id.vendor_id;
799 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
800 hw->allow_unsupported_sfp = 1;
802 /* Initialize the shared code (base driver) */
803 #ifdef RTE_NIC_BYPASS
804 diag = ixgbe_bypass_init_shared_code(hw);
806 diag = ixgbe_init_shared_code(hw);
807 #endif /* RTE_NIC_BYPASS */
809 if (diag != IXGBE_SUCCESS) {
810 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
814 /* pick up the PCI bus settings for reporting later */
815 ixgbe_get_bus_info(hw);
817 /* Unlock any pending hardware semaphore */
818 ixgbe_swfw_lock_reset(hw);
820 /* Initialize DCB configuration*/
821 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
822 ixgbe_dcb_init(hw,dcb_config);
823 /* Get Hardware Flow Control setting */
824 hw->fc.requested_mode = ixgbe_fc_full;
825 hw->fc.current_mode = ixgbe_fc_full;
826 hw->fc.pause_time = IXGBE_FC_PAUSE;
827 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
828 hw->fc.low_water[i] = IXGBE_FC_LO;
829 hw->fc.high_water[i] = IXGBE_FC_HI;
833 /* Make sure we have a good EEPROM before we read from it */
834 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
835 if (diag != IXGBE_SUCCESS) {
836 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
840 #ifdef RTE_NIC_BYPASS
841 diag = ixgbe_bypass_init_hw(hw);
843 diag = ixgbe_init_hw(hw);
844 #endif /* RTE_NIC_BYPASS */
847 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
848 * is called too soon after the kernel driver unbinding/binding occurs.
849 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
850 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
851 * also called. See ixgbe_identify_phy_82599(). The reason for the
852 * failure is not known, and only occuts when virtualisation features
853 * are disabled in the bios. A delay of 100ms was found to be enough by
854 * trial-and-error, and is doubled to be safe.
856 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
858 diag = ixgbe_init_hw(hw);
861 if (diag == IXGBE_ERR_EEPROM_VERSION) {
862 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
863 "LOM. Please be aware there may be issues associated "
864 "with your hardware.");
865 PMD_INIT_LOG(ERR, "If you are experiencing problems "
866 "please contact your Intel or hardware representative "
867 "who provided you with this hardware.");
868 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
869 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
871 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
875 /* Reset the hw statistics */
876 ixgbe_dev_stats_reset(eth_dev);
878 /* disable interrupt */
879 ixgbe_disable_intr(hw);
881 /* reset mappings for queue statistics hw counters*/
882 ixgbe_reset_qstat_mappings(hw);
884 /* Allocate memory for storing MAC addresses */
885 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
886 hw->mac.num_rar_entries, 0);
887 if (eth_dev->data->mac_addrs == NULL) {
889 "Failed to allocate %u bytes needed to store "
891 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
894 /* Copy the permanent MAC address */
895 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
896 ð_dev->data->mac_addrs[0]);
898 /* Allocate memory for storing hash filter MAC addresses */
899 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
900 IXGBE_VMDQ_NUM_UC_MAC, 0);
901 if (eth_dev->data->hash_mac_addrs == NULL) {
903 "Failed to allocate %d bytes needed to store MAC addresses",
904 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
908 /* initialize the vfta */
909 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
911 /* initialize the hw strip bitmap*/
912 memset(hwstrip, 0, sizeof(*hwstrip));
914 /* initialize PF if max_vfs not zero */
915 ixgbe_pf_host_init(eth_dev);
917 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
918 /* let hardware know driver is loaded */
919 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
920 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
921 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
922 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
923 IXGBE_WRITE_FLUSH(hw);
925 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
926 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
927 (int) hw->mac.type, (int) hw->phy.type,
928 (int) hw->phy.sfp_type);
930 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
931 (int) hw->mac.type, (int) hw->phy.type);
933 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
934 eth_dev->data->port_id, pci_dev->id.vendor_id,
935 pci_dev->id.device_id);
937 rte_intr_callback_register(&(pci_dev->intr_handle),
938 ixgbe_dev_interrupt_handler, (void *)eth_dev);
940 /* enable uio intr after callback register */
941 rte_intr_enable(&(pci_dev->intr_handle));
943 /* enable support intr */
944 ixgbe_enable_intr(eth_dev);
946 /* initialize 5tuple filter list */
947 TAILQ_INIT(&filter_info->fivetuple_list);
948 memset(filter_info->fivetuple_mask, 0,
949 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
956 * Negotiate mailbox API version with the PF.
957 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
958 * Then we try to negotiate starting with the most recent one.
959 * If all negotiation attempts fail, then we will proceed with
960 * the default one (ixgbe_mbox_api_10).
963 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
967 /* start with highest supported, proceed down */
968 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
974 i != RTE_DIM(sup_ver) &&
975 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
981 generate_random_mac_addr(struct ether_addr *mac_addr)
985 /* Set Organizationally Unique Identifier (OUI) prefix. */
986 mac_addr->addr_bytes[0] = 0x00;
987 mac_addr->addr_bytes[1] = 0x09;
988 mac_addr->addr_bytes[2] = 0xC0;
989 /* Force indication of locally assigned MAC address. */
990 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
991 /* Generate the last 3 bytes of the MAC address with a random number. */
993 memcpy(&mac_addr->addr_bytes[3], &random, 3);
997 * Virtual Function device init
1000 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1004 struct rte_pci_device *pci_dev;
1005 struct ixgbe_hw *hw =
1006 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1007 struct ixgbe_vfta * shadow_vfta =
1008 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1009 struct ixgbe_hwstrip *hwstrip =
1010 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1011 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1013 PMD_INIT_FUNC_TRACE();
1015 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1016 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1017 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1019 /* for secondary processes, we don't initialise any further as primary
1020 * has already done this work. Only check we don't need a different
1022 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1023 if (eth_dev->data->scattered_rx)
1024 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1028 pci_dev = eth_dev->pci_dev;
1030 hw->device_id = pci_dev->id.device_id;
1031 hw->vendor_id = pci_dev->id.vendor_id;
1032 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1034 /* initialize the vfta */
1035 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1037 /* initialize the hw strip bitmap*/
1038 memset(hwstrip, 0, sizeof(*hwstrip));
1040 /* Initialize the shared code (base driver) */
1041 diag = ixgbe_init_shared_code(hw);
1042 if (diag != IXGBE_SUCCESS) {
1043 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1047 /* init_mailbox_params */
1048 hw->mbx.ops.init_params(hw);
1050 /* Reset the hw statistics */
1051 ixgbevf_dev_stats_reset(eth_dev);
1053 /* Disable the interrupts for VF */
1054 ixgbevf_intr_disable(hw);
1056 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1057 diag = hw->mac.ops.reset_hw(hw);
1060 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1061 * the underlying PF driver has not assigned a MAC address to the VF.
1062 * In this case, assign a random MAC address.
1064 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1065 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1069 /* negotiate mailbox API version to use with the PF. */
1070 ixgbevf_negotiate_api(hw);
1072 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1073 ixgbevf_get_queues(hw, &tcs, &tc);
1075 /* Allocate memory for storing MAC addresses */
1076 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1077 hw->mac.num_rar_entries, 0);
1078 if (eth_dev->data->mac_addrs == NULL) {
1080 "Failed to allocate %u bytes needed to store "
1082 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1086 /* Generate a random MAC address, if none was assigned by PF. */
1087 if (is_zero_ether_addr(perm_addr)) {
1088 generate_random_mac_addr(perm_addr);
1089 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1091 rte_free(eth_dev->data->mac_addrs);
1092 eth_dev->data->mac_addrs = NULL;
1095 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1096 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1097 "%02x:%02x:%02x:%02x:%02x:%02x",
1098 perm_addr->addr_bytes[0],
1099 perm_addr->addr_bytes[1],
1100 perm_addr->addr_bytes[2],
1101 perm_addr->addr_bytes[3],
1102 perm_addr->addr_bytes[4],
1103 perm_addr->addr_bytes[5]);
1106 /* Copy the permanent MAC address */
1107 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1109 /* reset the hardware with the new settings */
1110 diag = hw->mac.ops.start_hw(hw);
1116 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1120 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1121 eth_dev->data->port_id, pci_dev->id.vendor_id,
1122 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1127 static struct eth_driver rte_ixgbe_pmd = {
1129 .name = "rte_ixgbe_pmd",
1130 .id_table = pci_id_ixgbe_map,
1131 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1133 .eth_dev_init = eth_ixgbe_dev_init,
1134 .dev_private_size = sizeof(struct ixgbe_adapter),
1138 * virtual function driver struct
1140 static struct eth_driver rte_ixgbevf_pmd = {
1142 .name = "rte_ixgbevf_pmd",
1143 .id_table = pci_id_ixgbevf_map,
1144 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1146 .eth_dev_init = eth_ixgbevf_dev_init,
1147 .dev_private_size = sizeof(struct ixgbe_adapter),
1151 * Driver initialization routine.
1152 * Invoked once at EAL init time.
1153 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1156 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1158 PMD_INIT_FUNC_TRACE();
1160 rte_eth_driver_register(&rte_ixgbe_pmd);
1165 * VF Driver initialization routine.
1166 * Invoked one at EAL init time.
1167 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1170 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1172 PMD_INIT_FUNC_TRACE();
1174 rte_eth_driver_register(&rte_ixgbevf_pmd);
1179 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1181 struct ixgbe_hw *hw =
1182 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 struct ixgbe_vfta * shadow_vfta =
1184 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1189 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1190 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1191 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1196 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1198 /* update local VFTA copy */
1199 shadow_vfta->vfta[vid_idx] = vfta;
1205 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1208 ixgbe_vlan_hw_strip_enable(dev, queue);
1210 ixgbe_vlan_hw_strip_disable(dev, queue);
1214 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1216 struct ixgbe_hw *hw =
1217 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219 /* Only the high 16-bits is valid */
1220 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1224 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1226 struct ixgbe_hw *hw =
1227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230 PMD_INIT_FUNC_TRACE();
1232 /* Filter Table Disable */
1233 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1234 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1236 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1240 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1242 struct ixgbe_hw *hw =
1243 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244 struct ixgbe_vfta * shadow_vfta =
1245 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1249 PMD_INIT_FUNC_TRACE();
1251 /* Filter Table Enable */
1252 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1253 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1254 vlnctrl |= IXGBE_VLNCTRL_VFE;
1256 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1258 /* write whatever is in local vfta copy */
1259 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1260 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1264 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1266 struct ixgbe_hwstrip *hwstrip =
1267 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1269 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1273 IXGBE_SET_HWSTRIP(hwstrip, queue);
1275 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1279 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1281 struct ixgbe_hw *hw =
1282 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 PMD_INIT_FUNC_TRACE();
1287 if (hw->mac.type == ixgbe_mac_82598EB) {
1288 /* No queue level support */
1289 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1293 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1294 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1295 ctrl &= ~IXGBE_RXDCTL_VME;
1296 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1298 /* record those setting for HW strip per queue */
1299 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1303 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1305 struct ixgbe_hw *hw =
1306 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 PMD_INIT_FUNC_TRACE();
1311 if (hw->mac.type == ixgbe_mac_82598EB) {
1312 /* No queue level supported */
1313 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1317 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1318 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1319 ctrl |= IXGBE_RXDCTL_VME;
1320 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1322 /* record those setting for HW strip per queue */
1323 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1327 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1329 struct ixgbe_hw *hw =
1330 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334 PMD_INIT_FUNC_TRACE();
1336 if (hw->mac.type == ixgbe_mac_82598EB) {
1337 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1338 ctrl &= ~IXGBE_VLNCTRL_VME;
1339 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1342 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1343 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1344 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1345 ctrl &= ~IXGBE_RXDCTL_VME;
1346 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1348 /* record those setting for HW strip per queue */
1349 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1355 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1357 struct ixgbe_hw *hw =
1358 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 PMD_INIT_FUNC_TRACE();
1364 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1366 ctrl |= IXGBE_VLNCTRL_VME;
1367 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1370 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1371 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1372 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1373 ctrl |= IXGBE_RXDCTL_VME;
1374 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1376 /* record those setting for HW strip per queue */
1377 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1383 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1385 struct ixgbe_hw *hw =
1386 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389 PMD_INIT_FUNC_TRACE();
1391 /* DMATXCTRL: Geric Double VLAN Disable */
1392 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1393 ctrl &= ~IXGBE_DMATXCTL_GDV;
1394 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1396 /* CTRL_EXT: Global Double VLAN Disable */
1397 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1398 ctrl &= ~IXGBE_EXTENDED_VLAN;
1399 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1404 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1406 struct ixgbe_hw *hw =
1407 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410 PMD_INIT_FUNC_TRACE();
1412 /* DMATXCTRL: Geric Double VLAN Enable */
1413 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1414 ctrl |= IXGBE_DMATXCTL_GDV;
1415 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1417 /* CTRL_EXT: Global Double VLAN Enable */
1418 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1419 ctrl |= IXGBE_EXTENDED_VLAN;
1420 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1423 * VET EXT field in the EXVET register = 0x8100 by default
1424 * So no need to change. Same to VT field of DMATXCTL register
1429 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1431 if(mask & ETH_VLAN_STRIP_MASK){
1432 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1433 ixgbe_vlan_hw_strip_enable_all(dev);
1435 ixgbe_vlan_hw_strip_disable_all(dev);
1438 if(mask & ETH_VLAN_FILTER_MASK){
1439 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1440 ixgbe_vlan_hw_filter_enable(dev);
1442 ixgbe_vlan_hw_filter_disable(dev);
1445 if(mask & ETH_VLAN_EXTEND_MASK){
1446 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1447 ixgbe_vlan_hw_extend_enable(dev);
1449 ixgbe_vlan_hw_extend_disable(dev);
1454 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1456 struct ixgbe_hw *hw =
1457 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1459 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1460 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1461 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1465 ixgbe_dev_configure(struct rte_eth_dev *dev)
1467 struct ixgbe_interrupt *intr =
1468 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1469 struct ixgbe_adapter *adapter =
1470 (struct ixgbe_adapter *)dev->data->dev_private;
1472 PMD_INIT_FUNC_TRACE();
1474 /* set flag to update link status after init */
1475 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1478 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1479 * allocation or vector Rx preconditions we will reset it.
1481 adapter->rx_bulk_alloc_allowed = true;
1482 adapter->rx_vec_allowed = true;
1488 * Configure device link speed and setup link.
1489 * It returns 0 on success.
1492 ixgbe_dev_start(struct rte_eth_dev *dev)
1494 struct ixgbe_hw *hw =
1495 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496 struct ixgbe_vf_info *vfinfo =
1497 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1498 int err, link_up = 0, negotiate = 0;
1504 PMD_INIT_FUNC_TRACE();
1506 /* IXGBE devices don't support half duplex */
1507 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1508 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1509 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1510 dev->data->dev_conf.link_duplex,
1511 dev->data->port_id);
1516 hw->adapter_stopped = FALSE;
1517 ixgbe_stop_adapter(hw);
1519 /* reinitialize adapter
1520 * this calls reset and start */
1521 status = ixgbe_pf_reset_hw(hw);
1524 hw->mac.ops.start_hw(hw);
1525 hw->mac.get_link_status = true;
1527 /* configure PF module if SRIOV enabled */
1528 ixgbe_pf_host_configure(dev);
1530 /* initialize transmission unit */
1531 ixgbe_dev_tx_init(dev);
1533 /* This can fail when allocating mbufs for descriptor rings */
1534 err = ixgbe_dev_rx_init(dev);
1536 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1540 err = ixgbe_dev_rxtx_start(dev);
1542 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1546 /* Skip link setup if loopback mode is enabled for 82599. */
1547 if (hw->mac.type == ixgbe_mac_82599EB &&
1548 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1549 goto skip_link_setup;
1551 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1552 err = hw->mac.ops.setup_sfp(hw);
1557 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1558 /* Turn on the copper */
1559 ixgbe_set_phy_power(hw, true);
1561 /* Turn on the laser */
1562 ixgbe_enable_tx_laser(hw);
1565 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1568 dev->data->dev_link.link_status = link_up;
1570 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1574 switch(dev->data->dev_conf.link_speed) {
1575 case ETH_LINK_SPEED_AUTONEG:
1576 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1577 IXGBE_LINK_SPEED_82599_AUTONEG :
1578 IXGBE_LINK_SPEED_82598_AUTONEG;
1580 case ETH_LINK_SPEED_100:
1582 * Invalid for 82598 but error will be detected by
1583 * ixgbe_setup_link()
1585 speed = IXGBE_LINK_SPEED_100_FULL;
1587 case ETH_LINK_SPEED_1000:
1588 speed = IXGBE_LINK_SPEED_1GB_FULL;
1590 case ETH_LINK_SPEED_10000:
1591 speed = IXGBE_LINK_SPEED_10GB_FULL;
1594 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1595 dev->data->dev_conf.link_speed,
1596 dev->data->port_id);
1600 err = ixgbe_setup_link(hw, speed, link_up);
1606 /* check if lsc interrupt is enabled */
1607 if (dev->data->dev_conf.intr_conf.lsc != 0)
1608 ixgbe_dev_lsc_interrupt_setup(dev);
1610 /* resume enabled intr since hw reset */
1611 ixgbe_enable_intr(dev);
1613 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1614 ETH_VLAN_EXTEND_MASK;
1615 ixgbe_vlan_offload_set(dev, mask);
1617 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1618 /* Enable vlan filtering for VMDq */
1619 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1622 /* Configure DCB hw */
1623 ixgbe_configure_dcb(dev);
1625 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1626 err = ixgbe_fdir_configure(dev);
1631 /* Restore vf rate limit */
1632 if (vfinfo != NULL) {
1633 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1634 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1635 if (vfinfo[vf].tx_rate[idx] != 0)
1636 ixgbe_set_vf_rate_limit(dev, vf,
1637 vfinfo[vf].tx_rate[idx],
1641 ixgbe_restore_statistics_mapping(dev);
1646 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1647 ixgbe_dev_clear_queues(dev);
1652 * Stop device: disable rx and tx functions to allow for reconfiguring.
1655 ixgbe_dev_stop(struct rte_eth_dev *dev)
1657 struct rte_eth_link link;
1658 struct ixgbe_hw *hw =
1659 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 struct ixgbe_vf_info *vfinfo =
1661 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1662 struct ixgbe_filter_info *filter_info =
1663 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1664 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1667 PMD_INIT_FUNC_TRACE();
1669 /* disable interrupts */
1670 ixgbe_disable_intr(hw);
1673 ixgbe_pf_reset_hw(hw);
1674 hw->adapter_stopped = FALSE;
1677 ixgbe_stop_adapter(hw);
1679 for (vf = 0; vfinfo != NULL &&
1680 vf < dev->pci_dev->max_vfs; vf++)
1681 vfinfo[vf].clear_to_send = false;
1683 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1684 /* Turn off the copper */
1685 ixgbe_set_phy_power(hw, false);
1687 /* Turn off the laser */
1688 ixgbe_disable_tx_laser(hw);
1691 ixgbe_dev_clear_queues(dev);
1693 /* Clear stored conf */
1694 dev->data->scattered_rx = 0;
1697 /* Clear recorded link status */
1698 memset(&link, 0, sizeof(link));
1699 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1701 /* Remove all ntuple filters of the device */
1702 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1703 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1704 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1705 TAILQ_REMOVE(&filter_info->fivetuple_list,
1709 memset(filter_info->fivetuple_mask, 0,
1710 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1715 * Set device link up: enable tx.
1718 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1720 struct ixgbe_hw *hw =
1721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 if (hw->mac.type == ixgbe_mac_82599EB) {
1723 #ifdef RTE_NIC_BYPASS
1724 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1725 /* Not suported in bypass mode */
1726 PMD_INIT_LOG(ERR, "Set link up is not supported "
1727 "by device id 0x%x", hw->device_id);
1733 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1734 /* Turn on the copper */
1735 ixgbe_set_phy_power(hw, true);
1737 /* Turn on the laser */
1738 ixgbe_enable_tx_laser(hw);
1745 * Set device link down: disable tx.
1748 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1750 struct ixgbe_hw *hw =
1751 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752 if (hw->mac.type == ixgbe_mac_82599EB) {
1753 #ifdef RTE_NIC_BYPASS
1754 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1755 /* Not suported in bypass mode */
1756 PMD_INIT_LOG(ERR, "Set link down is not supported "
1757 "by device id 0x%x", hw->device_id);
1763 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1764 /* Turn off the copper */
1765 ixgbe_set_phy_power(hw, false);
1767 /* Turn off the laser */
1768 ixgbe_disable_tx_laser(hw);
1775 * Reest and stop device.
1778 ixgbe_dev_close(struct rte_eth_dev *dev)
1780 struct ixgbe_hw *hw =
1781 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783 PMD_INIT_FUNC_TRACE();
1785 ixgbe_pf_reset_hw(hw);
1787 ixgbe_dev_stop(dev);
1788 hw->adapter_stopped = 1;
1790 ixgbe_disable_pcie_master(hw);
1792 /* reprogram the RAR[0] in case user changed it. */
1793 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1797 * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1800 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1802 struct ixgbe_hw *hw =
1803 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 struct ixgbe_hw_stats *hw_stats =
1805 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1806 uint32_t bprc, lxon, lxoff, total;
1807 uint64_t total_missed_rx, total_qbrc, total_qprc;
1810 total_missed_rx = 0;
1814 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1815 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1816 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1817 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1819 for (i = 0; i < 8; i++) {
1821 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1822 /* global total per queue */
1823 hw_stats->mpc[i] += mp;
1824 /* Running comprehensive total for stats display */
1825 total_missed_rx += hw_stats->mpc[i];
1826 if (hw->mac.type == ixgbe_mac_82598EB)
1827 hw_stats->rnbc[i] +=
1828 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1829 hw_stats->pxontxc[i] +=
1830 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1831 hw_stats->pxonrxc[i] +=
1832 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1833 hw_stats->pxofftxc[i] +=
1834 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1835 hw_stats->pxoffrxc[i] +=
1836 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1837 hw_stats->pxon2offc[i] +=
1838 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1840 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1841 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1842 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1843 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1844 hw_stats->qbrc[i] +=
1845 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1846 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1847 hw_stats->qbtc[i] +=
1848 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1849 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1851 total_qprc += hw_stats->qprc[i];
1852 total_qbrc += hw_stats->qbrc[i];
1854 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1855 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1856 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1858 /* Note that gprc counts missed packets */
1859 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1861 if (hw->mac.type != ixgbe_mac_82598EB) {
1862 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1863 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1864 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1865 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1866 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1867 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1868 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1869 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1871 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1872 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1873 /* 82598 only has a counter in the high register */
1874 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1875 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1876 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1880 * Workaround: mprc hardware is incorrectly counting
1881 * broadcasts, so for now we subtract those.
1883 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1884 hw_stats->bprc += bprc;
1885 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1886 if (hw->mac.type == ixgbe_mac_82598EB)
1887 hw_stats->mprc -= bprc;
1889 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1890 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1891 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1892 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1893 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1894 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1896 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1897 hw_stats->lxontxc += lxon;
1898 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1899 hw_stats->lxofftxc += lxoff;
1900 total = lxon + lxoff;
1902 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1903 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1904 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1905 hw_stats->gptc -= total;
1906 hw_stats->mptc -= total;
1907 hw_stats->ptc64 -= total;
1908 hw_stats->gotc -= total * ETHER_MIN_LEN;
1910 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1911 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1912 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1913 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1914 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1915 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1916 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1917 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1918 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1919 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1920 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1921 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1922 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1923 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1924 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1925 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1926 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1927 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1928 /* Only read FCOE on 82599 */
1929 if (hw->mac.type != ixgbe_mac_82598EB) {
1930 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1931 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1932 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1933 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1934 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1940 /* Fill out the rte_eth_stats statistics structure */
1941 stats->ipackets = total_qprc;
1942 stats->ibytes = total_qbrc;
1943 stats->opackets = hw_stats->gptc;
1944 stats->obytes = hw_stats->gotc;
1945 stats->imcasts = hw_stats->mprc;
1947 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1948 stats->q_ipackets[i] = hw_stats->qprc[i];
1949 stats->q_opackets[i] = hw_stats->qptc[i];
1950 stats->q_ibytes[i] = hw_stats->qbrc[i];
1951 stats->q_obytes[i] = hw_stats->qbtc[i];
1952 stats->q_errors[i] = hw_stats->qprdc[i];
1956 stats->ibadcrc = hw_stats->crcerrs;
1957 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1958 stats->imissed = total_missed_rx;
1959 stats->ierrors = stats->ibadcrc +
1962 hw_stats->illerrc + hw_stats->errbc;
1967 /* XON/XOFF pause frames */
1968 stats->tx_pause_xon = hw_stats->lxontxc;
1969 stats->rx_pause_xon = hw_stats->lxonrxc;
1970 stats->tx_pause_xoff = hw_stats->lxofftxc;
1971 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1973 /* Flow Director Stats registers */
1974 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1975 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1976 stats->fdirmatch = hw_stats->fdirmatch;
1977 stats->fdirmiss = hw_stats->fdirmiss;
1981 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1983 struct ixgbe_hw_stats *stats =
1984 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1986 /* HW registers are cleared on read */
1987 ixgbe_dev_stats_get(dev, NULL);
1989 /* Reset software totals */
1990 memset(stats, 0, sizeof(*stats));
1994 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1998 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2000 /* Good Rx packet, include VF loopback */
2001 UPDATE_VF_STAT(IXGBE_VFGPRC,
2002 hw_stats->last_vfgprc, hw_stats->vfgprc);
2004 /* Good Rx octets, include VF loopback */
2005 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2006 hw_stats->last_vfgorc, hw_stats->vfgorc);
2008 /* Good Tx packet, include VF loopback */
2009 UPDATE_VF_STAT(IXGBE_VFGPTC,
2010 hw_stats->last_vfgptc, hw_stats->vfgptc);
2012 /* Good Tx octets, include VF loopback */
2013 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2014 hw_stats->last_vfgotc, hw_stats->vfgotc);
2016 /* Rx Multicst Packet */
2017 UPDATE_VF_STAT(IXGBE_VFMPRC,
2018 hw_stats->last_vfmprc, hw_stats->vfmprc);
2023 stats->ipackets = hw_stats->vfgprc;
2024 stats->ibytes = hw_stats->vfgorc;
2025 stats->opackets = hw_stats->vfgptc;
2026 stats->obytes = hw_stats->vfgotc;
2027 stats->imcasts = hw_stats->vfmprc;
2031 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2033 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2034 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2036 /* Sync HW register to the last stats */
2037 ixgbevf_dev_stats_get(dev, NULL);
2039 /* reset HW current stats*/
2040 hw_stats->vfgprc = 0;
2041 hw_stats->vfgorc = 0;
2042 hw_stats->vfgptc = 0;
2043 hw_stats->vfgotc = 0;
2044 hw_stats->vfmprc = 0;
2049 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2054 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2055 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2056 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2057 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2058 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2059 dev_info->max_vfs = dev->pci_dev->max_vfs;
2060 if (hw->mac.type == ixgbe_mac_82598EB)
2061 dev_info->max_vmdq_pools = ETH_16_POOLS;
2063 dev_info->max_vmdq_pools = ETH_64_POOLS;
2064 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2065 dev_info->rx_offload_capa =
2066 DEV_RX_OFFLOAD_VLAN_STRIP |
2067 DEV_RX_OFFLOAD_IPV4_CKSUM |
2068 DEV_RX_OFFLOAD_UDP_CKSUM |
2069 DEV_RX_OFFLOAD_TCP_CKSUM;
2072 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2075 if ((hw->mac.type == ixgbe_mac_82599EB ||
2076 hw->mac.type == ixgbe_mac_X540) &&
2077 !RTE_ETH_DEV_SRIOV(dev).active)
2078 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2080 dev_info->tx_offload_capa =
2081 DEV_TX_OFFLOAD_VLAN_INSERT |
2082 DEV_TX_OFFLOAD_IPV4_CKSUM |
2083 DEV_TX_OFFLOAD_UDP_CKSUM |
2084 DEV_TX_OFFLOAD_TCP_CKSUM |
2085 DEV_TX_OFFLOAD_SCTP_CKSUM |
2086 DEV_TX_OFFLOAD_TCP_TSO;
2088 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2090 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2091 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2092 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2094 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2098 dev_info->default_txconf = (struct rte_eth_txconf) {
2100 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2101 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2102 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2104 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2105 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2106 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2107 ETH_TXQ_FLAGS_NOOFFLOADS,
2109 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2110 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2111 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2115 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2116 struct rte_eth_dev_info *dev_info)
2118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2121 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2122 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2123 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2124 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2125 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2126 dev_info->max_vfs = dev->pci_dev->max_vfs;
2127 if (hw->mac.type == ixgbe_mac_82598EB)
2128 dev_info->max_vmdq_pools = ETH_16_POOLS;
2130 dev_info->max_vmdq_pools = ETH_64_POOLS;
2131 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2132 DEV_RX_OFFLOAD_IPV4_CKSUM |
2133 DEV_RX_OFFLOAD_UDP_CKSUM |
2134 DEV_RX_OFFLOAD_TCP_CKSUM;
2135 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2136 DEV_TX_OFFLOAD_IPV4_CKSUM |
2137 DEV_TX_OFFLOAD_UDP_CKSUM |
2138 DEV_TX_OFFLOAD_TCP_CKSUM |
2139 DEV_TX_OFFLOAD_SCTP_CKSUM;
2141 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2143 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2144 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2145 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2147 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2151 dev_info->default_txconf = (struct rte_eth_txconf) {
2153 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2154 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2155 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2157 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2158 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2159 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2160 ETH_TXQ_FLAGS_NOOFFLOADS,
2164 /* return 0 means link status changed, -1 means not changed */
2166 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 struct rte_eth_link link, old;
2170 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2174 link.link_status = 0;
2175 link.link_speed = 0;
2176 link.link_duplex = 0;
2177 memset(&old, 0, sizeof(old));
2178 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2180 hw->mac.get_link_status = true;
2182 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2183 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2184 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2186 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2189 link.link_speed = ETH_LINK_SPEED_100;
2190 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2191 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2192 if (link.link_status == old.link_status)
2198 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2199 if (link.link_status == old.link_status)
2203 link.link_status = 1;
2204 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2206 switch (link_speed) {
2208 case IXGBE_LINK_SPEED_UNKNOWN:
2209 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2210 link.link_speed = ETH_LINK_SPEED_100;
2213 case IXGBE_LINK_SPEED_100_FULL:
2214 link.link_speed = ETH_LINK_SPEED_100;
2217 case IXGBE_LINK_SPEED_1GB_FULL:
2218 link.link_speed = ETH_LINK_SPEED_1000;
2221 case IXGBE_LINK_SPEED_10GB_FULL:
2222 link.link_speed = ETH_LINK_SPEED_10000;
2225 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2227 if (link.link_status == old.link_status)
2234 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2240 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2241 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2245 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2251 fctrl &= (~IXGBE_FCTRL_UPE);
2252 if (dev->data->all_multicast == 1)
2253 fctrl |= IXGBE_FCTRL_MPE;
2255 fctrl &= (~IXGBE_FCTRL_MPE);
2256 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2260 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2266 fctrl |= IXGBE_FCTRL_MPE;
2267 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2271 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276 if (dev->data->promiscuous == 1)
2277 return; /* must remain in all_multicast mode */
2279 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2280 fctrl &= (~IXGBE_FCTRL_MPE);
2281 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2285 * It clears the interrupt causes and enables the interrupt.
2286 * It will be called once only during nic initialized.
2289 * Pointer to struct rte_eth_dev.
2292 * - On success, zero.
2293 * - On failure, a negative value.
2296 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2298 struct ixgbe_interrupt *intr =
2299 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2301 ixgbe_dev_link_status_print(dev);
2302 intr->mask |= IXGBE_EICR_LSC;
2308 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2311 * Pointer to struct rte_eth_dev.
2314 * - On success, zero.
2315 * - On failure, a negative value.
2318 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2321 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 struct ixgbe_interrupt *intr =
2323 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2325 /* clear all cause mask */
2326 ixgbe_disable_intr(hw);
2328 /* read-on-clear nic registers here */
2329 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2330 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2333 if (eicr & IXGBE_EICR_LSC) {
2334 /* set flag for async link update */
2335 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2338 if (eicr & IXGBE_EICR_MAILBOX)
2339 intr->flags |= IXGBE_FLAG_MAILBOX;
2345 * It gets and then prints the link status.
2348 * Pointer to struct rte_eth_dev.
2351 * - On success, zero.
2352 * - On failure, a negative value.
2355 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2357 struct rte_eth_link link;
2359 memset(&link, 0, sizeof(link));
2360 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2361 if (link.link_status) {
2362 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2363 (int)(dev->data->port_id),
2364 (unsigned)link.link_speed,
2365 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2366 "full-duplex" : "half-duplex");
2368 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2369 (int)(dev->data->port_id));
2371 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2372 dev->pci_dev->addr.domain,
2373 dev->pci_dev->addr.bus,
2374 dev->pci_dev->addr.devid,
2375 dev->pci_dev->addr.function);
2379 * It executes link_update after knowing an interrupt occurred.
2382 * Pointer to struct rte_eth_dev.
2385 * - On success, zero.
2386 * - On failure, a negative value.
2389 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2391 struct ixgbe_interrupt *intr =
2392 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2394 struct rte_eth_link link;
2395 int intr_enable_delay = false;
2397 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2399 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2400 ixgbe_pf_mbx_process(dev);
2401 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2404 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2405 /* get the link status before link update, for predicting later */
2406 memset(&link, 0, sizeof(link));
2407 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2409 ixgbe_dev_link_update(dev, 0);
2412 if (!link.link_status)
2413 /* handle it 1 sec later, wait it being stable */
2414 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2415 /* likely to down */
2417 /* handle it 4 sec later, wait it being stable */
2418 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2420 ixgbe_dev_link_status_print(dev);
2422 intr_enable_delay = true;
2425 if (intr_enable_delay) {
2426 if (rte_eal_alarm_set(timeout * 1000,
2427 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2428 PMD_DRV_LOG(ERR, "Error setting alarm");
2430 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2431 ixgbe_enable_intr(dev);
2432 rte_intr_enable(&(dev->pci_dev->intr_handle));
2440 * Interrupt handler which shall be registered for alarm callback for delayed
2441 * handling specific interrupt to wait for the stable nic state. As the
2442 * NIC interrupt state is not stable for ixgbe after link is just down,
2443 * it needs to wait 4 seconds to get the stable status.
2446 * Pointer to interrupt handle.
2448 * The address of parameter (struct rte_eth_dev *) regsitered before.
2454 ixgbe_dev_interrupt_delayed_handler(void *param)
2456 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2457 struct ixgbe_interrupt *intr =
2458 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2459 struct ixgbe_hw *hw =
2460 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2464 if (eicr & IXGBE_EICR_MAILBOX)
2465 ixgbe_pf_mbx_process(dev);
2467 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2468 ixgbe_dev_link_update(dev, 0);
2469 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2470 ixgbe_dev_link_status_print(dev);
2471 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2474 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2475 ixgbe_enable_intr(dev);
2476 rte_intr_enable(&(dev->pci_dev->intr_handle));
2480 * Interrupt handler triggered by NIC for handling
2481 * specific interrupt.
2484 * Pointer to interrupt handle.
2486 * The address of parameter (struct rte_eth_dev *) regsitered before.
2492 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2495 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2496 ixgbe_dev_interrupt_get_status(dev);
2497 ixgbe_dev_interrupt_action(dev);
2501 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2503 struct ixgbe_hw *hw;
2505 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2510 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2512 struct ixgbe_hw *hw;
2514 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2519 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2521 struct ixgbe_hw *hw;
2527 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529 fc_conf->pause_time = hw->fc.pause_time;
2530 fc_conf->high_water = hw->fc.high_water[0];
2531 fc_conf->low_water = hw->fc.low_water[0];
2532 fc_conf->send_xon = hw->fc.send_xon;
2533 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2536 * Return rx_pause status according to actual setting of
2539 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2540 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2546 * Return tx_pause status according to actual setting of
2549 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2550 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2555 if (rx_pause && tx_pause)
2556 fc_conf->mode = RTE_FC_FULL;
2558 fc_conf->mode = RTE_FC_RX_PAUSE;
2560 fc_conf->mode = RTE_FC_TX_PAUSE;
2562 fc_conf->mode = RTE_FC_NONE;
2568 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2570 struct ixgbe_hw *hw;
2572 uint32_t rx_buf_size;
2573 uint32_t max_high_water;
2575 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2582 PMD_INIT_FUNC_TRACE();
2584 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2586 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2589 * At least reserve one Ethernet frame for watermark
2590 * high_water/low_water in kilo bytes for ixgbe
2592 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2593 if ((fc_conf->high_water > max_high_water) ||
2594 (fc_conf->high_water < fc_conf->low_water)) {
2595 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2596 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2600 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2601 hw->fc.pause_time = fc_conf->pause_time;
2602 hw->fc.high_water[0] = fc_conf->high_water;
2603 hw->fc.low_water[0] = fc_conf->low_water;
2604 hw->fc.send_xon = fc_conf->send_xon;
2605 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2607 err = ixgbe_fc_enable(hw);
2609 /* Not negotiated is not an error case */
2610 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2612 /* check if we want to forward MAC frames - driver doesn't have native
2613 * capability to do that, so we'll write the registers ourselves */
2615 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2617 /* set or clear MFLCN.PMCF bit depending on configuration */
2618 if (fc_conf->mac_ctrl_frame_fwd != 0)
2619 mflcn |= IXGBE_MFLCN_PMCF;
2621 mflcn &= ~IXGBE_MFLCN_PMCF;
2623 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2624 IXGBE_WRITE_FLUSH(hw);
2629 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2634 * ixgbe_pfc_enable_generic - Enable flow control
2635 * @hw: pointer to hardware structure
2636 * @tc_num: traffic class number
2637 * Enable flow control according to the current settings.
2640 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2643 uint32_t mflcn_reg, fccfg_reg;
2645 uint32_t fcrtl, fcrth;
2649 /* Validate the water mark configuration */
2650 if (!hw->fc.pause_time) {
2651 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2655 /* Low water mark of zero causes XOFF floods */
2656 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2657 /* High/Low water can not be 0 */
2658 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2659 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2660 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2664 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2665 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2666 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2670 /* Negotiate the fc mode to use */
2671 ixgbe_fc_autoneg(hw);
2673 /* Disable any previous flow control settings */
2674 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2675 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2677 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2678 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2680 switch (hw->fc.current_mode) {
2683 * If the count of enabled RX Priority Flow control >1,
2684 * and the TX pause can not be disabled
2687 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2688 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2689 if (reg & IXGBE_FCRTH_FCEN)
2693 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2695 case ixgbe_fc_rx_pause:
2697 * Rx Flow control is enabled and Tx Flow control is
2698 * disabled by software override. Since there really
2699 * isn't a way to advertise that we are capable of RX
2700 * Pause ONLY, we will advertise that we support both
2701 * symmetric and asymmetric Rx PAUSE. Later, we will
2702 * disable the adapter's ability to send PAUSE frames.
2704 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2706 * If the count of enabled RX Priority Flow control >1,
2707 * and the TX pause can not be disabled
2710 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2711 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2712 if (reg & IXGBE_FCRTH_FCEN)
2716 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2718 case ixgbe_fc_tx_pause:
2720 * Tx Flow control is enabled, and Rx Flow control is
2721 * disabled by software override.
2723 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2726 /* Flow control (both Rx and Tx) is enabled by SW override. */
2727 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2728 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2731 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2732 ret_val = IXGBE_ERR_CONFIG;
2737 /* Set 802.3x based flow control settings. */
2738 mflcn_reg |= IXGBE_MFLCN_DPF;
2739 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2740 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2742 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2743 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2744 hw->fc.high_water[tc_num]) {
2745 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2746 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2747 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2749 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2751 * In order to prevent Tx hangs when the internal Tx
2752 * switch is enabled we must set the high water mark
2753 * to the maximum FCRTH value. This allows the Tx
2754 * switch to function even under heavy Rx workloads.
2756 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2758 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2760 /* Configure pause time (2 TCs per register) */
2761 reg = hw->fc.pause_time * 0x00010001;
2762 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2763 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2765 /* Configure flow control refresh threshold value */
2766 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2773 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2778 if(hw->mac.type != ixgbe_mac_82598EB) {
2779 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2785 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2788 uint32_t rx_buf_size;
2789 uint32_t max_high_water;
2791 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2792 struct ixgbe_hw *hw =
2793 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794 struct ixgbe_dcb_config *dcb_config =
2795 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2797 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2804 PMD_INIT_FUNC_TRACE();
2806 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2807 tc_num = map[pfc_conf->priority];
2808 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2809 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2811 * At least reserve one Ethernet frame for watermark
2812 * high_water/low_water in kilo bytes for ixgbe
2814 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2815 if ((pfc_conf->fc.high_water > max_high_water) ||
2816 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2817 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2818 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2822 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2823 hw->fc.pause_time = pfc_conf->fc.pause_time;
2824 hw->fc.send_xon = pfc_conf->fc.send_xon;
2825 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2826 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2828 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2830 /* Not negotiated is not an error case */
2831 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2834 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2839 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2840 struct rte_eth_rss_reta_entry64 *reta_conf,
2845 uint16_t idx, shift;
2846 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 PMD_INIT_FUNC_TRACE();
2849 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2850 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2851 "(%d) doesn't match the number hardware can supported "
2852 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2856 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2857 idx = i / RTE_RETA_GROUP_SIZE;
2858 shift = i % RTE_RETA_GROUP_SIZE;
2859 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2863 if (mask == IXGBE_4_BIT_MASK)
2866 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2867 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2868 if (mask & (0x1 << j))
2869 reta |= reta_conf[idx].reta[shift + j] <<
2872 reta |= r & (IXGBE_8_BIT_MASK <<
2875 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2882 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2883 struct rte_eth_rss_reta_entry64 *reta_conf,
2888 uint16_t idx, shift;
2889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891 PMD_INIT_FUNC_TRACE();
2892 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2893 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2894 "(%d) doesn't match the number hardware can supported "
2895 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2899 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2900 idx = i / RTE_RETA_GROUP_SIZE;
2901 shift = i % RTE_RETA_GROUP_SIZE;
2902 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2907 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2908 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2909 if (mask & (0x1 << j))
2910 reta_conf[idx].reta[shift + j] =
2911 ((reta >> (CHAR_BIT * j)) &
2920 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2921 uint32_t index, uint32_t pool)
2923 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924 uint32_t enable_addr = 1;
2926 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2930 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934 ixgbe_clear_rar(hw, index);
2938 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
2940 ixgbe_remove_rar(dev, 0);
2942 ixgbe_add_rar(dev, addr, 0, 0);
2946 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2950 struct ixgbe_hw *hw;
2951 struct rte_eth_dev_info dev_info;
2952 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2954 ixgbe_dev_info_get(dev, &dev_info);
2956 /* check that mtu is within the allowed range */
2957 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2960 /* refuse mtu that requires the support of scattered packets when this
2961 * feature has not been enabled before. */
2962 if (!dev->data->scattered_rx &&
2963 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2964 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2967 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2970 /* switch to jumbo mode if needed */
2971 if (frame_size > ETHER_MAX_LEN) {
2972 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2973 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2975 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2976 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2978 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2980 /* update max frame size */
2981 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2983 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2984 maxfrs &= 0x0000FFFF;
2985 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2986 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2992 * Virtual Function operations
2995 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2997 PMD_INIT_FUNC_TRACE();
2999 /* Clear interrupt mask to stop from interrupts being generated */
3000 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3002 IXGBE_WRITE_FLUSH(hw);
3006 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3008 struct rte_eth_conf* conf = &dev->data->dev_conf;
3009 struct ixgbe_adapter *adapter =
3010 (struct ixgbe_adapter *)dev->data->dev_private;
3012 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3013 dev->data->port_id);
3016 * VF has no ability to enable/disable HW CRC
3017 * Keep the persistent behavior the same as Host PF
3019 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3020 if (!conf->rxmode.hw_strip_crc) {
3021 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3022 conf->rxmode.hw_strip_crc = 1;
3025 if (conf->rxmode.hw_strip_crc) {
3026 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3027 conf->rxmode.hw_strip_crc = 0;
3032 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3033 * allocation or vector Rx preconditions we will reset it.
3035 adapter->rx_bulk_alloc_allowed = true;
3036 adapter->rx_vec_allowed = true;
3042 ixgbevf_dev_start(struct rte_eth_dev *dev)
3044 struct ixgbe_hw *hw =
3045 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048 PMD_INIT_FUNC_TRACE();
3050 hw->mac.ops.reset_hw(hw);
3051 hw->mac.get_link_status = true;
3053 /* negotiate mailbox API version to use with the PF. */
3054 ixgbevf_negotiate_api(hw);
3056 ixgbevf_dev_tx_init(dev);
3058 /* This can fail when allocating mbufs for descriptor rings */
3059 err = ixgbevf_dev_rx_init(dev);
3061 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3062 ixgbe_dev_clear_queues(dev);
3067 ixgbevf_set_vfta_all(dev,1);
3070 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3071 ETH_VLAN_EXTEND_MASK;
3072 ixgbevf_vlan_offload_set(dev, mask);
3074 ixgbevf_dev_rxtx_start(dev);
3080 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3082 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084 PMD_INIT_FUNC_TRACE();
3086 hw->adapter_stopped = TRUE;
3087 ixgbe_stop_adapter(hw);
3090 * Clear what we set, but we still keep shadow_vfta to
3091 * restore after device starts
3093 ixgbevf_set_vfta_all(dev,0);
3095 /* Clear stored conf */
3096 dev->data->scattered_rx = 0;
3098 ixgbe_dev_clear_queues(dev);
3102 ixgbevf_dev_close(struct rte_eth_dev *dev)
3104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106 PMD_INIT_FUNC_TRACE();
3110 ixgbevf_dev_stop(dev);
3112 /* reprogram the RAR[0] in case user changed it. */
3113 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3116 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119 struct ixgbe_vfta * shadow_vfta =
3120 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3121 int i = 0, j = 0, vfta = 0, mask = 1;
3123 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3124 vfta = shadow_vfta->vfta[i];
3127 for (j = 0; j < 32; j++){
3129 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3138 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3140 struct ixgbe_hw *hw =
3141 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142 struct ixgbe_vfta * shadow_vfta =
3143 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3144 uint32_t vid_idx = 0;
3145 uint32_t vid_bit = 0;
3148 PMD_INIT_FUNC_TRACE();
3150 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3151 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3153 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3156 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3157 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3159 /* Save what we set and retore it after device reset */
3161 shadow_vfta->vfta[vid_idx] |= vid_bit;
3163 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3169 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3171 struct ixgbe_hw *hw =
3172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175 PMD_INIT_FUNC_TRACE();
3177 if(queue >= hw->mac.max_rx_queues)
3180 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3182 ctrl |= IXGBE_RXDCTL_VME;
3184 ctrl &= ~IXGBE_RXDCTL_VME;
3185 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3187 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3191 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3193 struct ixgbe_hw *hw =
3194 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198 /* VF function only support hw strip feature, others are not support */
3199 if(mask & ETH_VLAN_STRIP_MASK){
3200 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3202 for(i=0; i < hw->mac.max_rx_queues; i++)
3203 ixgbevf_vlan_strip_queue_set(dev,i,on);
3208 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3212 /* we only need to do this if VMDq is enabled */
3213 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3214 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3215 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3223 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3225 uint32_t vector = 0;
3226 switch (hw->mac.mc_filter_type) {
3227 case 0: /* use bits [47:36] of the address */
3228 vector = ((uc_addr->addr_bytes[4] >> 4) |
3229 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3231 case 1: /* use bits [46:35] of the address */
3232 vector = ((uc_addr->addr_bytes[4] >> 3) |
3233 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3235 case 2: /* use bits [45:34] of the address */
3236 vector = ((uc_addr->addr_bytes[4] >> 2) |
3237 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3239 case 3: /* use bits [43:32] of the address */
3240 vector = ((uc_addr->addr_bytes[4]) |
3241 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3243 default: /* Invalid mc_filter_type */
3247 /* vector can only be 12-bits or boundary will be exceeded */
3253 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3261 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3262 const uint32_t ixgbe_uta_bit_shift = 5;
3263 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3264 const uint32_t bit1 = 0x1;
3266 struct ixgbe_hw *hw =
3267 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268 struct ixgbe_uta_info *uta_info =
3269 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3271 /* The UTA table only exists on 82599 hardware and newer */
3272 if (hw->mac.type < ixgbe_mac_82599EB)
3275 vector = ixgbe_uta_vector(hw,mac_addr);
3276 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3277 uta_shift = vector & ixgbe_uta_bit_mask;
3279 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3283 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3285 uta_info->uta_in_use++;
3286 reg_val |= (bit1 << uta_shift);
3287 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3289 uta_info->uta_in_use--;
3290 reg_val &= ~(bit1 << uta_shift);
3291 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3294 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3296 if (uta_info->uta_in_use > 0)
3297 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3298 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3300 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3306 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3309 struct ixgbe_hw *hw =
3310 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311 struct ixgbe_uta_info *uta_info =
3312 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3314 /* The UTA table only exists on 82599 hardware and newer */
3315 if (hw->mac.type < ixgbe_mac_82599EB)
3319 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3320 uta_info->uta_shadow[i] = ~0;
3321 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3324 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3325 uta_info->uta_shadow[i] = 0;
3326 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3334 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3336 uint32_t new_val = orig_val;
3338 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3339 new_val |= IXGBE_VMOLR_AUPE;
3340 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3341 new_val |= IXGBE_VMOLR_ROMPE;
3342 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3343 new_val |= IXGBE_VMOLR_ROPE;
3344 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3345 new_val |= IXGBE_VMOLR_BAM;
3346 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3347 new_val |= IXGBE_VMOLR_MPE;
3353 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3354 uint16_t rx_mask, uint8_t on)
3358 struct ixgbe_hw *hw =
3359 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3362 if (hw->mac.type == ixgbe_mac_82598EB) {
3363 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3364 " on 82599 hardware and newer");
3367 if (ixgbe_vmdq_mode_check(hw) < 0)
3370 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3377 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3383 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3387 const uint8_t bit1 = 0x1;
3389 struct ixgbe_hw *hw =
3390 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392 if (ixgbe_vmdq_mode_check(hw) < 0)
3395 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3396 reg = IXGBE_READ_REG(hw, addr);
3404 IXGBE_WRITE_REG(hw, addr,reg);
3410 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3414 const uint8_t bit1 = 0x1;
3416 struct ixgbe_hw *hw =
3417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419 if (ixgbe_vmdq_mode_check(hw) < 0)
3422 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3423 reg = IXGBE_READ_REG(hw, addr);
3431 IXGBE_WRITE_REG(hw, addr,reg);
3437 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3438 uint64_t pool_mask, uint8_t vlan_on)
3442 struct ixgbe_hw *hw =
3443 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 if (ixgbe_vmdq_mode_check(hw) < 0)
3447 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3448 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3449 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3457 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
3458 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
3459 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
3460 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
3461 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3462 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3463 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3466 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3467 struct rte_eth_mirror_conf *mirror_conf,
3468 uint8_t rule_id, uint8_t on)
3470 uint32_t mr_ctl,vlvf;
3471 uint32_t mp_lsb = 0;
3472 uint32_t mv_msb = 0;
3473 uint32_t mv_lsb = 0;
3474 uint32_t mp_msb = 0;
3477 uint64_t vlan_mask = 0;
3479 const uint8_t pool_mask_offset = 32;
3480 const uint8_t vlan_mask_offset = 32;
3481 const uint8_t dst_pool_offset = 8;
3482 const uint8_t rule_mr_offset = 4;
3483 const uint8_t mirror_rule_mask= 0x0F;
3485 struct ixgbe_mirror_info *mr_info =
3486 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3487 struct ixgbe_hw *hw =
3488 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489 uint8_t mirror_type = 0;
3491 if (ixgbe_vmdq_mode_check(hw) < 0)
3494 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3497 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3498 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3499 mirror_conf->rule_type);
3503 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3504 mirror_type |= IXGBE_MRCTL_VLME;
3505 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3506 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3507 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3508 /* search vlan id related pool vlan filter index */
3509 reg_index = ixgbe_find_vlvf_slot(hw,
3510 mirror_conf->vlan.vlan_id[i]);
3513 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3514 if ((vlvf & IXGBE_VLVF_VIEN) &&
3515 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3516 mirror_conf->vlan.vlan_id[i]))
3517 vlan_mask |= (1ULL << reg_index);
3524 mv_lsb = vlan_mask & 0xFFFFFFFF;
3525 mv_msb = vlan_mask >> vlan_mask_offset;
3527 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3528 mirror_conf->vlan.vlan_mask;
3529 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3530 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3531 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3532 mirror_conf->vlan.vlan_id[i];
3537 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3538 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3539 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3544 * if enable pool mirror, write related pool mask register,if disable
3545 * pool mirror, clear PFMRVM register
3547 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3548 mirror_type |= IXGBE_MRCTL_VPME;
3550 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3551 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3552 mr_info->mr_conf[rule_id].pool_mask =
3553 mirror_conf->pool_mask;
3558 mr_info->mr_conf[rule_id].pool_mask = 0;
3561 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3562 mirror_type |= IXGBE_MRCTL_UPME;
3563 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3564 mirror_type |= IXGBE_MRCTL_DPME;
3566 /* read mirror control register and recalculate it */
3567 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3570 mr_ctl |= mirror_type;
3571 mr_ctl &= mirror_rule_mask;
3572 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3574 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3576 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3577 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3579 /* write mirrror control register */
3580 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3582 /* write pool mirrror control register */
3583 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3584 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3585 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3588 /* write VLAN mirrror control register */
3589 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3590 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3591 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3599 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3602 uint32_t lsb_val = 0;
3603 uint32_t msb_val = 0;
3604 const uint8_t rule_mr_offset = 4;
3606 struct ixgbe_hw *hw =
3607 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608 struct ixgbe_mirror_info *mr_info =
3609 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3611 if (ixgbe_vmdq_mode_check(hw) < 0)
3614 memset(&mr_info->mr_conf[rule_id], 0,
3615 sizeof(struct rte_eth_mirror_conf));
3617 /* clear PFVMCTL register */
3618 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3620 /* clear pool mask register */
3621 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3622 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3624 /* clear vlan mask register */
3625 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3626 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3631 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3632 uint16_t queue_idx, uint16_t tx_rate)
3634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 uint32_t rf_dec, rf_int;
3637 uint16_t link_speed = dev->data->dev_link.link_speed;
3639 if (queue_idx >= hw->mac.max_tx_queues)
3643 /* Calculate the rate factor values to set */
3644 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3645 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3646 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3648 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3649 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3650 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3651 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3657 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3658 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3661 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3662 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3663 IXGBE_MAX_JUMBO_FRAME_SIZE))
3664 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3665 IXGBE_MMW_SIZE_JUMBO_FRAME);
3667 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3668 IXGBE_MMW_SIZE_DEFAULT);
3670 /* Set RTTBCNRC of queue X */
3671 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3672 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3673 IXGBE_WRITE_FLUSH(hw);
3678 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3679 uint16_t tx_rate, uint64_t q_msk)
3681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 struct ixgbe_vf_info *vfinfo =
3683 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3684 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3685 uint32_t queue_stride =
3686 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3687 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3688 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3689 uint16_t total_rate = 0;
3691 if (queue_end >= hw->mac.max_tx_queues)
3694 if (vfinfo != NULL) {
3695 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3698 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3700 total_rate += vfinfo[vf_idx].tx_rate[idx];
3705 /* Store tx_rate for this vf. */
3706 for (idx = 0; idx < nb_q_per_pool; idx++) {
3707 if (((uint64_t)0x1 << idx) & q_msk) {
3708 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3709 vfinfo[vf].tx_rate[idx] = tx_rate;
3710 total_rate += tx_rate;
3714 if (total_rate > dev->data->dev_link.link_speed) {
3716 * Reset stored TX rate of the VF if it causes exceed
3719 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3723 /* Set RTTBCNRC of each queue/pool for vf X */
3724 for (; queue_idx <= queue_end; queue_idx++) {
3726 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3734 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3735 __attribute__((unused)) uint32_t index,
3736 __attribute__((unused)) uint32_t pool)
3738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3743 * operation. Trap this case to avoid exhausting the [very limited]
3744 * set of PF resources used to store VF MAC addresses.
3746 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3748 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3751 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3755 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3757 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3759 struct ether_addr *mac_addr;
3764 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3765 * not support the deletion of a given MAC address.
3766 * Instead, it imposes to delete all MAC addresses, then to add again
3767 * all MAC addresses with the exception of the one to be deleted.
3769 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3772 * Add again all MAC addresses, with the exception of the deleted one
3773 * and of the permanent MAC address.
3775 for (i = 0, mac_addr = dev->data->mac_addrs;
3776 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3777 /* Skip the deleted MAC address */
3780 /* Skip NULL MAC addresses */
3781 if (is_zero_ether_addr(mac_addr))
3783 /* Skip the permanent MAC address */
3784 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3786 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3789 "Adding again MAC address "
3790 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3792 mac_addr->addr_bytes[0],
3793 mac_addr->addr_bytes[1],
3794 mac_addr->addr_bytes[2],
3795 mac_addr->addr_bytes[3],
3796 mac_addr->addr_bytes[4],
3797 mac_addr->addr_bytes[5],
3803 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
3810 #define MAC_TYPE_FILTER_SUP(type) do {\
3811 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3812 (type) != ixgbe_mac_X550)\
3817 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3818 struct rte_eth_syn_filter *filter,
3821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3827 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3830 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3832 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3833 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3835 if (filter->hig_pri)
3836 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3838 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3840 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3842 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3844 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3845 IXGBE_WRITE_FLUSH(hw);
3850 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3851 struct rte_eth_syn_filter *filter)
3853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3854 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3856 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3857 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3858 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3865 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3866 enum rte_filter_op filter_op,
3869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872 MAC_TYPE_FILTER_SUP(hw->mac.type);
3874 if (filter_op == RTE_ETH_FILTER_NOP)
3878 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3883 switch (filter_op) {
3884 case RTE_ETH_FILTER_ADD:
3885 ret = ixgbe_syn_filter_set(dev,
3886 (struct rte_eth_syn_filter *)arg,
3889 case RTE_ETH_FILTER_DELETE:
3890 ret = ixgbe_syn_filter_set(dev,
3891 (struct rte_eth_syn_filter *)arg,
3894 case RTE_ETH_FILTER_GET:
3895 ret = ixgbe_syn_filter_get(dev,
3896 (struct rte_eth_syn_filter *)arg);
3899 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3908 static inline enum ixgbe_5tuple_protocol
3909 convert_protocol_type(uint8_t protocol_value)
3911 if (protocol_value == IPPROTO_TCP)
3912 return IXGBE_FILTER_PROTOCOL_TCP;
3913 else if (protocol_value == IPPROTO_UDP)
3914 return IXGBE_FILTER_PROTOCOL_UDP;
3915 else if (protocol_value == IPPROTO_SCTP)
3916 return IXGBE_FILTER_PROTOCOL_SCTP;
3918 return IXGBE_FILTER_PROTOCOL_NONE;
3922 * add a 5tuple filter
3925 * dev: Pointer to struct rte_eth_dev.
3926 * index: the index the filter allocates.
3927 * filter: ponter to the filter that will be added.
3928 * rx_queue: the queue id the filter assigned to.
3931 * - On success, zero.
3932 * - On failure, a negative value.
3935 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3936 struct ixgbe_5tuple_filter *filter)
3938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 struct ixgbe_filter_info *filter_info =
3940 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3942 uint32_t ftqf, sdpqf;
3943 uint32_t l34timir = 0;
3944 uint8_t mask = 0xff;
3947 * look for an unused 5tuple filter index,
3948 * and insert the filter to list.
3950 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3951 idx = i / (sizeof(uint32_t) * NBBY);
3952 shift = i % (sizeof(uint32_t) * NBBY);
3953 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3954 filter_info->fivetuple_mask[idx] |= 1 << shift;
3956 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3962 if (i >= IXGBE_MAX_FTQF_FILTERS) {
3963 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3967 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3968 IXGBE_SDPQF_DSTPORT_SHIFT);
3969 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3971 ftqf = (uint32_t)(filter->filter_info.proto &
3972 IXGBE_FTQF_PROTOCOL_MASK);
3973 ftqf |= (uint32_t)((filter->filter_info.priority &
3974 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3975 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3976 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3977 if (filter->filter_info.dst_ip_mask == 0)
3978 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3979 if (filter->filter_info.src_port_mask == 0)
3980 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3981 if (filter->filter_info.dst_port_mask == 0)
3982 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3983 if (filter->filter_info.proto_mask == 0)
3984 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3985 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3986 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3987 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3989 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3990 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3991 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3992 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3994 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3995 l34timir |= (uint32_t)(filter->queue <<
3996 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3997 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4002 * remove a 5tuple filter
4005 * dev: Pointer to struct rte_eth_dev.
4006 * filter: the pointer of the filter will be removed.
4009 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4010 struct ixgbe_5tuple_filter *filter)
4012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013 struct ixgbe_filter_info *filter_info =
4014 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4015 uint16_t index = filter->index;
4017 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4018 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4019 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4022 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4023 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4024 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4025 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4026 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4030 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4032 struct ixgbe_hw *hw;
4033 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4035 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4040 /* refuse mtu that requires the support of scattered packets when this
4041 * feature has not been enabled before. */
4042 if (!dev->data->scattered_rx &&
4043 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4044 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4048 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4049 * request of the version 2.0 of the mailbox API.
4050 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4051 * of the mailbox API.
4052 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4053 * prior to 3.11.33 which contains the following change:
4054 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4056 ixgbevf_rlpml_set_vf(hw, max_frame);
4058 /* update max frame size */
4059 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4063 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
4064 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4068 static inline struct ixgbe_5tuple_filter *
4069 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4070 struct ixgbe_5tuple_filter_info *key)
4072 struct ixgbe_5tuple_filter *it;
4074 TAILQ_FOREACH(it, filter_list, entries) {
4075 if (memcmp(key, &it->filter_info,
4076 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4083 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4085 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4086 struct ixgbe_5tuple_filter_info *filter_info)
4088 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4089 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4090 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4093 switch (filter->dst_ip_mask) {
4095 filter_info->dst_ip_mask = 0;
4096 filter_info->dst_ip = filter->dst_ip;
4099 filter_info->dst_ip_mask = 1;
4102 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4106 switch (filter->src_ip_mask) {
4108 filter_info->src_ip_mask = 0;
4109 filter_info->src_ip = filter->src_ip;
4112 filter_info->src_ip_mask = 1;
4115 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4119 switch (filter->dst_port_mask) {
4121 filter_info->dst_port_mask = 0;
4122 filter_info->dst_port = filter->dst_port;
4125 filter_info->dst_port_mask = 1;
4128 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4132 switch (filter->src_port_mask) {
4134 filter_info->src_port_mask = 0;
4135 filter_info->src_port = filter->src_port;
4138 filter_info->src_port_mask = 1;
4141 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4145 switch (filter->proto_mask) {
4147 filter_info->proto_mask = 0;
4148 filter_info->proto =
4149 convert_protocol_type(filter->proto);
4152 filter_info->proto_mask = 1;
4155 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4159 filter_info->priority = (uint8_t)filter->priority;
4164 * add or delete a ntuple filter
4167 * dev: Pointer to struct rte_eth_dev.
4168 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4169 * add: if true, add filter, if false, remove filter
4172 * - On success, zero.
4173 * - On failure, a negative value.
4176 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4177 struct rte_eth_ntuple_filter *ntuple_filter,
4180 struct ixgbe_filter_info *filter_info =
4181 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4182 struct ixgbe_5tuple_filter_info filter_5tuple;
4183 struct ixgbe_5tuple_filter *filter;
4186 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4187 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4191 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4192 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4196 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4198 if (filter != NULL && add) {
4199 PMD_DRV_LOG(ERR, "filter exists.");
4202 if (filter == NULL && !add) {
4203 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4208 filter = rte_zmalloc("ixgbe_5tuple_filter",
4209 sizeof(struct ixgbe_5tuple_filter), 0);
4212 (void)rte_memcpy(&filter->filter_info,
4214 sizeof(struct ixgbe_5tuple_filter_info));
4215 filter->queue = ntuple_filter->queue;
4216 ret = ixgbe_add_5tuple_filter(dev, filter);
4222 ixgbe_remove_5tuple_filter(dev, filter);
4228 * get a ntuple filter
4231 * dev: Pointer to struct rte_eth_dev.
4232 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4235 * - On success, zero.
4236 * - On failure, a negative value.
4239 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4240 struct rte_eth_ntuple_filter *ntuple_filter)
4242 struct ixgbe_filter_info *filter_info =
4243 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4244 struct ixgbe_5tuple_filter_info filter_5tuple;
4245 struct ixgbe_5tuple_filter *filter;
4248 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4249 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4253 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4254 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4258 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4260 if (filter == NULL) {
4261 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4264 ntuple_filter->queue = filter->queue;
4269 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4270 * @dev: pointer to rte_eth_dev structure
4271 * @filter_op:operation will be taken.
4272 * @arg: a pointer to specific structure corresponding to the filter_op
4275 * - On success, zero.
4276 * - On failure, a negative value.
4279 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4280 enum rte_filter_op filter_op,
4283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4288 if (filter_op == RTE_ETH_FILTER_NOP)
4292 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4297 switch (filter_op) {
4298 case RTE_ETH_FILTER_ADD:
4299 ret = ixgbe_add_del_ntuple_filter(dev,
4300 (struct rte_eth_ntuple_filter *)arg,
4303 case RTE_ETH_FILTER_DELETE:
4304 ret = ixgbe_add_del_ntuple_filter(dev,
4305 (struct rte_eth_ntuple_filter *)arg,
4308 case RTE_ETH_FILTER_GET:
4309 ret = ixgbe_get_ntuple_filter(dev,
4310 (struct rte_eth_ntuple_filter *)arg);
4313 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4321 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4326 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4327 if (filter_info->ethertype_filters[i] == ethertype &&
4328 (filter_info->ethertype_mask & (1 << i)))
4335 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4340 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4341 if (!(filter_info->ethertype_mask & (1 << i))) {
4342 filter_info->ethertype_mask |= 1 << i;
4343 filter_info->ethertype_filters[i] = ethertype;
4351 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4354 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4356 filter_info->ethertype_mask &= ~(1 << idx);
4357 filter_info->ethertype_filters[idx] = 0;
4362 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4363 struct rte_eth_ethertype_filter *filter,
4366 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367 struct ixgbe_filter_info *filter_info =
4368 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4373 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4376 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4377 filter->ether_type == ETHER_TYPE_IPv6) {
4378 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4379 " ethertype filter.", filter->ether_type);
4383 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4384 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4387 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4388 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4392 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4393 if (ret >= 0 && add) {
4394 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4395 filter->ether_type);
4398 if (ret < 0 && !add) {
4399 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4400 filter->ether_type);
4405 ret = ixgbe_ethertype_filter_insert(filter_info,
4406 filter->ether_type);
4408 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4411 etqf = IXGBE_ETQF_FILTER_EN;
4412 etqf |= (uint32_t)filter->ether_type;
4413 etqs |= (uint32_t)((filter->queue <<
4414 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4415 IXGBE_ETQS_RX_QUEUE);
4416 etqs |= IXGBE_ETQS_QUEUE_EN;
4418 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4422 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4423 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4424 IXGBE_WRITE_FLUSH(hw);
4430 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4431 struct rte_eth_ethertype_filter *filter)
4433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4434 struct ixgbe_filter_info *filter_info =
4435 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4436 uint32_t etqf, etqs;
4439 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4441 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4442 filter->ether_type);
4446 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4447 if (etqf & IXGBE_ETQF_FILTER_EN) {
4448 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4449 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4451 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4452 IXGBE_ETQS_RX_QUEUE_SHIFT;
4459 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4460 * @dev: pointer to rte_eth_dev structure
4461 * @filter_op:operation will be taken.
4462 * @arg: a pointer to specific structure corresponding to the filter_op
4465 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4466 enum rte_filter_op filter_op,
4469 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4472 MAC_TYPE_FILTER_SUP(hw->mac.type);
4474 if (filter_op == RTE_ETH_FILTER_NOP)
4478 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4483 switch (filter_op) {
4484 case RTE_ETH_FILTER_ADD:
4485 ret = ixgbe_add_del_ethertype_filter(dev,
4486 (struct rte_eth_ethertype_filter *)arg,
4489 case RTE_ETH_FILTER_DELETE:
4490 ret = ixgbe_add_del_ethertype_filter(dev,
4491 (struct rte_eth_ethertype_filter *)arg,
4494 case RTE_ETH_FILTER_GET:
4495 ret = ixgbe_get_ethertype_filter(dev,
4496 (struct rte_eth_ethertype_filter *)arg);
4499 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4507 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4508 enum rte_filter_type filter_type,
4509 enum rte_filter_op filter_op,
4514 switch (filter_type) {
4515 case RTE_ETH_FILTER_NTUPLE:
4516 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4518 case RTE_ETH_FILTER_ETHERTYPE:
4519 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4521 case RTE_ETH_FILTER_SYN:
4522 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4524 case RTE_ETH_FILTER_FDIR:
4525 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4528 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4537 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4538 u8 **mc_addr_ptr, u32 *vmdq)
4543 mc_addr = *mc_addr_ptr;
4544 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4549 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4550 struct ether_addr *mc_addr_set,
4551 uint32_t nb_mc_addr)
4553 struct ixgbe_hw *hw;
4556 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557 mc_addr_list = (u8 *)mc_addr_set;
4558 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4559 ixgbe_dev_addr_list_itr, TRUE);
4563 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4565 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4569 /* Enable system time for platforms where it isn't on by default. */
4570 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4571 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4572 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4574 /* Start incrementing the register used to timestamp PTP packets. */
4575 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4577 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4578 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4580 IXGBE_ETQF_FILTER_EN |
4583 /* Enable timestamping of received PTP packets. */
4584 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4585 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4586 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4588 /* Enable timestamping of transmitted PTP packets. */
4589 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4590 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4591 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4597 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602 /* Disable timestamping of transmitted PTP packets. */
4603 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4604 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4605 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4607 /* Disable timestamping of received PTP packets. */
4608 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4609 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4610 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4612 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4613 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4615 /* Stop incrementating the System Time registers. */
4616 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4622 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4623 struct timespec *timestamp,
4624 uint32_t flags __rte_unused)
4626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 uint32_t tsync_rxctl;
4631 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4632 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4635 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4636 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4638 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4639 timestamp->tv_nsec = 0;
4645 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4646 struct timespec *timestamp)
4648 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649 uint32_t tsync_txctl;
4653 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4654 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4657 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4658 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4660 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4661 timestamp->tv_nsec = 0;
4666 static struct rte_driver rte_ixgbe_driver = {
4668 .init = rte_ixgbe_pmd_init,
4671 static struct rte_driver rte_ixgbevf_driver = {
4673 .init = rte_ixgbevf_pmd_init,
4676 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4677 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);