4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
77 * High threshold controlling when to start sending XOFF frames. Must be at
78 * least 8 bytes less than receive packet buffer size. This value is in units
81 #define IXGBE_FC_HI 0x80
84 * Low threshold controlling when to start sending XON frames. This value is
85 * in units of 1024 bytes.
87 #define IXGBE_FC_LO 0x40
89 /* Default minimum inter-interrupt interval for EITR configuration */
90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
92 /* Timer value included in XOFF frames. */
93 #define IXGBE_FC_PAUSE 0x680
95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
96 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
97 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
99 #define IXGBE_MMW_SIZE_DEFAULT 0x4
100 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
101 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
104 * Default values for RX/TX configuration
106 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
107 #define IXGBE_DEFAULT_RX_PTHRESH 8
108 #define IXGBE_DEFAULT_RX_HTHRESH 8
109 #define IXGBE_DEFAULT_RX_WTHRESH 0
111 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
112 #define IXGBE_DEFAULT_TX_PTHRESH 32
113 #define IXGBE_DEFAULT_TX_HTHRESH 0
114 #define IXGBE_DEFAULT_TX_WTHRESH 0
115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
117 /* Bit shift and mask */
118 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
119 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
120 #define IXGBE_8_BIT_WIDTH CHAR_BIT
121 #define IXGBE_8_BIT_MASK UINT8_MAX
123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
127 #define IXGBE_HKEY_MAX_INDEX 10
129 /* Additional timesync values. */
130 #define NSEC_PER_SEC 1000000000L
131 #define IXGBE_INCVAL_10GB 0x66666666
132 #define IXGBE_INCVAL_1GB 0x40000000
133 #define IXGBE_INCVAL_100 0x50000000
134 #define IXGBE_INCVAL_SHIFT_10GB 28
135 #define IXGBE_INCVAL_SHIFT_1GB 24
136 #define IXGBE_INCVAL_SHIFT_100 21
137 #define IXGBE_INCVAL_SHIFT_82599 7
138 #define IXGBE_INCPER_SHIFT_82599 24
140 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
144 #define DEFAULT_ETAG_ETYPE 0x893f
145 #define IXGBE_ETAG_ETYPE 0x00005084
146 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
147 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
148 #define IXGBE_RAH_ADTYPE 0x40000000
149 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
150 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
153 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 #define IXGBE_VTEICR_MASK 0x07
156 #define IXGBE_EXVET_VET_EXT_SHIFT 16
157 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
266 int wait_to_complete);
267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
269 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
270 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
271 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
272 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
273 struct rte_eth_stats *stats);
274 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
275 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
276 uint16_t vlan_id, int on);
277 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 uint16_t queue, int on);
279 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
280 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
281 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
283 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
285 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
286 uint8_t queue, uint8_t msix_vector);
287 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
288 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
289 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
291 /* For Eth VMDQ APIs support */
292 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
293 ether_addr * mac_addr, uint8_t on);
294 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
295 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
296 struct rte_eth_mirror_conf *mirror_conf,
297 uint8_t rule_id, uint8_t on);
298 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
300 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
302 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
304 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
305 uint8_t queue, uint8_t msix_vector);
306 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
309 struct ether_addr *mac_addr,
310 uint32_t index, uint32_t pool);
311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
313 struct ether_addr *mac_addr);
314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
315 struct rte_eth_syn_filter *filter);
316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
327 struct rte_eth_ntuple_filter *filter);
328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
329 enum rte_filter_op filter_op,
331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
332 struct rte_eth_ethertype_filter *filter);
333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
334 enum rte_filter_type filter_type,
335 enum rte_filter_op filter_op,
337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
340 struct ether_addr *mc_addr_set,
341 uint32_t nb_mc_addr);
342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
343 struct rte_eth_dcb_info *dcb_info);
345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
347 struct rte_dev_reg_info *regs);
348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
361 struct timespec *timestamp,
363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp);
365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
369 const struct timespec *timestamp);
370 static void ixgbevf_dev_interrupt_handler(void *param);
372 static int ixgbe_dev_l2_tunnel_eth_type_conf
373 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
374 static int ixgbe_dev_l2_tunnel_offload_set
375 (struct rte_eth_dev *dev,
376 struct rte_eth_l2_tunnel_conf *l2_tunnel,
379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
391 * Define VF Stats MACRO for Non "cleared on read" register
393 #define UPDATE_VF_STAT(reg, last, cur) \
395 uint32_t latest = IXGBE_READ_REG(hw, reg); \
396 cur += (latest - last) & UINT_MAX; \
400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
402 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
403 u64 new_msb = IXGBE_READ_REG(hw, msb); \
404 u64 latest = ((new_msb << 32) | new_lsb); \
405 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 #define IXGBE_SET_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] |= 1 << bit;\
415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (h)->bitmap[idx] &= ~(1 << bit);\
421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
422 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
423 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
424 (r) = (h)->bitmap[idx] >> bit & 1;\
428 * The set of PCI devices this driver supports
430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
479 #ifdef RTE_LIBRTE_IXGBE_BYPASS
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
482 { .vendor_id = 0, /* sentinel */ },
486 * The set of PCI devices this driver supports (for 82599 VF)
488 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
499 { .vendor_id = 0, /* sentinel */ },
502 static const struct rte_eth_desc_lim rx_desc_lim = {
503 .nb_max = IXGBE_MAX_RING_DESC,
504 .nb_min = IXGBE_MIN_RING_DESC,
505 .nb_align = IXGBE_RXD_ALIGN,
508 static const struct rte_eth_desc_lim tx_desc_lim = {
509 .nb_max = IXGBE_MAX_RING_DESC,
510 .nb_min = IXGBE_MIN_RING_DESC,
511 .nb_align = IXGBE_TXD_ALIGN,
512 .nb_seg_max = IXGBE_TX_MAX_SEG,
513 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
516 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
517 .dev_configure = ixgbe_dev_configure,
518 .dev_start = ixgbe_dev_start,
519 .dev_stop = ixgbe_dev_stop,
520 .dev_set_link_up = ixgbe_dev_set_link_up,
521 .dev_set_link_down = ixgbe_dev_set_link_down,
522 .dev_close = ixgbe_dev_close,
523 .dev_reset = ixgbe_dev_reset,
524 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
525 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
526 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
527 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
528 .link_update = ixgbe_dev_link_update,
529 .stats_get = ixgbe_dev_stats_get,
530 .xstats_get = ixgbe_dev_xstats_get,
531 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
532 .stats_reset = ixgbe_dev_stats_reset,
533 .xstats_reset = ixgbe_dev_xstats_reset,
534 .xstats_get_names = ixgbe_dev_xstats_get_names,
535 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
536 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
537 .fw_version_get = ixgbe_fw_version_get,
538 .dev_infos_get = ixgbe_dev_info_get,
539 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
540 .mtu_set = ixgbe_dev_mtu_set,
541 .vlan_filter_set = ixgbe_vlan_filter_set,
542 .vlan_tpid_set = ixgbe_vlan_tpid_set,
543 .vlan_offload_set = ixgbe_vlan_offload_set,
544 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
545 .rx_queue_start = ixgbe_dev_rx_queue_start,
546 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
547 .tx_queue_start = ixgbe_dev_tx_queue_start,
548 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
549 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
550 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
551 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
552 .rx_queue_release = ixgbe_dev_rx_queue_release,
553 .rx_queue_count = ixgbe_dev_rx_queue_count,
554 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
555 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
556 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
557 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
558 .tx_queue_release = ixgbe_dev_tx_queue_release,
559 .dev_led_on = ixgbe_dev_led_on,
560 .dev_led_off = ixgbe_dev_led_off,
561 .flow_ctrl_get = ixgbe_flow_ctrl_get,
562 .flow_ctrl_set = ixgbe_flow_ctrl_set,
563 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
564 .mac_addr_add = ixgbe_add_rar,
565 .mac_addr_remove = ixgbe_remove_rar,
566 .mac_addr_set = ixgbe_set_default_mac_addr,
567 .uc_hash_table_set = ixgbe_uc_hash_table_set,
568 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
569 .mirror_rule_set = ixgbe_mirror_rule_set,
570 .mirror_rule_reset = ixgbe_mirror_rule_reset,
571 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
572 .reta_update = ixgbe_dev_rss_reta_update,
573 .reta_query = ixgbe_dev_rss_reta_query,
574 .rss_hash_update = ixgbe_dev_rss_hash_update,
575 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
576 .filter_ctrl = ixgbe_dev_filter_ctrl,
577 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
578 .rxq_info_get = ixgbe_rxq_info_get,
579 .txq_info_get = ixgbe_txq_info_get,
580 .timesync_enable = ixgbe_timesync_enable,
581 .timesync_disable = ixgbe_timesync_disable,
582 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
583 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
584 .get_reg = ixgbe_get_regs,
585 .get_eeprom_length = ixgbe_get_eeprom_length,
586 .get_eeprom = ixgbe_get_eeprom,
587 .set_eeprom = ixgbe_set_eeprom,
588 .get_dcb_info = ixgbe_dev_get_dcb_info,
589 .timesync_adjust_time = ixgbe_timesync_adjust_time,
590 .timesync_read_time = ixgbe_timesync_read_time,
591 .timesync_write_time = ixgbe_timesync_write_time,
592 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
593 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
594 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
595 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
596 .tm_ops_get = ixgbe_tm_ops_get,
600 * dev_ops for virtual function, bare necessities for basic vf
601 * operation have been implemented
603 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
604 .dev_configure = ixgbevf_dev_configure,
605 .dev_start = ixgbevf_dev_start,
606 .dev_stop = ixgbevf_dev_stop,
607 .link_update = ixgbevf_dev_link_update,
608 .stats_get = ixgbevf_dev_stats_get,
609 .xstats_get = ixgbevf_dev_xstats_get,
610 .stats_reset = ixgbevf_dev_stats_reset,
611 .xstats_reset = ixgbevf_dev_stats_reset,
612 .xstats_get_names = ixgbevf_dev_xstats_get_names,
613 .dev_close = ixgbevf_dev_close,
614 .dev_reset = ixgbevf_dev_reset,
615 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
616 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
617 .dev_infos_get = ixgbevf_dev_info_get,
618 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
619 .mtu_set = ixgbevf_dev_set_mtu,
620 .vlan_filter_set = ixgbevf_vlan_filter_set,
621 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
622 .vlan_offload_set = ixgbevf_vlan_offload_set,
623 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
624 .rx_queue_release = ixgbe_dev_rx_queue_release,
625 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
626 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
627 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
628 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
629 .tx_queue_release = ixgbe_dev_tx_queue_release,
630 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
631 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
632 .mac_addr_add = ixgbevf_add_mac_addr,
633 .mac_addr_remove = ixgbevf_remove_mac_addr,
634 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
635 .rxq_info_get = ixgbe_rxq_info_get,
636 .txq_info_get = ixgbe_txq_info_get,
637 .mac_addr_set = ixgbevf_set_default_mac_addr,
638 .get_reg = ixgbevf_get_regs,
639 .reta_update = ixgbe_dev_rss_reta_update,
640 .reta_query = ixgbe_dev_rss_reta_query,
641 .rss_hash_update = ixgbe_dev_rss_hash_update,
642 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
645 /* store statistics names and its offset in stats structure */
646 struct rte_ixgbe_xstats_name_off {
647 char name[RTE_ETH_XSTATS_NAME_SIZE];
651 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
652 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
653 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
654 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
655 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
656 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
657 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
658 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
659 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
660 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
661 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
662 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
663 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
664 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
665 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
666 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
668 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
671 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
672 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
673 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
674 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
675 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
676 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
677 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
678 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
679 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
680 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
681 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
682 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
683 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
684 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
685 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
686 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
688 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
690 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
691 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
692 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
693 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
695 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
697 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
708 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
709 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
710 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
712 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
713 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
714 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
715 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
716 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
718 {"rx_fcoe_no_direct_data_placement_ext_buff",
719 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
721 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
723 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
725 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
727 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
732 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
733 sizeof(rte_ixgbe_stats_strings[0]))
735 /* MACsec statistics */
736 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
737 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
739 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
740 out_pkts_encrypted)},
741 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
742 out_pkts_protected)},
743 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
744 out_octets_encrypted)},
745 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
746 out_octets_protected)},
747 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
754 in_pkts_unknownsci)},
755 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
756 in_octets_decrypted)},
757 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
758 in_octets_validated)},
759 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
761 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
774 in_pkts_notusingsa)},
777 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
778 sizeof(rte_ixgbe_macsec_strings[0]))
780 /* Per-queue statistics */
781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
782 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
783 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
784 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
785 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
788 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
789 sizeof(rte_ixgbe_rxq_strings[0]))
790 #define IXGBE_NB_RXQ_PRIO_VALUES 8
792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
795 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
799 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
800 sizeof(rte_ixgbe_txq_strings[0]))
801 #define IXGBE_NB_TXQ_PRIO_VALUES 8
803 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
804 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
807 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
808 sizeof(rte_ixgbevf_stats_strings[0]))
811 * Atomically reads the link status information from global
812 * structure rte_eth_dev.
815 * - Pointer to the structure rte_eth_dev to read from.
816 * - Pointer to the buffer to be saved with the link status.
819 * - On success, zero.
820 * - On failure, negative value.
823 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
824 struct rte_eth_link *link)
826 struct rte_eth_link *dst = link;
827 struct rte_eth_link *src = &(dev->data->dev_link);
829 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
830 *(uint64_t *)src) == 0)
837 * Atomically writes the link status information into global
838 * structure rte_eth_dev.
841 * - Pointer to the structure rte_eth_dev to read from.
842 * - Pointer to the buffer to be saved with the link status.
845 * - On success, zero.
846 * - On failure, negative value.
849 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
850 struct rte_eth_link *link)
852 struct rte_eth_link *dst = &(dev->data->dev_link);
853 struct rte_eth_link *src = link;
855 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
856 *(uint64_t *)src) == 0)
863 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
866 ixgbe_is_sfp(struct ixgbe_hw *hw)
868 switch (hw->phy.type) {
869 case ixgbe_phy_sfp_avago:
870 case ixgbe_phy_sfp_ftl:
871 case ixgbe_phy_sfp_intel:
872 case ixgbe_phy_sfp_unknown:
873 case ixgbe_phy_sfp_passive_tyco:
874 case ixgbe_phy_sfp_passive_unknown:
881 static inline int32_t
882 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
887 status = ixgbe_reset_hw(hw);
889 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
890 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
891 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
892 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
893 IXGBE_WRITE_FLUSH(hw);
895 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
896 status = IXGBE_SUCCESS;
901 ixgbe_enable_intr(struct rte_eth_dev *dev)
903 struct ixgbe_interrupt *intr =
904 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
905 struct ixgbe_hw *hw =
906 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
908 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
909 IXGBE_WRITE_FLUSH(hw);
913 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
916 ixgbe_disable_intr(struct ixgbe_hw *hw)
918 PMD_INIT_FUNC_TRACE();
920 if (hw->mac.type == ixgbe_mac_82598EB) {
921 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
923 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
927 IXGBE_WRITE_FLUSH(hw);
931 * This function resets queue statistics mapping registers.
932 * From Niantic datasheet, Initialization of Statistics section:
933 * "...if software requires the queue counters, the RQSMR and TQSM registers
934 * must be re-programmed following a device reset.
937 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
941 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
942 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
943 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
949 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
954 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
955 #define NB_QMAP_FIELDS_PER_QSM_REG 4
956 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
958 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ixgbe_stat_mapping_registers *stat_mappings =
960 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
961 uint32_t qsmr_mask = 0;
962 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
966 if ((hw->mac.type != ixgbe_mac_82599EB) &&
967 (hw->mac.type != ixgbe_mac_X540) &&
968 (hw->mac.type != ixgbe_mac_X550) &&
969 (hw->mac.type != ixgbe_mac_X550EM_x) &&
970 (hw->mac.type != ixgbe_mac_X550EM_a))
973 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
974 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
977 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
978 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
979 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
982 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
984 /* Now clear any previous stat_idx set */
985 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
987 stat_mappings->tqsm[n] &= ~clearing_mask;
989 stat_mappings->rqsmr[n] &= ~clearing_mask;
991 q_map = (uint32_t)stat_idx;
992 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
993 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
995 stat_mappings->tqsm[n] |= qsmr_mask;
997 stat_mappings->rqsmr[n] |= qsmr_mask;
999 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1000 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1001 queue_id, stat_idx);
1002 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1003 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1005 /* Now write the mapping in the appropriate register */
1007 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1008 stat_mappings->rqsmr[n], n);
1009 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1011 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1012 stat_mappings->tqsm[n], n);
1013 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1021 struct ixgbe_stat_mapping_registers *stat_mappings =
1022 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026 /* write whatever was in stat mapping table to the NIC */
1027 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1029 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1037 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 struct ixgbe_dcb_tc_config *tc;
1041 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1043 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1044 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1045 for (i = 0; i < dcb_max_tc; i++) {
1046 tc = &dcb_config->tc_config[i];
1047 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1049 (uint8_t)(100/dcb_max_tc + (i & 1));
1050 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1052 (uint8_t)(100/dcb_max_tc + (i & 1));
1053 tc->pfc = ixgbe_dcb_pfc_disabled;
1056 /* Initialize default user to priority mapping, UPx->TC0 */
1057 tc = &dcb_config->tc_config[0];
1058 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1059 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1061 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1062 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1064 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1065 dcb_config->pfc_mode_enable = false;
1066 dcb_config->vt_mode = true;
1067 dcb_config->round_robin_enable = false;
1068 /* support all DCB capabilities in 82599 */
1069 dcb_config->support.capabilities = 0xFF;
1071 /*we only support 4 Tcs for X540, X550 */
1072 if (hw->mac.type == ixgbe_mac_X540 ||
1073 hw->mac.type == ixgbe_mac_X550 ||
1074 hw->mac.type == ixgbe_mac_X550EM_x ||
1075 hw->mac.type == ixgbe_mac_X550EM_a) {
1076 dcb_config->num_tcs.pg_tcs = 4;
1077 dcb_config->num_tcs.pfc_tcs = 4;
1082 * Ensure that all locks are released before first NVM or PHY access
1085 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1090 * Phy lock should not fail in this early stage. If this is the case,
1091 * it is due to an improper exit of the application.
1092 * So force the release of the faulty lock. Release of common lock
1093 * is done automatically by swfw_sync function.
1095 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1096 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1097 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1099 ixgbe_release_swfw_semaphore(hw, mask);
1102 * These ones are more tricky since they are common to all ports; but
1103 * swfw_sync retries last long enough (1s) to be almost sure that if
1104 * lock can not be taken it is due to an improper lock of the
1107 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1108 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1111 ixgbe_release_swfw_semaphore(hw, mask);
1115 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1116 * It returns 0 on success.
1119 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1121 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1122 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1123 struct ixgbe_hw *hw =
1124 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1125 struct ixgbe_vfta *shadow_vfta =
1126 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1127 struct ixgbe_hwstrip *hwstrip =
1128 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1129 struct ixgbe_dcb_config *dcb_config =
1130 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1131 struct ixgbe_filter_info *filter_info =
1132 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1133 struct ixgbe_bw_conf *bw_conf =
1134 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1139 PMD_INIT_FUNC_TRACE();
1141 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1142 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1143 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1144 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147 * For secondary processes, we don't initialise any further as primary
1148 * has already done this work. Only check we don't need a different
1149 * RX and TX function.
1151 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152 struct ixgbe_tx_queue *txq;
1153 /* TX queue function in primary, set by last queue initialized
1154 * Tx queue may not initialized by primary process
1156 if (eth_dev->data->tx_queues) {
1157 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1158 ixgbe_set_tx_function(eth_dev, txq);
1160 /* Use default TX function if we get here */
1161 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1162 "Using default TX function.");
1165 ixgbe_set_rx_function(eth_dev);
1170 rte_eth_copy_pci_info(eth_dev, pci_dev);
1171 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1173 /* Vendor and Device ID need to be set before init of shared code */
1174 hw->device_id = pci_dev->id.device_id;
1175 hw->vendor_id = pci_dev->id.vendor_id;
1176 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1177 hw->allow_unsupported_sfp = 1;
1179 /* Initialize the shared code (base driver) */
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181 diag = ixgbe_bypass_init_shared_code(hw);
1183 diag = ixgbe_init_shared_code(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1186 if (diag != IXGBE_SUCCESS) {
1187 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191 /* pick up the PCI bus settings for reporting later */
1192 ixgbe_get_bus_info(hw);
1194 /* Unlock any pending hardware semaphore */
1195 ixgbe_swfw_lock_reset(hw);
1197 /* Initialize DCB configuration*/
1198 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1199 ixgbe_dcb_init(hw, dcb_config);
1200 /* Get Hardware Flow Control setting */
1201 hw->fc.requested_mode = ixgbe_fc_full;
1202 hw->fc.current_mode = ixgbe_fc_full;
1203 hw->fc.pause_time = IXGBE_FC_PAUSE;
1204 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1205 hw->fc.low_water[i] = IXGBE_FC_LO;
1206 hw->fc.high_water[i] = IXGBE_FC_HI;
1208 hw->fc.send_xon = 1;
1210 /* Make sure we have a good EEPROM before we read from it */
1211 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1212 if (diag != IXGBE_SUCCESS) {
1213 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1218 diag = ixgbe_bypass_init_hw(hw);
1220 diag = ixgbe_init_hw(hw);
1221 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1224 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1225 * is called too soon after the kernel driver unbinding/binding occurs.
1226 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1227 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1228 * also called. See ixgbe_identify_phy_82599(). The reason for the
1229 * failure is not known, and only occuts when virtualisation features
1230 * are disabled in the bios. A delay of 100ms was found to be enough by
1231 * trial-and-error, and is doubled to be safe.
1233 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1235 diag = ixgbe_init_hw(hw);
1238 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1239 diag = IXGBE_SUCCESS;
1241 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243 "LOM. Please be aware there may be issues associated "
1244 "with your hardware.");
1245 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246 "please contact your Intel or hardware representative "
1247 "who provided you with this hardware.");
1248 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1251 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255 /* Reset the hw statistics */
1256 ixgbe_dev_stats_reset(eth_dev);
1258 /* disable interrupt */
1259 ixgbe_disable_intr(hw);
1261 /* reset mappings for queue statistics hw counters*/
1262 ixgbe_reset_qstat_mappings(hw);
1264 /* Allocate memory for storing MAC addresses */
1265 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266 hw->mac.num_rar_entries, 0);
1267 if (eth_dev->data->mac_addrs == NULL) {
1269 "Failed to allocate %u bytes needed to store "
1271 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274 /* Copy the permanent MAC address */
1275 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276 ð_dev->data->mac_addrs[0]);
1278 /* Allocate memory for storing hash filter MAC addresses */
1279 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280 IXGBE_VMDQ_NUM_UC_MAC, 0);
1281 if (eth_dev->data->hash_mac_addrs == NULL) {
1283 "Failed to allocate %d bytes needed to store MAC addresses",
1284 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288 /* initialize the vfta */
1289 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1291 /* initialize the hw strip bitmap*/
1292 memset(hwstrip, 0, sizeof(*hwstrip));
1294 /* initialize PF if max_vfs not zero */
1295 ixgbe_pf_host_init(eth_dev);
1297 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298 /* let hardware know driver is loaded */
1299 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303 IXGBE_WRITE_FLUSH(hw);
1305 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307 (int) hw->mac.type, (int) hw->phy.type,
1308 (int) hw->phy.sfp_type);
1310 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311 (int) hw->mac.type, (int) hw->phy.type);
1313 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314 eth_dev->data->port_id, pci_dev->id.vendor_id,
1315 pci_dev->id.device_id);
1317 rte_intr_callback_register(intr_handle,
1318 ixgbe_dev_interrupt_handler, eth_dev);
1320 /* enable uio/vfio intr/eventfd mapping */
1321 rte_intr_enable(intr_handle);
1323 /* enable support intr */
1324 ixgbe_enable_intr(eth_dev);
1326 /* initialize filter info */
1327 memset(filter_info, 0,
1328 sizeof(struct ixgbe_filter_info));
1330 /* initialize 5tuple filter list */
1331 TAILQ_INIT(&filter_info->fivetuple_list);
1333 /* initialize flow director filter list & hash */
1334 ixgbe_fdir_filter_init(eth_dev);
1336 /* initialize l2 tunnel filter list & hash */
1337 ixgbe_l2_tn_filter_init(eth_dev);
1339 /* initialize flow filter lists */
1340 ixgbe_filterlist_init();
1342 /* initialize bandwidth configuration info */
1343 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1345 /* initialize Traffic Manager configuration */
1346 ixgbe_tm_conf_init(eth_dev);
1352 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1354 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356 struct ixgbe_hw *hw;
1358 PMD_INIT_FUNC_TRACE();
1360 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1363 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1365 if (hw->adapter_stopped == 0)
1366 ixgbe_dev_close(eth_dev);
1368 eth_dev->dev_ops = NULL;
1369 eth_dev->rx_pkt_burst = NULL;
1370 eth_dev->tx_pkt_burst = NULL;
1372 /* Unlock any pending hardware semaphore */
1373 ixgbe_swfw_lock_reset(hw);
1375 /* disable uio intr before callback unregister */
1376 rte_intr_disable(intr_handle);
1377 rte_intr_callback_unregister(intr_handle,
1378 ixgbe_dev_interrupt_handler, eth_dev);
1380 /* uninitialize PF if max_vfs not zero */
1381 ixgbe_pf_host_uninit(eth_dev);
1383 rte_free(eth_dev->data->mac_addrs);
1384 eth_dev->data->mac_addrs = NULL;
1386 rte_free(eth_dev->data->hash_mac_addrs);
1387 eth_dev->data->hash_mac_addrs = NULL;
1389 /* remove all the fdir filters & hash */
1390 ixgbe_fdir_filter_uninit(eth_dev);
1392 /* remove all the L2 tunnel filters & hash */
1393 ixgbe_l2_tn_filter_uninit(eth_dev);
1395 /* Remove all ntuple filters of the device */
1396 ixgbe_ntuple_filter_uninit(eth_dev);
1398 /* clear all the filters list */
1399 ixgbe_filterlist_flush();
1401 /* Remove all Traffic Manager configuration */
1402 ixgbe_tm_conf_uninit(eth_dev);
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1409 struct ixgbe_filter_info *filter_info =
1410 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411 struct ixgbe_5tuple_filter *p_5tuple;
1413 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414 TAILQ_REMOVE(&filter_info->fivetuple_list,
1419 memset(filter_info->fivetuple_mask, 0,
1420 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1427 struct ixgbe_hw_fdir_info *fdir_info =
1428 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429 struct ixgbe_fdir_filter *fdir_filter;
1431 if (fdir_info->hash_map)
1432 rte_free(fdir_info->hash_map);
1433 if (fdir_info->hash_handle)
1434 rte_hash_free(fdir_info->hash_handle);
1436 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437 TAILQ_REMOVE(&fdir_info->fdir_list,
1440 rte_free(fdir_filter);
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1448 struct ixgbe_l2_tn_info *l2_tn_info =
1449 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450 struct ixgbe_l2_tn_filter *l2_tn_filter;
1452 if (l2_tn_info->hash_map)
1453 rte_free(l2_tn_info->hash_map);
1454 if (l2_tn_info->hash_handle)
1455 rte_hash_free(l2_tn_info->hash_handle);
1457 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1461 rte_free(l2_tn_filter);
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1469 struct ixgbe_hw_fdir_info *fdir_info =
1470 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471 char fdir_hash_name[RTE_HASH_NAMESIZE];
1472 struct rte_hash_parameters fdir_hash_params = {
1473 .name = fdir_hash_name,
1474 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475 .key_len = sizeof(union ixgbe_atr_input),
1476 .hash_func = rte_hash_crc,
1477 .hash_func_init_val = 0,
1478 .socket_id = rte_socket_id(),
1481 TAILQ_INIT(&fdir_info->fdir_list);
1482 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483 "fdir_%s", eth_dev->device->name);
1484 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485 if (!fdir_info->hash_handle) {
1486 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1489 fdir_info->hash_map = rte_zmalloc("ixgbe",
1490 sizeof(struct ixgbe_fdir_filter *) *
1491 IXGBE_MAX_FDIR_FILTER_NUM,
1493 if (!fdir_info->hash_map) {
1495 "Failed to allocate memory for fdir hash map!");
1498 fdir_info->mask_added = FALSE;
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1505 struct ixgbe_l2_tn_info *l2_tn_info =
1506 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508 struct rte_hash_parameters l2_tn_hash_params = {
1509 .name = l2_tn_hash_name,
1510 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512 .hash_func = rte_hash_crc,
1513 .hash_func_init_val = 0,
1514 .socket_id = rte_socket_id(),
1517 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519 "l2_tn_%s", eth_dev->device->name);
1520 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521 if (!l2_tn_info->hash_handle) {
1522 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1525 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526 sizeof(struct ixgbe_l2_tn_filter *) *
1527 IXGBE_MAX_L2_TN_FILTER_NUM,
1529 if (!l2_tn_info->hash_map) {
1531 "Failed to allocate memory for L2 TN hash map!");
1534 l2_tn_info->e_tag_en = FALSE;
1535 l2_tn_info->e_tag_fwd_en = FALSE;
1536 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1541 * Negotiate mailbox API version with the PF.
1542 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543 * Then we try to negotiate starting with the most recent one.
1544 * If all negotiation attempts fail, then we will proceed with
1545 * the default one (ixgbe_mbox_api_10).
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1552 /* start with highest supported, proceed down */
1553 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1560 i != RTE_DIM(sup_ver) &&
1561 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1571 /* Set Organizationally Unique Identifier (OUI) prefix. */
1572 mac_addr->addr_bytes[0] = 0x00;
1573 mac_addr->addr_bytes[1] = 0x09;
1574 mac_addr->addr_bytes[2] = 0xC0;
1575 /* Force indication of locally assigned MAC address. */
1576 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577 /* Generate the last 3 bytes of the MAC address with a random number. */
1578 random = rte_rand();
1579 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1583 * Virtual Function device init
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1590 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592 struct ixgbe_hw *hw =
1593 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594 struct ixgbe_vfta *shadow_vfta =
1595 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596 struct ixgbe_hwstrip *hwstrip =
1597 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1600 PMD_INIT_FUNC_TRACE();
1602 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1606 /* for secondary processes, we don't initialise any further as primary
1607 * has already done this work. Only check we don't need a different
1610 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611 struct ixgbe_tx_queue *txq;
1612 /* TX queue function in primary, set by last queue initialized
1613 * Tx queue may not initialized by primary process
1615 if (eth_dev->data->tx_queues) {
1616 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617 ixgbe_set_tx_function(eth_dev, txq);
1619 /* Use default TX function if we get here */
1620 PMD_INIT_LOG(NOTICE,
1621 "No TX queues configured yet. Using default TX function.");
1624 ixgbe_set_rx_function(eth_dev);
1629 rte_eth_copy_pci_info(eth_dev, pci_dev);
1630 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1632 hw->device_id = pci_dev->id.device_id;
1633 hw->vendor_id = pci_dev->id.vendor_id;
1634 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1636 /* initialize the vfta */
1637 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1639 /* initialize the hw strip bitmap*/
1640 memset(hwstrip, 0, sizeof(*hwstrip));
1642 /* Initialize the shared code (base driver) */
1643 diag = ixgbe_init_shared_code(hw);
1644 if (diag != IXGBE_SUCCESS) {
1645 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1649 /* init_mailbox_params */
1650 hw->mbx.ops.init_params(hw);
1652 /* Reset the hw statistics */
1653 ixgbevf_dev_stats_reset(eth_dev);
1655 /* Disable the interrupts for VF */
1656 ixgbevf_intr_disable(hw);
1658 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659 diag = hw->mac.ops.reset_hw(hw);
1662 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663 * the underlying PF driver has not assigned a MAC address to the VF.
1664 * In this case, assign a random MAC address.
1666 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671 /* negotiate mailbox API version to use with the PF. */
1672 ixgbevf_negotiate_api(hw);
1674 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675 ixgbevf_get_queues(hw, &tcs, &tc);
1677 /* Allocate memory for storing MAC addresses */
1678 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679 hw->mac.num_rar_entries, 0);
1680 if (eth_dev->data->mac_addrs == NULL) {
1682 "Failed to allocate %u bytes needed to store "
1684 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1688 /* Generate a random MAC address, if none was assigned by PF. */
1689 if (is_zero_ether_addr(perm_addr)) {
1690 generate_random_mac_addr(perm_addr);
1691 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1693 rte_free(eth_dev->data->mac_addrs);
1694 eth_dev->data->mac_addrs = NULL;
1697 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699 "%02x:%02x:%02x:%02x:%02x:%02x",
1700 perm_addr->addr_bytes[0],
1701 perm_addr->addr_bytes[1],
1702 perm_addr->addr_bytes[2],
1703 perm_addr->addr_bytes[3],
1704 perm_addr->addr_bytes[4],
1705 perm_addr->addr_bytes[5]);
1708 /* Copy the permanent MAC address */
1709 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1711 /* reset the hardware with the new settings */
1712 diag = hw->mac.ops.start_hw(hw);
1718 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1722 rte_intr_callback_register(intr_handle,
1723 ixgbevf_dev_interrupt_handler, eth_dev);
1724 rte_intr_enable(intr_handle);
1725 ixgbevf_intr_enable(hw);
1727 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728 eth_dev->data->port_id, pci_dev->id.vendor_id,
1729 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1734 /* Virtual Function device uninit */
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1739 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741 struct ixgbe_hw *hw;
1743 PMD_INIT_FUNC_TRACE();
1745 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1750 if (hw->adapter_stopped == 0)
1751 ixgbevf_dev_close(eth_dev);
1753 eth_dev->dev_ops = NULL;
1754 eth_dev->rx_pkt_burst = NULL;
1755 eth_dev->tx_pkt_burst = NULL;
1757 /* Disable the interrupts for VF */
1758 ixgbevf_intr_disable(hw);
1760 rte_free(eth_dev->data->mac_addrs);
1761 eth_dev->data->mac_addrs = NULL;
1763 rte_intr_disable(intr_handle);
1764 rte_intr_callback_unregister(intr_handle,
1765 ixgbevf_dev_interrupt_handler, eth_dev);
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771 struct rte_pci_device *pci_dev)
1773 return rte_eth_dev_pci_generic_probe(pci_dev,
1774 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1779 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783 .id_table = pci_id_ixgbe_map,
1784 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785 .probe = eth_ixgbe_pci_probe,
1786 .remove = eth_ixgbe_pci_remove,
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790 struct rte_pci_device *pci_dev)
1792 return rte_eth_dev_pci_generic_probe(pci_dev,
1793 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1802 * virtual function driver struct
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805 .id_table = pci_id_ixgbevf_map,
1806 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807 .probe = eth_ixgbevf_pci_probe,
1808 .remove = eth_ixgbevf_pci_remove,
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 struct ixgbe_hw *hw =
1815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816 struct ixgbe_vfta *shadow_vfta =
1817 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831 /* update local VFTA copy */
1832 shadow_vfta->vfta[vid_idx] = vfta;
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 ixgbe_vlan_hw_strip_enable(dev, queue);
1843 ixgbe_vlan_hw_strip_disable(dev, queue);
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848 enum rte_vlan_type vlan_type,
1851 struct ixgbe_hw *hw =
1852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858 qinq &= IXGBE_DMATXCTL_GDV;
1860 switch (vlan_type) {
1861 case ETH_VLAN_TYPE_INNER:
1863 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872 PMD_DRV_LOG(ERR, "Inner type is not supported"
1876 case ETH_VLAN_TYPE_OUTER:
1878 /* Only the high 16-bits is valid */
1879 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880 IXGBE_EXVET_VET_EXT_SHIFT);
1882 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 struct ixgbe_hw *hw =
1905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 PMD_INIT_FUNC_TRACE();
1910 /* Filter Table Disable */
1911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922 struct ixgbe_vfta *shadow_vfta =
1923 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1927 PMD_INIT_FUNC_TRACE();
1929 /* Filter Table Enable */
1930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932 vlnctrl |= IXGBE_VLNCTRL_VFE;
1934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 /* write whatever is in local vfta copy */
1937 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 struct ixgbe_hwstrip *hwstrip =
1945 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946 struct ixgbe_rx_queue *rxq;
1948 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1952 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956 if (queue >= dev->data->nb_rx_queues)
1959 rxq = dev->data->rx_queues[queue];
1962 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1964 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1970 struct ixgbe_hw *hw =
1971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 PMD_INIT_FUNC_TRACE();
1976 if (hw->mac.type == ixgbe_mac_82598EB) {
1977 /* No queue level support */
1978 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1982 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984 ctrl &= ~IXGBE_RXDCTL_VME;
1985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1987 /* record those setting for HW strip per queue */
1988 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1994 struct ixgbe_hw *hw =
1995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998 PMD_INIT_FUNC_TRACE();
2000 if (hw->mac.type == ixgbe_mac_82598EB) {
2001 /* No queue level supported */
2002 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008 ctrl |= IXGBE_RXDCTL_VME;
2009 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2011 /* record those setting for HW strip per queue */
2012 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2018 struct ixgbe_hw *hw =
2019 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022 struct ixgbe_rx_queue *rxq;
2024 PMD_INIT_FUNC_TRACE();
2026 if (hw->mac.type == ixgbe_mac_82598EB) {
2027 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028 ctrl &= ~IXGBE_VLNCTRL_VME;
2029 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2031 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033 rxq = dev->data->rx_queues[i];
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035 ctrl &= ~IXGBE_RXDCTL_VME;
2036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2038 /* record those setting for HW strip per queue */
2039 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2047 struct ixgbe_hw *hw =
2048 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 struct ixgbe_rx_queue *rxq;
2053 PMD_INIT_FUNC_TRACE();
2055 if (hw->mac.type == ixgbe_mac_82598EB) {
2056 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057 ctrl |= IXGBE_VLNCTRL_VME;
2058 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2060 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062 rxq = dev->data->rx_queues[i];
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064 ctrl |= IXGBE_RXDCTL_VME;
2065 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2067 /* record those setting for HW strip per queue */
2068 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2076 struct ixgbe_hw *hw =
2077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080 PMD_INIT_FUNC_TRACE();
2082 /* DMATXCTRL: Geric Double VLAN Disable */
2083 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084 ctrl &= ~IXGBE_DMATXCTL_GDV;
2085 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2087 /* CTRL_EXT: Global Double VLAN Disable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089 ctrl &= ~IXGBE_EXTENDED_VLAN;
2090 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2097 struct ixgbe_hw *hw =
2098 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 PMD_INIT_FUNC_TRACE();
2103 /* DMATXCTRL: Geric Double VLAN Enable */
2104 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105 ctrl |= IXGBE_DMATXCTL_GDV;
2106 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2108 /* CTRL_EXT: Global Double VLAN Enable */
2109 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110 ctrl |= IXGBE_EXTENDED_VLAN;
2111 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2113 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114 if (hw->mac.type == ixgbe_mac_X550 ||
2115 hw->mac.type == ixgbe_mac_X550EM_x ||
2116 hw->mac.type == ixgbe_mac_X550EM_a) {
2117 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2123 * VET EXT field in the EXVET register = 0x8100 by default
2124 * So no need to change. Same to VT field of DMATXCTL register
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2131 if (mask & ETH_VLAN_STRIP_MASK) {
2132 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133 ixgbe_vlan_hw_strip_enable_all(dev);
2135 ixgbe_vlan_hw_strip_disable_all(dev);
2138 if (mask & ETH_VLAN_FILTER_MASK) {
2139 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140 ixgbe_vlan_hw_filter_enable(dev);
2142 ixgbe_vlan_hw_filter_disable(dev);
2145 if (mask & ETH_VLAN_EXTEND_MASK) {
2146 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147 ixgbe_vlan_hw_extend_enable(dev);
2149 ixgbe_vlan_hw_extend_disable(dev);
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2156 struct ixgbe_hw *hw =
2157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2161 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2168 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2173 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2176 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2182 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2191 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2196 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197 /* check multi-queue mode */
2198 switch (dev_conf->rxmode.mq_mode) {
2199 case ETH_MQ_RX_VMDQ_DCB:
2200 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2202 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204 PMD_INIT_LOG(ERR, "SRIOV active,"
2205 " unsupported mq_mode rx %d.",
2206 dev_conf->rxmode.mq_mode);
2209 case ETH_MQ_RX_VMDQ_RSS:
2210 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213 PMD_INIT_LOG(ERR, "SRIOV is active,"
2214 " invalid queue number"
2215 " for VMDQ RSS, allowed"
2216 " value are 1, 2 or 4.");
2220 case ETH_MQ_RX_VMDQ_ONLY:
2221 case ETH_MQ_RX_NONE:
2222 /* if nothing mq mode configure, use default scheme */
2223 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2227 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228 /* SRIOV only works in VMDq enable mode */
2229 PMD_INIT_LOG(ERR, "SRIOV is active,"
2230 " wrong mq_mode rx %d.",
2231 dev_conf->rxmode.mq_mode);
2235 switch (dev_conf->txmode.mq_mode) {
2236 case ETH_MQ_TX_VMDQ_DCB:
2237 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2240 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2245 /* check valid queue number */
2246 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248 PMD_INIT_LOG(ERR, "SRIOV is active,"
2249 " nb_rx_q=%d nb_tx_q=%d queue number"
2250 " must be less than or equal to %d.",
2252 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2256 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2261 /* check configuration for vmdb+dcb mode */
2262 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263 const struct rte_eth_vmdq_dcb_conf *conf;
2265 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267 IXGBE_VMDQ_DCB_NB_QUEUES);
2270 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272 conf->nb_queue_pools == ETH_32_POOLS)) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274 " nb_queue_pools must be %d or %d.",
2275 ETH_16_POOLS, ETH_32_POOLS);
2279 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2282 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284 IXGBE_VMDQ_DCB_NB_QUEUES);
2287 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289 conf->nb_queue_pools == ETH_32_POOLS)) {
2290 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291 " nb_queue_pools != %d and"
2292 " nb_queue_pools != %d.",
2293 ETH_16_POOLS, ETH_32_POOLS);
2298 /* For DCB mode check our configuration before we go further */
2299 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300 const struct rte_eth_dcb_rx_conf *conf;
2302 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304 IXGBE_DCB_NB_QUEUES);
2307 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308 if (!(conf->nb_tcs == ETH_4_TCS ||
2309 conf->nb_tcs == ETH_8_TCS)) {
2310 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311 " and nb_tcs != %d.",
2312 ETH_4_TCS, ETH_8_TCS);
2317 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318 const struct rte_eth_dcb_tx_conf *conf;
2320 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322 IXGBE_DCB_NB_QUEUES);
2325 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326 if (!(conf->nb_tcs == ETH_4_TCS ||
2327 conf->nb_tcs == ETH_8_TCS)) {
2328 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329 " and nb_tcs != %d.",
2330 ETH_4_TCS, ETH_8_TCS);
2336 * When DCB/VT is off, maximum number of queues changes,
2337 * except for 82598EB, which remains constant.
2339 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340 hw->mac.type != ixgbe_mac_82598EB) {
2341 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2343 "Neither VT nor DCB are enabled, "
2345 IXGBE_NONE_MODE_TX_NB_QUEUES);
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2356 struct ixgbe_interrupt *intr =
2357 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358 struct ixgbe_adapter *adapter =
2359 (struct ixgbe_adapter *)dev->data->dev_private;
2362 PMD_INIT_FUNC_TRACE();
2363 /* multipe queue mode checking */
2364 ret = ixgbe_check_mq_mode(dev);
2366 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2371 /* set flag to update link status after init */
2372 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2375 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376 * allocation or vector Rx preconditions we will reset it.
2378 adapter->rx_bulk_alloc_allowed = true;
2379 adapter->rx_vec_allowed = true;
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2387 struct ixgbe_hw *hw =
2388 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct ixgbe_interrupt *intr =
2390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393 /* only set up it on X550EM_X */
2394 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405 uint16_t tx_rate, uint64_t q_msk)
2407 struct ixgbe_hw *hw;
2408 struct ixgbe_vf_info *vfinfo;
2409 struct rte_eth_link link;
2410 uint8_t nb_q_per_pool;
2411 uint32_t queue_stride;
2412 uint32_t queue_idx, idx = 0, vf_idx;
2414 uint16_t total_rate = 0;
2415 struct rte_pci_device *pci_dev;
2417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418 rte_eth_link_get_nowait(dev->data->port_id, &link);
2420 if (vf >= pci_dev->max_vfs)
2423 if (tx_rate > link.link_speed)
2429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433 queue_idx = vf * queue_stride;
2434 queue_end = queue_idx + nb_q_per_pool - 1;
2435 if (queue_end >= hw->mac.max_tx_queues)
2439 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2442 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2444 total_rate += vfinfo[vf_idx].tx_rate[idx];
2450 /* Store tx_rate for this vf. */
2451 for (idx = 0; idx < nb_q_per_pool; idx++) {
2452 if (((uint64_t)0x1 << idx) & q_msk) {
2453 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454 vfinfo[vf].tx_rate[idx] = tx_rate;
2455 total_rate += tx_rate;
2459 if (total_rate > dev->data->dev_link.link_speed) {
2460 /* Reset stored TX rate of the VF if it causes exceed
2463 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2467 /* Set RTTBCNRC of each queue/pool for vf X */
2468 for (; queue_idx <= queue_end; queue_idx++) {
2470 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2478 * Configure device link speed and setup link.
2479 * It returns 0 on success.
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2484 struct ixgbe_hw *hw =
2485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 struct ixgbe_vf_info *vfinfo =
2487 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490 uint32_t intr_vector = 0;
2491 int err, link_up = 0, negotiate = 0;
2496 uint32_t *link_speeds;
2497 struct ixgbe_tm_conf *tm_conf =
2498 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2500 PMD_INIT_FUNC_TRACE();
2502 /* IXGBE devices don't support:
2503 * - half duplex (checked afterwards for valid speeds)
2504 * - fixed speed: TODO implement
2506 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2507 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2508 dev->data->port_id);
2512 /* disable uio/vfio intr/eventfd mapping */
2513 rte_intr_disable(intr_handle);
2516 hw->adapter_stopped = 0;
2517 ixgbe_stop_adapter(hw);
2519 /* reinitialize adapter
2520 * this calls reset and start
2522 status = ixgbe_pf_reset_hw(hw);
2525 hw->mac.ops.start_hw(hw);
2526 hw->mac.get_link_status = true;
2528 /* configure PF module if SRIOV enabled */
2529 ixgbe_pf_host_configure(dev);
2531 ixgbe_dev_phy_intr_setup(dev);
2533 /* check and configure queue intr-vector mapping */
2534 if ((rte_intr_cap_multiple(intr_handle) ||
2535 !RTE_ETH_DEV_SRIOV(dev).active) &&
2536 dev->data->dev_conf.intr_conf.rxq != 0) {
2537 intr_vector = dev->data->nb_rx_queues;
2538 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2539 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2540 IXGBE_MAX_INTR_QUEUE_NUM);
2543 if (rte_intr_efd_enable(intr_handle, intr_vector))
2547 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2548 intr_handle->intr_vec =
2549 rte_zmalloc("intr_vec",
2550 dev->data->nb_rx_queues * sizeof(int), 0);
2551 if (intr_handle->intr_vec == NULL) {
2552 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2553 " intr_vec", dev->data->nb_rx_queues);
2558 /* confiugre msix for sleep until rx interrupt */
2559 ixgbe_configure_msix(dev);
2561 /* initialize transmission unit */
2562 ixgbe_dev_tx_init(dev);
2564 /* This can fail when allocating mbufs for descriptor rings */
2565 err = ixgbe_dev_rx_init(dev);
2567 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2571 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2572 ETH_VLAN_EXTEND_MASK;
2573 ixgbe_vlan_offload_set(dev, mask);
2575 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2576 /* Enable vlan filtering for VMDq */
2577 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2580 /* Configure DCB hw */
2581 ixgbe_configure_dcb(dev);
2583 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2584 err = ixgbe_fdir_configure(dev);
2589 /* Restore vf rate limit */
2590 if (vfinfo != NULL) {
2591 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2592 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2593 if (vfinfo[vf].tx_rate[idx] != 0)
2594 ixgbe_set_vf_rate_limit(
2596 vfinfo[vf].tx_rate[idx],
2600 ixgbe_restore_statistics_mapping(dev);
2602 err = ixgbe_dev_rxtx_start(dev);
2604 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2608 /* Skip link setup if loopback mode is enabled for 82599. */
2609 if (hw->mac.type == ixgbe_mac_82599EB &&
2610 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2611 goto skip_link_setup;
2613 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2614 err = hw->mac.ops.setup_sfp(hw);
2619 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2620 /* Turn on the copper */
2621 ixgbe_set_phy_power(hw, true);
2623 /* Turn on the laser */
2624 ixgbe_enable_tx_laser(hw);
2627 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2630 dev->data->dev_link.link_status = link_up;
2632 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2636 link_speeds = &dev->data->dev_conf.link_speeds;
2637 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2638 ETH_LINK_SPEED_10G)) {
2639 PMD_INIT_LOG(ERR, "Invalid link setting");
2644 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2645 switch (hw->mac.type) {
2646 case ixgbe_mac_82598EB:
2647 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2649 case ixgbe_mac_82599EB:
2650 case ixgbe_mac_X540:
2651 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2653 case ixgbe_mac_X550:
2654 case ixgbe_mac_X550EM_x:
2655 case ixgbe_mac_X550EM_a:
2656 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2659 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2662 if (*link_speeds & ETH_LINK_SPEED_10G)
2663 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2664 if (*link_speeds & ETH_LINK_SPEED_1G)
2665 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2666 if (*link_speeds & ETH_LINK_SPEED_100M)
2667 speed |= IXGBE_LINK_SPEED_100_FULL;
2670 err = ixgbe_setup_link(hw, speed, link_up);
2676 if (rte_intr_allow_others(intr_handle)) {
2677 /* check if lsc interrupt is enabled */
2678 if (dev->data->dev_conf.intr_conf.lsc != 0)
2679 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2681 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2682 ixgbe_dev_macsec_interrupt_setup(dev);
2684 rte_intr_callback_unregister(intr_handle,
2685 ixgbe_dev_interrupt_handler, dev);
2686 if (dev->data->dev_conf.intr_conf.lsc != 0)
2687 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2688 " no intr multiplex");
2691 /* check if rxq interrupt is enabled */
2692 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2693 rte_intr_dp_is_en(intr_handle))
2694 ixgbe_dev_rxq_interrupt_setup(dev);
2696 /* enable uio/vfio intr/eventfd mapping */
2697 rte_intr_enable(intr_handle);
2699 /* resume enabled intr since hw reset */
2700 ixgbe_enable_intr(dev);
2701 ixgbe_l2_tunnel_conf(dev);
2702 ixgbe_filter_restore(dev);
2704 if (tm_conf->root && !tm_conf->committed)
2705 PMD_DRV_LOG(WARNING,
2706 "please call hierarchy_commit() "
2707 "before starting the port");
2712 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2713 ixgbe_dev_clear_queues(dev);
2718 * Stop device: disable rx and tx functions to allow for reconfiguring.
2721 ixgbe_dev_stop(struct rte_eth_dev *dev)
2723 struct rte_eth_link link;
2724 struct ixgbe_hw *hw =
2725 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726 struct ixgbe_vf_info *vfinfo =
2727 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2728 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2729 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2731 struct ixgbe_tm_conf *tm_conf =
2732 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2734 PMD_INIT_FUNC_TRACE();
2736 /* disable interrupts */
2737 ixgbe_disable_intr(hw);
2740 ixgbe_pf_reset_hw(hw);
2741 hw->adapter_stopped = 0;
2744 ixgbe_stop_adapter(hw);
2746 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2747 vfinfo[vf].clear_to_send = false;
2749 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2750 /* Turn off the copper */
2751 ixgbe_set_phy_power(hw, false);
2753 /* Turn off the laser */
2754 ixgbe_disable_tx_laser(hw);
2757 ixgbe_dev_clear_queues(dev);
2759 /* Clear stored conf */
2760 dev->data->scattered_rx = 0;
2763 /* Clear recorded link status */
2764 memset(&link, 0, sizeof(link));
2765 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2767 if (!rte_intr_allow_others(intr_handle))
2768 /* resume to the default handler */
2769 rte_intr_callback_register(intr_handle,
2770 ixgbe_dev_interrupt_handler,
2773 /* Clean datapath event and queue/vec mapping */
2774 rte_intr_efd_disable(intr_handle);
2775 if (intr_handle->intr_vec != NULL) {
2776 rte_free(intr_handle->intr_vec);
2777 intr_handle->intr_vec = NULL;
2780 /* reset hierarchy commit */
2781 tm_conf->committed = false;
2785 * Set device link up: enable tx.
2788 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2790 struct ixgbe_hw *hw =
2791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792 if (hw->mac.type == ixgbe_mac_82599EB) {
2793 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2794 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2795 /* Not suported in bypass mode */
2796 PMD_INIT_LOG(ERR, "Set link up is not supported "
2797 "by device id 0x%x", hw->device_id);
2803 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2804 /* Turn on the copper */
2805 ixgbe_set_phy_power(hw, true);
2807 /* Turn on the laser */
2808 ixgbe_enable_tx_laser(hw);
2815 * Set device link down: disable tx.
2818 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2820 struct ixgbe_hw *hw =
2821 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822 if (hw->mac.type == ixgbe_mac_82599EB) {
2823 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2824 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2825 /* Not suported in bypass mode */
2826 PMD_INIT_LOG(ERR, "Set link down is not supported "
2827 "by device id 0x%x", hw->device_id);
2833 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2834 /* Turn off the copper */
2835 ixgbe_set_phy_power(hw, false);
2837 /* Turn off the laser */
2838 ixgbe_disable_tx_laser(hw);
2845 * Reset and stop device.
2848 ixgbe_dev_close(struct rte_eth_dev *dev)
2850 struct ixgbe_hw *hw =
2851 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853 PMD_INIT_FUNC_TRACE();
2855 ixgbe_pf_reset_hw(hw);
2857 ixgbe_dev_stop(dev);
2858 hw->adapter_stopped = 1;
2860 ixgbe_dev_free_queues(dev);
2862 ixgbe_disable_pcie_master(hw);
2864 /* reprogram the RAR[0] in case user changed it. */
2865 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2872 ixgbe_dev_reset(struct rte_eth_dev *dev)
2876 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2877 * its VF to make them align with it. The detailed notification
2878 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2879 * To avoid unexpected behavior in VF, currently reset of PF with
2880 * SR-IOV activation is not supported. It might be supported later.
2882 if (dev->data->sriov.active)
2885 ret = eth_ixgbe_dev_uninit(dev);
2889 ret = eth_ixgbe_dev_init(dev);
2895 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2896 struct ixgbe_hw_stats *hw_stats,
2897 struct ixgbe_macsec_stats *macsec_stats,
2898 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2899 uint64_t *total_qprc, uint64_t *total_qprdc)
2901 uint32_t bprc, lxon, lxoff, total;
2902 uint32_t delta_gprc = 0;
2904 /* Workaround for RX byte count not including CRC bytes when CRC
2905 * strip is enabled. CRC bytes are removed from counters when crc_strip
2908 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2909 IXGBE_HLREG0_RXCRCSTRP);
2911 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2912 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2913 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2914 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2916 for (i = 0; i < 8; i++) {
2917 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2919 /* global total per queue */
2920 hw_stats->mpc[i] += mp;
2921 /* Running comprehensive total for stats display */
2922 *total_missed_rx += hw_stats->mpc[i];
2923 if (hw->mac.type == ixgbe_mac_82598EB) {
2924 hw_stats->rnbc[i] +=
2925 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2926 hw_stats->pxonrxc[i] +=
2927 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2928 hw_stats->pxoffrxc[i] +=
2929 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2931 hw_stats->pxonrxc[i] +=
2932 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2933 hw_stats->pxoffrxc[i] +=
2934 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2935 hw_stats->pxon2offc[i] +=
2936 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2938 hw_stats->pxontxc[i] +=
2939 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2940 hw_stats->pxofftxc[i] +=
2941 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2943 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2944 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2945 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2946 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2948 delta_gprc += delta_qprc;
2950 hw_stats->qprc[i] += delta_qprc;
2951 hw_stats->qptc[i] += delta_qptc;
2953 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2954 hw_stats->qbrc[i] +=
2955 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2957 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2959 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2960 hw_stats->qbtc[i] +=
2961 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2963 hw_stats->qprdc[i] += delta_qprdc;
2964 *total_qprdc += hw_stats->qprdc[i];
2966 *total_qprc += hw_stats->qprc[i];
2967 *total_qbrc += hw_stats->qbrc[i];
2969 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2970 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2971 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2974 * An errata states that gprc actually counts good + missed packets:
2975 * Workaround to set gprc to summated queue packet receives
2977 hw_stats->gprc = *total_qprc;
2979 if (hw->mac.type != ixgbe_mac_82598EB) {
2980 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2981 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2982 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2983 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2984 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2985 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2986 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2987 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2989 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2990 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2991 /* 82598 only has a counter in the high register */
2992 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2993 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2994 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2996 uint64_t old_tpr = hw_stats->tpr;
2998 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2999 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3002 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3004 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3005 hw_stats->gptc += delta_gptc;
3006 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3007 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3010 * Workaround: mprc hardware is incorrectly counting
3011 * broadcasts, so for now we subtract those.
3013 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3014 hw_stats->bprc += bprc;
3015 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3016 if (hw->mac.type == ixgbe_mac_82598EB)
3017 hw_stats->mprc -= bprc;
3019 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3020 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3021 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3022 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3023 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3024 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3026 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3027 hw_stats->lxontxc += lxon;
3028 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3029 hw_stats->lxofftxc += lxoff;
3030 total = lxon + lxoff;
3032 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3033 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3034 hw_stats->gptc -= total;
3035 hw_stats->mptc -= total;
3036 hw_stats->ptc64 -= total;
3037 hw_stats->gotc -= total * ETHER_MIN_LEN;
3039 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3040 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3041 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3042 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3043 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3044 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3045 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3046 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3047 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3048 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3049 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3050 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3051 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3052 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3053 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3054 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3055 /* Only read FCOE on 82599 */
3056 if (hw->mac.type != ixgbe_mac_82598EB) {
3057 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3058 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3059 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3060 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3061 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3064 /* Flow Director Stats registers */
3065 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3066 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3068 /* MACsec Stats registers */
3069 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3070 macsec_stats->out_pkts_encrypted +=
3071 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3072 macsec_stats->out_pkts_protected +=
3073 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3074 macsec_stats->out_octets_encrypted +=
3075 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3076 macsec_stats->out_octets_protected +=
3077 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3078 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3079 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3080 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3081 macsec_stats->in_pkts_unknownsci +=
3082 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3083 macsec_stats->in_octets_decrypted +=
3084 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3085 macsec_stats->in_octets_validated +=
3086 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3087 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3088 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3089 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3090 for (i = 0; i < 2; i++) {
3091 macsec_stats->in_pkts_ok +=
3092 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3093 macsec_stats->in_pkts_invalid +=
3094 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3095 macsec_stats->in_pkts_notvalid +=
3096 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3098 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3099 macsec_stats->in_pkts_notusingsa +=
3100 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3104 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3107 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3109 struct ixgbe_hw *hw =
3110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3111 struct ixgbe_hw_stats *hw_stats =
3112 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113 struct ixgbe_macsec_stats *macsec_stats =
3114 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3115 dev->data->dev_private);
3116 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3119 total_missed_rx = 0;
3124 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3125 &total_qbrc, &total_qprc, &total_qprdc);
3130 /* Fill out the rte_eth_stats statistics structure */
3131 stats->ipackets = total_qprc;
3132 stats->ibytes = total_qbrc;
3133 stats->opackets = hw_stats->gptc;
3134 stats->obytes = hw_stats->gotc;
3136 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3137 stats->q_ipackets[i] = hw_stats->qprc[i];
3138 stats->q_opackets[i] = hw_stats->qptc[i];
3139 stats->q_ibytes[i] = hw_stats->qbrc[i];
3140 stats->q_obytes[i] = hw_stats->qbtc[i];
3141 stats->q_errors[i] = hw_stats->qprdc[i];
3145 stats->imissed = total_missed_rx;
3146 stats->ierrors = hw_stats->crcerrs +
3162 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3164 struct ixgbe_hw_stats *stats =
3165 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3167 /* HW registers are cleared on read */
3168 ixgbe_dev_stats_get(dev, NULL);
3170 /* Reset software totals */
3171 memset(stats, 0, sizeof(*stats));
3174 /* This function calculates the number of xstats based on the current config */
3176 ixgbe_xstats_calc_num(void) {
3177 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3178 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3179 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3182 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3183 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3185 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3186 unsigned stat, i, count;
3188 if (xstats_names != NULL) {
3191 /* Note: limit >= cnt_stats checked upstream
3192 * in rte_eth_xstats_names()
3195 /* Extended stats from ixgbe_hw_stats */
3196 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3197 snprintf(xstats_names[count].name,
3198 sizeof(xstats_names[count].name),
3200 rte_ixgbe_stats_strings[i].name);
3205 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3206 snprintf(xstats_names[count].name,
3207 sizeof(xstats_names[count].name),
3209 rte_ixgbe_macsec_strings[i].name);
3213 /* RX Priority Stats */
3214 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3215 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3216 snprintf(xstats_names[count].name,
3217 sizeof(xstats_names[count].name),
3218 "rx_priority%u_%s", i,
3219 rte_ixgbe_rxq_strings[stat].name);
3224 /* TX Priority Stats */
3225 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3226 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3227 snprintf(xstats_names[count].name,
3228 sizeof(xstats_names[count].name),
3229 "tx_priority%u_%s", i,
3230 rte_ixgbe_txq_strings[stat].name);
3238 static int ixgbe_dev_xstats_get_names_by_id(
3239 struct rte_eth_dev *dev,
3240 struct rte_eth_xstat_name *xstats_names,
3241 const uint64_t *ids,
3245 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3246 unsigned int stat, i, count;
3248 if (xstats_names != NULL) {
3251 /* Note: limit >= cnt_stats checked upstream
3252 * in rte_eth_xstats_names()
3255 /* Extended stats from ixgbe_hw_stats */
3256 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3257 snprintf(xstats_names[count].name,
3258 sizeof(xstats_names[count].name),
3260 rte_ixgbe_stats_strings[i].name);
3265 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3266 snprintf(xstats_names[count].name,
3267 sizeof(xstats_names[count].name),
3269 rte_ixgbe_macsec_strings[i].name);
3273 /* RX Priority Stats */
3274 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3275 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3276 snprintf(xstats_names[count].name,
3277 sizeof(xstats_names[count].name),
3278 "rx_priority%u_%s", i,
3279 rte_ixgbe_rxq_strings[stat].name);
3284 /* TX Priority Stats */
3285 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3286 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3287 snprintf(xstats_names[count].name,
3288 sizeof(xstats_names[count].name),
3289 "tx_priority%u_%s", i,
3290 rte_ixgbe_txq_strings[stat].name);
3299 uint16_t size = ixgbe_xstats_calc_num();
3300 struct rte_eth_xstat_name xstats_names_copy[size];
3302 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3305 for (i = 0; i < limit; i++) {
3306 if (ids[i] >= size) {
3307 PMD_INIT_LOG(ERR, "id value isn't valid");
3310 strcpy(xstats_names[i].name,
3311 xstats_names_copy[ids[i]].name);
3316 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3317 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3321 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3324 if (xstats_names != NULL)
3325 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3326 snprintf(xstats_names[i].name,
3327 sizeof(xstats_names[i].name),
3328 "%s", rte_ixgbevf_stats_strings[i].name);
3329 return IXGBEVF_NB_XSTATS;
3333 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3336 struct ixgbe_hw *hw =
3337 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338 struct ixgbe_hw_stats *hw_stats =
3339 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3340 struct ixgbe_macsec_stats *macsec_stats =
3341 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3342 dev->data->dev_private);
3343 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3344 unsigned i, stat, count = 0;
3346 count = ixgbe_xstats_calc_num();
3351 total_missed_rx = 0;
3356 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3357 &total_qbrc, &total_qprc, &total_qprdc);
3359 /* If this is a reset xstats is NULL, and we have cleared the
3360 * registers by reading them.
3365 /* Extended stats from ixgbe_hw_stats */
3367 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3368 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3369 rte_ixgbe_stats_strings[i].offset);
3370 xstats[count].id = count;
3375 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3376 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3377 rte_ixgbe_macsec_strings[i].offset);
3378 xstats[count].id = count;
3382 /* RX Priority Stats */
3383 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3384 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3385 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3386 rte_ixgbe_rxq_strings[stat].offset +
3387 (sizeof(uint64_t) * i));
3388 xstats[count].id = count;
3393 /* TX Priority Stats */
3394 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3395 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3396 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3397 rte_ixgbe_txq_strings[stat].offset +
3398 (sizeof(uint64_t) * i));
3399 xstats[count].id = count;
3407 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3408 uint64_t *values, unsigned int n)
3411 struct ixgbe_hw *hw =
3412 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413 struct ixgbe_hw_stats *hw_stats =
3414 IXGBE_DEV_PRIVATE_TO_STATS(
3415 dev->data->dev_private);
3416 struct ixgbe_macsec_stats *macsec_stats =
3417 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3418 dev->data->dev_private);
3419 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3420 unsigned int i, stat, count = 0;
3422 count = ixgbe_xstats_calc_num();
3424 if (!ids && n < count)
3427 total_missed_rx = 0;
3432 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3433 &total_missed_rx, &total_qbrc, &total_qprc,
3436 /* If this is a reset xstats is NULL, and we have cleared the
3437 * registers by reading them.
3439 if (!ids && !values)
3442 /* Extended stats from ixgbe_hw_stats */
3444 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3445 values[count] = *(uint64_t *)(((char *)hw_stats) +
3446 rte_ixgbe_stats_strings[i].offset);
3451 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3452 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3453 rte_ixgbe_macsec_strings[i].offset);
3457 /* RX Priority Stats */
3458 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3459 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3461 *(uint64_t *)(((char *)hw_stats) +
3462 rte_ixgbe_rxq_strings[stat].offset +
3463 (sizeof(uint64_t) * i));
3468 /* TX Priority Stats */
3469 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3470 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3472 *(uint64_t *)(((char *)hw_stats) +
3473 rte_ixgbe_txq_strings[stat].offset +
3474 (sizeof(uint64_t) * i));
3482 uint16_t size = ixgbe_xstats_calc_num();
3483 uint64_t values_copy[size];
3485 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3487 for (i = 0; i < n; i++) {
3488 if (ids[i] >= size) {
3489 PMD_INIT_LOG(ERR, "id value isn't valid");
3492 values[i] = values_copy[ids[i]];
3498 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3500 struct ixgbe_hw_stats *stats =
3501 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3502 struct ixgbe_macsec_stats *macsec_stats =
3503 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3504 dev->data->dev_private);
3506 unsigned count = ixgbe_xstats_calc_num();
3508 /* HW registers are cleared on read */
3509 ixgbe_dev_xstats_get(dev, NULL, count);
3511 /* Reset software totals */
3512 memset(stats, 0, sizeof(*stats));
3513 memset(macsec_stats, 0, sizeof(*macsec_stats));
3517 ixgbevf_update_stats(struct rte_eth_dev *dev)
3519 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3521 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3523 /* Good Rx packet, include VF loopback */
3524 UPDATE_VF_STAT(IXGBE_VFGPRC,
3525 hw_stats->last_vfgprc, hw_stats->vfgprc);
3527 /* Good Rx octets, include VF loopback */
3528 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3529 hw_stats->last_vfgorc, hw_stats->vfgorc);
3531 /* Good Tx packet, include VF loopback */
3532 UPDATE_VF_STAT(IXGBE_VFGPTC,
3533 hw_stats->last_vfgptc, hw_stats->vfgptc);
3535 /* Good Tx octets, include VF loopback */
3536 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3537 hw_stats->last_vfgotc, hw_stats->vfgotc);
3539 /* Rx Multicst Packet */
3540 UPDATE_VF_STAT(IXGBE_VFMPRC,
3541 hw_stats->last_vfmprc, hw_stats->vfmprc);
3545 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3548 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552 if (n < IXGBEVF_NB_XSTATS)
3553 return IXGBEVF_NB_XSTATS;
3555 ixgbevf_update_stats(dev);
3560 /* Extended stats */
3561 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3563 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3564 rte_ixgbevf_stats_strings[i].offset);
3567 return IXGBEVF_NB_XSTATS;
3571 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3573 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3574 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3576 ixgbevf_update_stats(dev);
3581 stats->ipackets = hw_stats->vfgprc;
3582 stats->ibytes = hw_stats->vfgorc;
3583 stats->opackets = hw_stats->vfgptc;
3584 stats->obytes = hw_stats->vfgotc;
3588 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3590 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3591 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3593 /* Sync HW register to the last stats */
3594 ixgbevf_dev_stats_get(dev, NULL);
3596 /* reset HW current stats*/
3597 hw_stats->vfgprc = 0;
3598 hw_stats->vfgorc = 0;
3599 hw_stats->vfgptc = 0;
3600 hw_stats->vfgotc = 0;
3604 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3606 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607 u16 eeprom_verh, eeprom_verl;
3611 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3612 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3614 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3615 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3617 ret += 1; /* add the size of '\0' */
3618 if (fw_size < (u32)ret)
3625 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3627 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3628 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3629 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3631 dev_info->pci_dev = pci_dev;
3632 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3633 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3634 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3636 * When DCB/VT is off, maximum number of queues changes,
3637 * except for 82598EB, which remains constant.
3639 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3640 hw->mac.type != ixgbe_mac_82598EB)
3641 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3643 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3644 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3645 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3646 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3647 dev_info->max_vfs = pci_dev->max_vfs;
3648 if (hw->mac.type == ixgbe_mac_82598EB)
3649 dev_info->max_vmdq_pools = ETH_16_POOLS;
3651 dev_info->max_vmdq_pools = ETH_64_POOLS;
3652 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3653 dev_info->rx_offload_capa =
3654 DEV_RX_OFFLOAD_VLAN_STRIP |
3655 DEV_RX_OFFLOAD_IPV4_CKSUM |
3656 DEV_RX_OFFLOAD_UDP_CKSUM |
3657 DEV_RX_OFFLOAD_TCP_CKSUM;
3660 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3663 if ((hw->mac.type == ixgbe_mac_82599EB ||
3664 hw->mac.type == ixgbe_mac_X540) &&
3665 !RTE_ETH_DEV_SRIOV(dev).active)
3666 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3668 if (hw->mac.type == ixgbe_mac_82599EB ||
3669 hw->mac.type == ixgbe_mac_X540)
3670 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3672 if (hw->mac.type == ixgbe_mac_X550 ||
3673 hw->mac.type == ixgbe_mac_X550EM_x ||
3674 hw->mac.type == ixgbe_mac_X550EM_a)
3675 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3677 dev_info->tx_offload_capa =
3678 DEV_TX_OFFLOAD_VLAN_INSERT |
3679 DEV_TX_OFFLOAD_IPV4_CKSUM |
3680 DEV_TX_OFFLOAD_UDP_CKSUM |
3681 DEV_TX_OFFLOAD_TCP_CKSUM |
3682 DEV_TX_OFFLOAD_SCTP_CKSUM |
3683 DEV_TX_OFFLOAD_TCP_TSO;
3685 if (hw->mac.type == ixgbe_mac_82599EB ||
3686 hw->mac.type == ixgbe_mac_X540)
3687 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3689 if (hw->mac.type == ixgbe_mac_X550 ||
3690 hw->mac.type == ixgbe_mac_X550EM_x ||
3691 hw->mac.type == ixgbe_mac_X550EM_a)
3692 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3694 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3696 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3697 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3698 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3700 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3704 dev_info->default_txconf = (struct rte_eth_txconf) {
3706 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3707 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3708 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3710 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3711 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3712 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3713 ETH_TXQ_FLAGS_NOOFFLOADS,
3716 dev_info->rx_desc_lim = rx_desc_lim;
3717 dev_info->tx_desc_lim = tx_desc_lim;
3719 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3720 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3721 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3723 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3724 if (hw->mac.type == ixgbe_mac_X540 ||
3725 hw->mac.type == ixgbe_mac_X540_vf ||
3726 hw->mac.type == ixgbe_mac_X550 ||
3727 hw->mac.type == ixgbe_mac_X550_vf) {
3728 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3730 if (hw->mac.type == ixgbe_mac_X550) {
3731 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3732 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3736 static const uint32_t *
3737 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3739 static const uint32_t ptypes[] = {
3740 /* For non-vec functions,
3741 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3742 * for vec functions,
3743 * refers to _recv_raw_pkts_vec().
3747 RTE_PTYPE_L3_IPV4_EXT,
3749 RTE_PTYPE_L3_IPV6_EXT,
3753 RTE_PTYPE_TUNNEL_IP,
3754 RTE_PTYPE_INNER_L3_IPV6,
3755 RTE_PTYPE_INNER_L3_IPV6_EXT,
3756 RTE_PTYPE_INNER_L4_TCP,
3757 RTE_PTYPE_INNER_L4_UDP,
3761 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3762 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3763 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3764 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3767 #if defined(RTE_ARCH_X86)
3768 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3769 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3776 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3777 struct rte_eth_dev_info *dev_info)
3779 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 dev_info->pci_dev = pci_dev;
3783 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3784 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3785 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3786 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3787 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3788 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3789 dev_info->max_vfs = pci_dev->max_vfs;
3790 if (hw->mac.type == ixgbe_mac_82598EB)
3791 dev_info->max_vmdq_pools = ETH_16_POOLS;
3793 dev_info->max_vmdq_pools = ETH_64_POOLS;
3794 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3795 DEV_RX_OFFLOAD_IPV4_CKSUM |
3796 DEV_RX_OFFLOAD_UDP_CKSUM |
3797 DEV_RX_OFFLOAD_TCP_CKSUM;
3798 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3799 DEV_TX_OFFLOAD_IPV4_CKSUM |
3800 DEV_TX_OFFLOAD_UDP_CKSUM |
3801 DEV_TX_OFFLOAD_TCP_CKSUM |
3802 DEV_TX_OFFLOAD_SCTP_CKSUM |
3803 DEV_TX_OFFLOAD_TCP_TSO;
3805 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3807 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3808 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3809 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3811 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3815 dev_info->default_txconf = (struct rte_eth_txconf) {
3817 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3818 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3819 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3821 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3822 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3823 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3824 ETH_TXQ_FLAGS_NOOFFLOADS,
3827 dev_info->rx_desc_lim = rx_desc_lim;
3828 dev_info->tx_desc_lim = tx_desc_lim;
3832 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3833 int *link_up, int wait_to_complete)
3836 * for a quick link status checking, wait_to_compelet == 0,
3837 * skip PF link status checking
3839 bool no_pflink_check = wait_to_complete == 0;
3840 struct ixgbe_mbx_info *mbx = &hw->mbx;
3841 struct ixgbe_mac_info *mac = &hw->mac;
3842 uint32_t links_reg, in_msg;
3845 /* If we were hit with a reset drop the link */
3846 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3847 mac->get_link_status = true;
3849 if (!mac->get_link_status)
3852 /* if link status is down no point in checking to see if pf is up */
3853 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3854 if (!(links_reg & IXGBE_LINKS_UP))
3857 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3858 * before the link status is correct
3860 if (mac->type == ixgbe_mac_82599_vf) {
3863 for (i = 0; i < 5; i++) {
3865 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3867 if (!(links_reg & IXGBE_LINKS_UP))
3872 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3873 case IXGBE_LINKS_SPEED_10G_82599:
3874 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3875 if (hw->mac.type >= ixgbe_mac_X550) {
3876 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3877 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3880 case IXGBE_LINKS_SPEED_1G_82599:
3881 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3883 case IXGBE_LINKS_SPEED_100_82599:
3884 *speed = IXGBE_LINK_SPEED_100_FULL;
3885 if (hw->mac.type == ixgbe_mac_X550) {
3886 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3887 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3890 case IXGBE_LINKS_SPEED_10_X550EM_A:
3891 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3892 /* Since Reserved in older MAC's */
3893 if (hw->mac.type >= ixgbe_mac_X550)
3894 *speed = IXGBE_LINK_SPEED_10_FULL;
3897 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3900 if (no_pflink_check) {
3901 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3902 mac->get_link_status = true;
3904 mac->get_link_status = false;
3908 /* if the read failed it could just be a mailbox collision, best wait
3909 * until we are called again and don't report an error
3911 if (mbx->ops.read(hw, &in_msg, 1, 0))
3914 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3915 /* msg is not CTS and is NACK we must have lost CTS status */
3916 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3921 /* the pf is talking, if we timed out in the past we reinit */
3922 if (!mbx->timeout) {
3927 /* if we passed all the tests above then the link is up and we no
3928 * longer need to check for link
3930 mac->get_link_status = false;
3933 *link_up = !mac->get_link_status;
3937 /* return 0 means link status changed, -1 means not changed */
3939 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3940 int wait_to_complete, int vf)
3942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943 struct rte_eth_link link, old;
3944 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3945 struct ixgbe_interrupt *intr =
3946 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3951 bool autoneg = false;
3953 link.link_status = ETH_LINK_DOWN;
3954 link.link_speed = 0;
3955 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3956 memset(&old, 0, sizeof(old));
3957 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3959 hw->mac.get_link_status = true;
3961 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3962 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3963 speed = hw->phy.autoneg_advertised;
3965 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3966 ixgbe_setup_link(hw, speed, true);
3969 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3970 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3974 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3976 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3979 link.link_speed = ETH_SPEED_NUM_100M;
3980 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3981 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3982 if (link.link_status == old.link_status)
3988 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3989 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3990 if (link.link_status == old.link_status)
3994 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3995 link.link_status = ETH_LINK_UP;
3996 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3998 switch (link_speed) {
4000 case IXGBE_LINK_SPEED_UNKNOWN:
4001 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4002 link.link_speed = ETH_SPEED_NUM_100M;
4005 case IXGBE_LINK_SPEED_100_FULL:
4006 link.link_speed = ETH_SPEED_NUM_100M;
4009 case IXGBE_LINK_SPEED_1GB_FULL:
4010 link.link_speed = ETH_SPEED_NUM_1G;
4013 case IXGBE_LINK_SPEED_2_5GB_FULL:
4014 link.link_speed = ETH_SPEED_NUM_2_5G;
4017 case IXGBE_LINK_SPEED_5GB_FULL:
4018 link.link_speed = ETH_SPEED_NUM_5G;
4021 case IXGBE_LINK_SPEED_10GB_FULL:
4022 link.link_speed = ETH_SPEED_NUM_10G;
4025 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4027 if (link.link_status == old.link_status)
4034 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4036 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4040 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4042 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4046 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4051 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4052 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4053 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4057 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4062 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4063 fctrl &= (~IXGBE_FCTRL_UPE);
4064 if (dev->data->all_multicast == 1)
4065 fctrl |= IXGBE_FCTRL_MPE;
4067 fctrl &= (~IXGBE_FCTRL_MPE);
4068 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4072 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4078 fctrl |= IXGBE_FCTRL_MPE;
4079 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4083 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4085 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088 if (dev->data->promiscuous == 1)
4089 return; /* must remain in all_multicast mode */
4091 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4092 fctrl &= (~IXGBE_FCTRL_MPE);
4093 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4097 * It clears the interrupt causes and enables the interrupt.
4098 * It will be called once only during nic initialized.
4101 * Pointer to struct rte_eth_dev.
4103 * Enable or Disable.
4106 * - On success, zero.
4107 * - On failure, a negative value.
4110 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4112 struct ixgbe_interrupt *intr =
4113 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4115 ixgbe_dev_link_status_print(dev);
4117 intr->mask |= IXGBE_EICR_LSC;
4119 intr->mask &= ~IXGBE_EICR_LSC;
4125 * It clears the interrupt causes and enables the interrupt.
4126 * It will be called once only during nic initialized.
4129 * Pointer to struct rte_eth_dev.
4132 * - On success, zero.
4133 * - On failure, a negative value.
4136 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4138 struct ixgbe_interrupt *intr =
4139 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4141 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4147 * It clears the interrupt causes and enables the interrupt.
4148 * It will be called once only during nic initialized.
4151 * Pointer to struct rte_eth_dev.
4154 * - On success, zero.
4155 * - On failure, a negative value.
4158 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4160 struct ixgbe_interrupt *intr =
4161 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4163 intr->mask |= IXGBE_EICR_LINKSEC;
4169 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4172 * Pointer to struct rte_eth_dev.
4175 * - On success, zero.
4176 * - On failure, a negative value.
4179 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4182 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4183 struct ixgbe_interrupt *intr =
4184 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4186 /* clear all cause mask */
4187 ixgbe_disable_intr(hw);
4189 /* read-on-clear nic registers here */
4190 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4191 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4195 /* set flag for async link update */
4196 if (eicr & IXGBE_EICR_LSC)
4197 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4199 if (eicr & IXGBE_EICR_MAILBOX)
4200 intr->flags |= IXGBE_FLAG_MAILBOX;
4202 if (eicr & IXGBE_EICR_LINKSEC)
4203 intr->flags |= IXGBE_FLAG_MACSEC;
4205 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4206 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4207 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4208 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4214 * It gets and then prints the link status.
4217 * Pointer to struct rte_eth_dev.
4220 * - On success, zero.
4221 * - On failure, a negative value.
4224 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4226 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4227 struct rte_eth_link link;
4229 memset(&link, 0, sizeof(link));
4230 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4231 if (link.link_status) {
4232 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4233 (int)(dev->data->port_id),
4234 (unsigned)link.link_speed,
4235 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4236 "full-duplex" : "half-duplex");
4238 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4239 (int)(dev->data->port_id));
4241 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4242 pci_dev->addr.domain,
4244 pci_dev->addr.devid,
4245 pci_dev->addr.function);
4249 * It executes link_update after knowing an interrupt occurred.
4252 * Pointer to struct rte_eth_dev.
4255 * - On success, zero.
4256 * - On failure, a negative value.
4259 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4260 struct rte_intr_handle *intr_handle)
4262 struct ixgbe_interrupt *intr =
4263 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4265 struct rte_eth_link link;
4266 struct ixgbe_hw *hw =
4267 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4271 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4272 ixgbe_pf_mbx_process(dev);
4273 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4276 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4277 ixgbe_handle_lasi(hw);
4278 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4281 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4282 /* get the link status before link update, for predicting later */
4283 memset(&link, 0, sizeof(link));
4284 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4286 ixgbe_dev_link_update(dev, 0);
4289 if (!link.link_status)
4290 /* handle it 1 sec later, wait it being stable */
4291 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4292 /* likely to down */
4294 /* handle it 4 sec later, wait it being stable */
4295 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4297 ixgbe_dev_link_status_print(dev);
4298 if (rte_eal_alarm_set(timeout * 1000,
4299 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4300 PMD_DRV_LOG(ERR, "Error setting alarm");
4302 /* remember original mask */
4303 intr->mask_original = intr->mask;
4304 /* only disable lsc interrupt */
4305 intr->mask &= ~IXGBE_EIMS_LSC;
4309 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4310 ixgbe_enable_intr(dev);
4311 rte_intr_enable(intr_handle);
4317 * Interrupt handler which shall be registered for alarm callback for delayed
4318 * handling specific interrupt to wait for the stable nic state. As the
4319 * NIC interrupt state is not stable for ixgbe after link is just down,
4320 * it needs to wait 4 seconds to get the stable status.
4323 * Pointer to interrupt handle.
4325 * The address of parameter (struct rte_eth_dev *) regsitered before.
4331 ixgbe_dev_interrupt_delayed_handler(void *param)
4333 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4334 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4335 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4336 struct ixgbe_interrupt *intr =
4337 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4338 struct ixgbe_hw *hw =
4339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342 ixgbe_disable_intr(hw);
4344 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4345 if (eicr & IXGBE_EICR_MAILBOX)
4346 ixgbe_pf_mbx_process(dev);
4348 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4349 ixgbe_handle_lasi(hw);
4350 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4353 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4354 ixgbe_dev_link_update(dev, 0);
4355 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4356 ixgbe_dev_link_status_print(dev);
4357 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4361 if (intr->flags & IXGBE_FLAG_MACSEC) {
4362 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4364 intr->flags &= ~IXGBE_FLAG_MACSEC;
4367 /* restore original mask */
4368 intr->mask = intr->mask_original;
4369 intr->mask_original = 0;
4371 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4372 ixgbe_enable_intr(dev);
4373 rte_intr_enable(intr_handle);
4377 * Interrupt handler triggered by NIC for handling
4378 * specific interrupt.
4381 * Pointer to interrupt handle.
4383 * The address of parameter (struct rte_eth_dev *) regsitered before.
4389 ixgbe_dev_interrupt_handler(void *param)
4391 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4393 ixgbe_dev_interrupt_get_status(dev);
4394 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4398 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4400 struct ixgbe_hw *hw;
4402 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4403 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4407 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4409 struct ixgbe_hw *hw;
4411 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4416 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4418 struct ixgbe_hw *hw;
4424 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426 fc_conf->pause_time = hw->fc.pause_time;
4427 fc_conf->high_water = hw->fc.high_water[0];
4428 fc_conf->low_water = hw->fc.low_water[0];
4429 fc_conf->send_xon = hw->fc.send_xon;
4430 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4433 * Return rx_pause status according to actual setting of
4436 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4437 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4443 * Return tx_pause status according to actual setting of
4446 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4447 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4452 if (rx_pause && tx_pause)
4453 fc_conf->mode = RTE_FC_FULL;
4455 fc_conf->mode = RTE_FC_RX_PAUSE;
4457 fc_conf->mode = RTE_FC_TX_PAUSE;
4459 fc_conf->mode = RTE_FC_NONE;
4465 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4467 struct ixgbe_hw *hw;
4469 uint32_t rx_buf_size;
4470 uint32_t max_high_water;
4472 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4479 PMD_INIT_FUNC_TRACE();
4481 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4483 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4486 * At least reserve one Ethernet frame for watermark
4487 * high_water/low_water in kilo bytes for ixgbe
4489 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4490 if ((fc_conf->high_water > max_high_water) ||
4491 (fc_conf->high_water < fc_conf->low_water)) {
4492 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4493 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4497 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4498 hw->fc.pause_time = fc_conf->pause_time;
4499 hw->fc.high_water[0] = fc_conf->high_water;
4500 hw->fc.low_water[0] = fc_conf->low_water;
4501 hw->fc.send_xon = fc_conf->send_xon;
4502 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4504 err = ixgbe_fc_enable(hw);
4506 /* Not negotiated is not an error case */
4507 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4509 /* check if we want to forward MAC frames - driver doesn't have native
4510 * capability to do that, so we'll write the registers ourselves */
4512 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4514 /* set or clear MFLCN.PMCF bit depending on configuration */
4515 if (fc_conf->mac_ctrl_frame_fwd != 0)
4516 mflcn |= IXGBE_MFLCN_PMCF;
4518 mflcn &= ~IXGBE_MFLCN_PMCF;
4520 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4521 IXGBE_WRITE_FLUSH(hw);
4526 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4531 * ixgbe_pfc_enable_generic - Enable flow control
4532 * @hw: pointer to hardware structure
4533 * @tc_num: traffic class number
4534 * Enable flow control according to the current settings.
4537 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4540 uint32_t mflcn_reg, fccfg_reg;
4542 uint32_t fcrtl, fcrth;
4546 /* Validate the water mark configuration */
4547 if (!hw->fc.pause_time) {
4548 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4552 /* Low water mark of zero causes XOFF floods */
4553 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4554 /* High/Low water can not be 0 */
4555 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4556 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4557 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4561 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4562 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4563 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4567 /* Negotiate the fc mode to use */
4568 ixgbe_fc_autoneg(hw);
4570 /* Disable any previous flow control settings */
4571 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4572 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4574 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4575 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4577 switch (hw->fc.current_mode) {
4580 * If the count of enabled RX Priority Flow control >1,
4581 * and the TX pause can not be disabled
4584 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4585 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4586 if (reg & IXGBE_FCRTH_FCEN)
4590 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4592 case ixgbe_fc_rx_pause:
4594 * Rx Flow control is enabled and Tx Flow control is
4595 * disabled by software override. Since there really
4596 * isn't a way to advertise that we are capable of RX
4597 * Pause ONLY, we will advertise that we support both
4598 * symmetric and asymmetric Rx PAUSE. Later, we will
4599 * disable the adapter's ability to send PAUSE frames.
4601 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4603 * If the count of enabled RX Priority Flow control >1,
4604 * and the TX pause can not be disabled
4607 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4608 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4609 if (reg & IXGBE_FCRTH_FCEN)
4613 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4615 case ixgbe_fc_tx_pause:
4617 * Tx Flow control is enabled, and Rx Flow control is
4618 * disabled by software override.
4620 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4623 /* Flow control (both Rx and Tx) is enabled by SW override. */
4624 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4625 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4628 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4629 ret_val = IXGBE_ERR_CONFIG;
4633 /* Set 802.3x based flow control settings. */
4634 mflcn_reg |= IXGBE_MFLCN_DPF;
4635 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4636 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4638 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4639 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4640 hw->fc.high_water[tc_num]) {
4641 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4642 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4643 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4645 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4647 * In order to prevent Tx hangs when the internal Tx
4648 * switch is enabled we must set the high water mark
4649 * to the maximum FCRTH value. This allows the Tx
4650 * switch to function even under heavy Rx workloads.
4652 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4654 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4656 /* Configure pause time (2 TCs per register) */
4657 reg = hw->fc.pause_time * 0x00010001;
4658 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4659 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4661 /* Configure flow control refresh threshold value */
4662 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4669 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4671 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4674 if (hw->mac.type != ixgbe_mac_82598EB) {
4675 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4681 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4684 uint32_t rx_buf_size;
4685 uint32_t max_high_water;
4687 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4688 struct ixgbe_hw *hw =
4689 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690 struct ixgbe_dcb_config *dcb_config =
4691 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4693 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4700 PMD_INIT_FUNC_TRACE();
4702 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4703 tc_num = map[pfc_conf->priority];
4704 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4705 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4707 * At least reserve one Ethernet frame for watermark
4708 * high_water/low_water in kilo bytes for ixgbe
4710 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4711 if ((pfc_conf->fc.high_water > max_high_water) ||
4712 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4713 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4714 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4718 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4719 hw->fc.pause_time = pfc_conf->fc.pause_time;
4720 hw->fc.send_xon = pfc_conf->fc.send_xon;
4721 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4722 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4724 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4726 /* Not negotiated is not an error case */
4727 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4730 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4735 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4736 struct rte_eth_rss_reta_entry64 *reta_conf,
4739 uint16_t i, sp_reta_size;
4742 uint16_t idx, shift;
4743 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746 PMD_INIT_FUNC_TRACE();
4748 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4749 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4754 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4755 if (reta_size != sp_reta_size) {
4756 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4757 "(%d) doesn't match the number hardware can supported "
4758 "(%d)", reta_size, sp_reta_size);
4762 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4763 idx = i / RTE_RETA_GROUP_SIZE;
4764 shift = i % RTE_RETA_GROUP_SIZE;
4765 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4769 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4770 if (mask == IXGBE_4_BIT_MASK)
4773 r = IXGBE_READ_REG(hw, reta_reg);
4774 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4775 if (mask & (0x1 << j))
4776 reta |= reta_conf[idx].reta[shift + j] <<
4779 reta |= r & (IXGBE_8_BIT_MASK <<
4782 IXGBE_WRITE_REG(hw, reta_reg, reta);
4789 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4790 struct rte_eth_rss_reta_entry64 *reta_conf,
4793 uint16_t i, sp_reta_size;
4796 uint16_t idx, shift;
4797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800 PMD_INIT_FUNC_TRACE();
4801 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4802 if (reta_size != sp_reta_size) {
4803 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4804 "(%d) doesn't match the number hardware can supported "
4805 "(%d)", reta_size, sp_reta_size);
4809 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4810 idx = i / RTE_RETA_GROUP_SIZE;
4811 shift = i % RTE_RETA_GROUP_SIZE;
4812 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4817 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4818 reta = IXGBE_READ_REG(hw, reta_reg);
4819 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4820 if (mask & (0x1 << j))
4821 reta_conf[idx].reta[shift + j] =
4822 ((reta >> (CHAR_BIT * j)) &
4831 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4832 uint32_t index, uint32_t pool)
4834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835 uint32_t enable_addr = 1;
4837 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4842 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846 ixgbe_clear_rar(hw, index);
4850 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4852 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4854 ixgbe_remove_rar(dev, 0);
4856 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4860 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4862 if (strcmp(dev->device->driver->name, drv->driver.name))
4869 is_ixgbe_supported(struct rte_eth_dev *dev)
4871 return is_device_supported(dev, &rte_ixgbe_pmd);
4875 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4879 struct ixgbe_hw *hw;
4880 struct rte_eth_dev_info dev_info;
4881 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4882 struct rte_eth_dev_data *dev_data = dev->data;
4884 ixgbe_dev_info_get(dev, &dev_info);
4886 /* check that mtu is within the allowed range */
4887 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4890 /* If device is started, refuse mtu that requires the support of
4891 * scattered packets when this feature has not been enabled before.
4893 if (dev_data->dev_started && !dev_data->scattered_rx &&
4894 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4895 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4896 PMD_INIT_LOG(ERR, "Stop port first.");
4900 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4903 /* switch to jumbo mode if needed */
4904 if (frame_size > ETHER_MAX_LEN) {
4905 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4906 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4908 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4909 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4911 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4913 /* update max frame size */
4914 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4916 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4917 maxfrs &= 0x0000FFFF;
4918 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4919 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4925 * Virtual Function operations
4928 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4930 PMD_INIT_FUNC_TRACE();
4932 /* Clear interrupt mask to stop from interrupts being generated */
4933 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4935 IXGBE_WRITE_FLUSH(hw);
4939 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4941 PMD_INIT_FUNC_TRACE();
4943 /* VF enable interrupt autoclean */
4944 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4945 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4946 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4948 IXGBE_WRITE_FLUSH(hw);
4952 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4954 struct rte_eth_conf *conf = &dev->data->dev_conf;
4955 struct ixgbe_adapter *adapter =
4956 (struct ixgbe_adapter *)dev->data->dev_private;
4958 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4959 dev->data->port_id);
4962 * VF has no ability to enable/disable HW CRC
4963 * Keep the persistent behavior the same as Host PF
4965 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4966 if (!conf->rxmode.hw_strip_crc) {
4967 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4968 conf->rxmode.hw_strip_crc = 1;
4971 if (conf->rxmode.hw_strip_crc) {
4972 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4973 conf->rxmode.hw_strip_crc = 0;
4978 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4979 * allocation or vector Rx preconditions we will reset it.
4981 adapter->rx_bulk_alloc_allowed = true;
4982 adapter->rx_vec_allowed = true;
4988 ixgbevf_dev_start(struct rte_eth_dev *dev)
4990 struct ixgbe_hw *hw =
4991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 uint32_t intr_vector = 0;
4993 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4994 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4998 PMD_INIT_FUNC_TRACE();
5000 hw->mac.ops.reset_hw(hw);
5001 hw->mac.get_link_status = true;
5003 /* negotiate mailbox API version to use with the PF. */
5004 ixgbevf_negotiate_api(hw);
5006 ixgbevf_dev_tx_init(dev);
5008 /* This can fail when allocating mbufs for descriptor rings */
5009 err = ixgbevf_dev_rx_init(dev);
5011 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5012 ixgbe_dev_clear_queues(dev);
5017 ixgbevf_set_vfta_all(dev, 1);
5020 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5021 ETH_VLAN_EXTEND_MASK;
5022 ixgbevf_vlan_offload_set(dev, mask);
5024 ixgbevf_dev_rxtx_start(dev);
5026 /* check and configure queue intr-vector mapping */
5027 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5028 intr_vector = dev->data->nb_rx_queues;
5029 if (rte_intr_efd_enable(intr_handle, intr_vector))
5033 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5034 intr_handle->intr_vec =
5035 rte_zmalloc("intr_vec",
5036 dev->data->nb_rx_queues * sizeof(int), 0);
5037 if (intr_handle->intr_vec == NULL) {
5038 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5039 " intr_vec", dev->data->nb_rx_queues);
5043 ixgbevf_configure_msix(dev);
5045 rte_intr_enable(intr_handle);
5047 /* Re-enable interrupt for VF */
5048 ixgbevf_intr_enable(hw);
5054 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5060 PMD_INIT_FUNC_TRACE();
5062 ixgbevf_intr_disable(hw);
5064 hw->adapter_stopped = 1;
5065 ixgbe_stop_adapter(hw);
5068 * Clear what we set, but we still keep shadow_vfta to
5069 * restore after device starts
5071 ixgbevf_set_vfta_all(dev, 0);
5073 /* Clear stored conf */
5074 dev->data->scattered_rx = 0;
5076 ixgbe_dev_clear_queues(dev);
5078 /* Clean datapath event and queue/vec mapping */
5079 rte_intr_efd_disable(intr_handle);
5080 if (intr_handle->intr_vec != NULL) {
5081 rte_free(intr_handle->intr_vec);
5082 intr_handle->intr_vec = NULL;
5087 ixgbevf_dev_close(struct rte_eth_dev *dev)
5089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5091 PMD_INIT_FUNC_TRACE();
5095 ixgbevf_dev_stop(dev);
5097 ixgbe_dev_free_queues(dev);
5100 * Remove the VF MAC address ro ensure
5101 * that the VF traffic goes to the PF
5102 * after stop, close and detach of the VF
5104 ixgbevf_remove_mac_addr(dev, 0);
5111 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5115 ret = eth_ixgbevf_dev_uninit(dev);
5119 ret = eth_ixgbevf_dev_init(dev);
5124 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127 struct ixgbe_vfta *shadow_vfta =
5128 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5129 int i = 0, j = 0, vfta = 0, mask = 1;
5131 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5132 vfta = shadow_vfta->vfta[i];
5135 for (j = 0; j < 32; j++) {
5137 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5147 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5149 struct ixgbe_hw *hw =
5150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151 struct ixgbe_vfta *shadow_vfta =
5152 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5153 uint32_t vid_idx = 0;
5154 uint32_t vid_bit = 0;
5157 PMD_INIT_FUNC_TRACE();
5159 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5160 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5162 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5165 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5166 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5168 /* Save what we set and retore it after device reset */
5170 shadow_vfta->vfta[vid_idx] |= vid_bit;
5172 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5178 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5180 struct ixgbe_hw *hw =
5181 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5184 PMD_INIT_FUNC_TRACE();
5186 if (queue >= hw->mac.max_rx_queues)
5189 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5191 ctrl |= IXGBE_RXDCTL_VME;
5193 ctrl &= ~IXGBE_RXDCTL_VME;
5194 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5196 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5200 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5202 struct ixgbe_hw *hw =
5203 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207 /* VF function only support hw strip feature, others are not support */
5208 if (mask & ETH_VLAN_STRIP_MASK) {
5209 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5211 for (i = 0; i < hw->mac.max_rx_queues; i++)
5212 ixgbevf_vlan_strip_queue_set(dev, i, on);
5217 ixgbe_vt_check(struct ixgbe_hw *hw)
5221 /* if Virtualization Technology is enabled */
5222 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5223 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5224 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5232 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5234 uint32_t vector = 0;
5236 switch (hw->mac.mc_filter_type) {
5237 case 0: /* use bits [47:36] of the address */
5238 vector = ((uc_addr->addr_bytes[4] >> 4) |
5239 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5241 case 1: /* use bits [46:35] of the address */
5242 vector = ((uc_addr->addr_bytes[4] >> 3) |
5243 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5245 case 2: /* use bits [45:34] of the address */
5246 vector = ((uc_addr->addr_bytes[4] >> 2) |
5247 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5249 case 3: /* use bits [43:32] of the address */
5250 vector = ((uc_addr->addr_bytes[4]) |
5251 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5253 default: /* Invalid mc_filter_type */
5257 /* vector can only be 12-bits or boundary will be exceeded */
5263 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5271 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5272 const uint32_t ixgbe_uta_bit_shift = 5;
5273 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5274 const uint32_t bit1 = 0x1;
5276 struct ixgbe_hw *hw =
5277 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278 struct ixgbe_uta_info *uta_info =
5279 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5281 /* The UTA table only exists on 82599 hardware and newer */
5282 if (hw->mac.type < ixgbe_mac_82599EB)
5285 vector = ixgbe_uta_vector(hw, mac_addr);
5286 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5287 uta_shift = vector & ixgbe_uta_bit_mask;
5289 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5293 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5295 uta_info->uta_in_use++;
5296 reg_val |= (bit1 << uta_shift);
5297 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5299 uta_info->uta_in_use--;
5300 reg_val &= ~(bit1 << uta_shift);
5301 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5304 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5306 if (uta_info->uta_in_use > 0)
5307 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5308 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5310 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5316 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5319 struct ixgbe_hw *hw =
5320 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321 struct ixgbe_uta_info *uta_info =
5322 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5324 /* The UTA table only exists on 82599 hardware and newer */
5325 if (hw->mac.type < ixgbe_mac_82599EB)
5329 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5330 uta_info->uta_shadow[i] = ~0;
5331 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5334 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5335 uta_info->uta_shadow[i] = 0;
5336 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5344 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5346 uint32_t new_val = orig_val;
5348 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5349 new_val |= IXGBE_VMOLR_AUPE;
5350 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5351 new_val |= IXGBE_VMOLR_ROMPE;
5352 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5353 new_val |= IXGBE_VMOLR_ROPE;
5354 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5355 new_val |= IXGBE_VMOLR_BAM;
5356 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5357 new_val |= IXGBE_VMOLR_MPE;
5362 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5363 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5364 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5365 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5366 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5367 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5368 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5371 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5372 struct rte_eth_mirror_conf *mirror_conf,
5373 uint8_t rule_id, uint8_t on)
5375 uint32_t mr_ctl, vlvf;
5376 uint32_t mp_lsb = 0;
5377 uint32_t mv_msb = 0;
5378 uint32_t mv_lsb = 0;
5379 uint32_t mp_msb = 0;
5382 uint64_t vlan_mask = 0;
5384 const uint8_t pool_mask_offset = 32;
5385 const uint8_t vlan_mask_offset = 32;
5386 const uint8_t dst_pool_offset = 8;
5387 const uint8_t rule_mr_offset = 4;
5388 const uint8_t mirror_rule_mask = 0x0F;
5390 struct ixgbe_mirror_info *mr_info =
5391 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5392 struct ixgbe_hw *hw =
5393 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394 uint8_t mirror_type = 0;
5396 if (ixgbe_vt_check(hw) < 0)
5399 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5402 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5403 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5404 mirror_conf->rule_type);
5408 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5409 mirror_type |= IXGBE_MRCTL_VLME;
5410 /* Check if vlan id is valid and find conresponding VLAN ID
5413 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5414 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5415 /* search vlan id related pool vlan filter
5418 reg_index = ixgbe_find_vlvf_slot(
5420 mirror_conf->vlan.vlan_id[i],
5424 vlvf = IXGBE_READ_REG(hw,
5425 IXGBE_VLVF(reg_index));
5426 if ((vlvf & IXGBE_VLVF_VIEN) &&
5427 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5428 mirror_conf->vlan.vlan_id[i]))
5429 vlan_mask |= (1ULL << reg_index);
5436 mv_lsb = vlan_mask & 0xFFFFFFFF;
5437 mv_msb = vlan_mask >> vlan_mask_offset;
5439 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5440 mirror_conf->vlan.vlan_mask;
5441 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5442 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5443 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5444 mirror_conf->vlan.vlan_id[i];
5449 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5450 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5451 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5456 * if enable pool mirror, write related pool mask register,if disable
5457 * pool mirror, clear PFMRVM register
5459 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5460 mirror_type |= IXGBE_MRCTL_VPME;
5462 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5463 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5464 mr_info->mr_conf[rule_id].pool_mask =
5465 mirror_conf->pool_mask;
5470 mr_info->mr_conf[rule_id].pool_mask = 0;
5473 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5474 mirror_type |= IXGBE_MRCTL_UPME;
5475 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5476 mirror_type |= IXGBE_MRCTL_DPME;
5478 /* read mirror control register and recalculate it */
5479 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5482 mr_ctl |= mirror_type;
5483 mr_ctl &= mirror_rule_mask;
5484 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5486 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5489 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5490 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5492 /* write mirrror control register */
5493 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5495 /* write pool mirrror control register */
5496 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5497 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5498 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5501 /* write VLAN mirrror control register */
5502 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5503 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5504 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5512 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5515 uint32_t lsb_val = 0;
5516 uint32_t msb_val = 0;
5517 const uint8_t rule_mr_offset = 4;
5519 struct ixgbe_hw *hw =
5520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521 struct ixgbe_mirror_info *mr_info =
5522 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5524 if (ixgbe_vt_check(hw) < 0)
5527 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5530 memset(&mr_info->mr_conf[rule_id], 0,
5531 sizeof(struct rte_eth_mirror_conf));
5533 /* clear PFVMCTL register */
5534 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5536 /* clear pool mask register */
5537 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5538 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5540 /* clear vlan mask register */
5541 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5542 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5548 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5553 struct ixgbe_hw *hw =
5554 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5556 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5557 mask |= (1 << IXGBE_MISC_VEC_ID);
5558 RTE_SET_USED(queue_id);
5559 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5561 rte_intr_enable(intr_handle);
5567 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5570 struct ixgbe_hw *hw =
5571 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5573 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5574 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5575 RTE_SET_USED(queue_id);
5576 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5582 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5584 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5585 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5587 struct ixgbe_hw *hw =
5588 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5589 struct ixgbe_interrupt *intr =
5590 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5592 if (queue_id < 16) {
5593 ixgbe_disable_intr(hw);
5594 intr->mask |= (1 << queue_id);
5595 ixgbe_enable_intr(dev);
5596 } else if (queue_id < 32) {
5597 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5598 mask &= (1 << queue_id);
5599 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5600 } else if (queue_id < 64) {
5601 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5602 mask &= (1 << (queue_id - 32));
5603 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5605 rte_intr_enable(intr_handle);
5611 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5614 struct ixgbe_hw *hw =
5615 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5616 struct ixgbe_interrupt *intr =
5617 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5619 if (queue_id < 16) {
5620 ixgbe_disable_intr(hw);
5621 intr->mask &= ~(1 << queue_id);
5622 ixgbe_enable_intr(dev);
5623 } else if (queue_id < 32) {
5624 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5625 mask &= ~(1 << queue_id);
5626 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5627 } else if (queue_id < 64) {
5628 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5629 mask &= ~(1 << (queue_id - 32));
5630 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5637 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5638 uint8_t queue, uint8_t msix_vector)
5642 if (direction == -1) {
5644 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5645 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5648 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5650 /* rx or tx cause */
5651 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5652 idx = ((16 * (queue & 1)) + (8 * direction));
5653 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5654 tmp &= ~(0xFF << idx);
5655 tmp |= (msix_vector << idx);
5656 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5661 * set the IVAR registers, mapping interrupt causes to vectors
5663 * pointer to ixgbe_hw struct
5665 * 0 for Rx, 1 for Tx, -1 for other causes
5667 * queue to map the corresponding interrupt to
5669 * the vector to map to the corresponding queue
5672 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5673 uint8_t queue, uint8_t msix_vector)
5677 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678 if (hw->mac.type == ixgbe_mac_82598EB) {
5679 if (direction == -1)
5681 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5682 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5683 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5684 tmp |= (msix_vector << (8 * (queue & 0x3)));
5685 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5686 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5687 (hw->mac.type == ixgbe_mac_X540) ||
5688 (hw->mac.type == ixgbe_mac_X550)) {
5689 if (direction == -1) {
5691 idx = ((queue & 1) * 8);
5692 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5693 tmp &= ~(0xFF << idx);
5694 tmp |= (msix_vector << idx);
5695 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5697 /* rx or tx causes */
5698 idx = ((16 * (queue & 1)) + (8 * direction));
5699 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5700 tmp &= ~(0xFF << idx);
5701 tmp |= (msix_vector << idx);
5702 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5708 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5710 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5711 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5712 struct ixgbe_hw *hw =
5713 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5715 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5717 /* Configure VF other cause ivar */
5718 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5720 /* won't configure msix register if no mapping is done
5721 * between intr vector and event fd.
5723 if (!rte_intr_dp_is_en(intr_handle))
5726 /* Configure all RX queues of VF */
5727 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5728 /* Force all queue use vector 0,
5729 * as IXGBE_VF_MAXMSIVECOTR = 1
5731 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5732 intr_handle->intr_vec[q_idx] = vector_idx;
5737 * Sets up the hardware to properly generate MSI-X interrupts
5739 * board private structure
5742 ixgbe_configure_msix(struct rte_eth_dev *dev)
5744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5745 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5746 struct ixgbe_hw *hw =
5747 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5748 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5749 uint32_t vec = IXGBE_MISC_VEC_ID;
5753 /* won't configure msix register if no mapping is done
5754 * between intr vector and event fd
5756 if (!rte_intr_dp_is_en(intr_handle))
5759 if (rte_intr_allow_others(intr_handle))
5760 vec = base = IXGBE_RX_VEC_START;
5762 /* setup GPIE for MSI-x mode */
5763 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5764 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5765 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5766 /* auto clearing and auto setting corresponding bits in EIMS
5767 * when MSI-X interrupt is triggered
5769 if (hw->mac.type == ixgbe_mac_82598EB) {
5770 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5772 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5773 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5775 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5777 /* Populate the IVAR table and set the ITR values to the
5778 * corresponding register.
5780 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5782 /* by default, 1:1 mapping */
5783 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5784 intr_handle->intr_vec[queue_id] = vec;
5785 if (vec < base + intr_handle->nb_efd - 1)
5789 switch (hw->mac.type) {
5790 case ixgbe_mac_82598EB:
5791 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5794 case ixgbe_mac_82599EB:
5795 case ixgbe_mac_X540:
5796 case ixgbe_mac_X550:
5797 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5802 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5803 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5805 /* set up to autoclear timer, and the vectors */
5806 mask = IXGBE_EIMS_ENABLE_MASK;
5807 mask &= ~(IXGBE_EIMS_OTHER |
5808 IXGBE_EIMS_MAILBOX |
5811 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5815 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5816 uint16_t queue_idx, uint16_t tx_rate)
5818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5819 uint32_t rf_dec, rf_int;
5821 uint16_t link_speed = dev->data->dev_link.link_speed;
5823 if (queue_idx >= hw->mac.max_tx_queues)
5827 /* Calculate the rate factor values to set */
5828 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5829 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5830 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5832 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5833 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5834 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5835 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5841 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5842 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5845 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5846 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5847 IXGBE_MAX_JUMBO_FRAME_SIZE))
5848 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5849 IXGBE_MMW_SIZE_JUMBO_FRAME);
5851 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5852 IXGBE_MMW_SIZE_DEFAULT);
5854 /* Set RTTBCNRC of queue X */
5855 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5856 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5857 IXGBE_WRITE_FLUSH(hw);
5863 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5864 __attribute__((unused)) uint32_t index,
5865 __attribute__((unused)) uint32_t pool)
5867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5871 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5872 * operation. Trap this case to avoid exhausting the [very limited]
5873 * set of PF resources used to store VF MAC addresses.
5875 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5877 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5879 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5880 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5881 mac_addr->addr_bytes[0],
5882 mac_addr->addr_bytes[1],
5883 mac_addr->addr_bytes[2],
5884 mac_addr->addr_bytes[3],
5885 mac_addr->addr_bytes[4],
5886 mac_addr->addr_bytes[5],
5892 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5895 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5896 struct ether_addr *mac_addr;
5901 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5902 * not support the deletion of a given MAC address.
5903 * Instead, it imposes to delete all MAC addresses, then to add again
5904 * all MAC addresses with the exception of the one to be deleted.
5906 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5909 * Add again all MAC addresses, with the exception of the deleted one
5910 * and of the permanent MAC address.
5912 for (i = 0, mac_addr = dev->data->mac_addrs;
5913 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5914 /* Skip the deleted MAC address */
5917 /* Skip NULL MAC addresses */
5918 if (is_zero_ether_addr(mac_addr))
5920 /* Skip the permanent MAC address */
5921 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5923 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5926 "Adding again MAC address "
5927 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5929 mac_addr->addr_bytes[0],
5930 mac_addr->addr_bytes[1],
5931 mac_addr->addr_bytes[2],
5932 mac_addr->addr_bytes[3],
5933 mac_addr->addr_bytes[4],
5934 mac_addr->addr_bytes[5],
5940 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5944 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5948 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5949 struct rte_eth_syn_filter *filter,
5952 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5953 struct ixgbe_filter_info *filter_info =
5954 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5958 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5961 syn_info = filter_info->syn_info;
5964 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5966 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5967 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5969 if (filter->hig_pri)
5970 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5972 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5974 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5975 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5977 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5980 filter_info->syn_info = synqf;
5981 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5982 IXGBE_WRITE_FLUSH(hw);
5987 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5988 struct rte_eth_syn_filter *filter)
5990 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5993 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5994 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5995 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6002 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6003 enum rte_filter_op filter_op,
6006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009 MAC_TYPE_FILTER_SUP(hw->mac.type);
6011 if (filter_op == RTE_ETH_FILTER_NOP)
6015 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6020 switch (filter_op) {
6021 case RTE_ETH_FILTER_ADD:
6022 ret = ixgbe_syn_filter_set(dev,
6023 (struct rte_eth_syn_filter *)arg,
6026 case RTE_ETH_FILTER_DELETE:
6027 ret = ixgbe_syn_filter_set(dev,
6028 (struct rte_eth_syn_filter *)arg,
6031 case RTE_ETH_FILTER_GET:
6032 ret = ixgbe_syn_filter_get(dev,
6033 (struct rte_eth_syn_filter *)arg);
6036 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6045 static inline enum ixgbe_5tuple_protocol
6046 convert_protocol_type(uint8_t protocol_value)
6048 if (protocol_value == IPPROTO_TCP)
6049 return IXGBE_FILTER_PROTOCOL_TCP;
6050 else if (protocol_value == IPPROTO_UDP)
6051 return IXGBE_FILTER_PROTOCOL_UDP;
6052 else if (protocol_value == IPPROTO_SCTP)
6053 return IXGBE_FILTER_PROTOCOL_SCTP;
6055 return IXGBE_FILTER_PROTOCOL_NONE;
6058 /* inject a 5-tuple filter to HW */
6060 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6061 struct ixgbe_5tuple_filter *filter)
6063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6065 uint32_t ftqf, sdpqf;
6066 uint32_t l34timir = 0;
6067 uint8_t mask = 0xff;
6071 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6072 IXGBE_SDPQF_DSTPORT_SHIFT);
6073 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6075 ftqf = (uint32_t)(filter->filter_info.proto &
6076 IXGBE_FTQF_PROTOCOL_MASK);
6077 ftqf |= (uint32_t)((filter->filter_info.priority &
6078 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6079 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6080 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6081 if (filter->filter_info.dst_ip_mask == 0)
6082 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6083 if (filter->filter_info.src_port_mask == 0)
6084 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6085 if (filter->filter_info.dst_port_mask == 0)
6086 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6087 if (filter->filter_info.proto_mask == 0)
6088 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6089 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6090 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6091 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6093 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6094 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6095 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6096 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6098 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6099 l34timir |= (uint32_t)(filter->queue <<
6100 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6101 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6105 * add a 5tuple filter
6108 * dev: Pointer to struct rte_eth_dev.
6109 * index: the index the filter allocates.
6110 * filter: ponter to the filter that will be added.
6111 * rx_queue: the queue id the filter assigned to.
6114 * - On success, zero.
6115 * - On failure, a negative value.
6118 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6119 struct ixgbe_5tuple_filter *filter)
6121 struct ixgbe_filter_info *filter_info =
6122 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6126 * look for an unused 5tuple filter index,
6127 * and insert the filter to list.
6129 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6130 idx = i / (sizeof(uint32_t) * NBBY);
6131 shift = i % (sizeof(uint32_t) * NBBY);
6132 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6133 filter_info->fivetuple_mask[idx] |= 1 << shift;
6135 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6141 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6142 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6146 ixgbe_inject_5tuple_filter(dev, filter);
6152 * remove a 5tuple filter
6155 * dev: Pointer to struct rte_eth_dev.
6156 * filter: the pointer of the filter will be removed.
6159 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6160 struct ixgbe_5tuple_filter *filter)
6162 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163 struct ixgbe_filter_info *filter_info =
6164 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6165 uint16_t index = filter->index;
6167 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6168 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6169 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6172 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6173 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6174 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6175 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6176 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6180 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6182 struct ixgbe_hw *hw;
6183 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6184 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6186 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6191 /* refuse mtu that requires the support of scattered packets when this
6192 * feature has not been enabled before.
6194 if (!rx_conf->enable_scatter &&
6195 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6196 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6200 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6201 * request of the version 2.0 of the mailbox API.
6202 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6203 * of the mailbox API.
6204 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6205 * prior to 3.11.33 which contains the following change:
6206 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6208 ixgbevf_rlpml_set_vf(hw, max_frame);
6210 /* update max frame size */
6211 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6215 static inline struct ixgbe_5tuple_filter *
6216 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6217 struct ixgbe_5tuple_filter_info *key)
6219 struct ixgbe_5tuple_filter *it;
6221 TAILQ_FOREACH(it, filter_list, entries) {
6222 if (memcmp(key, &it->filter_info,
6223 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6230 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6232 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6233 struct ixgbe_5tuple_filter_info *filter_info)
6235 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6236 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6237 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6240 switch (filter->dst_ip_mask) {
6242 filter_info->dst_ip_mask = 0;
6243 filter_info->dst_ip = filter->dst_ip;
6246 filter_info->dst_ip_mask = 1;
6249 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6253 switch (filter->src_ip_mask) {
6255 filter_info->src_ip_mask = 0;
6256 filter_info->src_ip = filter->src_ip;
6259 filter_info->src_ip_mask = 1;
6262 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6266 switch (filter->dst_port_mask) {
6268 filter_info->dst_port_mask = 0;
6269 filter_info->dst_port = filter->dst_port;
6272 filter_info->dst_port_mask = 1;
6275 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6279 switch (filter->src_port_mask) {
6281 filter_info->src_port_mask = 0;
6282 filter_info->src_port = filter->src_port;
6285 filter_info->src_port_mask = 1;
6288 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6292 switch (filter->proto_mask) {
6294 filter_info->proto_mask = 0;
6295 filter_info->proto =
6296 convert_protocol_type(filter->proto);
6299 filter_info->proto_mask = 1;
6302 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6306 filter_info->priority = (uint8_t)filter->priority;
6311 * add or delete a ntuple filter
6314 * dev: Pointer to struct rte_eth_dev.
6315 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6316 * add: if true, add filter, if false, remove filter
6319 * - On success, zero.
6320 * - On failure, a negative value.
6323 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6324 struct rte_eth_ntuple_filter *ntuple_filter,
6327 struct ixgbe_filter_info *filter_info =
6328 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6329 struct ixgbe_5tuple_filter_info filter_5tuple;
6330 struct ixgbe_5tuple_filter *filter;
6333 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6334 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6338 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6339 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6343 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6345 if (filter != NULL && add) {
6346 PMD_DRV_LOG(ERR, "filter exists.");
6349 if (filter == NULL && !add) {
6350 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6355 filter = rte_zmalloc("ixgbe_5tuple_filter",
6356 sizeof(struct ixgbe_5tuple_filter), 0);
6359 rte_memcpy(&filter->filter_info,
6361 sizeof(struct ixgbe_5tuple_filter_info));
6362 filter->queue = ntuple_filter->queue;
6363 ret = ixgbe_add_5tuple_filter(dev, filter);
6369 ixgbe_remove_5tuple_filter(dev, filter);
6375 * get a ntuple filter
6378 * dev: Pointer to struct rte_eth_dev.
6379 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6382 * - On success, zero.
6383 * - On failure, a negative value.
6386 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6387 struct rte_eth_ntuple_filter *ntuple_filter)
6389 struct ixgbe_filter_info *filter_info =
6390 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6391 struct ixgbe_5tuple_filter_info filter_5tuple;
6392 struct ixgbe_5tuple_filter *filter;
6395 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6396 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6400 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6401 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6405 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6407 if (filter == NULL) {
6408 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6411 ntuple_filter->queue = filter->queue;
6416 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6417 * @dev: pointer to rte_eth_dev structure
6418 * @filter_op:operation will be taken.
6419 * @arg: a pointer to specific structure corresponding to the filter_op
6422 * - On success, zero.
6423 * - On failure, a negative value.
6426 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6427 enum rte_filter_op filter_op,
6430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6435 if (filter_op == RTE_ETH_FILTER_NOP)
6439 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6444 switch (filter_op) {
6445 case RTE_ETH_FILTER_ADD:
6446 ret = ixgbe_add_del_ntuple_filter(dev,
6447 (struct rte_eth_ntuple_filter *)arg,
6450 case RTE_ETH_FILTER_DELETE:
6451 ret = ixgbe_add_del_ntuple_filter(dev,
6452 (struct rte_eth_ntuple_filter *)arg,
6455 case RTE_ETH_FILTER_GET:
6456 ret = ixgbe_get_ntuple_filter(dev,
6457 (struct rte_eth_ntuple_filter *)arg);
6460 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6468 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6469 struct rte_eth_ethertype_filter *filter,
6472 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6473 struct ixgbe_filter_info *filter_info =
6474 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6478 struct ixgbe_ethertype_filter ethertype_filter;
6480 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6483 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6484 filter->ether_type == ETHER_TYPE_IPv6) {
6485 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6486 " ethertype filter.", filter->ether_type);
6490 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6491 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6494 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6495 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6499 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6500 if (ret >= 0 && add) {
6501 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6502 filter->ether_type);
6505 if (ret < 0 && !add) {
6506 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6507 filter->ether_type);
6512 etqf = IXGBE_ETQF_FILTER_EN;
6513 etqf |= (uint32_t)filter->ether_type;
6514 etqs |= (uint32_t)((filter->queue <<
6515 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6516 IXGBE_ETQS_RX_QUEUE);
6517 etqs |= IXGBE_ETQS_QUEUE_EN;
6519 ethertype_filter.ethertype = filter->ether_type;
6520 ethertype_filter.etqf = etqf;
6521 ethertype_filter.etqs = etqs;
6522 ethertype_filter.conf = FALSE;
6523 ret = ixgbe_ethertype_filter_insert(filter_info,
6526 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6530 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6534 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6535 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6536 IXGBE_WRITE_FLUSH(hw);
6542 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6543 struct rte_eth_ethertype_filter *filter)
6545 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546 struct ixgbe_filter_info *filter_info =
6547 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6548 uint32_t etqf, etqs;
6551 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6553 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6554 filter->ether_type);
6558 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6559 if (etqf & IXGBE_ETQF_FILTER_EN) {
6560 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6561 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6563 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6564 IXGBE_ETQS_RX_QUEUE_SHIFT;
6571 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6572 * @dev: pointer to rte_eth_dev structure
6573 * @filter_op:operation will be taken.
6574 * @arg: a pointer to specific structure corresponding to the filter_op
6577 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6578 enum rte_filter_op filter_op,
6581 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6584 MAC_TYPE_FILTER_SUP(hw->mac.type);
6586 if (filter_op == RTE_ETH_FILTER_NOP)
6590 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6595 switch (filter_op) {
6596 case RTE_ETH_FILTER_ADD:
6597 ret = ixgbe_add_del_ethertype_filter(dev,
6598 (struct rte_eth_ethertype_filter *)arg,
6601 case RTE_ETH_FILTER_DELETE:
6602 ret = ixgbe_add_del_ethertype_filter(dev,
6603 (struct rte_eth_ethertype_filter *)arg,
6606 case RTE_ETH_FILTER_GET:
6607 ret = ixgbe_get_ethertype_filter(dev,
6608 (struct rte_eth_ethertype_filter *)arg);
6611 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6619 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6620 enum rte_filter_type filter_type,
6621 enum rte_filter_op filter_op,
6626 switch (filter_type) {
6627 case RTE_ETH_FILTER_NTUPLE:
6628 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6630 case RTE_ETH_FILTER_ETHERTYPE:
6631 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6633 case RTE_ETH_FILTER_SYN:
6634 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6636 case RTE_ETH_FILTER_FDIR:
6637 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6639 case RTE_ETH_FILTER_L2_TUNNEL:
6640 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6642 case RTE_ETH_FILTER_GENERIC:
6643 if (filter_op != RTE_ETH_FILTER_GET)
6645 *(const void **)arg = &ixgbe_flow_ops;
6648 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6658 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6659 u8 **mc_addr_ptr, u32 *vmdq)
6664 mc_addr = *mc_addr_ptr;
6665 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6670 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6671 struct ether_addr *mc_addr_set,
6672 uint32_t nb_mc_addr)
6674 struct ixgbe_hw *hw;
6677 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6678 mc_addr_list = (u8 *)mc_addr_set;
6679 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6680 ixgbe_dev_addr_list_itr, TRUE);
6684 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687 uint64_t systime_cycles;
6689 switch (hw->mac.type) {
6690 case ixgbe_mac_X550:
6691 case ixgbe_mac_X550EM_x:
6692 case ixgbe_mac_X550EM_a:
6693 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6694 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6695 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6699 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6700 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6704 return systime_cycles;
6708 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711 uint64_t rx_tstamp_cycles;
6713 switch (hw->mac.type) {
6714 case ixgbe_mac_X550:
6715 case ixgbe_mac_X550EM_x:
6716 case ixgbe_mac_X550EM_a:
6717 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6718 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6719 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6723 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6724 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6725 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6729 return rx_tstamp_cycles;
6733 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6735 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736 uint64_t tx_tstamp_cycles;
6738 switch (hw->mac.type) {
6739 case ixgbe_mac_X550:
6740 case ixgbe_mac_X550EM_x:
6741 case ixgbe_mac_X550EM_a:
6742 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6743 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6744 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6748 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6749 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6750 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6754 return tx_tstamp_cycles;
6758 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6760 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761 struct ixgbe_adapter *adapter =
6762 (struct ixgbe_adapter *)dev->data->dev_private;
6763 struct rte_eth_link link;
6764 uint32_t incval = 0;
6767 /* Get current link speed. */
6768 memset(&link, 0, sizeof(link));
6769 ixgbe_dev_link_update(dev, 1);
6770 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6772 switch (link.link_speed) {
6773 case ETH_SPEED_NUM_100M:
6774 incval = IXGBE_INCVAL_100;
6775 shift = IXGBE_INCVAL_SHIFT_100;
6777 case ETH_SPEED_NUM_1G:
6778 incval = IXGBE_INCVAL_1GB;
6779 shift = IXGBE_INCVAL_SHIFT_1GB;
6781 case ETH_SPEED_NUM_10G:
6783 incval = IXGBE_INCVAL_10GB;
6784 shift = IXGBE_INCVAL_SHIFT_10GB;
6788 switch (hw->mac.type) {
6789 case ixgbe_mac_X550:
6790 case ixgbe_mac_X550EM_x:
6791 case ixgbe_mac_X550EM_a:
6792 /* Independent of link speed. */
6794 /* Cycles read will be interpreted as ns. */
6797 case ixgbe_mac_X540:
6798 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6800 case ixgbe_mac_82599EB:
6801 incval >>= IXGBE_INCVAL_SHIFT_82599;
6802 shift -= IXGBE_INCVAL_SHIFT_82599;
6803 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6804 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6807 /* Not supported. */
6811 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6812 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6813 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6815 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6816 adapter->systime_tc.cc_shift = shift;
6817 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6819 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6820 adapter->rx_tstamp_tc.cc_shift = shift;
6821 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6823 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6824 adapter->tx_tstamp_tc.cc_shift = shift;
6825 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6829 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6831 struct ixgbe_adapter *adapter =
6832 (struct ixgbe_adapter *)dev->data->dev_private;
6834 adapter->systime_tc.nsec += delta;
6835 adapter->rx_tstamp_tc.nsec += delta;
6836 adapter->tx_tstamp_tc.nsec += delta;
6842 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6845 struct ixgbe_adapter *adapter =
6846 (struct ixgbe_adapter *)dev->data->dev_private;
6848 ns = rte_timespec_to_ns(ts);
6849 /* Set the timecounters to a new value. */
6850 adapter->systime_tc.nsec = ns;
6851 adapter->rx_tstamp_tc.nsec = ns;
6852 adapter->tx_tstamp_tc.nsec = ns;
6858 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6860 uint64_t ns, systime_cycles;
6861 struct ixgbe_adapter *adapter =
6862 (struct ixgbe_adapter *)dev->data->dev_private;
6864 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6865 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6866 *ts = rte_ns_to_timespec(ns);
6872 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6878 /* Stop the timesync system time. */
6879 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6880 /* Reset the timesync system time value. */
6881 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6882 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6884 /* Enable system time for platforms where it isn't on by default. */
6885 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6886 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6887 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6889 ixgbe_start_timecounters(dev);
6891 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6892 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6894 IXGBE_ETQF_FILTER_EN |
6897 /* Enable timestamping of received PTP packets. */
6898 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6899 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6900 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6902 /* Enable timestamping of transmitted PTP packets. */
6903 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6904 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6905 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6907 IXGBE_WRITE_FLUSH(hw);
6913 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918 /* Disable timestamping of transmitted PTP packets. */
6919 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6920 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6921 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6923 /* Disable timestamping of received PTP packets. */
6924 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6925 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6926 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6928 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6929 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6931 /* Stop incrementating the System Time registers. */
6932 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6938 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6939 struct timespec *timestamp,
6940 uint32_t flags __rte_unused)
6942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6943 struct ixgbe_adapter *adapter =
6944 (struct ixgbe_adapter *)dev->data->dev_private;
6945 uint32_t tsync_rxctl;
6946 uint64_t rx_tstamp_cycles;
6949 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6950 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6953 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6954 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6955 *timestamp = rte_ns_to_timespec(ns);
6961 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6962 struct timespec *timestamp)
6964 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6965 struct ixgbe_adapter *adapter =
6966 (struct ixgbe_adapter *)dev->data->dev_private;
6967 uint32_t tsync_txctl;
6968 uint64_t tx_tstamp_cycles;
6971 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6972 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6975 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6976 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6977 *timestamp = rte_ns_to_timespec(ns);
6983 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6985 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988 const struct reg_info *reg_group;
6989 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6990 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6992 while ((reg_group = reg_set[g_ind++]))
6993 count += ixgbe_regs_group_count(reg_group);
6999 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7003 const struct reg_info *reg_group;
7005 while ((reg_group = ixgbevf_regs[g_ind++]))
7006 count += ixgbe_regs_group_count(reg_group);
7012 ixgbe_get_regs(struct rte_eth_dev *dev,
7013 struct rte_dev_reg_info *regs)
7015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7016 uint32_t *data = regs->data;
7019 const struct reg_info *reg_group;
7020 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7021 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7024 regs->length = ixgbe_get_reg_length(dev);
7025 regs->width = sizeof(uint32_t);
7029 /* Support only full register dump */
7030 if ((regs->length == 0) ||
7031 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7032 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7034 while ((reg_group = reg_set[g_ind++]))
7035 count += ixgbe_read_regs_group(dev, &data[count],
7044 ixgbevf_get_regs(struct rte_eth_dev *dev,
7045 struct rte_dev_reg_info *regs)
7047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7048 uint32_t *data = regs->data;
7051 const struct reg_info *reg_group;
7054 regs->length = ixgbevf_get_reg_length(dev);
7055 regs->width = sizeof(uint32_t);
7059 /* Support only full register dump */
7060 if ((regs->length == 0) ||
7061 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7062 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7064 while ((reg_group = ixgbevf_regs[g_ind++]))
7065 count += ixgbe_read_regs_group(dev, &data[count],
7074 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7078 /* Return unit is byte count */
7079 return hw->eeprom.word_size * 2;
7083 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7084 struct rte_dev_eeprom_info *in_eeprom)
7086 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7088 uint16_t *data = in_eeprom->data;
7091 first = in_eeprom->offset >> 1;
7092 length = in_eeprom->length >> 1;
7093 if ((first > hw->eeprom.word_size) ||
7094 ((first + length) > hw->eeprom.word_size))
7097 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7099 return eeprom->ops.read_buffer(hw, first, length, data);
7103 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7104 struct rte_dev_eeprom_info *in_eeprom)
7106 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7107 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7108 uint16_t *data = in_eeprom->data;
7111 first = in_eeprom->offset >> 1;
7112 length = in_eeprom->length >> 1;
7113 if ((first > hw->eeprom.word_size) ||
7114 ((first + length) > hw->eeprom.word_size))
7117 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7119 return eeprom->ops.write_buffer(hw, first, length, data);
7123 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7125 case ixgbe_mac_X550:
7126 case ixgbe_mac_X550EM_x:
7127 case ixgbe_mac_X550EM_a:
7128 return ETH_RSS_RETA_SIZE_512;
7129 case ixgbe_mac_X550_vf:
7130 case ixgbe_mac_X550EM_x_vf:
7131 case ixgbe_mac_X550EM_a_vf:
7132 return ETH_RSS_RETA_SIZE_64;
7134 return ETH_RSS_RETA_SIZE_128;
7139 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7141 case ixgbe_mac_X550:
7142 case ixgbe_mac_X550EM_x:
7143 case ixgbe_mac_X550EM_a:
7144 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7145 return IXGBE_RETA(reta_idx >> 2);
7147 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7148 case ixgbe_mac_X550_vf:
7149 case ixgbe_mac_X550EM_x_vf:
7150 case ixgbe_mac_X550EM_a_vf:
7151 return IXGBE_VFRETA(reta_idx >> 2);
7153 return IXGBE_RETA(reta_idx >> 2);
7158 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7160 case ixgbe_mac_X550_vf:
7161 case ixgbe_mac_X550EM_x_vf:
7162 case ixgbe_mac_X550EM_a_vf:
7163 return IXGBE_VFMRQC;
7170 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7172 case ixgbe_mac_X550_vf:
7173 case ixgbe_mac_X550EM_x_vf:
7174 case ixgbe_mac_X550EM_a_vf:
7175 return IXGBE_VFRSSRK(i);
7177 return IXGBE_RSSRK(i);
7182 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7184 case ixgbe_mac_82599_vf:
7185 case ixgbe_mac_X540_vf:
7193 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7194 struct rte_eth_dcb_info *dcb_info)
7196 struct ixgbe_dcb_config *dcb_config =
7197 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7198 struct ixgbe_dcb_tc_config *tc;
7201 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7202 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7204 dcb_info->nb_tcs = 1;
7206 if (dcb_config->vt_mode) { /* vt is enabled*/
7207 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7208 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7209 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7210 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7211 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7212 for (j = 0; j < dcb_info->nb_tcs; j++) {
7213 dcb_info->tc_queue.tc_rxq[i][j].base =
7214 i * dcb_info->nb_tcs + j;
7215 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7216 dcb_info->tc_queue.tc_txq[i][j].base =
7217 i * dcb_info->nb_tcs + j;
7218 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7221 } else { /* vt is disabled*/
7222 struct rte_eth_dcb_rx_conf *rx_conf =
7223 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7224 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7225 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7226 if (dcb_info->nb_tcs == ETH_4_TCS) {
7227 for (i = 0; i < dcb_info->nb_tcs; i++) {
7228 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7229 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7231 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7232 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7233 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7234 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7235 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7236 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7237 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7238 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7239 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7240 for (i = 0; i < dcb_info->nb_tcs; i++) {
7241 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7242 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7244 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7245 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7246 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7247 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7248 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7249 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7250 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7251 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7252 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7253 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7254 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7255 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7256 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7257 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7258 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7259 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7262 for (i = 0; i < dcb_info->nb_tcs; i++) {
7263 tc = &dcb_config->tc_config[i];
7264 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7269 /* Update e-tag ether type */
7271 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7272 uint16_t ether_type)
7274 uint32_t etag_etype;
7276 if (hw->mac.type != ixgbe_mac_X550 &&
7277 hw->mac.type != ixgbe_mac_X550EM_x &&
7278 hw->mac.type != ixgbe_mac_X550EM_a) {
7282 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7283 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7284 etag_etype |= ether_type;
7285 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7286 IXGBE_WRITE_FLUSH(hw);
7291 /* Config l2 tunnel ether type */
7293 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7294 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7298 struct ixgbe_l2_tn_info *l2_tn_info =
7299 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7301 if (l2_tunnel == NULL)
7304 switch (l2_tunnel->l2_tunnel_type) {
7305 case RTE_L2_TUNNEL_TYPE_E_TAG:
7306 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7307 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7310 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7318 /* Enable e-tag tunnel */
7320 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7322 uint32_t etag_etype;
7324 if (hw->mac.type != ixgbe_mac_X550 &&
7325 hw->mac.type != ixgbe_mac_X550EM_x &&
7326 hw->mac.type != ixgbe_mac_X550EM_a) {
7330 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7331 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7332 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7333 IXGBE_WRITE_FLUSH(hw);
7338 /* Enable l2 tunnel */
7340 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7341 enum rte_eth_tunnel_type l2_tunnel_type)
7344 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7345 struct ixgbe_l2_tn_info *l2_tn_info =
7346 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7348 switch (l2_tunnel_type) {
7349 case RTE_L2_TUNNEL_TYPE_E_TAG:
7350 l2_tn_info->e_tag_en = TRUE;
7351 ret = ixgbe_e_tag_enable(hw);
7354 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7362 /* Disable e-tag tunnel */
7364 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7366 uint32_t etag_etype;
7368 if (hw->mac.type != ixgbe_mac_X550 &&
7369 hw->mac.type != ixgbe_mac_X550EM_x &&
7370 hw->mac.type != ixgbe_mac_X550EM_a) {
7374 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7375 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7376 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7377 IXGBE_WRITE_FLUSH(hw);
7382 /* Disable l2 tunnel */
7384 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7385 enum rte_eth_tunnel_type l2_tunnel_type)
7388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389 struct ixgbe_l2_tn_info *l2_tn_info =
7390 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7392 switch (l2_tunnel_type) {
7393 case RTE_L2_TUNNEL_TYPE_E_TAG:
7394 l2_tn_info->e_tag_en = FALSE;
7395 ret = ixgbe_e_tag_disable(hw);
7398 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7407 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7408 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7412 uint32_t i, rar_entries;
7413 uint32_t rar_low, rar_high;
7415 if (hw->mac.type != ixgbe_mac_X550 &&
7416 hw->mac.type != ixgbe_mac_X550EM_x &&
7417 hw->mac.type != ixgbe_mac_X550EM_a) {
7421 rar_entries = ixgbe_get_num_rx_addrs(hw);
7423 for (i = 1; i < rar_entries; i++) {
7424 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7425 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7426 if ((rar_high & IXGBE_RAH_AV) &&
7427 (rar_high & IXGBE_RAH_ADTYPE) &&
7428 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7429 l2_tunnel->tunnel_id)) {
7430 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7431 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7433 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7443 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7444 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7448 uint32_t i, rar_entries;
7449 uint32_t rar_low, rar_high;
7451 if (hw->mac.type != ixgbe_mac_X550 &&
7452 hw->mac.type != ixgbe_mac_X550EM_x &&
7453 hw->mac.type != ixgbe_mac_X550EM_a) {
7457 /* One entry for one tunnel. Try to remove potential existing entry. */
7458 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7460 rar_entries = ixgbe_get_num_rx_addrs(hw);
7462 for (i = 1; i < rar_entries; i++) {
7463 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7464 if (rar_high & IXGBE_RAH_AV) {
7467 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7468 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7469 rar_low = l2_tunnel->tunnel_id;
7471 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7472 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7478 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7479 " Please remove a rule before adding a new one.");
7483 static inline struct ixgbe_l2_tn_filter *
7484 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7485 struct ixgbe_l2_tn_key *key)
7489 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7493 return l2_tn_info->hash_map[ret];
7497 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7498 struct ixgbe_l2_tn_filter *l2_tn_filter)
7502 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7503 &l2_tn_filter->key);
7507 "Failed to insert L2 tunnel filter"
7508 " to hash table %d!",
7513 l2_tn_info->hash_map[ret] = l2_tn_filter;
7515 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7521 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7522 struct ixgbe_l2_tn_key *key)
7525 struct ixgbe_l2_tn_filter *l2_tn_filter;
7527 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7531 "No such L2 tunnel filter to delete %d!",
7536 l2_tn_filter = l2_tn_info->hash_map[ret];
7537 l2_tn_info->hash_map[ret] = NULL;
7539 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7540 rte_free(l2_tn_filter);
7545 /* Add l2 tunnel filter */
7547 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7548 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7552 struct ixgbe_l2_tn_info *l2_tn_info =
7553 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7554 struct ixgbe_l2_tn_key key;
7555 struct ixgbe_l2_tn_filter *node;
7558 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7559 key.tn_id = l2_tunnel->tunnel_id;
7561 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7565 "The L2 tunnel filter already exists!");
7569 node = rte_zmalloc("ixgbe_l2_tn",
7570 sizeof(struct ixgbe_l2_tn_filter),
7575 rte_memcpy(&node->key,
7577 sizeof(struct ixgbe_l2_tn_key));
7578 node->pool = l2_tunnel->pool;
7579 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7586 switch (l2_tunnel->l2_tunnel_type) {
7587 case RTE_L2_TUNNEL_TYPE_E_TAG:
7588 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7591 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7596 if ((!restore) && (ret < 0))
7597 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7602 /* Delete l2 tunnel filter */
7604 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7605 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7608 struct ixgbe_l2_tn_info *l2_tn_info =
7609 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7610 struct ixgbe_l2_tn_key key;
7612 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7613 key.tn_id = l2_tunnel->tunnel_id;
7614 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7618 switch (l2_tunnel->l2_tunnel_type) {
7619 case RTE_L2_TUNNEL_TYPE_E_TAG:
7620 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7623 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7632 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7633 * @dev: pointer to rte_eth_dev structure
7634 * @filter_op:operation will be taken.
7635 * @arg: a pointer to specific structure corresponding to the filter_op
7638 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7639 enum rte_filter_op filter_op,
7644 if (filter_op == RTE_ETH_FILTER_NOP)
7648 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7653 switch (filter_op) {
7654 case RTE_ETH_FILTER_ADD:
7655 ret = ixgbe_dev_l2_tunnel_filter_add
7657 (struct rte_eth_l2_tunnel_conf *)arg,
7660 case RTE_ETH_FILTER_DELETE:
7661 ret = ixgbe_dev_l2_tunnel_filter_del
7663 (struct rte_eth_l2_tunnel_conf *)arg);
7666 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7674 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7678 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680 if (hw->mac.type != ixgbe_mac_X550 &&
7681 hw->mac.type != ixgbe_mac_X550EM_x &&
7682 hw->mac.type != ixgbe_mac_X550EM_a) {
7686 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7687 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7689 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7690 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7695 /* Enable l2 tunnel forwarding */
7697 ixgbe_dev_l2_tunnel_forwarding_enable
7698 (struct rte_eth_dev *dev,
7699 enum rte_eth_tunnel_type l2_tunnel_type)
7701 struct ixgbe_l2_tn_info *l2_tn_info =
7702 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7705 switch (l2_tunnel_type) {
7706 case RTE_L2_TUNNEL_TYPE_E_TAG:
7707 l2_tn_info->e_tag_fwd_en = TRUE;
7708 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7711 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7719 /* Disable l2 tunnel forwarding */
7721 ixgbe_dev_l2_tunnel_forwarding_disable
7722 (struct rte_eth_dev *dev,
7723 enum rte_eth_tunnel_type l2_tunnel_type)
7725 struct ixgbe_l2_tn_info *l2_tn_info =
7726 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7729 switch (l2_tunnel_type) {
7730 case RTE_L2_TUNNEL_TYPE_E_TAG:
7731 l2_tn_info->e_tag_fwd_en = FALSE;
7732 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7735 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7744 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7745 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7748 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7750 uint32_t vmtir, vmvir;
7751 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7753 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7755 "VF id %u should be less than %u",
7761 if (hw->mac.type != ixgbe_mac_X550 &&
7762 hw->mac.type != ixgbe_mac_X550EM_x &&
7763 hw->mac.type != ixgbe_mac_X550EM_a) {
7768 vmtir = l2_tunnel->tunnel_id;
7772 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7774 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7775 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7777 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7778 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7783 /* Enable l2 tunnel tag insertion */
7785 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7786 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7790 switch (l2_tunnel->l2_tunnel_type) {
7791 case RTE_L2_TUNNEL_TYPE_E_TAG:
7792 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7795 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7803 /* Disable l2 tunnel tag insertion */
7805 ixgbe_dev_l2_tunnel_insertion_disable
7806 (struct rte_eth_dev *dev,
7807 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7811 switch (l2_tunnel->l2_tunnel_type) {
7812 case RTE_L2_TUNNEL_TYPE_E_TAG:
7813 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7816 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7825 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7830 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7832 if (hw->mac.type != ixgbe_mac_X550 &&
7833 hw->mac.type != ixgbe_mac_X550EM_x &&
7834 hw->mac.type != ixgbe_mac_X550EM_a) {
7838 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7840 qde |= IXGBE_QDE_STRIP_TAG;
7842 qde &= ~IXGBE_QDE_STRIP_TAG;
7843 qde &= ~IXGBE_QDE_READ;
7844 qde |= IXGBE_QDE_WRITE;
7845 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7850 /* Enable l2 tunnel tag stripping */
7852 ixgbe_dev_l2_tunnel_stripping_enable
7853 (struct rte_eth_dev *dev,
7854 enum rte_eth_tunnel_type l2_tunnel_type)
7858 switch (l2_tunnel_type) {
7859 case RTE_L2_TUNNEL_TYPE_E_TAG:
7860 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7863 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871 /* Disable l2 tunnel tag stripping */
7873 ixgbe_dev_l2_tunnel_stripping_disable
7874 (struct rte_eth_dev *dev,
7875 enum rte_eth_tunnel_type l2_tunnel_type)
7879 switch (l2_tunnel_type) {
7880 case RTE_L2_TUNNEL_TYPE_E_TAG:
7881 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7884 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7892 /* Enable/disable l2 tunnel offload functions */
7894 ixgbe_dev_l2_tunnel_offload_set
7895 (struct rte_eth_dev *dev,
7896 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7902 if (l2_tunnel == NULL)
7906 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7908 ret = ixgbe_dev_l2_tunnel_enable(
7910 l2_tunnel->l2_tunnel_type);
7912 ret = ixgbe_dev_l2_tunnel_disable(
7914 l2_tunnel->l2_tunnel_type);
7917 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7919 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7923 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7928 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7930 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7932 l2_tunnel->l2_tunnel_type);
7934 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7936 l2_tunnel->l2_tunnel_type);
7939 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7941 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7943 l2_tunnel->l2_tunnel_type);
7945 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7947 l2_tunnel->l2_tunnel_type);
7954 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7957 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7958 IXGBE_WRITE_FLUSH(hw);
7963 /* There's only one register for VxLAN UDP port.
7964 * So, we cannot add several ports. Will update it.
7967 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7971 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7975 return ixgbe_update_vxlan_port(hw, port);
7978 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7979 * UDP port, it must have a value.
7980 * So, will reset it to the original value 0.
7983 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7988 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7990 if (cur_port != port) {
7991 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7995 return ixgbe_update_vxlan_port(hw, 0);
7998 /* Add UDP tunneling port */
8000 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8001 struct rte_eth_udp_tunnel *udp_tunnel)
8004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8006 if (hw->mac.type != ixgbe_mac_X550 &&
8007 hw->mac.type != ixgbe_mac_X550EM_x &&
8008 hw->mac.type != ixgbe_mac_X550EM_a) {
8012 if (udp_tunnel == NULL)
8015 switch (udp_tunnel->prot_type) {
8016 case RTE_TUNNEL_TYPE_VXLAN:
8017 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8020 case RTE_TUNNEL_TYPE_GENEVE:
8021 case RTE_TUNNEL_TYPE_TEREDO:
8022 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8027 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8035 /* Remove UDP tunneling port */
8037 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8038 struct rte_eth_udp_tunnel *udp_tunnel)
8041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8043 if (hw->mac.type != ixgbe_mac_X550 &&
8044 hw->mac.type != ixgbe_mac_X550EM_x &&
8045 hw->mac.type != ixgbe_mac_X550EM_a) {
8049 if (udp_tunnel == NULL)
8052 switch (udp_tunnel->prot_type) {
8053 case RTE_TUNNEL_TYPE_VXLAN:
8054 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8056 case RTE_TUNNEL_TYPE_GENEVE:
8057 case RTE_TUNNEL_TYPE_TEREDO:
8058 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8062 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8071 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8075 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8079 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8081 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8083 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8086 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8091 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8094 /* PF reset VF event */
8095 if (in_msg == IXGBE_PF_CONTROL_MSG)
8096 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8101 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105 struct ixgbe_interrupt *intr =
8106 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8107 ixgbevf_intr_disable(hw);
8109 /* read-on-clear nic registers here */
8110 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8113 /* only one misc vector supported - mailbox */
8114 eicr &= IXGBE_VTEICR_MASK;
8115 if (eicr == IXGBE_MISC_VEC_ID)
8116 intr->flags |= IXGBE_FLAG_MAILBOX;
8122 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8125 struct ixgbe_interrupt *intr =
8126 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8128 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8129 ixgbevf_mbx_process(dev);
8130 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8133 ixgbevf_intr_enable(hw);
8139 ixgbevf_dev_interrupt_handler(void *param)
8141 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8143 ixgbevf_dev_interrupt_get_status(dev);
8144 ixgbevf_dev_interrupt_action(dev);
8148 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8149 * @hw: pointer to hardware structure
8151 * Stops the transmit data path and waits for the HW to internally empty
8152 * the Tx security block
8154 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8156 #define IXGBE_MAX_SECTX_POLL 40
8161 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8162 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8163 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8164 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8165 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8166 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8168 /* Use interrupt-safe sleep just in case */
8172 /* For informational purposes only */
8173 if (i >= IXGBE_MAX_SECTX_POLL)
8174 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8175 "path fully disabled. Continuing with init.");
8177 return IXGBE_SUCCESS;
8181 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8182 * @hw: pointer to hardware structure
8184 * Enables the transmit data path.
8186 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8190 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8191 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8192 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8193 IXGBE_WRITE_FLUSH(hw);
8195 return IXGBE_SUCCESS;
8198 /* restore n-tuple filter */
8200 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8202 struct ixgbe_filter_info *filter_info =
8203 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8204 struct ixgbe_5tuple_filter *node;
8206 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8207 ixgbe_inject_5tuple_filter(dev, node);
8211 /* restore ethernet type filter */
8213 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8215 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216 struct ixgbe_filter_info *filter_info =
8217 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8220 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8221 if (filter_info->ethertype_mask & (1 << i)) {
8222 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8223 filter_info->ethertype_filters[i].etqf);
8224 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8225 filter_info->ethertype_filters[i].etqs);
8226 IXGBE_WRITE_FLUSH(hw);
8231 /* restore SYN filter */
8233 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8235 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8236 struct ixgbe_filter_info *filter_info =
8237 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8240 synqf = filter_info->syn_info;
8242 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8243 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8244 IXGBE_WRITE_FLUSH(hw);
8248 /* restore L2 tunnel filter */
8250 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8252 struct ixgbe_l2_tn_info *l2_tn_info =
8253 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8254 struct ixgbe_l2_tn_filter *node;
8255 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8257 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8258 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8259 l2_tn_conf.tunnel_id = node->key.tn_id;
8260 l2_tn_conf.pool = node->pool;
8261 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8266 ixgbe_filter_restore(struct rte_eth_dev *dev)
8268 ixgbe_ntuple_filter_restore(dev);
8269 ixgbe_ethertype_filter_restore(dev);
8270 ixgbe_syn_filter_restore(dev);
8271 ixgbe_fdir_filter_restore(dev);
8272 ixgbe_l2_tn_filter_restore(dev);
8278 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8280 struct ixgbe_l2_tn_info *l2_tn_info =
8281 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8282 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284 if (l2_tn_info->e_tag_en)
8285 (void)ixgbe_e_tag_enable(hw);
8287 if (l2_tn_info->e_tag_fwd_en)
8288 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8290 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8293 /* remove all the n-tuple filters */
8295 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8297 struct ixgbe_filter_info *filter_info =
8298 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8299 struct ixgbe_5tuple_filter *p_5tuple;
8301 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8302 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8305 /* remove all the ether type filters */
8307 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8309 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8310 struct ixgbe_filter_info *filter_info =
8311 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8314 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8315 if (filter_info->ethertype_mask & (1 << i) &&
8316 !filter_info->ethertype_filters[i].conf) {
8317 (void)ixgbe_ethertype_filter_remove(filter_info,
8319 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8320 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8321 IXGBE_WRITE_FLUSH(hw);
8326 /* remove the SYN filter */
8328 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331 struct ixgbe_filter_info *filter_info =
8332 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8334 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8335 filter_info->syn_info = 0;
8337 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8338 IXGBE_WRITE_FLUSH(hw);
8342 /* remove all the L2 tunnel filters */
8344 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8346 struct ixgbe_l2_tn_info *l2_tn_info =
8347 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8348 struct ixgbe_l2_tn_filter *l2_tn_filter;
8349 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8352 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8353 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8354 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8355 l2_tn_conf.pool = l2_tn_filter->pool;
8356 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8364 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8365 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8366 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8367 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8368 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8369 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");