4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_hash_crc.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
192 __rte_unused unsigned int size);
193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 __rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
270 struct rte_eth_stats *stats);
271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
273 uint16_t vlan_id, int on);
274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
275 uint16_t queue, int on);
276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
283 uint8_t queue, uint8_t msix_vector);
284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
288 /* For Eth VMDQ APIs support */
289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
290 ether_addr * mac_addr, uint8_t on);
291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
293 struct rte_eth_mirror_conf *mirror_conf,
294 uint8_t rule_id, uint8_t on);
295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
302 uint8_t queue, uint8_t msix_vector);
303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
306 uint16_t queue_idx, uint16_t tx_rate);
308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
309 struct ether_addr *mac_addr,
310 uint32_t index, uint32_t pool);
311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
313 struct ether_addr *mac_addr);
314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
315 struct rte_eth_syn_filter *filter);
316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
327 struct rte_eth_ntuple_filter *filter);
328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
329 enum rte_filter_op filter_op,
331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
332 struct rte_eth_ethertype_filter *filter);
333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
334 enum rte_filter_type filter_type,
335 enum rte_filter_op filter_op,
337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
340 struct ether_addr *mc_addr_set,
341 uint32_t nb_mc_addr);
342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
343 struct rte_eth_dcb_info *dcb_info);
345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
347 struct rte_dev_reg_info *regs);
348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
361 struct timespec *timestamp,
363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp);
365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
369 const struct timespec *timestamp);
370 static void ixgbevf_dev_interrupt_handler(void *param);
372 static int ixgbe_dev_l2_tunnel_eth_type_conf
373 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
374 static int ixgbe_dev_l2_tunnel_offload_set
375 (struct rte_eth_dev *dev,
376 struct rte_eth_l2_tunnel_conf *l2_tunnel,
379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
391 * Define VF Stats MACRO for Non "cleared on read" register
393 #define UPDATE_VF_STAT(reg, last, cur) \
395 uint32_t latest = IXGBE_READ_REG(hw, reg); \
396 cur += (latest - last) & UINT_MAX; \
400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
402 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
403 u64 new_msb = IXGBE_READ_REG(hw, msb); \
404 u64 latest = ((new_msb << 32) | new_lsb); \
405 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 #define IXGBE_SET_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] |= 1 << bit;\
415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (h)->bitmap[idx] &= ~(1 << bit);\
421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
422 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
423 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
424 (r) = (h)->bitmap[idx] >> bit & 1;\
428 * The set of PCI devices this driver supports
430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
484 #ifdef RTE_NIC_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
529 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
530 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
531 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
532 .link_update = ixgbe_dev_link_update,
533 .stats_get = ixgbe_dev_stats_get,
534 .xstats_get = ixgbe_dev_xstats_get,
535 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
536 .stats_reset = ixgbe_dev_stats_reset,
537 .xstats_reset = ixgbe_dev_xstats_reset,
538 .xstats_get_names = ixgbe_dev_xstats_get_names,
539 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
540 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
541 .fw_version_get = ixgbe_fw_version_get,
542 .dev_infos_get = ixgbe_dev_info_get,
543 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
544 .mtu_set = ixgbe_dev_mtu_set,
545 .vlan_filter_set = ixgbe_vlan_filter_set,
546 .vlan_tpid_set = ixgbe_vlan_tpid_set,
547 .vlan_offload_set = ixgbe_vlan_offload_set,
548 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
549 .rx_queue_start = ixgbe_dev_rx_queue_start,
550 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
551 .tx_queue_start = ixgbe_dev_tx_queue_start,
552 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
553 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
554 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
555 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
556 .rx_queue_release = ixgbe_dev_rx_queue_release,
557 .rx_queue_count = ixgbe_dev_rx_queue_count,
558 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
559 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
560 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
561 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
562 .tx_queue_release = ixgbe_dev_tx_queue_release,
563 .dev_led_on = ixgbe_dev_led_on,
564 .dev_led_off = ixgbe_dev_led_off,
565 .flow_ctrl_get = ixgbe_flow_ctrl_get,
566 .flow_ctrl_set = ixgbe_flow_ctrl_set,
567 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
568 .mac_addr_add = ixgbe_add_rar,
569 .mac_addr_remove = ixgbe_remove_rar,
570 .mac_addr_set = ixgbe_set_default_mac_addr,
571 .uc_hash_table_set = ixgbe_uc_hash_table_set,
572 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
573 .mirror_rule_set = ixgbe_mirror_rule_set,
574 .mirror_rule_reset = ixgbe_mirror_rule_reset,
575 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
576 .reta_update = ixgbe_dev_rss_reta_update,
577 .reta_query = ixgbe_dev_rss_reta_query,
578 #ifdef RTE_NIC_BYPASS
579 .bypass_init = ixgbe_bypass_init,
580 .bypass_state_set = ixgbe_bypass_state_store,
581 .bypass_state_show = ixgbe_bypass_state_show,
582 .bypass_event_set = ixgbe_bypass_event_store,
583 .bypass_event_show = ixgbe_bypass_event_show,
584 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
585 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
586 .bypass_ver_show = ixgbe_bypass_ver_show,
587 .bypass_wd_reset = ixgbe_bypass_wd_reset,
588 #endif /* RTE_NIC_BYPASS */
589 .rss_hash_update = ixgbe_dev_rss_hash_update,
590 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
591 .filter_ctrl = ixgbe_dev_filter_ctrl,
592 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
593 .rxq_info_get = ixgbe_rxq_info_get,
594 .txq_info_get = ixgbe_txq_info_get,
595 .timesync_enable = ixgbe_timesync_enable,
596 .timesync_disable = ixgbe_timesync_disable,
597 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
598 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
599 .get_reg = ixgbe_get_regs,
600 .get_eeprom_length = ixgbe_get_eeprom_length,
601 .get_eeprom = ixgbe_get_eeprom,
602 .set_eeprom = ixgbe_set_eeprom,
603 .get_dcb_info = ixgbe_dev_get_dcb_info,
604 .timesync_adjust_time = ixgbe_timesync_adjust_time,
605 .timesync_read_time = ixgbe_timesync_read_time,
606 .timesync_write_time = ixgbe_timesync_write_time,
607 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
608 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
609 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
610 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
614 * dev_ops for virtual function, bare necessities for basic vf
615 * operation have been implemented
617 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
618 .dev_configure = ixgbevf_dev_configure,
619 .dev_start = ixgbevf_dev_start,
620 .dev_stop = ixgbevf_dev_stop,
621 .link_update = ixgbe_dev_link_update,
622 .stats_get = ixgbevf_dev_stats_get,
623 .xstats_get = ixgbevf_dev_xstats_get,
624 .stats_reset = ixgbevf_dev_stats_reset,
625 .xstats_reset = ixgbevf_dev_stats_reset,
626 .xstats_get_names = ixgbevf_dev_xstats_get_names,
627 .dev_close = ixgbevf_dev_close,
628 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
629 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
630 .dev_infos_get = ixgbevf_dev_info_get,
631 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
632 .mtu_set = ixgbevf_dev_set_mtu,
633 .vlan_filter_set = ixgbevf_vlan_filter_set,
634 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
635 .vlan_offload_set = ixgbevf_vlan_offload_set,
636 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
637 .rx_queue_release = ixgbe_dev_rx_queue_release,
638 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
639 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
640 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
641 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
642 .tx_queue_release = ixgbe_dev_tx_queue_release,
643 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
644 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
645 .mac_addr_add = ixgbevf_add_mac_addr,
646 .mac_addr_remove = ixgbevf_remove_mac_addr,
647 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
648 .rxq_info_get = ixgbe_rxq_info_get,
649 .txq_info_get = ixgbe_txq_info_get,
650 .mac_addr_set = ixgbevf_set_default_mac_addr,
651 .get_reg = ixgbevf_get_regs,
652 .reta_update = ixgbe_dev_rss_reta_update,
653 .reta_query = ixgbe_dev_rss_reta_query,
654 .rss_hash_update = ixgbe_dev_rss_hash_update,
655 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
658 /* store statistics names and its offset in stats structure */
659 struct rte_ixgbe_xstats_name_off {
660 char name[RTE_ETH_XSTATS_NAME_SIZE];
664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
665 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
666 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
667 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
668 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
669 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
670 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
671 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
672 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
673 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
674 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
675 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
676 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
677 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
678 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
679 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
681 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
683 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
684 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
685 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
686 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
687 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
688 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
689 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
690 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
691 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
692 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
693 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
694 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
695 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
696 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
697 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
698 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
699 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
701 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
703 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
704 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
705 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
706 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
708 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
716 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
718 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
722 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
723 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
725 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
726 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
727 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
728 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
729 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
731 {"rx_fcoe_no_direct_data_placement_ext_buff",
732 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
734 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
736 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
738 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
740 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
742 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
746 sizeof(rte_ixgbe_stats_strings[0]))
748 /* MACsec statistics */
749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
750 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
752 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
753 out_pkts_encrypted)},
754 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
755 out_pkts_protected)},
756 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
757 out_octets_encrypted)},
758 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
759 out_octets_protected)},
760 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
767 in_pkts_unknownsci)},
768 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
769 in_octets_decrypted)},
770 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
771 in_octets_validated)},
772 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
784 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
786 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
787 in_pkts_notusingsa)},
790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
791 sizeof(rte_ixgbe_macsec_strings[0]))
793 /* Per-queue statistics */
794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
795 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
796 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
797 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
798 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
802 sizeof(rte_ixgbe_rxq_strings[0]))
803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
806 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
807 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
808 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
813 sizeof(rte_ixgbe_txq_strings[0]))
814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
817 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
821 sizeof(rte_ixgbevf_stats_strings[0]))
824 * Atomically reads the link status information from global
825 * structure rte_eth_dev.
828 * - Pointer to the structure rte_eth_dev to read from.
829 * - Pointer to the buffer to be saved with the link status.
832 * - On success, zero.
833 * - On failure, negative value.
836 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
837 struct rte_eth_link *link)
839 struct rte_eth_link *dst = link;
840 struct rte_eth_link *src = &(dev->data->dev_link);
842 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
843 *(uint64_t *)src) == 0)
850 * Atomically writes the link status information into global
851 * structure rte_eth_dev.
854 * - Pointer to the structure rte_eth_dev to read from.
855 * - Pointer to the buffer to be saved with the link status.
858 * - On success, zero.
859 * - On failure, negative value.
862 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
863 struct rte_eth_link *link)
865 struct rte_eth_link *dst = &(dev->data->dev_link);
866 struct rte_eth_link *src = link;
868 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
869 *(uint64_t *)src) == 0)
876 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
879 ixgbe_is_sfp(struct ixgbe_hw *hw)
881 switch (hw->phy.type) {
882 case ixgbe_phy_sfp_avago:
883 case ixgbe_phy_sfp_ftl:
884 case ixgbe_phy_sfp_intel:
885 case ixgbe_phy_sfp_unknown:
886 case ixgbe_phy_sfp_passive_tyco:
887 case ixgbe_phy_sfp_passive_unknown:
894 static inline int32_t
895 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
900 status = ixgbe_reset_hw(hw);
902 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
903 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
904 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
905 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
906 IXGBE_WRITE_FLUSH(hw);
908 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
909 status = IXGBE_SUCCESS;
914 ixgbe_enable_intr(struct rte_eth_dev *dev)
916 struct ixgbe_interrupt *intr =
917 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
918 struct ixgbe_hw *hw =
919 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
922 IXGBE_WRITE_FLUSH(hw);
926 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
929 ixgbe_disable_intr(struct ixgbe_hw *hw)
931 PMD_INIT_FUNC_TRACE();
933 if (hw->mac.type == ixgbe_mac_82598EB) {
934 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
936 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
937 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
938 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
940 IXGBE_WRITE_FLUSH(hw);
944 * This function resets queue statistics mapping registers.
945 * From Niantic datasheet, Initialization of Statistics section:
946 * "...if software requires the queue counters, the RQSMR and TQSM registers
947 * must be re-programmed following a device reset.
950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
954 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
955 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
956 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
972 struct ixgbe_stat_mapping_registers *stat_mappings =
973 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
974 uint32_t qsmr_mask = 0;
975 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
979 if ((hw->mac.type != ixgbe_mac_82599EB) &&
980 (hw->mac.type != ixgbe_mac_X540) &&
981 (hw->mac.type != ixgbe_mac_X550) &&
982 (hw->mac.type != ixgbe_mac_X550EM_x) &&
983 (hw->mac.type != ixgbe_mac_X550EM_a))
986 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
987 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
990 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
991 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
992 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
995 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
997 /* Now clear any previous stat_idx set */
998 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1000 stat_mappings->tqsm[n] &= ~clearing_mask;
1002 stat_mappings->rqsmr[n] &= ~clearing_mask;
1004 q_map = (uint32_t)stat_idx;
1005 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1008 stat_mappings->tqsm[n] |= qsmr_mask;
1010 stat_mappings->rqsmr[n] |= qsmr_mask;
1012 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014 queue_id, stat_idx);
1015 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1018 /* Now write the mapping in the appropriate register */
1020 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021 stat_mappings->rqsmr[n], n);
1022 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1024 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025 stat_mappings->tqsm[n], n);
1026 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1034 struct ixgbe_stat_mapping_registers *stat_mappings =
1035 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 /* write whatever was in stat mapping table to the NIC */
1040 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1042 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1045 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1053 struct ixgbe_dcb_tc_config *tc;
1054 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1056 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058 for (i = 0; i < dcb_max_tc; i++) {
1059 tc = &dcb_config->tc_config[i];
1060 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062 (uint8_t)(100/dcb_max_tc + (i & 1));
1063 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065 (uint8_t)(100/dcb_max_tc + (i & 1));
1066 tc->pfc = ixgbe_dcb_pfc_disabled;
1069 /* Initialize default user to priority mapping, UPx->TC0 */
1070 tc = &dcb_config->tc_config[0];
1071 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1077 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078 dcb_config->pfc_mode_enable = false;
1079 dcb_config->vt_mode = true;
1080 dcb_config->round_robin_enable = false;
1081 /* support all DCB capabilities in 82599 */
1082 dcb_config->support.capabilities = 0xFF;
1084 /*we only support 4 Tcs for X540, X550 */
1085 if (hw->mac.type == ixgbe_mac_X540 ||
1086 hw->mac.type == ixgbe_mac_X550 ||
1087 hw->mac.type == ixgbe_mac_X550EM_x ||
1088 hw->mac.type == ixgbe_mac_X550EM_a) {
1089 dcb_config->num_tcs.pg_tcs = 4;
1090 dcb_config->num_tcs.pfc_tcs = 4;
1095 * Ensure that all locks are released before first NVM or PHY access
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1103 * Phy lock should not fail in this early stage. If this is the case,
1104 * it is due to an improper exit of the application.
1105 * So force the release of the faulty lock. Release of common lock
1106 * is done automatically by swfw_sync function.
1108 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1112 ixgbe_release_swfw_semaphore(hw, mask);
1115 * These ones are more tricky since they are common to all ports; but
1116 * swfw_sync retries last long enough (1s) to be almost sure that if
1117 * lock can not be taken it is due to an improper lock of the
1120 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1124 ixgbe_release_swfw_semaphore(hw, mask);
1128 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129 * It returns 0 on success.
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1134 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136 struct ixgbe_hw *hw =
1137 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138 struct ixgbe_vfta *shadow_vfta =
1139 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140 struct ixgbe_hwstrip *hwstrip =
1141 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142 struct ixgbe_dcb_config *dcb_config =
1143 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144 struct ixgbe_filter_info *filter_info =
1145 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146 struct ixgbe_bw_conf *bw_conf =
1147 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1152 PMD_INIT_FUNC_TRACE();
1154 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1155 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1156 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1160 * For secondary processes, we don't initialise any further as primary
1161 * has already done this work. Only check we don't need a different
1162 * RX and TX function.
1164 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1165 struct ixgbe_tx_queue *txq;
1166 /* TX queue function in primary, set by last queue initialized
1167 * Tx queue may not initialized by primary process
1169 if (eth_dev->data->tx_queues) {
1170 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1171 ixgbe_set_tx_function(eth_dev, txq);
1173 /* Use default TX function if we get here */
1174 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1175 "Using default TX function.");
1178 ixgbe_set_rx_function(eth_dev);
1183 rte_eth_copy_pci_info(eth_dev, pci_dev);
1184 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1186 /* Vendor and Device ID need to be set before init of shared code */
1187 hw->device_id = pci_dev->id.device_id;
1188 hw->vendor_id = pci_dev->id.vendor_id;
1189 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1190 hw->allow_unsupported_sfp = 1;
1192 /* Initialize the shared code (base driver) */
1193 #ifdef RTE_NIC_BYPASS
1194 diag = ixgbe_bypass_init_shared_code(hw);
1196 diag = ixgbe_init_shared_code(hw);
1197 #endif /* RTE_NIC_BYPASS */
1199 if (diag != IXGBE_SUCCESS) {
1200 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1204 /* pick up the PCI bus settings for reporting later */
1205 ixgbe_get_bus_info(hw);
1207 /* Unlock any pending hardware semaphore */
1208 ixgbe_swfw_lock_reset(hw);
1210 /* Initialize DCB configuration*/
1211 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1212 ixgbe_dcb_init(hw, dcb_config);
1213 /* Get Hardware Flow Control setting */
1214 hw->fc.requested_mode = ixgbe_fc_full;
1215 hw->fc.current_mode = ixgbe_fc_full;
1216 hw->fc.pause_time = IXGBE_FC_PAUSE;
1217 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1218 hw->fc.low_water[i] = IXGBE_FC_LO;
1219 hw->fc.high_water[i] = IXGBE_FC_HI;
1221 hw->fc.send_xon = 1;
1223 /* Make sure we have a good EEPROM before we read from it */
1224 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1225 if (diag != IXGBE_SUCCESS) {
1226 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1230 #ifdef RTE_NIC_BYPASS
1231 diag = ixgbe_bypass_init_hw(hw);
1233 diag = ixgbe_init_hw(hw);
1234 #endif /* RTE_NIC_BYPASS */
1237 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1238 * is called too soon after the kernel driver unbinding/binding occurs.
1239 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1240 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1241 * also called. See ixgbe_identify_phy_82599(). The reason for the
1242 * failure is not known, and only occuts when virtualisation features
1243 * are disabled in the bios. A delay of 100ms was found to be enough by
1244 * trial-and-error, and is doubled to be safe.
1246 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1248 diag = ixgbe_init_hw(hw);
1251 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1252 diag = IXGBE_SUCCESS;
1254 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1255 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1256 "LOM. Please be aware there may be issues associated "
1257 "with your hardware.");
1258 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1259 "please contact your Intel or hardware representative "
1260 "who provided you with this hardware.");
1261 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1262 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1264 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1268 /* Reset the hw statistics */
1269 ixgbe_dev_stats_reset(eth_dev);
1271 /* disable interrupt */
1272 ixgbe_disable_intr(hw);
1274 /* reset mappings for queue statistics hw counters*/
1275 ixgbe_reset_qstat_mappings(hw);
1277 /* Allocate memory for storing MAC addresses */
1278 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279 hw->mac.num_rar_entries, 0);
1280 if (eth_dev->data->mac_addrs == NULL) {
1282 "Failed to allocate %u bytes needed to store "
1284 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1287 /* Copy the permanent MAC address */
1288 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1289 ð_dev->data->mac_addrs[0]);
1291 /* Allocate memory for storing hash filter MAC addresses */
1292 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1293 IXGBE_VMDQ_NUM_UC_MAC, 0);
1294 if (eth_dev->data->hash_mac_addrs == NULL) {
1296 "Failed to allocate %d bytes needed to store MAC addresses",
1297 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1301 /* initialize the vfta */
1302 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1304 /* initialize the hw strip bitmap*/
1305 memset(hwstrip, 0, sizeof(*hwstrip));
1307 /* initialize PF if max_vfs not zero */
1308 ixgbe_pf_host_init(eth_dev);
1310 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1311 /* let hardware know driver is loaded */
1312 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1313 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1314 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1315 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1316 IXGBE_WRITE_FLUSH(hw);
1318 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1319 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1320 (int) hw->mac.type, (int) hw->phy.type,
1321 (int) hw->phy.sfp_type);
1323 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1324 (int) hw->mac.type, (int) hw->phy.type);
1326 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1327 eth_dev->data->port_id, pci_dev->id.vendor_id,
1328 pci_dev->id.device_id);
1330 rte_intr_callback_register(intr_handle,
1331 ixgbe_dev_interrupt_handler, eth_dev);
1333 /* enable uio/vfio intr/eventfd mapping */
1334 rte_intr_enable(intr_handle);
1336 /* enable support intr */
1337 ixgbe_enable_intr(eth_dev);
1339 /* initialize filter info */
1340 memset(filter_info, 0,
1341 sizeof(struct ixgbe_filter_info));
1343 /* initialize 5tuple filter list */
1344 TAILQ_INIT(&filter_info->fivetuple_list);
1346 /* initialize flow director filter list & hash */
1347 ixgbe_fdir_filter_init(eth_dev);
1349 /* initialize l2 tunnel filter list & hash */
1350 ixgbe_l2_tn_filter_init(eth_dev);
1352 TAILQ_INIT(&filter_ntuple_list);
1353 TAILQ_INIT(&filter_ethertype_list);
1354 TAILQ_INIT(&filter_syn_list);
1355 TAILQ_INIT(&filter_fdir_list);
1356 TAILQ_INIT(&filter_l2_tunnel_list);
1357 TAILQ_INIT(&ixgbe_flow_list);
1359 /* initialize bandwidth configuration info */
1360 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1366 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1368 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1369 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1370 struct ixgbe_hw *hw;
1372 PMD_INIT_FUNC_TRACE();
1374 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1377 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1379 if (hw->adapter_stopped == 0)
1380 ixgbe_dev_close(eth_dev);
1382 eth_dev->dev_ops = NULL;
1383 eth_dev->rx_pkt_burst = NULL;
1384 eth_dev->tx_pkt_burst = NULL;
1386 /* Unlock any pending hardware semaphore */
1387 ixgbe_swfw_lock_reset(hw);
1389 /* disable uio intr before callback unregister */
1390 rte_intr_disable(intr_handle);
1391 rte_intr_callback_unregister(intr_handle,
1392 ixgbe_dev_interrupt_handler, eth_dev);
1394 /* uninitialize PF if max_vfs not zero */
1395 ixgbe_pf_host_uninit(eth_dev);
1397 rte_free(eth_dev->data->mac_addrs);
1398 eth_dev->data->mac_addrs = NULL;
1400 rte_free(eth_dev->data->hash_mac_addrs);
1401 eth_dev->data->hash_mac_addrs = NULL;
1403 /* remove all the fdir filters & hash */
1404 ixgbe_fdir_filter_uninit(eth_dev);
1406 /* remove all the L2 tunnel filters & hash */
1407 ixgbe_l2_tn_filter_uninit(eth_dev);
1409 /* Remove all ntuple filters of the device */
1410 ixgbe_ntuple_filter_uninit(eth_dev);
1412 /* clear all the filters list */
1413 ixgbe_filterlist_flush();
1418 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1420 struct ixgbe_filter_info *filter_info =
1421 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1422 struct ixgbe_5tuple_filter *p_5tuple;
1424 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1425 TAILQ_REMOVE(&filter_info->fivetuple_list,
1430 memset(filter_info->fivetuple_mask, 0,
1431 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1436 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1438 struct ixgbe_hw_fdir_info *fdir_info =
1439 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1440 struct ixgbe_fdir_filter *fdir_filter;
1442 if (fdir_info->hash_map)
1443 rte_free(fdir_info->hash_map);
1444 if (fdir_info->hash_handle)
1445 rte_hash_free(fdir_info->hash_handle);
1447 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1448 TAILQ_REMOVE(&fdir_info->fdir_list,
1451 rte_free(fdir_filter);
1457 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1459 struct ixgbe_l2_tn_info *l2_tn_info =
1460 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461 struct ixgbe_l2_tn_filter *l2_tn_filter;
1463 if (l2_tn_info->hash_map)
1464 rte_free(l2_tn_info->hash_map);
1465 if (l2_tn_info->hash_handle)
1466 rte_hash_free(l2_tn_info->hash_handle);
1468 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1469 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1472 rte_free(l2_tn_filter);
1478 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1480 struct ixgbe_hw_fdir_info *fdir_info =
1481 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1482 char fdir_hash_name[RTE_HASH_NAMESIZE];
1483 struct rte_hash_parameters fdir_hash_params = {
1484 .name = fdir_hash_name,
1485 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1486 .key_len = sizeof(union ixgbe_atr_input),
1487 .hash_func = rte_hash_crc,
1488 .hash_func_init_val = 0,
1489 .socket_id = rte_socket_id(),
1492 TAILQ_INIT(&fdir_info->fdir_list);
1493 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1494 "fdir_%s", eth_dev->data->name);
1495 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1496 if (!fdir_info->hash_handle) {
1497 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1500 fdir_info->hash_map = rte_zmalloc("ixgbe",
1501 sizeof(struct ixgbe_fdir_filter *) *
1502 IXGBE_MAX_FDIR_FILTER_NUM,
1504 if (!fdir_info->hash_map) {
1506 "Failed to allocate memory for fdir hash map!");
1509 fdir_info->mask_added = FALSE;
1514 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1516 struct ixgbe_l2_tn_info *l2_tn_info =
1517 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1518 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1519 struct rte_hash_parameters l2_tn_hash_params = {
1520 .name = l2_tn_hash_name,
1521 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1522 .key_len = sizeof(struct ixgbe_l2_tn_key),
1523 .hash_func = rte_hash_crc,
1524 .hash_func_init_val = 0,
1525 .socket_id = rte_socket_id(),
1528 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1529 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1530 "l2_tn_%s", eth_dev->data->name);
1531 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1532 if (!l2_tn_info->hash_handle) {
1533 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1536 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1537 sizeof(struct ixgbe_l2_tn_filter *) *
1538 IXGBE_MAX_L2_TN_FILTER_NUM,
1540 if (!l2_tn_info->hash_map) {
1542 "Failed to allocate memory for L2 TN hash map!");
1545 l2_tn_info->e_tag_en = FALSE;
1546 l2_tn_info->e_tag_fwd_en = FALSE;
1547 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1552 * Negotiate mailbox API version with the PF.
1553 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1554 * Then we try to negotiate starting with the most recent one.
1555 * If all negotiation attempts fail, then we will proceed with
1556 * the default one (ixgbe_mbox_api_10).
1559 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1563 /* start with highest supported, proceed down */
1564 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1571 i != RTE_DIM(sup_ver) &&
1572 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1578 generate_random_mac_addr(struct ether_addr *mac_addr)
1582 /* Set Organizationally Unique Identifier (OUI) prefix. */
1583 mac_addr->addr_bytes[0] = 0x00;
1584 mac_addr->addr_bytes[1] = 0x09;
1585 mac_addr->addr_bytes[2] = 0xC0;
1586 /* Force indication of locally assigned MAC address. */
1587 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1588 /* Generate the last 3 bytes of the MAC address with a random number. */
1589 random = rte_rand();
1590 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1594 * Virtual Function device init
1597 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1601 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603 struct ixgbe_hw *hw =
1604 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1605 struct ixgbe_vfta *shadow_vfta =
1606 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1607 struct ixgbe_hwstrip *hwstrip =
1608 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1609 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1611 PMD_INIT_FUNC_TRACE();
1613 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1614 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1615 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1617 /* for secondary processes, we don't initialise any further as primary
1618 * has already done this work. Only check we don't need a different
1621 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1622 struct ixgbe_tx_queue *txq;
1623 /* TX queue function in primary, set by last queue initialized
1624 * Tx queue may not initialized by primary process
1626 if (eth_dev->data->tx_queues) {
1627 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1628 ixgbe_set_tx_function(eth_dev, txq);
1630 /* Use default TX function if we get here */
1631 PMD_INIT_LOG(NOTICE,
1632 "No TX queues configured yet. Using default TX function.");
1635 ixgbe_set_rx_function(eth_dev);
1640 rte_eth_copy_pci_info(eth_dev, pci_dev);
1641 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1643 hw->device_id = pci_dev->id.device_id;
1644 hw->vendor_id = pci_dev->id.vendor_id;
1645 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1647 /* initialize the vfta */
1648 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1650 /* initialize the hw strip bitmap*/
1651 memset(hwstrip, 0, sizeof(*hwstrip));
1653 /* Initialize the shared code (base driver) */
1654 diag = ixgbe_init_shared_code(hw);
1655 if (diag != IXGBE_SUCCESS) {
1656 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1660 /* init_mailbox_params */
1661 hw->mbx.ops.init_params(hw);
1663 /* Reset the hw statistics */
1664 ixgbevf_dev_stats_reset(eth_dev);
1666 /* Disable the interrupts for VF */
1667 ixgbevf_intr_disable(hw);
1669 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1670 diag = hw->mac.ops.reset_hw(hw);
1673 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1674 * the underlying PF driver has not assigned a MAC address to the VF.
1675 * In this case, assign a random MAC address.
1677 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1678 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1682 /* negotiate mailbox API version to use with the PF. */
1683 ixgbevf_negotiate_api(hw);
1685 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1686 ixgbevf_get_queues(hw, &tcs, &tc);
1688 /* Allocate memory for storing MAC addresses */
1689 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1690 hw->mac.num_rar_entries, 0);
1691 if (eth_dev->data->mac_addrs == NULL) {
1693 "Failed to allocate %u bytes needed to store "
1695 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1699 /* Generate a random MAC address, if none was assigned by PF. */
1700 if (is_zero_ether_addr(perm_addr)) {
1701 generate_random_mac_addr(perm_addr);
1702 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1704 rte_free(eth_dev->data->mac_addrs);
1705 eth_dev->data->mac_addrs = NULL;
1708 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1709 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1710 "%02x:%02x:%02x:%02x:%02x:%02x",
1711 perm_addr->addr_bytes[0],
1712 perm_addr->addr_bytes[1],
1713 perm_addr->addr_bytes[2],
1714 perm_addr->addr_bytes[3],
1715 perm_addr->addr_bytes[4],
1716 perm_addr->addr_bytes[5]);
1719 /* Copy the permanent MAC address */
1720 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1722 /* reset the hardware with the new settings */
1723 diag = hw->mac.ops.start_hw(hw);
1729 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1733 rte_intr_callback_register(intr_handle,
1734 ixgbevf_dev_interrupt_handler, eth_dev);
1735 rte_intr_enable(intr_handle);
1736 ixgbevf_intr_enable(hw);
1738 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1739 eth_dev->data->port_id, pci_dev->id.vendor_id,
1740 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1745 /* Virtual Function device uninit */
1748 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1750 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1751 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752 struct ixgbe_hw *hw;
1754 PMD_INIT_FUNC_TRACE();
1756 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1759 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1761 if (hw->adapter_stopped == 0)
1762 ixgbevf_dev_close(eth_dev);
1764 eth_dev->dev_ops = NULL;
1765 eth_dev->rx_pkt_burst = NULL;
1766 eth_dev->tx_pkt_burst = NULL;
1768 /* Disable the interrupts for VF */
1769 ixgbevf_intr_disable(hw);
1771 rte_free(eth_dev->data->mac_addrs);
1772 eth_dev->data->mac_addrs = NULL;
1774 rte_intr_disable(intr_handle);
1775 rte_intr_callback_unregister(intr_handle,
1776 ixgbevf_dev_interrupt_handler, eth_dev);
1781 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1782 struct rte_pci_device *pci_dev)
1784 return rte_eth_dev_pci_generic_probe(pci_dev,
1785 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1788 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1790 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1793 static struct rte_pci_driver rte_ixgbe_pmd = {
1794 .id_table = pci_id_ixgbe_map,
1795 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1796 .probe = eth_ixgbe_pci_probe,
1797 .remove = eth_ixgbe_pci_remove,
1800 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1801 struct rte_pci_device *pci_dev)
1803 return rte_eth_dev_pci_generic_probe(pci_dev,
1804 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1807 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1809 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1813 * virtual function driver struct
1815 static struct rte_pci_driver rte_ixgbevf_pmd = {
1816 .id_table = pci_id_ixgbevf_map,
1817 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1818 .probe = eth_ixgbevf_pci_probe,
1819 .remove = eth_ixgbevf_pci_remove,
1823 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1825 struct ixgbe_hw *hw =
1826 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827 struct ixgbe_vfta *shadow_vfta =
1828 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1833 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1834 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1835 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1840 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1842 /* update local VFTA copy */
1843 shadow_vfta->vfta[vid_idx] = vfta;
1849 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1852 ixgbe_vlan_hw_strip_enable(dev, queue);
1854 ixgbe_vlan_hw_strip_disable(dev, queue);
1858 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1859 enum rte_vlan_type vlan_type,
1862 struct ixgbe_hw *hw =
1863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869 qinq &= IXGBE_DMATXCTL_GDV;
1871 switch (vlan_type) {
1872 case ETH_VLAN_TYPE_INNER:
1874 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1875 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1876 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1877 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1879 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1880 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1883 PMD_DRV_LOG(ERR, "Inner type is not supported"
1887 case ETH_VLAN_TYPE_OUTER:
1889 /* Only the high 16-bits is valid */
1890 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1891 IXGBE_EXVET_VET_EXT_SHIFT);
1893 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1894 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1895 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1896 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1898 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1899 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1905 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1913 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1915 struct ixgbe_hw *hw =
1916 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919 PMD_INIT_FUNC_TRACE();
1921 /* Filter Table Disable */
1922 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1923 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1925 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1929 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1931 struct ixgbe_hw *hw =
1932 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933 struct ixgbe_vfta *shadow_vfta =
1934 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1938 PMD_INIT_FUNC_TRACE();
1940 /* Filter Table Enable */
1941 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1943 vlnctrl |= IXGBE_VLNCTRL_VFE;
1945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1947 /* write whatever is in local vfta copy */
1948 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1949 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1953 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1955 struct ixgbe_hwstrip *hwstrip =
1956 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1957 struct ixgbe_rx_queue *rxq;
1959 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1963 IXGBE_SET_HWSTRIP(hwstrip, queue);
1965 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1967 if (queue >= dev->data->nb_rx_queues)
1970 rxq = dev->data->rx_queues[queue];
1973 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1975 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1979 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1981 struct ixgbe_hw *hw =
1982 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 PMD_INIT_FUNC_TRACE();
1987 if (hw->mac.type == ixgbe_mac_82598EB) {
1988 /* No queue level support */
1989 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1993 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995 ctrl &= ~IXGBE_RXDCTL_VME;
1996 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1998 /* record those setting for HW strip per queue */
1999 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2003 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2005 struct ixgbe_hw *hw =
2006 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009 PMD_INIT_FUNC_TRACE();
2011 if (hw->mac.type == ixgbe_mac_82598EB) {
2012 /* No queue level supported */
2013 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2017 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019 ctrl |= IXGBE_RXDCTL_VME;
2020 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2022 /* record those setting for HW strip per queue */
2023 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2027 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2029 struct ixgbe_hw *hw =
2030 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033 struct ixgbe_rx_queue *rxq;
2035 PMD_INIT_FUNC_TRACE();
2037 if (hw->mac.type == ixgbe_mac_82598EB) {
2038 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2039 ctrl &= ~IXGBE_VLNCTRL_VME;
2040 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2044 rxq = dev->data->rx_queues[i];
2045 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2046 ctrl &= ~IXGBE_RXDCTL_VME;
2047 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2049 /* record those setting for HW strip per queue */
2050 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2056 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2058 struct ixgbe_hw *hw =
2059 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 struct ixgbe_rx_queue *rxq;
2064 PMD_INIT_FUNC_TRACE();
2066 if (hw->mac.type == ixgbe_mac_82598EB) {
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2068 ctrl |= IXGBE_VLNCTRL_VME;
2069 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2071 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2072 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2073 rxq = dev->data->rx_queues[i];
2074 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2075 ctrl |= IXGBE_RXDCTL_VME;
2076 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2078 /* record those setting for HW strip per queue */
2079 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2085 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2087 struct ixgbe_hw *hw =
2088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 PMD_INIT_FUNC_TRACE();
2093 /* DMATXCTRL: Geric Double VLAN Disable */
2094 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095 ctrl &= ~IXGBE_DMATXCTL_GDV;
2096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2098 /* CTRL_EXT: Global Double VLAN Disable */
2099 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100 ctrl &= ~IXGBE_EXTENDED_VLAN;
2101 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2106 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2108 struct ixgbe_hw *hw =
2109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 PMD_INIT_FUNC_TRACE();
2114 /* DMATXCTRL: Geric Double VLAN Enable */
2115 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2116 ctrl |= IXGBE_DMATXCTL_GDV;
2117 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2119 /* CTRL_EXT: Global Double VLAN Enable */
2120 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2121 ctrl |= IXGBE_EXTENDED_VLAN;
2122 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2124 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2125 if (hw->mac.type == ixgbe_mac_X550 ||
2126 hw->mac.type == ixgbe_mac_X550EM_x ||
2127 hw->mac.type == ixgbe_mac_X550EM_a) {
2128 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2129 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2130 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2134 * VET EXT field in the EXVET register = 0x8100 by default
2135 * So no need to change. Same to VT field of DMATXCTL register
2140 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2142 if (mask & ETH_VLAN_STRIP_MASK) {
2143 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2144 ixgbe_vlan_hw_strip_enable_all(dev);
2146 ixgbe_vlan_hw_strip_disable_all(dev);
2149 if (mask & ETH_VLAN_FILTER_MASK) {
2150 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2151 ixgbe_vlan_hw_filter_enable(dev);
2153 ixgbe_vlan_hw_filter_disable(dev);
2156 if (mask & ETH_VLAN_EXTEND_MASK) {
2157 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2158 ixgbe_vlan_hw_extend_enable(dev);
2160 ixgbe_vlan_hw_extend_disable(dev);
2165 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2167 struct ixgbe_hw *hw =
2168 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2170 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2172 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2173 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2177 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2179 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2184 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2187 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2193 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2194 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2200 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2202 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2205 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2207 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2208 /* check multi-queue mode */
2209 switch (dev_conf->rxmode.mq_mode) {
2210 case ETH_MQ_RX_VMDQ_DCB:
2211 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2213 case ETH_MQ_RX_VMDQ_DCB_RSS:
2214 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2215 PMD_INIT_LOG(ERR, "SRIOV active,"
2216 " unsupported mq_mode rx %d.",
2217 dev_conf->rxmode.mq_mode);
2220 case ETH_MQ_RX_VMDQ_RSS:
2221 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2222 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2223 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2224 PMD_INIT_LOG(ERR, "SRIOV is active,"
2225 " invalid queue number"
2226 " for VMDQ RSS, allowed"
2227 " value are 1, 2 or 4.");
2231 case ETH_MQ_RX_VMDQ_ONLY:
2232 case ETH_MQ_RX_NONE:
2233 /* if nothing mq mode configure, use default scheme */
2234 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2235 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2236 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2238 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2239 /* SRIOV only works in VMDq enable mode */
2240 PMD_INIT_LOG(ERR, "SRIOV is active,"
2241 " wrong mq_mode rx %d.",
2242 dev_conf->rxmode.mq_mode);
2246 switch (dev_conf->txmode.mq_mode) {
2247 case ETH_MQ_TX_VMDQ_DCB:
2248 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2249 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2251 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2252 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2256 /* check valid queue number */
2257 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2258 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2259 PMD_INIT_LOG(ERR, "SRIOV is active,"
2260 " nb_rx_q=%d nb_tx_q=%d queue number"
2261 " must be less than or equal to %d.",
2263 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2267 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2268 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2272 /* check configuration for vmdb+dcb mode */
2273 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2274 const struct rte_eth_vmdq_dcb_conf *conf;
2276 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2277 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2278 IXGBE_VMDQ_DCB_NB_QUEUES);
2281 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2282 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2283 conf->nb_queue_pools == ETH_32_POOLS)) {
2284 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2285 " nb_queue_pools must be %d or %d.",
2286 ETH_16_POOLS, ETH_32_POOLS);
2290 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2291 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2293 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2294 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2295 IXGBE_VMDQ_DCB_NB_QUEUES);
2298 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2299 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2300 conf->nb_queue_pools == ETH_32_POOLS)) {
2301 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2302 " nb_queue_pools != %d and"
2303 " nb_queue_pools != %d.",
2304 ETH_16_POOLS, ETH_32_POOLS);
2309 /* For DCB mode check our configuration before we go further */
2310 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2311 const struct rte_eth_dcb_rx_conf *conf;
2313 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2314 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2315 IXGBE_DCB_NB_QUEUES);
2318 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2319 if (!(conf->nb_tcs == ETH_4_TCS ||
2320 conf->nb_tcs == ETH_8_TCS)) {
2321 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2322 " and nb_tcs != %d.",
2323 ETH_4_TCS, ETH_8_TCS);
2328 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2329 const struct rte_eth_dcb_tx_conf *conf;
2331 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2332 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2333 IXGBE_DCB_NB_QUEUES);
2336 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2337 if (!(conf->nb_tcs == ETH_4_TCS ||
2338 conf->nb_tcs == ETH_8_TCS)) {
2339 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2340 " and nb_tcs != %d.",
2341 ETH_4_TCS, ETH_8_TCS);
2347 * When DCB/VT is off, maximum number of queues changes,
2348 * except for 82598EB, which remains constant.
2350 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2351 hw->mac.type != ixgbe_mac_82598EB) {
2352 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2354 "Neither VT nor DCB are enabled, "
2356 IXGBE_NONE_MODE_TX_NB_QUEUES);
2365 ixgbe_dev_configure(struct rte_eth_dev *dev)
2367 struct ixgbe_interrupt *intr =
2368 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369 struct ixgbe_adapter *adapter =
2370 (struct ixgbe_adapter *)dev->data->dev_private;
2373 PMD_INIT_FUNC_TRACE();
2374 /* multipe queue mode checking */
2375 ret = ixgbe_check_mq_mode(dev);
2377 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2382 /* set flag to update link status after init */
2383 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2386 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2387 * allocation or vector Rx preconditions we will reset it.
2389 adapter->rx_bulk_alloc_allowed = true;
2390 adapter->rx_vec_allowed = true;
2396 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2398 struct ixgbe_hw *hw =
2399 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 struct ixgbe_interrupt *intr =
2401 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2404 /* only set up it on X550EM_X */
2405 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2406 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2407 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2408 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2409 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2410 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2415 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2416 uint16_t tx_rate, uint64_t q_msk)
2418 struct ixgbe_hw *hw;
2419 struct ixgbe_vf_info *vfinfo;
2420 struct rte_eth_link link;
2421 uint8_t nb_q_per_pool;
2422 uint32_t queue_stride;
2423 uint32_t queue_idx, idx = 0, vf_idx;
2425 uint16_t total_rate = 0;
2426 struct rte_pci_device *pci_dev;
2428 pci_dev = IXGBE_DEV_TO_PCI(dev);
2429 rte_eth_link_get_nowait(dev->data->port_id, &link);
2431 if (vf >= pci_dev->max_vfs)
2434 if (tx_rate > link.link_speed)
2440 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2442 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2443 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2444 queue_idx = vf * queue_stride;
2445 queue_end = queue_idx + nb_q_per_pool - 1;
2446 if (queue_end >= hw->mac.max_tx_queues)
2450 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2453 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2455 total_rate += vfinfo[vf_idx].tx_rate[idx];
2461 /* Store tx_rate for this vf. */
2462 for (idx = 0; idx < nb_q_per_pool; idx++) {
2463 if (((uint64_t)0x1 << idx) & q_msk) {
2464 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2465 vfinfo[vf].tx_rate[idx] = tx_rate;
2466 total_rate += tx_rate;
2470 if (total_rate > dev->data->dev_link.link_speed) {
2471 /* Reset stored TX rate of the VF if it causes exceed
2474 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2478 /* Set RTTBCNRC of each queue/pool for vf X */
2479 for (; queue_idx <= queue_end; queue_idx++) {
2481 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2489 * Configure device link speed and setup link.
2490 * It returns 0 on success.
2493 ixgbe_dev_start(struct rte_eth_dev *dev)
2495 struct ixgbe_hw *hw =
2496 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497 struct ixgbe_vf_info *vfinfo =
2498 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2499 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2500 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2501 uint32_t intr_vector = 0;
2502 int err, link_up = 0, negotiate = 0;
2507 uint32_t *link_speeds;
2509 PMD_INIT_FUNC_TRACE();
2511 /* IXGBE devices don't support:
2512 * - half duplex (checked afterwards for valid speeds)
2513 * - fixed speed: TODO implement
2515 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2517 dev->data->port_id);
2521 /* disable uio/vfio intr/eventfd mapping */
2522 rte_intr_disable(intr_handle);
2525 hw->adapter_stopped = 0;
2526 ixgbe_stop_adapter(hw);
2528 /* reinitialize adapter
2529 * this calls reset and start
2531 status = ixgbe_pf_reset_hw(hw);
2534 hw->mac.ops.start_hw(hw);
2535 hw->mac.get_link_status = true;
2537 /* configure PF module if SRIOV enabled */
2538 ixgbe_pf_host_configure(dev);
2540 ixgbe_dev_phy_intr_setup(dev);
2542 /* check and configure queue intr-vector mapping */
2543 if ((rte_intr_cap_multiple(intr_handle) ||
2544 !RTE_ETH_DEV_SRIOV(dev).active) &&
2545 dev->data->dev_conf.intr_conf.rxq != 0) {
2546 intr_vector = dev->data->nb_rx_queues;
2547 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2548 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2549 IXGBE_MAX_INTR_QUEUE_NUM);
2552 if (rte_intr_efd_enable(intr_handle, intr_vector))
2556 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2557 intr_handle->intr_vec =
2558 rte_zmalloc("intr_vec",
2559 dev->data->nb_rx_queues * sizeof(int), 0);
2560 if (intr_handle->intr_vec == NULL) {
2561 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2562 " intr_vec", dev->data->nb_rx_queues);
2567 /* confiugre msix for sleep until rx interrupt */
2568 ixgbe_configure_msix(dev);
2570 /* initialize transmission unit */
2571 ixgbe_dev_tx_init(dev);
2573 /* This can fail when allocating mbufs for descriptor rings */
2574 err = ixgbe_dev_rx_init(dev);
2576 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2580 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2581 ETH_VLAN_EXTEND_MASK;
2582 ixgbe_vlan_offload_set(dev, mask);
2584 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2585 /* Enable vlan filtering for VMDq */
2586 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2589 /* Configure DCB hw */
2590 ixgbe_configure_dcb(dev);
2592 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2593 err = ixgbe_fdir_configure(dev);
2598 /* Restore vf rate limit */
2599 if (vfinfo != NULL) {
2600 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2601 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2602 if (vfinfo[vf].tx_rate[idx] != 0)
2603 ixgbe_set_vf_rate_limit(
2605 vfinfo[vf].tx_rate[idx],
2609 ixgbe_restore_statistics_mapping(dev);
2611 err = ixgbe_dev_rxtx_start(dev);
2613 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2617 /* Skip link setup if loopback mode is enabled for 82599. */
2618 if (hw->mac.type == ixgbe_mac_82599EB &&
2619 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2620 goto skip_link_setup;
2622 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2623 err = hw->mac.ops.setup_sfp(hw);
2628 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2629 /* Turn on the copper */
2630 ixgbe_set_phy_power(hw, true);
2632 /* Turn on the laser */
2633 ixgbe_enable_tx_laser(hw);
2636 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2639 dev->data->dev_link.link_status = link_up;
2641 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2645 link_speeds = &dev->data->dev_conf.link_speeds;
2646 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2647 ETH_LINK_SPEED_10G)) {
2648 PMD_INIT_LOG(ERR, "Invalid link setting");
2653 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2654 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2655 IXGBE_LINK_SPEED_82599_AUTONEG :
2656 IXGBE_LINK_SPEED_82598_AUTONEG;
2658 if (*link_speeds & ETH_LINK_SPEED_10G)
2659 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660 if (*link_speeds & ETH_LINK_SPEED_1G)
2661 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662 if (*link_speeds & ETH_LINK_SPEED_100M)
2663 speed |= IXGBE_LINK_SPEED_100_FULL;
2666 err = ixgbe_setup_link(hw, speed, link_up);
2672 if (rte_intr_allow_others(intr_handle)) {
2673 /* check if lsc interrupt is enabled */
2674 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675 ixgbe_dev_lsc_interrupt_setup(dev);
2676 ixgbe_dev_macsec_interrupt_setup(dev);
2678 rte_intr_callback_unregister(intr_handle,
2679 ixgbe_dev_interrupt_handler, dev);
2680 if (dev->data->dev_conf.intr_conf.lsc != 0)
2681 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2682 " no intr multiplex");
2685 /* check if rxq interrupt is enabled */
2686 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2687 rte_intr_dp_is_en(intr_handle))
2688 ixgbe_dev_rxq_interrupt_setup(dev);
2690 /* enable uio/vfio intr/eventfd mapping */
2691 rte_intr_enable(intr_handle);
2693 /* resume enabled intr since hw reset */
2694 ixgbe_enable_intr(dev);
2695 ixgbe_l2_tunnel_conf(dev);
2696 ixgbe_filter_restore(dev);
2701 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2702 ixgbe_dev_clear_queues(dev);
2707 * Stop device: disable rx and tx functions to allow for reconfiguring.
2710 ixgbe_dev_stop(struct rte_eth_dev *dev)
2712 struct rte_eth_link link;
2713 struct ixgbe_hw *hw =
2714 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715 struct ixgbe_vf_info *vfinfo =
2716 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2717 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2718 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2721 PMD_INIT_FUNC_TRACE();
2723 /* disable interrupts */
2724 ixgbe_disable_intr(hw);
2727 ixgbe_pf_reset_hw(hw);
2728 hw->adapter_stopped = 0;
2731 ixgbe_stop_adapter(hw);
2733 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734 vfinfo[vf].clear_to_send = false;
2736 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737 /* Turn off the copper */
2738 ixgbe_set_phy_power(hw, false);
2740 /* Turn off the laser */
2741 ixgbe_disable_tx_laser(hw);
2744 ixgbe_dev_clear_queues(dev);
2746 /* Clear stored conf */
2747 dev->data->scattered_rx = 0;
2750 /* Clear recorded link status */
2751 memset(&link, 0, sizeof(link));
2752 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2754 if (!rte_intr_allow_others(intr_handle))
2755 /* resume to the default handler */
2756 rte_intr_callback_register(intr_handle,
2757 ixgbe_dev_interrupt_handler,
2760 /* Clean datapath event and queue/vec mapping */
2761 rte_intr_efd_disable(intr_handle);
2762 if (intr_handle->intr_vec != NULL) {
2763 rte_free(intr_handle->intr_vec);
2764 intr_handle->intr_vec = NULL;
2769 * Set device link up: enable tx.
2772 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2774 struct ixgbe_hw *hw =
2775 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776 if (hw->mac.type == ixgbe_mac_82599EB) {
2777 #ifdef RTE_NIC_BYPASS
2778 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2779 /* Not suported in bypass mode */
2780 PMD_INIT_LOG(ERR, "Set link up is not supported "
2781 "by device id 0x%x", hw->device_id);
2787 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2788 /* Turn on the copper */
2789 ixgbe_set_phy_power(hw, true);
2791 /* Turn on the laser */
2792 ixgbe_enable_tx_laser(hw);
2799 * Set device link down: disable tx.
2802 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2804 struct ixgbe_hw *hw =
2805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 if (hw->mac.type == ixgbe_mac_82599EB) {
2807 #ifdef RTE_NIC_BYPASS
2808 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2809 /* Not suported in bypass mode */
2810 PMD_INIT_LOG(ERR, "Set link down is not supported "
2811 "by device id 0x%x", hw->device_id);
2817 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2818 /* Turn off the copper */
2819 ixgbe_set_phy_power(hw, false);
2821 /* Turn off the laser */
2822 ixgbe_disable_tx_laser(hw);
2829 * Reest and stop device.
2832 ixgbe_dev_close(struct rte_eth_dev *dev)
2834 struct ixgbe_hw *hw =
2835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 PMD_INIT_FUNC_TRACE();
2839 ixgbe_pf_reset_hw(hw);
2841 ixgbe_dev_stop(dev);
2842 hw->adapter_stopped = 1;
2844 ixgbe_dev_free_queues(dev);
2846 ixgbe_disable_pcie_master(hw);
2848 /* reprogram the RAR[0] in case user changed it. */
2849 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2853 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2854 struct ixgbe_hw_stats *hw_stats,
2855 struct ixgbe_macsec_stats *macsec_stats,
2856 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2857 uint64_t *total_qprc, uint64_t *total_qprdc)
2859 uint32_t bprc, lxon, lxoff, total;
2860 uint32_t delta_gprc = 0;
2862 /* Workaround for RX byte count not including CRC bytes when CRC
2863 * strip is enabled. CRC bytes are removed from counters when crc_strip
2866 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2867 IXGBE_HLREG0_RXCRCSTRP);
2869 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2870 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2871 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2872 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2874 for (i = 0; i < 8; i++) {
2875 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2877 /* global total per queue */
2878 hw_stats->mpc[i] += mp;
2879 /* Running comprehensive total for stats display */
2880 *total_missed_rx += hw_stats->mpc[i];
2881 if (hw->mac.type == ixgbe_mac_82598EB) {
2882 hw_stats->rnbc[i] +=
2883 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2884 hw_stats->pxonrxc[i] +=
2885 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2886 hw_stats->pxoffrxc[i] +=
2887 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2889 hw_stats->pxonrxc[i] +=
2890 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2891 hw_stats->pxoffrxc[i] +=
2892 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2893 hw_stats->pxon2offc[i] +=
2894 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2896 hw_stats->pxontxc[i] +=
2897 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2898 hw_stats->pxofftxc[i] +=
2899 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2901 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2902 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2903 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2904 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2906 delta_gprc += delta_qprc;
2908 hw_stats->qprc[i] += delta_qprc;
2909 hw_stats->qptc[i] += delta_qptc;
2911 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2912 hw_stats->qbrc[i] +=
2913 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2915 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2917 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2918 hw_stats->qbtc[i] +=
2919 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2921 hw_stats->qprdc[i] += delta_qprdc;
2922 *total_qprdc += hw_stats->qprdc[i];
2924 *total_qprc += hw_stats->qprc[i];
2925 *total_qbrc += hw_stats->qbrc[i];
2927 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2928 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2929 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2932 * An errata states that gprc actually counts good + missed packets:
2933 * Workaround to set gprc to summated queue packet receives
2935 hw_stats->gprc = *total_qprc;
2937 if (hw->mac.type != ixgbe_mac_82598EB) {
2938 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2939 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2940 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2941 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2942 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2943 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2944 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2945 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2947 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2948 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2949 /* 82598 only has a counter in the high register */
2950 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2951 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2952 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2954 uint64_t old_tpr = hw_stats->tpr;
2956 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2957 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2960 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2962 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2963 hw_stats->gptc += delta_gptc;
2964 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2965 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2968 * Workaround: mprc hardware is incorrectly counting
2969 * broadcasts, so for now we subtract those.
2971 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2972 hw_stats->bprc += bprc;
2973 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2974 if (hw->mac.type == ixgbe_mac_82598EB)
2975 hw_stats->mprc -= bprc;
2977 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2978 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2979 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2980 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2981 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2982 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2984 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2985 hw_stats->lxontxc += lxon;
2986 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2987 hw_stats->lxofftxc += lxoff;
2988 total = lxon + lxoff;
2990 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2991 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2992 hw_stats->gptc -= total;
2993 hw_stats->mptc -= total;
2994 hw_stats->ptc64 -= total;
2995 hw_stats->gotc -= total * ETHER_MIN_LEN;
2997 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2998 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2999 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3000 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3001 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3002 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3003 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3004 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3005 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3006 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3007 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3008 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3009 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3010 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3011 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3012 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3013 /* Only read FCOE on 82599 */
3014 if (hw->mac.type != ixgbe_mac_82598EB) {
3015 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3016 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3017 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3018 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3019 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3022 /* Flow Director Stats registers */
3023 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3024 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3026 /* MACsec Stats registers */
3027 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3028 macsec_stats->out_pkts_encrypted +=
3029 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3030 macsec_stats->out_pkts_protected +=
3031 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3032 macsec_stats->out_octets_encrypted +=
3033 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3034 macsec_stats->out_octets_protected +=
3035 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3036 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3037 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3038 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3039 macsec_stats->in_pkts_unknownsci +=
3040 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3041 macsec_stats->in_octets_decrypted +=
3042 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3043 macsec_stats->in_octets_validated +=
3044 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3045 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3046 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3047 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3048 for (i = 0; i < 2; i++) {
3049 macsec_stats->in_pkts_ok +=
3050 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3051 macsec_stats->in_pkts_invalid +=
3052 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3053 macsec_stats->in_pkts_notvalid +=
3054 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3056 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3057 macsec_stats->in_pkts_notusingsa +=
3058 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3062 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3065 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3067 struct ixgbe_hw *hw =
3068 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069 struct ixgbe_hw_stats *hw_stats =
3070 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3071 struct ixgbe_macsec_stats *macsec_stats =
3072 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3073 dev->data->dev_private);
3074 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3077 total_missed_rx = 0;
3082 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3083 &total_qbrc, &total_qprc, &total_qprdc);
3088 /* Fill out the rte_eth_stats statistics structure */
3089 stats->ipackets = total_qprc;
3090 stats->ibytes = total_qbrc;
3091 stats->opackets = hw_stats->gptc;
3092 stats->obytes = hw_stats->gotc;
3094 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3095 stats->q_ipackets[i] = hw_stats->qprc[i];
3096 stats->q_opackets[i] = hw_stats->qptc[i];
3097 stats->q_ibytes[i] = hw_stats->qbrc[i];
3098 stats->q_obytes[i] = hw_stats->qbtc[i];
3099 stats->q_errors[i] = hw_stats->qprdc[i];
3103 stats->imissed = total_missed_rx;
3104 stats->ierrors = hw_stats->crcerrs +
3120 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3122 struct ixgbe_hw_stats *stats =
3123 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3125 /* HW registers are cleared on read */
3126 ixgbe_dev_stats_get(dev, NULL);
3128 /* Reset software totals */
3129 memset(stats, 0, sizeof(*stats));
3132 /* This function calculates the number of xstats based on the current config */
3134 ixgbe_xstats_calc_num(void) {
3135 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3136 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3137 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3140 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3141 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3143 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3144 unsigned stat, i, count;
3146 if (xstats_names != NULL) {
3149 /* Note: limit >= cnt_stats checked upstream
3150 * in rte_eth_xstats_names()
3153 /* Extended stats from ixgbe_hw_stats */
3154 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3155 snprintf(xstats_names[count].name,
3156 sizeof(xstats_names[count].name),
3158 rte_ixgbe_stats_strings[i].name);
3163 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3164 snprintf(xstats_names[count].name,
3165 sizeof(xstats_names[count].name),
3167 rte_ixgbe_macsec_strings[i].name);
3171 /* RX Priority Stats */
3172 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3173 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3174 snprintf(xstats_names[count].name,
3175 sizeof(xstats_names[count].name),
3176 "rx_priority%u_%s", i,
3177 rte_ixgbe_rxq_strings[stat].name);
3182 /* TX Priority Stats */
3183 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3184 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3185 snprintf(xstats_names[count].name,
3186 sizeof(xstats_names[count].name),
3187 "tx_priority%u_%s", i,
3188 rte_ixgbe_txq_strings[stat].name);
3196 static int ixgbe_dev_xstats_get_names_by_id(
3197 __rte_unused struct rte_eth_dev *dev,
3198 struct rte_eth_xstat_name *xstats_names,
3199 const uint64_t *ids,
3203 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3204 unsigned int stat, i, count;
3206 if (xstats_names != NULL) {
3209 /* Note: limit >= cnt_stats checked upstream
3210 * in rte_eth_xstats_names()
3213 /* Extended stats from ixgbe_hw_stats */
3214 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3215 snprintf(xstats_names[count].name,
3216 sizeof(xstats_names[count].name),
3218 rte_ixgbe_stats_strings[i].name);
3223 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3224 snprintf(xstats_names[count].name,
3225 sizeof(xstats_names[count].name),
3227 rte_ixgbe_macsec_strings[i].name);
3231 /* RX Priority Stats */
3232 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3233 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3234 snprintf(xstats_names[count].name,
3235 sizeof(xstats_names[count].name),
3236 "rx_priority%u_%s", i,
3237 rte_ixgbe_rxq_strings[stat].name);
3242 /* TX Priority Stats */
3243 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3244 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3245 snprintf(xstats_names[count].name,
3246 sizeof(xstats_names[count].name),
3247 "tx_priority%u_%s", i,
3248 rte_ixgbe_txq_strings[stat].name);
3257 uint16_t size = ixgbe_xstats_calc_num();
3258 struct rte_eth_xstat_name xstats_names_copy[size];
3260 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3263 for (i = 0; i < limit; i++) {
3264 if (ids[i] >= size) {
3265 PMD_INIT_LOG(ERR, "id value isn't valid");
3268 strcpy(xstats_names[i].name,
3269 xstats_names_copy[ids[i]].name);
3274 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3275 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3279 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3282 if (xstats_names != NULL)
3283 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3284 snprintf(xstats_names[i].name,
3285 sizeof(xstats_names[i].name),
3286 "%s", rte_ixgbevf_stats_strings[i].name);
3287 return IXGBEVF_NB_XSTATS;
3291 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3294 struct ixgbe_hw *hw =
3295 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296 struct ixgbe_hw_stats *hw_stats =
3297 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298 struct ixgbe_macsec_stats *macsec_stats =
3299 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3300 dev->data->dev_private);
3301 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3302 unsigned i, stat, count = 0;
3304 count = ixgbe_xstats_calc_num();
3309 total_missed_rx = 0;
3314 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3315 &total_qbrc, &total_qprc, &total_qprdc);
3317 /* If this is a reset xstats is NULL, and we have cleared the
3318 * registers by reading them.
3323 /* Extended stats from ixgbe_hw_stats */
3325 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3326 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3327 rte_ixgbe_stats_strings[i].offset);
3328 xstats[count].id = count;
3333 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3334 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3335 rte_ixgbe_macsec_strings[i].offset);
3336 xstats[count].id = count;
3340 /* RX Priority Stats */
3341 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3342 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3343 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344 rte_ixgbe_rxq_strings[stat].offset +
3345 (sizeof(uint64_t) * i));
3346 xstats[count].id = count;
3351 /* TX Priority Stats */
3352 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3353 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3354 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3355 rte_ixgbe_txq_strings[stat].offset +
3356 (sizeof(uint64_t) * i));
3357 xstats[count].id = count;
3365 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3366 uint64_t *values, unsigned int n)
3369 struct ixgbe_hw *hw =
3370 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3371 struct ixgbe_hw_stats *hw_stats =
3372 IXGBE_DEV_PRIVATE_TO_STATS(
3373 dev->data->dev_private);
3374 struct ixgbe_macsec_stats *macsec_stats =
3375 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3376 dev->data->dev_private);
3377 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3378 unsigned int i, stat, count = 0;
3380 count = ixgbe_xstats_calc_num();
3382 if (!ids && n < count)
3385 total_missed_rx = 0;
3390 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3391 &total_missed_rx, &total_qbrc, &total_qprc,
3394 /* If this is a reset xstats is NULL, and we have cleared the
3395 * registers by reading them.
3397 if (!ids && !values)
3400 /* Extended stats from ixgbe_hw_stats */
3402 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3403 values[count] = *(uint64_t *)(((char *)hw_stats) +
3404 rte_ixgbe_stats_strings[i].offset);
3409 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3411 rte_ixgbe_macsec_strings[i].offset);
3415 /* RX Priority Stats */
3416 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3417 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3419 *(uint64_t *)(((char *)hw_stats) +
3420 rte_ixgbe_rxq_strings[stat].offset +
3421 (sizeof(uint64_t) * i));
3426 /* TX Priority Stats */
3427 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3428 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3430 *(uint64_t *)(((char *)hw_stats) +
3431 rte_ixgbe_txq_strings[stat].offset +
3432 (sizeof(uint64_t) * i));
3440 uint16_t size = ixgbe_xstats_calc_num();
3441 uint64_t values_copy[size];
3443 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3445 for (i = 0; i < n; i++) {
3446 if (ids[i] >= size) {
3447 PMD_INIT_LOG(ERR, "id value isn't valid");
3450 values[i] = values_copy[ids[i]];
3456 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3458 struct ixgbe_hw_stats *stats =
3459 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3460 struct ixgbe_macsec_stats *macsec_stats =
3461 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3462 dev->data->dev_private);
3464 unsigned count = ixgbe_xstats_calc_num();
3466 /* HW registers are cleared on read */
3467 ixgbe_dev_xstats_get(dev, NULL, count);
3469 /* Reset software totals */
3470 memset(stats, 0, sizeof(*stats));
3471 memset(macsec_stats, 0, sizeof(*macsec_stats));
3475 ixgbevf_update_stats(struct rte_eth_dev *dev)
3477 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3478 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3479 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3481 /* Good Rx packet, include VF loopback */
3482 UPDATE_VF_STAT(IXGBE_VFGPRC,
3483 hw_stats->last_vfgprc, hw_stats->vfgprc);
3485 /* Good Rx octets, include VF loopback */
3486 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3487 hw_stats->last_vfgorc, hw_stats->vfgorc);
3489 /* Good Tx packet, include VF loopback */
3490 UPDATE_VF_STAT(IXGBE_VFGPTC,
3491 hw_stats->last_vfgptc, hw_stats->vfgptc);
3493 /* Good Tx octets, include VF loopback */
3494 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3495 hw_stats->last_vfgotc, hw_stats->vfgotc);
3497 /* Rx Multicst Packet */
3498 UPDATE_VF_STAT(IXGBE_VFMPRC,
3499 hw_stats->last_vfmprc, hw_stats->vfmprc);
3503 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3506 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3507 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3510 if (n < IXGBEVF_NB_XSTATS)
3511 return IXGBEVF_NB_XSTATS;
3513 ixgbevf_update_stats(dev);
3518 /* Extended stats */
3519 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3521 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3522 rte_ixgbevf_stats_strings[i].offset);
3525 return IXGBEVF_NB_XSTATS;
3529 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3531 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3534 ixgbevf_update_stats(dev);
3539 stats->ipackets = hw_stats->vfgprc;
3540 stats->ibytes = hw_stats->vfgorc;
3541 stats->opackets = hw_stats->vfgptc;
3542 stats->obytes = hw_stats->vfgotc;
3546 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3548 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551 /* Sync HW register to the last stats */
3552 ixgbevf_dev_stats_get(dev, NULL);
3554 /* reset HW current stats*/
3555 hw_stats->vfgprc = 0;
3556 hw_stats->vfgorc = 0;
3557 hw_stats->vfgptc = 0;
3558 hw_stats->vfgotc = 0;
3562 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 u16 eeprom_verh, eeprom_verl;
3569 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3570 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3572 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3573 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3575 ret += 1; /* add the size of '\0' */
3576 if (fw_size < (u32)ret)
3583 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3585 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3589 dev_info->pci_dev = pci_dev;
3590 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3591 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3592 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3594 * When DCB/VT is off, maximum number of queues changes,
3595 * except for 82598EB, which remains constant.
3597 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3598 hw->mac.type != ixgbe_mac_82598EB)
3599 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3601 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3602 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3603 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3604 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3605 dev_info->max_vfs = pci_dev->max_vfs;
3606 if (hw->mac.type == ixgbe_mac_82598EB)
3607 dev_info->max_vmdq_pools = ETH_16_POOLS;
3609 dev_info->max_vmdq_pools = ETH_64_POOLS;
3610 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3611 dev_info->rx_offload_capa =
3612 DEV_RX_OFFLOAD_VLAN_STRIP |
3613 DEV_RX_OFFLOAD_IPV4_CKSUM |
3614 DEV_RX_OFFLOAD_UDP_CKSUM |
3615 DEV_RX_OFFLOAD_TCP_CKSUM;
3618 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3621 if ((hw->mac.type == ixgbe_mac_82599EB ||
3622 hw->mac.type == ixgbe_mac_X540) &&
3623 !RTE_ETH_DEV_SRIOV(dev).active)
3624 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3626 if (hw->mac.type == ixgbe_mac_82599EB ||
3627 hw->mac.type == ixgbe_mac_X540)
3628 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3630 if (hw->mac.type == ixgbe_mac_X550 ||
3631 hw->mac.type == ixgbe_mac_X550EM_x ||
3632 hw->mac.type == ixgbe_mac_X550EM_a)
3633 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3635 dev_info->tx_offload_capa =
3636 DEV_TX_OFFLOAD_VLAN_INSERT |
3637 DEV_TX_OFFLOAD_IPV4_CKSUM |
3638 DEV_TX_OFFLOAD_UDP_CKSUM |
3639 DEV_TX_OFFLOAD_TCP_CKSUM |
3640 DEV_TX_OFFLOAD_SCTP_CKSUM |
3641 DEV_TX_OFFLOAD_TCP_TSO;
3643 if (hw->mac.type == ixgbe_mac_82599EB ||
3644 hw->mac.type == ixgbe_mac_X540)
3645 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3647 if (hw->mac.type == ixgbe_mac_X550 ||
3648 hw->mac.type == ixgbe_mac_X550EM_x ||
3649 hw->mac.type == ixgbe_mac_X550EM_a)
3650 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3652 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3654 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3655 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3656 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3658 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3662 dev_info->default_txconf = (struct rte_eth_txconf) {
3664 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3665 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3666 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3668 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3669 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3670 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3671 ETH_TXQ_FLAGS_NOOFFLOADS,
3674 dev_info->rx_desc_lim = rx_desc_lim;
3675 dev_info->tx_desc_lim = tx_desc_lim;
3677 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3678 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3679 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3681 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3682 if (hw->mac.type == ixgbe_mac_X540 ||
3683 hw->mac.type == ixgbe_mac_X540_vf ||
3684 hw->mac.type == ixgbe_mac_X550 ||
3685 hw->mac.type == ixgbe_mac_X550_vf) {
3686 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3690 static const uint32_t *
3691 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3693 static const uint32_t ptypes[] = {
3694 /* For non-vec functions,
3695 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3696 * for vec functions,
3697 * refers to _recv_raw_pkts_vec().
3701 RTE_PTYPE_L3_IPV4_EXT,
3703 RTE_PTYPE_L3_IPV6_EXT,
3707 RTE_PTYPE_TUNNEL_IP,
3708 RTE_PTYPE_INNER_L3_IPV6,
3709 RTE_PTYPE_INNER_L3_IPV6_EXT,
3710 RTE_PTYPE_INNER_L4_TCP,
3711 RTE_PTYPE_INNER_L4_UDP,
3715 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3716 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3717 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3718 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3724 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3725 struct rte_eth_dev_info *dev_info)
3727 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3730 dev_info->pci_dev = pci_dev;
3731 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3732 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3733 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3734 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3735 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3736 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3737 dev_info->max_vfs = pci_dev->max_vfs;
3738 if (hw->mac.type == ixgbe_mac_82598EB)
3739 dev_info->max_vmdq_pools = ETH_16_POOLS;
3741 dev_info->max_vmdq_pools = ETH_64_POOLS;
3742 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3743 DEV_RX_OFFLOAD_IPV4_CKSUM |
3744 DEV_RX_OFFLOAD_UDP_CKSUM |
3745 DEV_RX_OFFLOAD_TCP_CKSUM;
3746 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3747 DEV_TX_OFFLOAD_IPV4_CKSUM |
3748 DEV_TX_OFFLOAD_UDP_CKSUM |
3749 DEV_TX_OFFLOAD_TCP_CKSUM |
3750 DEV_TX_OFFLOAD_SCTP_CKSUM |
3751 DEV_TX_OFFLOAD_TCP_TSO;
3753 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3755 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3756 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3757 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3759 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3763 dev_info->default_txconf = (struct rte_eth_txconf) {
3765 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3766 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3767 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3769 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3770 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3771 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3772 ETH_TXQ_FLAGS_NOOFFLOADS,
3775 dev_info->rx_desc_lim = rx_desc_lim;
3776 dev_info->tx_desc_lim = tx_desc_lim;
3779 /* return 0 means link status changed, -1 means not changed */
3781 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3783 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 struct rte_eth_link link, old;
3785 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3786 struct ixgbe_interrupt *intr =
3787 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3791 bool autoneg = false;
3793 link.link_status = ETH_LINK_DOWN;
3794 link.link_speed = 0;
3795 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3796 memset(&old, 0, sizeof(old));
3797 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3799 hw->mac.get_link_status = true;
3801 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3802 hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3803 speed = hw->phy.autoneg_advertised;
3805 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3806 ixgbe_setup_link(hw, speed, true);
3809 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3810 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3811 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3813 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3816 link.link_speed = ETH_SPEED_NUM_100M;
3817 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3818 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3819 if (link.link_status == old.link_status)
3825 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3826 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3827 if (link.link_status == old.link_status)
3831 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3832 link.link_status = ETH_LINK_UP;
3833 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3835 switch (link_speed) {
3837 case IXGBE_LINK_SPEED_UNKNOWN:
3838 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3839 link.link_speed = ETH_SPEED_NUM_100M;
3842 case IXGBE_LINK_SPEED_100_FULL:
3843 link.link_speed = ETH_SPEED_NUM_100M;
3846 case IXGBE_LINK_SPEED_1GB_FULL:
3847 link.link_speed = ETH_SPEED_NUM_1G;
3850 case IXGBE_LINK_SPEED_10GB_FULL:
3851 link.link_speed = ETH_SPEED_NUM_10G;
3854 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3856 if (link.link_status == old.link_status)
3863 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3865 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3869 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3870 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3874 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3880 fctrl &= (~IXGBE_FCTRL_UPE);
3881 if (dev->data->all_multicast == 1)
3882 fctrl |= IXGBE_FCTRL_MPE;
3884 fctrl &= (~IXGBE_FCTRL_MPE);
3885 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3889 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3891 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3895 fctrl |= IXGBE_FCTRL_MPE;
3896 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3900 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3902 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905 if (dev->data->promiscuous == 1)
3906 return; /* must remain in all_multicast mode */
3908 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3909 fctrl &= (~IXGBE_FCTRL_MPE);
3910 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3914 * It clears the interrupt causes and enables the interrupt.
3915 * It will be called once only during nic initialized.
3918 * Pointer to struct rte_eth_dev.
3921 * - On success, zero.
3922 * - On failure, a negative value.
3925 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3927 struct ixgbe_interrupt *intr =
3928 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3930 ixgbe_dev_link_status_print(dev);
3931 intr->mask |= IXGBE_EICR_LSC;
3937 * It clears the interrupt causes and enables the interrupt.
3938 * It will be called once only during nic initialized.
3941 * Pointer to struct rte_eth_dev.
3944 * - On success, zero.
3945 * - On failure, a negative value.
3948 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3950 struct ixgbe_interrupt *intr =
3951 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3953 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3959 * It clears the interrupt causes and enables the interrupt.
3960 * It will be called once only during nic initialized.
3963 * Pointer to struct rte_eth_dev.
3966 * - On success, zero.
3967 * - On failure, a negative value.
3970 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3972 struct ixgbe_interrupt *intr =
3973 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3975 intr->mask |= IXGBE_EICR_LINKSEC;
3981 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3984 * Pointer to struct rte_eth_dev.
3987 * - On success, zero.
3988 * - On failure, a negative value.
3991 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995 struct ixgbe_interrupt *intr =
3996 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3998 /* clear all cause mask */
3999 ixgbe_disable_intr(hw);
4001 /* read-on-clear nic registers here */
4002 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4003 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4007 /* set flag for async link update */
4008 if (eicr & IXGBE_EICR_LSC)
4009 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4011 if (eicr & IXGBE_EICR_MAILBOX)
4012 intr->flags |= IXGBE_FLAG_MAILBOX;
4014 if (eicr & IXGBE_EICR_LINKSEC)
4015 intr->flags |= IXGBE_FLAG_MACSEC;
4017 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4018 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4019 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4020 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4026 * It gets and then prints the link status.
4029 * Pointer to struct rte_eth_dev.
4032 * - On success, zero.
4033 * - On failure, a negative value.
4036 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4038 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4039 struct rte_eth_link link;
4041 memset(&link, 0, sizeof(link));
4042 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4043 if (link.link_status) {
4044 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4045 (int)(dev->data->port_id),
4046 (unsigned)link.link_speed,
4047 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4048 "full-duplex" : "half-duplex");
4050 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4051 (int)(dev->data->port_id));
4053 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4054 pci_dev->addr.domain,
4056 pci_dev->addr.devid,
4057 pci_dev->addr.function);
4061 * It executes link_update after knowing an interrupt occurred.
4064 * Pointer to struct rte_eth_dev.
4067 * - On success, zero.
4068 * - On failure, a negative value.
4071 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4072 struct rte_intr_handle *intr_handle)
4074 struct ixgbe_interrupt *intr =
4075 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4077 struct rte_eth_link link;
4078 struct ixgbe_hw *hw =
4079 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4083 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4084 ixgbe_pf_mbx_process(dev);
4085 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4088 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4089 ixgbe_handle_lasi(hw);
4090 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4093 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4094 /* get the link status before link update, for predicting later */
4095 memset(&link, 0, sizeof(link));
4096 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4098 ixgbe_dev_link_update(dev, 0);
4101 if (!link.link_status)
4102 /* handle it 1 sec later, wait it being stable */
4103 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4104 /* likely to down */
4106 /* handle it 4 sec later, wait it being stable */
4107 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4109 ixgbe_dev_link_status_print(dev);
4110 intr->mask_original = intr->mask;
4111 /* only disable lsc interrupt */
4112 intr->mask &= ~IXGBE_EIMS_LSC;
4113 if (rte_eal_alarm_set(timeout * 1000,
4114 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4115 PMD_DRV_LOG(ERR, "Error setting alarm");
4117 intr->mask = intr->mask_original;
4120 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4121 ixgbe_enable_intr(dev);
4122 rte_intr_enable(intr_handle);
4128 * Interrupt handler which shall be registered for alarm callback for delayed
4129 * handling specific interrupt to wait for the stable nic state. As the
4130 * NIC interrupt state is not stable for ixgbe after link is just down,
4131 * it needs to wait 4 seconds to get the stable status.
4134 * Pointer to interrupt handle.
4136 * The address of parameter (struct rte_eth_dev *) regsitered before.
4142 ixgbe_dev_interrupt_delayed_handler(void *param)
4144 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4145 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4146 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4147 struct ixgbe_interrupt *intr =
4148 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4149 struct ixgbe_hw *hw =
4150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153 ixgbe_disable_intr(hw);
4155 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4156 if (eicr & IXGBE_EICR_MAILBOX)
4157 ixgbe_pf_mbx_process(dev);
4159 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4160 ixgbe_handle_lasi(hw);
4161 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4164 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4165 ixgbe_dev_link_update(dev, 0);
4166 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4167 ixgbe_dev_link_status_print(dev);
4168 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4171 if (intr->flags & IXGBE_FLAG_MACSEC) {
4172 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4174 intr->flags &= ~IXGBE_FLAG_MACSEC;
4177 /* restore original mask */
4178 intr->mask = intr->mask_original;
4179 intr->mask_original = 0;
4181 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4182 ixgbe_enable_intr(dev);
4183 rte_intr_enable(intr_handle);
4187 * Interrupt handler triggered by NIC for handling
4188 * specific interrupt.
4191 * Pointer to interrupt handle.
4193 * The address of parameter (struct rte_eth_dev *) regsitered before.
4199 ixgbe_dev_interrupt_handler(void *param)
4201 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4203 ixgbe_dev_interrupt_get_status(dev);
4204 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4208 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4210 struct ixgbe_hw *hw;
4212 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4217 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4219 struct ixgbe_hw *hw;
4221 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4226 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4228 struct ixgbe_hw *hw;
4234 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236 fc_conf->pause_time = hw->fc.pause_time;
4237 fc_conf->high_water = hw->fc.high_water[0];
4238 fc_conf->low_water = hw->fc.low_water[0];
4239 fc_conf->send_xon = hw->fc.send_xon;
4240 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4243 * Return rx_pause status according to actual setting of
4246 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4247 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4253 * Return tx_pause status according to actual setting of
4256 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4257 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4262 if (rx_pause && tx_pause)
4263 fc_conf->mode = RTE_FC_FULL;
4265 fc_conf->mode = RTE_FC_RX_PAUSE;
4267 fc_conf->mode = RTE_FC_TX_PAUSE;
4269 fc_conf->mode = RTE_FC_NONE;
4275 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4277 struct ixgbe_hw *hw;
4279 uint32_t rx_buf_size;
4280 uint32_t max_high_water;
4282 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4289 PMD_INIT_FUNC_TRACE();
4291 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4293 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4296 * At least reserve one Ethernet frame for watermark
4297 * high_water/low_water in kilo bytes for ixgbe
4299 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4300 if ((fc_conf->high_water > max_high_water) ||
4301 (fc_conf->high_water < fc_conf->low_water)) {
4302 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4303 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4307 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4308 hw->fc.pause_time = fc_conf->pause_time;
4309 hw->fc.high_water[0] = fc_conf->high_water;
4310 hw->fc.low_water[0] = fc_conf->low_water;
4311 hw->fc.send_xon = fc_conf->send_xon;
4312 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4314 err = ixgbe_fc_enable(hw);
4316 /* Not negotiated is not an error case */
4317 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4319 /* check if we want to forward MAC frames - driver doesn't have native
4320 * capability to do that, so we'll write the registers ourselves */
4322 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4324 /* set or clear MFLCN.PMCF bit depending on configuration */
4325 if (fc_conf->mac_ctrl_frame_fwd != 0)
4326 mflcn |= IXGBE_MFLCN_PMCF;
4328 mflcn &= ~IXGBE_MFLCN_PMCF;
4330 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4331 IXGBE_WRITE_FLUSH(hw);
4336 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4341 * ixgbe_pfc_enable_generic - Enable flow control
4342 * @hw: pointer to hardware structure
4343 * @tc_num: traffic class number
4344 * Enable flow control according to the current settings.
4347 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4350 uint32_t mflcn_reg, fccfg_reg;
4352 uint32_t fcrtl, fcrth;
4356 /* Validate the water mark configuration */
4357 if (!hw->fc.pause_time) {
4358 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4362 /* Low water mark of zero causes XOFF floods */
4363 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4364 /* High/Low water can not be 0 */
4365 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4366 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4367 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4371 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4372 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4373 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4377 /* Negotiate the fc mode to use */
4378 ixgbe_fc_autoneg(hw);
4380 /* Disable any previous flow control settings */
4381 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4382 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4384 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4385 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4387 switch (hw->fc.current_mode) {
4390 * If the count of enabled RX Priority Flow control >1,
4391 * and the TX pause can not be disabled
4394 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4395 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4396 if (reg & IXGBE_FCRTH_FCEN)
4400 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4402 case ixgbe_fc_rx_pause:
4404 * Rx Flow control is enabled and Tx Flow control is
4405 * disabled by software override. Since there really
4406 * isn't a way to advertise that we are capable of RX
4407 * Pause ONLY, we will advertise that we support both
4408 * symmetric and asymmetric Rx PAUSE. Later, we will
4409 * disable the adapter's ability to send PAUSE frames.
4411 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4413 * If the count of enabled RX Priority Flow control >1,
4414 * and the TX pause can not be disabled
4417 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4418 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4419 if (reg & IXGBE_FCRTH_FCEN)
4423 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4425 case ixgbe_fc_tx_pause:
4427 * Tx Flow control is enabled, and Rx Flow control is
4428 * disabled by software override.
4430 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4433 /* Flow control (both Rx and Tx) is enabled by SW override. */
4434 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4435 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4438 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4439 ret_val = IXGBE_ERR_CONFIG;
4443 /* Set 802.3x based flow control settings. */
4444 mflcn_reg |= IXGBE_MFLCN_DPF;
4445 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4446 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4448 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4449 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4450 hw->fc.high_water[tc_num]) {
4451 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4452 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4453 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4455 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4457 * In order to prevent Tx hangs when the internal Tx
4458 * switch is enabled we must set the high water mark
4459 * to the maximum FCRTH value. This allows the Tx
4460 * switch to function even under heavy Rx workloads.
4462 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4464 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4466 /* Configure pause time (2 TCs per register) */
4467 reg = hw->fc.pause_time * 0x00010001;
4468 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4469 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4471 /* Configure flow control refresh threshold value */
4472 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4479 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4481 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4484 if (hw->mac.type != ixgbe_mac_82598EB) {
4485 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4491 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4494 uint32_t rx_buf_size;
4495 uint32_t max_high_water;
4497 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4498 struct ixgbe_hw *hw =
4499 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500 struct ixgbe_dcb_config *dcb_config =
4501 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4503 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4510 PMD_INIT_FUNC_TRACE();
4512 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4513 tc_num = map[pfc_conf->priority];
4514 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4515 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4517 * At least reserve one Ethernet frame for watermark
4518 * high_water/low_water in kilo bytes for ixgbe
4520 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4521 if ((pfc_conf->fc.high_water > max_high_water) ||
4522 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4523 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4524 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4528 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4529 hw->fc.pause_time = pfc_conf->fc.pause_time;
4530 hw->fc.send_xon = pfc_conf->fc.send_xon;
4531 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4532 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4534 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4536 /* Not negotiated is not an error case */
4537 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4540 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4545 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4546 struct rte_eth_rss_reta_entry64 *reta_conf,
4549 uint16_t i, sp_reta_size;
4552 uint16_t idx, shift;
4553 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4556 PMD_INIT_FUNC_TRACE();
4558 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4559 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4564 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4565 if (reta_size != sp_reta_size) {
4566 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4567 "(%d) doesn't match the number hardware can supported "
4568 "(%d)", reta_size, sp_reta_size);
4572 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4573 idx = i / RTE_RETA_GROUP_SIZE;
4574 shift = i % RTE_RETA_GROUP_SIZE;
4575 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4579 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4580 if (mask == IXGBE_4_BIT_MASK)
4583 r = IXGBE_READ_REG(hw, reta_reg);
4584 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4585 if (mask & (0x1 << j))
4586 reta |= reta_conf[idx].reta[shift + j] <<
4589 reta |= r & (IXGBE_8_BIT_MASK <<
4592 IXGBE_WRITE_REG(hw, reta_reg, reta);
4599 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4600 struct rte_eth_rss_reta_entry64 *reta_conf,
4603 uint16_t i, sp_reta_size;
4606 uint16_t idx, shift;
4607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610 PMD_INIT_FUNC_TRACE();
4611 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4612 if (reta_size != sp_reta_size) {
4613 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4614 "(%d) doesn't match the number hardware can supported "
4615 "(%d)", reta_size, sp_reta_size);
4619 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4620 idx = i / RTE_RETA_GROUP_SIZE;
4621 shift = i % RTE_RETA_GROUP_SIZE;
4622 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4627 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4628 reta = IXGBE_READ_REG(hw, reta_reg);
4629 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4630 if (mask & (0x1 << j))
4631 reta_conf[idx].reta[shift + j] =
4632 ((reta >> (CHAR_BIT * j)) &
4641 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4642 uint32_t index, uint32_t pool)
4644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645 uint32_t enable_addr = 1;
4647 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4652 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656 ixgbe_clear_rar(hw, index);
4660 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4662 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4664 ixgbe_remove_rar(dev, 0);
4666 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4670 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4672 if (strcmp(dev->data->drv_name, drv->driver.name))
4679 is_ixgbe_supported(struct rte_eth_dev *dev)
4681 return is_device_supported(dev, &rte_ixgbe_pmd);
4685 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4689 struct ixgbe_hw *hw;
4690 struct rte_eth_dev_info dev_info;
4691 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4693 ixgbe_dev_info_get(dev, &dev_info);
4695 /* check that mtu is within the allowed range */
4696 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4699 /* refuse mtu that requires the support of scattered packets when this
4700 * feature has not been enabled before.
4702 if (!dev->data->scattered_rx &&
4703 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4704 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4707 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4710 /* switch to jumbo mode if needed */
4711 if (frame_size > ETHER_MAX_LEN) {
4712 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4713 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4715 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4716 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4718 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4720 /* update max frame size */
4721 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4723 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4724 maxfrs &= 0x0000FFFF;
4725 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4726 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4732 * Virtual Function operations
4735 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4737 PMD_INIT_FUNC_TRACE();
4739 /* Clear interrupt mask to stop from interrupts being generated */
4740 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4742 IXGBE_WRITE_FLUSH(hw);
4746 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4748 PMD_INIT_FUNC_TRACE();
4750 /* VF enable interrupt autoclean */
4751 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4752 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4753 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4755 IXGBE_WRITE_FLUSH(hw);
4759 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4761 struct rte_eth_conf *conf = &dev->data->dev_conf;
4762 struct ixgbe_adapter *adapter =
4763 (struct ixgbe_adapter *)dev->data->dev_private;
4765 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4766 dev->data->port_id);
4769 * VF has no ability to enable/disable HW CRC
4770 * Keep the persistent behavior the same as Host PF
4772 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4773 if (!conf->rxmode.hw_strip_crc) {
4774 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4775 conf->rxmode.hw_strip_crc = 1;
4778 if (conf->rxmode.hw_strip_crc) {
4779 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4780 conf->rxmode.hw_strip_crc = 0;
4785 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4786 * allocation or vector Rx preconditions we will reset it.
4788 adapter->rx_bulk_alloc_allowed = true;
4789 adapter->rx_vec_allowed = true;
4795 ixgbevf_dev_start(struct rte_eth_dev *dev)
4797 struct ixgbe_hw *hw =
4798 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799 uint32_t intr_vector = 0;
4800 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4801 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4805 PMD_INIT_FUNC_TRACE();
4807 hw->mac.ops.reset_hw(hw);
4808 hw->mac.get_link_status = true;
4810 /* negotiate mailbox API version to use with the PF. */
4811 ixgbevf_negotiate_api(hw);
4813 ixgbevf_dev_tx_init(dev);
4815 /* This can fail when allocating mbufs for descriptor rings */
4816 err = ixgbevf_dev_rx_init(dev);
4818 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4819 ixgbe_dev_clear_queues(dev);
4824 ixgbevf_set_vfta_all(dev, 1);
4827 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4828 ETH_VLAN_EXTEND_MASK;
4829 ixgbevf_vlan_offload_set(dev, mask);
4831 ixgbevf_dev_rxtx_start(dev);
4833 /* check and configure queue intr-vector mapping */
4834 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4835 intr_vector = dev->data->nb_rx_queues;
4836 if (rte_intr_efd_enable(intr_handle, intr_vector))
4840 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4841 intr_handle->intr_vec =
4842 rte_zmalloc("intr_vec",
4843 dev->data->nb_rx_queues * sizeof(int), 0);
4844 if (intr_handle->intr_vec == NULL) {
4845 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4846 " intr_vec", dev->data->nb_rx_queues);
4850 ixgbevf_configure_msix(dev);
4852 rte_intr_enable(intr_handle);
4854 /* Re-enable interrupt for VF */
4855 ixgbevf_intr_enable(hw);
4861 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4864 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4867 PMD_INIT_FUNC_TRACE();
4869 ixgbevf_intr_disable(hw);
4871 hw->adapter_stopped = 1;
4872 ixgbe_stop_adapter(hw);
4875 * Clear what we set, but we still keep shadow_vfta to
4876 * restore after device starts
4878 ixgbevf_set_vfta_all(dev, 0);
4880 /* Clear stored conf */
4881 dev->data->scattered_rx = 0;
4883 ixgbe_dev_clear_queues(dev);
4885 /* Clean datapath event and queue/vec mapping */
4886 rte_intr_efd_disable(intr_handle);
4887 if (intr_handle->intr_vec != NULL) {
4888 rte_free(intr_handle->intr_vec);
4889 intr_handle->intr_vec = NULL;
4894 ixgbevf_dev_close(struct rte_eth_dev *dev)
4896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898 PMD_INIT_FUNC_TRACE();
4902 ixgbevf_dev_stop(dev);
4904 ixgbe_dev_free_queues(dev);
4907 * Remove the VF MAC address ro ensure
4908 * that the VF traffic goes to the PF
4909 * after stop, close and detach of the VF
4911 ixgbevf_remove_mac_addr(dev, 0);
4914 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917 struct ixgbe_vfta *shadow_vfta =
4918 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4919 int i = 0, j = 0, vfta = 0, mask = 1;
4921 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4922 vfta = shadow_vfta->vfta[i];
4925 for (j = 0; j < 32; j++) {
4927 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4937 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4939 struct ixgbe_hw *hw =
4940 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 struct ixgbe_vfta *shadow_vfta =
4942 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4943 uint32_t vid_idx = 0;
4944 uint32_t vid_bit = 0;
4947 PMD_INIT_FUNC_TRACE();
4949 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4950 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4952 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4955 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4956 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4958 /* Save what we set and retore it after device reset */
4960 shadow_vfta->vfta[vid_idx] |= vid_bit;
4962 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4968 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4970 struct ixgbe_hw *hw =
4971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974 PMD_INIT_FUNC_TRACE();
4976 if (queue >= hw->mac.max_rx_queues)
4979 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4981 ctrl |= IXGBE_RXDCTL_VME;
4983 ctrl &= ~IXGBE_RXDCTL_VME;
4984 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4986 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4990 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4992 struct ixgbe_hw *hw =
4993 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997 /* VF function only support hw strip feature, others are not support */
4998 if (mask & ETH_VLAN_STRIP_MASK) {
4999 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5001 for (i = 0; i < hw->mac.max_rx_queues; i++)
5002 ixgbevf_vlan_strip_queue_set(dev, i, on);
5007 ixgbe_vt_check(struct ixgbe_hw *hw)
5011 /* if Virtualization Technology is enabled */
5012 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5013 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5014 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5022 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5024 uint32_t vector = 0;
5026 switch (hw->mac.mc_filter_type) {
5027 case 0: /* use bits [47:36] of the address */
5028 vector = ((uc_addr->addr_bytes[4] >> 4) |
5029 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5031 case 1: /* use bits [46:35] of the address */
5032 vector = ((uc_addr->addr_bytes[4] >> 3) |
5033 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5035 case 2: /* use bits [45:34] of the address */
5036 vector = ((uc_addr->addr_bytes[4] >> 2) |
5037 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5039 case 3: /* use bits [43:32] of the address */
5040 vector = ((uc_addr->addr_bytes[4]) |
5041 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5043 default: /* Invalid mc_filter_type */
5047 /* vector can only be 12-bits or boundary will be exceeded */
5053 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5061 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5062 const uint32_t ixgbe_uta_bit_shift = 5;
5063 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5064 const uint32_t bit1 = 0x1;
5066 struct ixgbe_hw *hw =
5067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068 struct ixgbe_uta_info *uta_info =
5069 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5071 /* The UTA table only exists on 82599 hardware and newer */
5072 if (hw->mac.type < ixgbe_mac_82599EB)
5075 vector = ixgbe_uta_vector(hw, mac_addr);
5076 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5077 uta_shift = vector & ixgbe_uta_bit_mask;
5079 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5083 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5085 uta_info->uta_in_use++;
5086 reg_val |= (bit1 << uta_shift);
5087 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5089 uta_info->uta_in_use--;
5090 reg_val &= ~(bit1 << uta_shift);
5091 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5094 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5096 if (uta_info->uta_in_use > 0)
5097 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5098 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5100 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5106 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5109 struct ixgbe_hw *hw =
5110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111 struct ixgbe_uta_info *uta_info =
5112 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5114 /* The UTA table only exists on 82599 hardware and newer */
5115 if (hw->mac.type < ixgbe_mac_82599EB)
5119 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5120 uta_info->uta_shadow[i] = ~0;
5121 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5124 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5125 uta_info->uta_shadow[i] = 0;
5126 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5134 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5136 uint32_t new_val = orig_val;
5138 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5139 new_val |= IXGBE_VMOLR_AUPE;
5140 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5141 new_val |= IXGBE_VMOLR_ROMPE;
5142 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5143 new_val |= IXGBE_VMOLR_ROPE;
5144 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5145 new_val |= IXGBE_VMOLR_BAM;
5146 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5147 new_val |= IXGBE_VMOLR_MPE;
5152 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5153 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5154 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5155 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5156 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5157 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5158 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5161 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5162 struct rte_eth_mirror_conf *mirror_conf,
5163 uint8_t rule_id, uint8_t on)
5165 uint32_t mr_ctl, vlvf;
5166 uint32_t mp_lsb = 0;
5167 uint32_t mv_msb = 0;
5168 uint32_t mv_lsb = 0;
5169 uint32_t mp_msb = 0;
5172 uint64_t vlan_mask = 0;
5174 const uint8_t pool_mask_offset = 32;
5175 const uint8_t vlan_mask_offset = 32;
5176 const uint8_t dst_pool_offset = 8;
5177 const uint8_t rule_mr_offset = 4;
5178 const uint8_t mirror_rule_mask = 0x0F;
5180 struct ixgbe_mirror_info *mr_info =
5181 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5182 struct ixgbe_hw *hw =
5183 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5184 uint8_t mirror_type = 0;
5186 if (ixgbe_vt_check(hw) < 0)
5189 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5192 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5193 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5194 mirror_conf->rule_type);
5198 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5199 mirror_type |= IXGBE_MRCTL_VLME;
5200 /* Check if vlan id is valid and find conresponding VLAN ID
5203 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5204 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5205 /* search vlan id related pool vlan filter
5208 reg_index = ixgbe_find_vlvf_slot(
5210 mirror_conf->vlan.vlan_id[i],
5214 vlvf = IXGBE_READ_REG(hw,
5215 IXGBE_VLVF(reg_index));
5216 if ((vlvf & IXGBE_VLVF_VIEN) &&
5217 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5218 mirror_conf->vlan.vlan_id[i]))
5219 vlan_mask |= (1ULL << reg_index);
5226 mv_lsb = vlan_mask & 0xFFFFFFFF;
5227 mv_msb = vlan_mask >> vlan_mask_offset;
5229 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5230 mirror_conf->vlan.vlan_mask;
5231 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5232 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5233 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5234 mirror_conf->vlan.vlan_id[i];
5239 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5240 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5241 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5246 * if enable pool mirror, write related pool mask register,if disable
5247 * pool mirror, clear PFMRVM register
5249 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5250 mirror_type |= IXGBE_MRCTL_VPME;
5252 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5253 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5254 mr_info->mr_conf[rule_id].pool_mask =
5255 mirror_conf->pool_mask;
5260 mr_info->mr_conf[rule_id].pool_mask = 0;
5263 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5264 mirror_type |= IXGBE_MRCTL_UPME;
5265 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5266 mirror_type |= IXGBE_MRCTL_DPME;
5268 /* read mirror control register and recalculate it */
5269 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5272 mr_ctl |= mirror_type;
5273 mr_ctl &= mirror_rule_mask;
5274 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5276 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5279 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5280 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5282 /* write mirrror control register */
5283 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5285 /* write pool mirrror control register */
5286 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5287 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5288 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5291 /* write VLAN mirrror control register */
5292 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5293 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5294 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5302 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5305 uint32_t lsb_val = 0;
5306 uint32_t msb_val = 0;
5307 const uint8_t rule_mr_offset = 4;
5309 struct ixgbe_hw *hw =
5310 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5311 struct ixgbe_mirror_info *mr_info =
5312 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5314 if (ixgbe_vt_check(hw) < 0)
5317 memset(&mr_info->mr_conf[rule_id], 0,
5318 sizeof(struct rte_eth_mirror_conf));
5320 /* clear PFVMCTL register */
5321 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5323 /* clear pool mask register */
5324 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5325 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5327 /* clear vlan mask register */
5328 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5329 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5335 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5337 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5338 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5340 struct ixgbe_hw *hw =
5341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5344 mask |= (1 << IXGBE_MISC_VEC_ID);
5345 RTE_SET_USED(queue_id);
5346 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5348 rte_intr_enable(intr_handle);
5354 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5357 struct ixgbe_hw *hw =
5358 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5361 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5362 RTE_SET_USED(queue_id);
5363 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5369 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5371 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5372 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5374 struct ixgbe_hw *hw =
5375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376 struct ixgbe_interrupt *intr =
5377 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5379 if (queue_id < 16) {
5380 ixgbe_disable_intr(hw);
5381 intr->mask |= (1 << queue_id);
5382 ixgbe_enable_intr(dev);
5383 } else if (queue_id < 32) {
5384 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5385 mask &= (1 << queue_id);
5386 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5387 } else if (queue_id < 64) {
5388 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5389 mask &= (1 << (queue_id - 32));
5390 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5392 rte_intr_enable(intr_handle);
5398 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5401 struct ixgbe_hw *hw =
5402 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5403 struct ixgbe_interrupt *intr =
5404 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5406 if (queue_id < 16) {
5407 ixgbe_disable_intr(hw);
5408 intr->mask &= ~(1 << queue_id);
5409 ixgbe_enable_intr(dev);
5410 } else if (queue_id < 32) {
5411 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5412 mask &= ~(1 << queue_id);
5413 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5414 } else if (queue_id < 64) {
5415 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5416 mask &= ~(1 << (queue_id - 32));
5417 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5424 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5425 uint8_t queue, uint8_t msix_vector)
5429 if (direction == -1) {
5431 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5432 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5435 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5437 /* rx or tx cause */
5438 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5439 idx = ((16 * (queue & 1)) + (8 * direction));
5440 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5441 tmp &= ~(0xFF << idx);
5442 tmp |= (msix_vector << idx);
5443 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5448 * set the IVAR registers, mapping interrupt causes to vectors
5450 * pointer to ixgbe_hw struct
5452 * 0 for Rx, 1 for Tx, -1 for other causes
5454 * queue to map the corresponding interrupt to
5456 * the vector to map to the corresponding queue
5459 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5460 uint8_t queue, uint8_t msix_vector)
5464 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5465 if (hw->mac.type == ixgbe_mac_82598EB) {
5466 if (direction == -1)
5468 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5469 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5470 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5471 tmp |= (msix_vector << (8 * (queue & 0x3)));
5472 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5473 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5474 (hw->mac.type == ixgbe_mac_X540)) {
5475 if (direction == -1) {
5477 idx = ((queue & 1) * 8);
5478 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5479 tmp &= ~(0xFF << idx);
5480 tmp |= (msix_vector << idx);
5481 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5483 /* rx or tx causes */
5484 idx = ((16 * (queue & 1)) + (8 * direction));
5485 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5486 tmp &= ~(0xFF << idx);
5487 tmp |= (msix_vector << idx);
5488 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5494 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5496 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5498 struct ixgbe_hw *hw =
5499 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5503 /* Configure VF other cause ivar */
5504 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5506 /* won't configure msix register if no mapping is done
5507 * between intr vector and event fd.
5509 if (!rte_intr_dp_is_en(intr_handle))
5512 /* Configure all RX queues of VF */
5513 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5514 /* Force all queue use vector 0,
5515 * as IXGBE_VF_MAXMSIVECOTR = 1
5517 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5518 intr_handle->intr_vec[q_idx] = vector_idx;
5523 * Sets up the hardware to properly generate MSI-X interrupts
5525 * board private structure
5528 ixgbe_configure_msix(struct rte_eth_dev *dev)
5530 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5531 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5532 struct ixgbe_hw *hw =
5533 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5534 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5535 uint32_t vec = IXGBE_MISC_VEC_ID;
5539 /* won't configure msix register if no mapping is done
5540 * between intr vector and event fd
5542 if (!rte_intr_dp_is_en(intr_handle))
5545 if (rte_intr_allow_others(intr_handle))
5546 vec = base = IXGBE_RX_VEC_START;
5548 /* setup GPIE for MSI-x mode */
5549 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5550 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5551 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5552 /* auto clearing and auto setting corresponding bits in EIMS
5553 * when MSI-X interrupt is triggered
5555 if (hw->mac.type == ixgbe_mac_82598EB) {
5556 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5558 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5559 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5561 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5563 /* Populate the IVAR table and set the ITR values to the
5564 * corresponding register.
5566 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5568 /* by default, 1:1 mapping */
5569 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5570 intr_handle->intr_vec[queue_id] = vec;
5571 if (vec < base + intr_handle->nb_efd - 1)
5575 switch (hw->mac.type) {
5576 case ixgbe_mac_82598EB:
5577 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5580 case ixgbe_mac_82599EB:
5581 case ixgbe_mac_X540:
5582 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5587 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5588 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5590 /* set up to autoclear timer, and the vectors */
5591 mask = IXGBE_EIMS_ENABLE_MASK;
5592 mask &= ~(IXGBE_EIMS_OTHER |
5593 IXGBE_EIMS_MAILBOX |
5596 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5599 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5600 uint16_t queue_idx, uint16_t tx_rate)
5602 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603 uint32_t rf_dec, rf_int;
5605 uint16_t link_speed = dev->data->dev_link.link_speed;
5607 if (queue_idx >= hw->mac.max_tx_queues)
5611 /* Calculate the rate factor values to set */
5612 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5613 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5614 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5616 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5617 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5618 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5619 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5625 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5626 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5629 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5630 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5631 IXGBE_MAX_JUMBO_FRAME_SIZE))
5632 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5633 IXGBE_MMW_SIZE_JUMBO_FRAME);
5635 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5636 IXGBE_MMW_SIZE_DEFAULT);
5638 /* Set RTTBCNRC of queue X */
5639 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5640 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5641 IXGBE_WRITE_FLUSH(hw);
5647 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5648 __attribute__((unused)) uint32_t index,
5649 __attribute__((unused)) uint32_t pool)
5651 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5655 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5656 * operation. Trap this case to avoid exhausting the [very limited]
5657 * set of PF resources used to store VF MAC addresses.
5659 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5661 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5663 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5664 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5665 mac_addr->addr_bytes[0],
5666 mac_addr->addr_bytes[1],
5667 mac_addr->addr_bytes[2],
5668 mac_addr->addr_bytes[3],
5669 mac_addr->addr_bytes[4],
5670 mac_addr->addr_bytes[5],
5676 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5678 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5679 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5680 struct ether_addr *mac_addr;
5685 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5686 * not support the deletion of a given MAC address.
5687 * Instead, it imposes to delete all MAC addresses, then to add again
5688 * all MAC addresses with the exception of the one to be deleted.
5690 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5693 * Add again all MAC addresses, with the exception of the deleted one
5694 * and of the permanent MAC address.
5696 for (i = 0, mac_addr = dev->data->mac_addrs;
5697 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5698 /* Skip the deleted MAC address */
5701 /* Skip NULL MAC addresses */
5702 if (is_zero_ether_addr(mac_addr))
5704 /* Skip the permanent MAC address */
5705 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5707 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5710 "Adding again MAC address "
5711 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5713 mac_addr->addr_bytes[0],
5714 mac_addr->addr_bytes[1],
5715 mac_addr->addr_bytes[2],
5716 mac_addr->addr_bytes[3],
5717 mac_addr->addr_bytes[4],
5718 mac_addr->addr_bytes[5],
5724 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5726 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5732 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5733 struct rte_eth_syn_filter *filter,
5736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737 struct ixgbe_filter_info *filter_info =
5738 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5742 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5745 syn_info = filter_info->syn_info;
5748 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5750 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5751 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5753 if (filter->hig_pri)
5754 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5756 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5758 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5759 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5761 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5764 filter_info->syn_info = synqf;
5765 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5766 IXGBE_WRITE_FLUSH(hw);
5771 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5772 struct rte_eth_syn_filter *filter)
5774 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5777 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5778 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5779 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5786 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5787 enum rte_filter_op filter_op,
5790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5793 MAC_TYPE_FILTER_SUP(hw->mac.type);
5795 if (filter_op == RTE_ETH_FILTER_NOP)
5799 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5804 switch (filter_op) {
5805 case RTE_ETH_FILTER_ADD:
5806 ret = ixgbe_syn_filter_set(dev,
5807 (struct rte_eth_syn_filter *)arg,
5810 case RTE_ETH_FILTER_DELETE:
5811 ret = ixgbe_syn_filter_set(dev,
5812 (struct rte_eth_syn_filter *)arg,
5815 case RTE_ETH_FILTER_GET:
5816 ret = ixgbe_syn_filter_get(dev,
5817 (struct rte_eth_syn_filter *)arg);
5820 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5829 static inline enum ixgbe_5tuple_protocol
5830 convert_protocol_type(uint8_t protocol_value)
5832 if (protocol_value == IPPROTO_TCP)
5833 return IXGBE_FILTER_PROTOCOL_TCP;
5834 else if (protocol_value == IPPROTO_UDP)
5835 return IXGBE_FILTER_PROTOCOL_UDP;
5836 else if (protocol_value == IPPROTO_SCTP)
5837 return IXGBE_FILTER_PROTOCOL_SCTP;
5839 return IXGBE_FILTER_PROTOCOL_NONE;
5842 /* inject a 5-tuple filter to HW */
5844 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5845 struct ixgbe_5tuple_filter *filter)
5847 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5849 uint32_t ftqf, sdpqf;
5850 uint32_t l34timir = 0;
5851 uint8_t mask = 0xff;
5855 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5856 IXGBE_SDPQF_DSTPORT_SHIFT);
5857 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5859 ftqf = (uint32_t)(filter->filter_info.proto &
5860 IXGBE_FTQF_PROTOCOL_MASK);
5861 ftqf |= (uint32_t)((filter->filter_info.priority &
5862 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5863 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5864 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5865 if (filter->filter_info.dst_ip_mask == 0)
5866 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5867 if (filter->filter_info.src_port_mask == 0)
5868 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5869 if (filter->filter_info.dst_port_mask == 0)
5870 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5871 if (filter->filter_info.proto_mask == 0)
5872 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5873 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5874 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5875 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5877 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5878 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5879 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5880 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5882 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5883 l34timir |= (uint32_t)(filter->queue <<
5884 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5885 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5889 * add a 5tuple filter
5892 * dev: Pointer to struct rte_eth_dev.
5893 * index: the index the filter allocates.
5894 * filter: ponter to the filter that will be added.
5895 * rx_queue: the queue id the filter assigned to.
5898 * - On success, zero.
5899 * - On failure, a negative value.
5902 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5903 struct ixgbe_5tuple_filter *filter)
5905 struct ixgbe_filter_info *filter_info =
5906 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5910 * look for an unused 5tuple filter index,
5911 * and insert the filter to list.
5913 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5914 idx = i / (sizeof(uint32_t) * NBBY);
5915 shift = i % (sizeof(uint32_t) * NBBY);
5916 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5917 filter_info->fivetuple_mask[idx] |= 1 << shift;
5919 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5925 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5926 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5930 ixgbe_inject_5tuple_filter(dev, filter);
5936 * remove a 5tuple filter
5939 * dev: Pointer to struct rte_eth_dev.
5940 * filter: the pointer of the filter will be removed.
5943 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5944 struct ixgbe_5tuple_filter *filter)
5946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5947 struct ixgbe_filter_info *filter_info =
5948 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5949 uint16_t index = filter->index;
5951 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5952 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5953 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5956 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5957 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5958 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5959 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5960 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5964 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5966 struct ixgbe_hw *hw;
5967 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5969 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5974 /* refuse mtu that requires the support of scattered packets when this
5975 * feature has not been enabled before.
5977 if (!dev->data->scattered_rx &&
5978 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5979 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5983 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5984 * request of the version 2.0 of the mailbox API.
5985 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5986 * of the mailbox API.
5987 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5988 * prior to 3.11.33 which contains the following change:
5989 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5991 ixgbevf_rlpml_set_vf(hw, max_frame);
5993 /* update max frame size */
5994 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5998 static inline struct ixgbe_5tuple_filter *
5999 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6000 struct ixgbe_5tuple_filter_info *key)
6002 struct ixgbe_5tuple_filter *it;
6004 TAILQ_FOREACH(it, filter_list, entries) {
6005 if (memcmp(key, &it->filter_info,
6006 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6013 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6015 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6016 struct ixgbe_5tuple_filter_info *filter_info)
6018 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6019 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6020 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6023 switch (filter->dst_ip_mask) {
6025 filter_info->dst_ip_mask = 0;
6026 filter_info->dst_ip = filter->dst_ip;
6029 filter_info->dst_ip_mask = 1;
6032 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6036 switch (filter->src_ip_mask) {
6038 filter_info->src_ip_mask = 0;
6039 filter_info->src_ip = filter->src_ip;
6042 filter_info->src_ip_mask = 1;
6045 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6049 switch (filter->dst_port_mask) {
6051 filter_info->dst_port_mask = 0;
6052 filter_info->dst_port = filter->dst_port;
6055 filter_info->dst_port_mask = 1;
6058 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6062 switch (filter->src_port_mask) {
6064 filter_info->src_port_mask = 0;
6065 filter_info->src_port = filter->src_port;
6068 filter_info->src_port_mask = 1;
6071 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6075 switch (filter->proto_mask) {
6077 filter_info->proto_mask = 0;
6078 filter_info->proto =
6079 convert_protocol_type(filter->proto);
6082 filter_info->proto_mask = 1;
6085 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6089 filter_info->priority = (uint8_t)filter->priority;
6094 * add or delete a ntuple filter
6097 * dev: Pointer to struct rte_eth_dev.
6098 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6099 * add: if true, add filter, if false, remove filter
6102 * - On success, zero.
6103 * - On failure, a negative value.
6106 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6107 struct rte_eth_ntuple_filter *ntuple_filter,
6110 struct ixgbe_filter_info *filter_info =
6111 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6112 struct ixgbe_5tuple_filter_info filter_5tuple;
6113 struct ixgbe_5tuple_filter *filter;
6116 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6117 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6121 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6122 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6126 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6128 if (filter != NULL && add) {
6129 PMD_DRV_LOG(ERR, "filter exists.");
6132 if (filter == NULL && !add) {
6133 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6138 filter = rte_zmalloc("ixgbe_5tuple_filter",
6139 sizeof(struct ixgbe_5tuple_filter), 0);
6142 (void)rte_memcpy(&filter->filter_info,
6144 sizeof(struct ixgbe_5tuple_filter_info));
6145 filter->queue = ntuple_filter->queue;
6146 ret = ixgbe_add_5tuple_filter(dev, filter);
6152 ixgbe_remove_5tuple_filter(dev, filter);
6158 * get a ntuple filter
6161 * dev: Pointer to struct rte_eth_dev.
6162 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6165 * - On success, zero.
6166 * - On failure, a negative value.
6169 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6170 struct rte_eth_ntuple_filter *ntuple_filter)
6172 struct ixgbe_filter_info *filter_info =
6173 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6174 struct ixgbe_5tuple_filter_info filter_5tuple;
6175 struct ixgbe_5tuple_filter *filter;
6178 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6179 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6183 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6184 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6188 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6190 if (filter == NULL) {
6191 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6194 ntuple_filter->queue = filter->queue;
6199 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6200 * @dev: pointer to rte_eth_dev structure
6201 * @filter_op:operation will be taken.
6202 * @arg: a pointer to specific structure corresponding to the filter_op
6205 * - On success, zero.
6206 * - On failure, a negative value.
6209 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6210 enum rte_filter_op filter_op,
6213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6218 if (filter_op == RTE_ETH_FILTER_NOP)
6222 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6227 switch (filter_op) {
6228 case RTE_ETH_FILTER_ADD:
6229 ret = ixgbe_add_del_ntuple_filter(dev,
6230 (struct rte_eth_ntuple_filter *)arg,
6233 case RTE_ETH_FILTER_DELETE:
6234 ret = ixgbe_add_del_ntuple_filter(dev,
6235 (struct rte_eth_ntuple_filter *)arg,
6238 case RTE_ETH_FILTER_GET:
6239 ret = ixgbe_get_ntuple_filter(dev,
6240 (struct rte_eth_ntuple_filter *)arg);
6243 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6251 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6252 struct rte_eth_ethertype_filter *filter,
6255 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6256 struct ixgbe_filter_info *filter_info =
6257 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6261 struct ixgbe_ethertype_filter ethertype_filter;
6263 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6266 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6267 filter->ether_type == ETHER_TYPE_IPv6) {
6268 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6269 " ethertype filter.", filter->ether_type);
6273 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6274 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6277 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6278 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6282 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6283 if (ret >= 0 && add) {
6284 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6285 filter->ether_type);
6288 if (ret < 0 && !add) {
6289 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6290 filter->ether_type);
6295 etqf = IXGBE_ETQF_FILTER_EN;
6296 etqf |= (uint32_t)filter->ether_type;
6297 etqs |= (uint32_t)((filter->queue <<
6298 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6299 IXGBE_ETQS_RX_QUEUE);
6300 etqs |= IXGBE_ETQS_QUEUE_EN;
6302 ethertype_filter.ethertype = filter->ether_type;
6303 ethertype_filter.etqf = etqf;
6304 ethertype_filter.etqs = etqs;
6305 ethertype_filter.conf = FALSE;
6306 ret = ixgbe_ethertype_filter_insert(filter_info,
6309 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6313 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6317 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6318 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6319 IXGBE_WRITE_FLUSH(hw);
6325 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6326 struct rte_eth_ethertype_filter *filter)
6328 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6329 struct ixgbe_filter_info *filter_info =
6330 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6331 uint32_t etqf, etqs;
6334 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6336 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6337 filter->ether_type);
6341 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6342 if (etqf & IXGBE_ETQF_FILTER_EN) {
6343 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6344 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6346 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6347 IXGBE_ETQS_RX_QUEUE_SHIFT;
6354 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6355 * @dev: pointer to rte_eth_dev structure
6356 * @filter_op:operation will be taken.
6357 * @arg: a pointer to specific structure corresponding to the filter_op
6360 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6361 enum rte_filter_op filter_op,
6364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367 MAC_TYPE_FILTER_SUP(hw->mac.type);
6369 if (filter_op == RTE_ETH_FILTER_NOP)
6373 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6378 switch (filter_op) {
6379 case RTE_ETH_FILTER_ADD:
6380 ret = ixgbe_add_del_ethertype_filter(dev,
6381 (struct rte_eth_ethertype_filter *)arg,
6384 case RTE_ETH_FILTER_DELETE:
6385 ret = ixgbe_add_del_ethertype_filter(dev,
6386 (struct rte_eth_ethertype_filter *)arg,
6389 case RTE_ETH_FILTER_GET:
6390 ret = ixgbe_get_ethertype_filter(dev,
6391 (struct rte_eth_ethertype_filter *)arg);
6394 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6402 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6403 enum rte_filter_type filter_type,
6404 enum rte_filter_op filter_op,
6409 switch (filter_type) {
6410 case RTE_ETH_FILTER_NTUPLE:
6411 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6413 case RTE_ETH_FILTER_ETHERTYPE:
6414 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6416 case RTE_ETH_FILTER_SYN:
6417 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6419 case RTE_ETH_FILTER_FDIR:
6420 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6422 case RTE_ETH_FILTER_L2_TUNNEL:
6423 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6425 case RTE_ETH_FILTER_GENERIC:
6426 if (filter_op != RTE_ETH_FILTER_GET)
6428 *(const void **)arg = &ixgbe_flow_ops;
6431 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6441 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6442 u8 **mc_addr_ptr, u32 *vmdq)
6447 mc_addr = *mc_addr_ptr;
6448 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6453 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6454 struct ether_addr *mc_addr_set,
6455 uint32_t nb_mc_addr)
6457 struct ixgbe_hw *hw;
6460 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6461 mc_addr_list = (u8 *)mc_addr_set;
6462 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6463 ixgbe_dev_addr_list_itr, TRUE);
6467 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6469 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470 uint64_t systime_cycles;
6472 switch (hw->mac.type) {
6473 case ixgbe_mac_X550:
6474 case ixgbe_mac_X550EM_x:
6475 case ixgbe_mac_X550EM_a:
6476 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6477 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6478 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6482 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6483 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6487 return systime_cycles;
6491 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6493 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6494 uint64_t rx_tstamp_cycles;
6496 switch (hw->mac.type) {
6497 case ixgbe_mac_X550:
6498 case ixgbe_mac_X550EM_x:
6499 case ixgbe_mac_X550EM_a:
6500 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6501 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6502 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6506 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6507 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6508 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6512 return rx_tstamp_cycles;
6516 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6518 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6519 uint64_t tx_tstamp_cycles;
6521 switch (hw->mac.type) {
6522 case ixgbe_mac_X550:
6523 case ixgbe_mac_X550EM_x:
6524 case ixgbe_mac_X550EM_a:
6525 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6526 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6527 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6531 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6532 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6533 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6537 return tx_tstamp_cycles;
6541 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6544 struct ixgbe_adapter *adapter =
6545 (struct ixgbe_adapter *)dev->data->dev_private;
6546 struct rte_eth_link link;
6547 uint32_t incval = 0;
6550 /* Get current link speed. */
6551 memset(&link, 0, sizeof(link));
6552 ixgbe_dev_link_update(dev, 1);
6553 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6555 switch (link.link_speed) {
6556 case ETH_SPEED_NUM_100M:
6557 incval = IXGBE_INCVAL_100;
6558 shift = IXGBE_INCVAL_SHIFT_100;
6560 case ETH_SPEED_NUM_1G:
6561 incval = IXGBE_INCVAL_1GB;
6562 shift = IXGBE_INCVAL_SHIFT_1GB;
6564 case ETH_SPEED_NUM_10G:
6566 incval = IXGBE_INCVAL_10GB;
6567 shift = IXGBE_INCVAL_SHIFT_10GB;
6571 switch (hw->mac.type) {
6572 case ixgbe_mac_X550:
6573 case ixgbe_mac_X550EM_x:
6574 case ixgbe_mac_X550EM_a:
6575 /* Independent of link speed. */
6577 /* Cycles read will be interpreted as ns. */
6580 case ixgbe_mac_X540:
6581 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6583 case ixgbe_mac_82599EB:
6584 incval >>= IXGBE_INCVAL_SHIFT_82599;
6585 shift -= IXGBE_INCVAL_SHIFT_82599;
6586 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6587 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6590 /* Not supported. */
6594 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6595 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6596 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6598 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6599 adapter->systime_tc.cc_shift = shift;
6600 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6602 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6603 adapter->rx_tstamp_tc.cc_shift = shift;
6604 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6606 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6607 adapter->tx_tstamp_tc.cc_shift = shift;
6608 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6612 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6614 struct ixgbe_adapter *adapter =
6615 (struct ixgbe_adapter *)dev->data->dev_private;
6617 adapter->systime_tc.nsec += delta;
6618 adapter->rx_tstamp_tc.nsec += delta;
6619 adapter->tx_tstamp_tc.nsec += delta;
6625 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6628 struct ixgbe_adapter *adapter =
6629 (struct ixgbe_adapter *)dev->data->dev_private;
6631 ns = rte_timespec_to_ns(ts);
6632 /* Set the timecounters to a new value. */
6633 adapter->systime_tc.nsec = ns;
6634 adapter->rx_tstamp_tc.nsec = ns;
6635 adapter->tx_tstamp_tc.nsec = ns;
6641 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6643 uint64_t ns, systime_cycles;
6644 struct ixgbe_adapter *adapter =
6645 (struct ixgbe_adapter *)dev->data->dev_private;
6647 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6648 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6649 *ts = rte_ns_to_timespec(ns);
6655 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6657 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661 /* Stop the timesync system time. */
6662 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6663 /* Reset the timesync system time value. */
6664 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6665 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6667 /* Enable system time for platforms where it isn't on by default. */
6668 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6669 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6670 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6672 ixgbe_start_timecounters(dev);
6674 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6675 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6677 IXGBE_ETQF_FILTER_EN |
6680 /* Enable timestamping of received PTP packets. */
6681 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6682 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6683 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6685 /* Enable timestamping of transmitted PTP packets. */
6686 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6687 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6688 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6690 IXGBE_WRITE_FLUSH(hw);
6696 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701 /* Disable timestamping of transmitted PTP packets. */
6702 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6703 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6704 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6706 /* Disable timestamping of received PTP packets. */
6707 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6708 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6709 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6711 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6712 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6714 /* Stop incrementating the System Time registers. */
6715 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6721 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6722 struct timespec *timestamp,
6723 uint32_t flags __rte_unused)
6725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726 struct ixgbe_adapter *adapter =
6727 (struct ixgbe_adapter *)dev->data->dev_private;
6728 uint32_t tsync_rxctl;
6729 uint64_t rx_tstamp_cycles;
6732 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6733 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6736 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6737 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6738 *timestamp = rte_ns_to_timespec(ns);
6744 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6745 struct timespec *timestamp)
6747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6748 struct ixgbe_adapter *adapter =
6749 (struct ixgbe_adapter *)dev->data->dev_private;
6750 uint32_t tsync_txctl;
6751 uint64_t tx_tstamp_cycles;
6754 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6755 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6758 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6759 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6760 *timestamp = rte_ns_to_timespec(ns);
6766 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771 const struct reg_info *reg_group;
6772 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6773 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6775 while ((reg_group = reg_set[g_ind++]))
6776 count += ixgbe_regs_group_count(reg_group);
6782 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6786 const struct reg_info *reg_group;
6788 while ((reg_group = ixgbevf_regs[g_ind++]))
6789 count += ixgbe_regs_group_count(reg_group);
6795 ixgbe_get_regs(struct rte_eth_dev *dev,
6796 struct rte_dev_reg_info *regs)
6798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799 uint32_t *data = regs->data;
6802 const struct reg_info *reg_group;
6803 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6804 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6807 regs->length = ixgbe_get_reg_length(dev);
6808 regs->width = sizeof(uint32_t);
6812 /* Support only full register dump */
6813 if ((regs->length == 0) ||
6814 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6815 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6817 while ((reg_group = reg_set[g_ind++]))
6818 count += ixgbe_read_regs_group(dev, &data[count],
6827 ixgbevf_get_regs(struct rte_eth_dev *dev,
6828 struct rte_dev_reg_info *regs)
6830 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831 uint32_t *data = regs->data;
6834 const struct reg_info *reg_group;
6837 regs->length = ixgbevf_get_reg_length(dev);
6838 regs->width = sizeof(uint32_t);
6842 /* Support only full register dump */
6843 if ((regs->length == 0) ||
6844 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6845 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6847 while ((reg_group = ixgbevf_regs[g_ind++]))
6848 count += ixgbe_read_regs_group(dev, &data[count],
6857 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6859 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861 /* Return unit is byte count */
6862 return hw->eeprom.word_size * 2;
6866 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6867 struct rte_dev_eeprom_info *in_eeprom)
6869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6870 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6871 uint16_t *data = in_eeprom->data;
6874 first = in_eeprom->offset >> 1;
6875 length = in_eeprom->length >> 1;
6876 if ((first > hw->eeprom.word_size) ||
6877 ((first + length) > hw->eeprom.word_size))
6880 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6882 return eeprom->ops.read_buffer(hw, first, length, data);
6886 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6887 struct rte_dev_eeprom_info *in_eeprom)
6889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6890 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6891 uint16_t *data = in_eeprom->data;
6894 first = in_eeprom->offset >> 1;
6895 length = in_eeprom->length >> 1;
6896 if ((first > hw->eeprom.word_size) ||
6897 ((first + length) > hw->eeprom.word_size))
6900 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6902 return eeprom->ops.write_buffer(hw, first, length, data);
6906 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6908 case ixgbe_mac_X550:
6909 case ixgbe_mac_X550EM_x:
6910 case ixgbe_mac_X550EM_a:
6911 return ETH_RSS_RETA_SIZE_512;
6912 case ixgbe_mac_X550_vf:
6913 case ixgbe_mac_X550EM_x_vf:
6914 case ixgbe_mac_X550EM_a_vf:
6915 return ETH_RSS_RETA_SIZE_64;
6917 return ETH_RSS_RETA_SIZE_128;
6922 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6924 case ixgbe_mac_X550:
6925 case ixgbe_mac_X550EM_x:
6926 case ixgbe_mac_X550EM_a:
6927 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6928 return IXGBE_RETA(reta_idx >> 2);
6930 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6931 case ixgbe_mac_X550_vf:
6932 case ixgbe_mac_X550EM_x_vf:
6933 case ixgbe_mac_X550EM_a_vf:
6934 return IXGBE_VFRETA(reta_idx >> 2);
6936 return IXGBE_RETA(reta_idx >> 2);
6941 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6943 case ixgbe_mac_X550_vf:
6944 case ixgbe_mac_X550EM_x_vf:
6945 case ixgbe_mac_X550EM_a_vf:
6946 return IXGBE_VFMRQC;
6953 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6955 case ixgbe_mac_X550_vf:
6956 case ixgbe_mac_X550EM_x_vf:
6957 case ixgbe_mac_X550EM_a_vf:
6958 return IXGBE_VFRSSRK(i);
6960 return IXGBE_RSSRK(i);
6965 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6967 case ixgbe_mac_82599_vf:
6968 case ixgbe_mac_X540_vf:
6976 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6977 struct rte_eth_dcb_info *dcb_info)
6979 struct ixgbe_dcb_config *dcb_config =
6980 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6981 struct ixgbe_dcb_tc_config *tc;
6984 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6985 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6987 dcb_info->nb_tcs = 1;
6989 if (dcb_config->vt_mode) { /* vt is enabled*/
6990 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6991 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6992 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6993 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6994 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6995 for (j = 0; j < dcb_info->nb_tcs; j++) {
6996 dcb_info->tc_queue.tc_rxq[i][j].base =
6997 i * dcb_info->nb_tcs + j;
6998 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6999 dcb_info->tc_queue.tc_txq[i][j].base =
7000 i * dcb_info->nb_tcs + j;
7001 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7004 } else { /* vt is disabled*/
7005 struct rte_eth_dcb_rx_conf *rx_conf =
7006 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7007 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7008 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7009 if (dcb_info->nb_tcs == ETH_4_TCS) {
7010 for (i = 0; i < dcb_info->nb_tcs; i++) {
7011 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7012 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7014 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7015 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7016 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7017 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7018 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7019 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7020 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7021 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7022 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7023 for (i = 0; i < dcb_info->nb_tcs; i++) {
7024 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7025 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7027 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7028 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7029 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7030 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7031 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7032 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7033 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7034 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7035 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7036 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7037 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7038 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7039 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7040 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7041 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7042 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7045 for (i = 0; i < dcb_info->nb_tcs; i++) {
7046 tc = &dcb_config->tc_config[i];
7047 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7052 /* Update e-tag ether type */
7054 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7055 uint16_t ether_type)
7057 uint32_t etag_etype;
7059 if (hw->mac.type != ixgbe_mac_X550 &&
7060 hw->mac.type != ixgbe_mac_X550EM_x &&
7061 hw->mac.type != ixgbe_mac_X550EM_a) {
7065 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7066 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7067 etag_etype |= ether_type;
7068 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7069 IXGBE_WRITE_FLUSH(hw);
7074 /* Config l2 tunnel ether type */
7076 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7077 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7081 struct ixgbe_l2_tn_info *l2_tn_info =
7082 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7084 if (l2_tunnel == NULL)
7087 switch (l2_tunnel->l2_tunnel_type) {
7088 case RTE_L2_TUNNEL_TYPE_E_TAG:
7089 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7090 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7093 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7101 /* Enable e-tag tunnel */
7103 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7105 uint32_t etag_etype;
7107 if (hw->mac.type != ixgbe_mac_X550 &&
7108 hw->mac.type != ixgbe_mac_X550EM_x &&
7109 hw->mac.type != ixgbe_mac_X550EM_a) {
7113 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7114 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7115 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7116 IXGBE_WRITE_FLUSH(hw);
7121 /* Enable l2 tunnel */
7123 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7124 enum rte_eth_tunnel_type l2_tunnel_type)
7127 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128 struct ixgbe_l2_tn_info *l2_tn_info =
7129 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7131 switch (l2_tunnel_type) {
7132 case RTE_L2_TUNNEL_TYPE_E_TAG:
7133 l2_tn_info->e_tag_en = TRUE;
7134 ret = ixgbe_e_tag_enable(hw);
7137 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7145 /* Disable e-tag tunnel */
7147 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7149 uint32_t etag_etype;
7151 if (hw->mac.type != ixgbe_mac_X550 &&
7152 hw->mac.type != ixgbe_mac_X550EM_x &&
7153 hw->mac.type != ixgbe_mac_X550EM_a) {
7157 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7158 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7159 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7160 IXGBE_WRITE_FLUSH(hw);
7165 /* Disable l2 tunnel */
7167 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7168 enum rte_eth_tunnel_type l2_tunnel_type)
7171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172 struct ixgbe_l2_tn_info *l2_tn_info =
7173 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7175 switch (l2_tunnel_type) {
7176 case RTE_L2_TUNNEL_TYPE_E_TAG:
7177 l2_tn_info->e_tag_en = FALSE;
7178 ret = ixgbe_e_tag_disable(hw);
7181 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7190 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7191 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7194 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7195 uint32_t i, rar_entries;
7196 uint32_t rar_low, rar_high;
7198 if (hw->mac.type != ixgbe_mac_X550 &&
7199 hw->mac.type != ixgbe_mac_X550EM_x &&
7200 hw->mac.type != ixgbe_mac_X550EM_a) {
7204 rar_entries = ixgbe_get_num_rx_addrs(hw);
7206 for (i = 1; i < rar_entries; i++) {
7207 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7208 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7209 if ((rar_high & IXGBE_RAH_AV) &&
7210 (rar_high & IXGBE_RAH_ADTYPE) &&
7211 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7212 l2_tunnel->tunnel_id)) {
7213 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7214 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7216 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7226 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7227 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7231 uint32_t i, rar_entries;
7232 uint32_t rar_low, rar_high;
7234 if (hw->mac.type != ixgbe_mac_X550 &&
7235 hw->mac.type != ixgbe_mac_X550EM_x &&
7236 hw->mac.type != ixgbe_mac_X550EM_a) {
7240 /* One entry for one tunnel. Try to remove potential existing entry. */
7241 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7243 rar_entries = ixgbe_get_num_rx_addrs(hw);
7245 for (i = 1; i < rar_entries; i++) {
7246 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7247 if (rar_high & IXGBE_RAH_AV) {
7250 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7251 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7252 rar_low = l2_tunnel->tunnel_id;
7254 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7255 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7261 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7262 " Please remove a rule before adding a new one.");
7266 static inline struct ixgbe_l2_tn_filter *
7267 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7268 struct ixgbe_l2_tn_key *key)
7272 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7276 return l2_tn_info->hash_map[ret];
7280 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7281 struct ixgbe_l2_tn_filter *l2_tn_filter)
7285 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7286 &l2_tn_filter->key);
7290 "Failed to insert L2 tunnel filter"
7291 " to hash table %d!",
7296 l2_tn_info->hash_map[ret] = l2_tn_filter;
7298 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7304 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7305 struct ixgbe_l2_tn_key *key)
7308 struct ixgbe_l2_tn_filter *l2_tn_filter;
7310 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7314 "No such L2 tunnel filter to delete %d!",
7319 l2_tn_filter = l2_tn_info->hash_map[ret];
7320 l2_tn_info->hash_map[ret] = NULL;
7322 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7323 rte_free(l2_tn_filter);
7328 /* Add l2 tunnel filter */
7330 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7331 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7335 struct ixgbe_l2_tn_info *l2_tn_info =
7336 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7337 struct ixgbe_l2_tn_key key;
7338 struct ixgbe_l2_tn_filter *node;
7341 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7342 key.tn_id = l2_tunnel->tunnel_id;
7344 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7348 "The L2 tunnel filter already exists!");
7352 node = rte_zmalloc("ixgbe_l2_tn",
7353 sizeof(struct ixgbe_l2_tn_filter),
7358 (void)rte_memcpy(&node->key,
7360 sizeof(struct ixgbe_l2_tn_key));
7361 node->pool = l2_tunnel->pool;
7362 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7369 switch (l2_tunnel->l2_tunnel_type) {
7370 case RTE_L2_TUNNEL_TYPE_E_TAG:
7371 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7374 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7379 if ((!restore) && (ret < 0))
7380 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7385 /* Delete l2 tunnel filter */
7387 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7388 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7391 struct ixgbe_l2_tn_info *l2_tn_info =
7392 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7393 struct ixgbe_l2_tn_key key;
7395 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7396 key.tn_id = l2_tunnel->tunnel_id;
7397 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7401 switch (l2_tunnel->l2_tunnel_type) {
7402 case RTE_L2_TUNNEL_TYPE_E_TAG:
7403 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7406 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7415 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7416 * @dev: pointer to rte_eth_dev structure
7417 * @filter_op:operation will be taken.
7418 * @arg: a pointer to specific structure corresponding to the filter_op
7421 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7422 enum rte_filter_op filter_op,
7427 if (filter_op == RTE_ETH_FILTER_NOP)
7431 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7436 switch (filter_op) {
7437 case RTE_ETH_FILTER_ADD:
7438 ret = ixgbe_dev_l2_tunnel_filter_add
7440 (struct rte_eth_l2_tunnel_conf *)arg,
7443 case RTE_ETH_FILTER_DELETE:
7444 ret = ixgbe_dev_l2_tunnel_filter_del
7446 (struct rte_eth_l2_tunnel_conf *)arg);
7449 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7457 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7461 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7463 if (hw->mac.type != ixgbe_mac_X550 &&
7464 hw->mac.type != ixgbe_mac_X550EM_x &&
7465 hw->mac.type != ixgbe_mac_X550EM_a) {
7469 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7470 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7472 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7473 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7478 /* Enable l2 tunnel forwarding */
7480 ixgbe_dev_l2_tunnel_forwarding_enable
7481 (struct rte_eth_dev *dev,
7482 enum rte_eth_tunnel_type l2_tunnel_type)
7484 struct ixgbe_l2_tn_info *l2_tn_info =
7485 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7488 switch (l2_tunnel_type) {
7489 case RTE_L2_TUNNEL_TYPE_E_TAG:
7490 l2_tn_info->e_tag_fwd_en = TRUE;
7491 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7494 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7502 /* Disable l2 tunnel forwarding */
7504 ixgbe_dev_l2_tunnel_forwarding_disable
7505 (struct rte_eth_dev *dev,
7506 enum rte_eth_tunnel_type l2_tunnel_type)
7508 struct ixgbe_l2_tn_info *l2_tn_info =
7509 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7512 switch (l2_tunnel_type) {
7513 case RTE_L2_TUNNEL_TYPE_E_TAG:
7514 l2_tn_info->e_tag_fwd_en = FALSE;
7515 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7518 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7527 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7528 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7531 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7533 uint32_t vmtir, vmvir;
7534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7536 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7538 "VF id %u should be less than %u",
7544 if (hw->mac.type != ixgbe_mac_X550 &&
7545 hw->mac.type != ixgbe_mac_X550EM_x &&
7546 hw->mac.type != ixgbe_mac_X550EM_a) {
7551 vmtir = l2_tunnel->tunnel_id;
7555 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7557 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7558 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7560 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7561 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7566 /* Enable l2 tunnel tag insertion */
7568 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7569 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7573 switch (l2_tunnel->l2_tunnel_type) {
7574 case RTE_L2_TUNNEL_TYPE_E_TAG:
7575 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7578 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7586 /* Disable l2 tunnel tag insertion */
7588 ixgbe_dev_l2_tunnel_insertion_disable
7589 (struct rte_eth_dev *dev,
7590 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7594 switch (l2_tunnel->l2_tunnel_type) {
7595 case RTE_L2_TUNNEL_TYPE_E_TAG:
7596 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7599 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7608 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7615 if (hw->mac.type != ixgbe_mac_X550 &&
7616 hw->mac.type != ixgbe_mac_X550EM_x &&
7617 hw->mac.type != ixgbe_mac_X550EM_a) {
7621 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7623 qde |= IXGBE_QDE_STRIP_TAG;
7625 qde &= ~IXGBE_QDE_STRIP_TAG;
7626 qde &= ~IXGBE_QDE_READ;
7627 qde |= IXGBE_QDE_WRITE;
7628 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7633 /* Enable l2 tunnel tag stripping */
7635 ixgbe_dev_l2_tunnel_stripping_enable
7636 (struct rte_eth_dev *dev,
7637 enum rte_eth_tunnel_type l2_tunnel_type)
7641 switch (l2_tunnel_type) {
7642 case RTE_L2_TUNNEL_TYPE_E_TAG:
7643 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7646 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7654 /* Disable l2 tunnel tag stripping */
7656 ixgbe_dev_l2_tunnel_stripping_disable
7657 (struct rte_eth_dev *dev,
7658 enum rte_eth_tunnel_type l2_tunnel_type)
7662 switch (l2_tunnel_type) {
7663 case RTE_L2_TUNNEL_TYPE_E_TAG:
7664 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7667 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7675 /* Enable/disable l2 tunnel offload functions */
7677 ixgbe_dev_l2_tunnel_offload_set
7678 (struct rte_eth_dev *dev,
7679 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7685 if (l2_tunnel == NULL)
7689 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7691 ret = ixgbe_dev_l2_tunnel_enable(
7693 l2_tunnel->l2_tunnel_type);
7695 ret = ixgbe_dev_l2_tunnel_disable(
7697 l2_tunnel->l2_tunnel_type);
7700 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7702 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7706 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7711 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7713 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7715 l2_tunnel->l2_tunnel_type);
7717 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7719 l2_tunnel->l2_tunnel_type);
7722 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7724 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7726 l2_tunnel->l2_tunnel_type);
7728 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7730 l2_tunnel->l2_tunnel_type);
7737 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7740 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7741 IXGBE_WRITE_FLUSH(hw);
7746 /* There's only one register for VxLAN UDP port.
7747 * So, we cannot add several ports. Will update it.
7750 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7754 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7758 return ixgbe_update_vxlan_port(hw, port);
7761 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7762 * UDP port, it must have a value.
7763 * So, will reset it to the original value 0.
7766 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7771 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7773 if (cur_port != port) {
7774 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7778 return ixgbe_update_vxlan_port(hw, 0);
7781 /* Add UDP tunneling port */
7783 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7784 struct rte_eth_udp_tunnel *udp_tunnel)
7787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7789 if (hw->mac.type != ixgbe_mac_X550 &&
7790 hw->mac.type != ixgbe_mac_X550EM_x &&
7791 hw->mac.type != ixgbe_mac_X550EM_a) {
7795 if (udp_tunnel == NULL)
7798 switch (udp_tunnel->prot_type) {
7799 case RTE_TUNNEL_TYPE_VXLAN:
7800 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7803 case RTE_TUNNEL_TYPE_GENEVE:
7804 case RTE_TUNNEL_TYPE_TEREDO:
7805 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7810 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7818 /* Remove UDP tunneling port */
7820 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7821 struct rte_eth_udp_tunnel *udp_tunnel)
7824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7826 if (hw->mac.type != ixgbe_mac_X550 &&
7827 hw->mac.type != ixgbe_mac_X550EM_x &&
7828 hw->mac.type != ixgbe_mac_X550EM_a) {
7832 if (udp_tunnel == NULL)
7835 switch (udp_tunnel->prot_type) {
7836 case RTE_TUNNEL_TYPE_VXLAN:
7837 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7839 case RTE_TUNNEL_TYPE_GENEVE:
7840 case RTE_TUNNEL_TYPE_TEREDO:
7841 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7845 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7854 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7856 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7862 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7864 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7866 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7869 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7874 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7877 /* PF reset VF event */
7878 if (in_msg == IXGBE_PF_CONTROL_MSG)
7879 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7883 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887 struct ixgbe_interrupt *intr =
7888 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7889 ixgbevf_intr_disable(hw);
7891 /* read-on-clear nic registers here */
7892 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7895 /* only one misc vector supported - mailbox */
7896 eicr &= IXGBE_VTEICR_MASK;
7897 if (eicr == IXGBE_MISC_VEC_ID)
7898 intr->flags |= IXGBE_FLAG_MAILBOX;
7904 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7907 struct ixgbe_interrupt *intr =
7908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7910 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7911 ixgbevf_mbx_process(dev);
7912 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7915 ixgbevf_intr_enable(hw);
7921 ixgbevf_dev_interrupt_handler(void *param)
7923 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7925 ixgbevf_dev_interrupt_get_status(dev);
7926 ixgbevf_dev_interrupt_action(dev);
7930 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7931 * @hw: pointer to hardware structure
7933 * Stops the transmit data path and waits for the HW to internally empty
7934 * the Tx security block
7936 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7938 #define IXGBE_MAX_SECTX_POLL 40
7943 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7944 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7945 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7946 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7947 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7948 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7950 /* Use interrupt-safe sleep just in case */
7954 /* For informational purposes only */
7955 if (i >= IXGBE_MAX_SECTX_POLL)
7956 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7957 "path fully disabled. Continuing with init.");
7959 return IXGBE_SUCCESS;
7963 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7964 * @hw: pointer to hardware structure
7966 * Enables the transmit data path.
7968 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7972 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7973 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7974 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7975 IXGBE_WRITE_FLUSH(hw);
7977 return IXGBE_SUCCESS;
7980 /* restore n-tuple filter */
7982 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7984 struct ixgbe_filter_info *filter_info =
7985 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7986 struct ixgbe_5tuple_filter *node;
7988 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7989 ixgbe_inject_5tuple_filter(dev, node);
7993 /* restore ethernet type filter */
7995 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7998 struct ixgbe_filter_info *filter_info =
7999 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8002 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8003 if (filter_info->ethertype_mask & (1 << i)) {
8004 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8005 filter_info->ethertype_filters[i].etqf);
8006 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8007 filter_info->ethertype_filters[i].etqs);
8008 IXGBE_WRITE_FLUSH(hw);
8013 /* restore SYN filter */
8015 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8018 struct ixgbe_filter_info *filter_info =
8019 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8022 synqf = filter_info->syn_info;
8024 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8025 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8026 IXGBE_WRITE_FLUSH(hw);
8030 /* restore L2 tunnel filter */
8032 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8034 struct ixgbe_l2_tn_info *l2_tn_info =
8035 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8036 struct ixgbe_l2_tn_filter *node;
8037 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8039 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8040 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8041 l2_tn_conf.tunnel_id = node->key.tn_id;
8042 l2_tn_conf.pool = node->pool;
8043 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8048 ixgbe_filter_restore(struct rte_eth_dev *dev)
8050 ixgbe_ntuple_filter_restore(dev);
8051 ixgbe_ethertype_filter_restore(dev);
8052 ixgbe_syn_filter_restore(dev);
8053 ixgbe_fdir_filter_restore(dev);
8054 ixgbe_l2_tn_filter_restore(dev);
8060 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8062 struct ixgbe_l2_tn_info *l2_tn_info =
8063 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8066 if (l2_tn_info->e_tag_en)
8067 (void)ixgbe_e_tag_enable(hw);
8069 if (l2_tn_info->e_tag_fwd_en)
8070 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8072 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8075 /* remove all the n-tuple filters */
8077 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8079 struct ixgbe_filter_info *filter_info =
8080 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8081 struct ixgbe_5tuple_filter *p_5tuple;
8083 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8084 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8087 /* remove all the ether type filters */
8089 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8092 struct ixgbe_filter_info *filter_info =
8093 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8096 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8097 if (filter_info->ethertype_mask & (1 << i) &&
8098 !filter_info->ethertype_filters[i].conf) {
8099 (void)ixgbe_ethertype_filter_remove(filter_info,
8101 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8102 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8103 IXGBE_WRITE_FLUSH(hw);
8108 /* remove the SYN filter */
8110 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8113 struct ixgbe_filter_info *filter_info =
8114 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8116 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8117 filter_info->syn_info = 0;
8119 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8120 IXGBE_WRITE_FLUSH(hw);
8124 /* remove all the L2 tunnel filters */
8126 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8128 struct ixgbe_l2_tn_info *l2_tn_info =
8129 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8130 struct ixgbe_l2_tn_filter *l2_tn_filter;
8131 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8134 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8135 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8136 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8137 l2_tn_conf.pool = l2_tn_filter->pool;
8138 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8146 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8147 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8148 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8149 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8150 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8151 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");