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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
96 * Default values for RX/TX configuration
98 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
99 #define IXGBE_DEFAULT_RX_PTHRESH 8
100 #define IXGBE_DEFAULT_RX_HTHRESH 8
101 #define IXGBE_DEFAULT_RX_WTHRESH 0
103 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
104 #define IXGBE_DEFAULT_TX_PTHRESH 32
105 #define IXGBE_DEFAULT_TX_HTHRESH 0
106 #define IXGBE_DEFAULT_TX_WTHRESH 0
107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
109 /* Bit shift and mask */
110 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
111 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
112 #define IXGBE_8_BIT_WIDTH CHAR_BIT
113 #define IXGBE_8_BIT_MASK UINT8_MAX
115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
120 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
121 static int ixgbe_dev_start(struct rte_eth_dev *dev);
122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
123 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
124 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
131 int wait_to_complete);
132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
133 struct rte_eth_stats *stats);
134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
140 struct rte_eth_dev_info *dev_info);
141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
146 uint16_t vlan_id, int on);
147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
149 uint16_t queue, bool on);
150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
161 struct rte_eth_fc_conf *fc_conf);
162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_pfc_conf *pfc_conf);
166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
167 struct rte_eth_rss_reta_entry64 *reta_conf,
169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
170 struct rte_eth_rss_reta_entry64 *reta_conf,
172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
180 uint32_t index, uint32_t pool);
181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
184 /* For Virtual Function support */
185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
186 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
187 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *stats);
193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
195 uint16_t vlan_id, int on);
196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
197 uint16_t queue, int on);
198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
201 /* For Eth VMDQ APIs support */
202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
203 ether_addr* mac_addr,uint8_t on);
204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
205 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
206 uint16_t rx_mask, uint8_t on);
207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
210 uint64_t pool_mask,uint8_t vlan_on);
211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
212 struct rte_eth_vmdq_mirror_conf *mirror_conf,
213 uint8_t rule_id, uint8_t on);
214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
218 uint16_t queue_idx, uint16_t tx_rate);
219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
220 uint16_t tx_rate, uint64_t q_msk);
222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
223 struct ether_addr *mac_addr,
224 uint32_t index, uint32_t pool);
225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
227 struct rte_eth_syn_filter *filter,
229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
230 struct rte_eth_syn_filter *filter);
231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
232 enum rte_filter_op filter_op,
234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
235 struct ixgbe_5tuple_filter *filter);
236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
237 struct ixgbe_5tuple_filter *filter);
238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
239 struct rte_eth_ntuple_filter *filter,
241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
242 enum rte_filter_op filter_op,
244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
245 struct rte_eth_ntuple_filter *filter);
246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
247 struct rte_eth_ethertype_filter *filter,
249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
250 enum rte_filter_op filter_op,
252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
253 struct rte_eth_ethertype_filter *filter);
254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
255 enum rte_filter_type filter_type,
256 enum rte_filter_op filter_op,
258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
260 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
261 struct ether_addr *mc_addr_set,
262 uint32_t nb_mc_addr);
265 * Define VF Stats MACRO for Non "cleared on read" register
267 #define UPDATE_VF_STAT(reg, last, cur) \
269 u32 latest = IXGBE_READ_REG(hw, reg); \
270 cur += latest - last; \
274 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
276 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
277 u64 new_msb = IXGBE_READ_REG(hw, msb); \
278 u64 latest = ((new_msb << 32) | new_lsb); \
279 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
283 #define IXGBE_SET_HWSTRIP(h, q) do{\
284 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
285 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
286 (h)->bitmap[idx] |= 1 << bit;\
289 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
290 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
291 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
292 (h)->bitmap[idx] &= ~(1 << bit);\
295 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
296 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
297 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
298 (r) = (h)->bitmap[idx] >> bit & 1;\
302 * The set of PCI devices this driver supports
304 static const struct rte_pci_id pci_id_ixgbe_map[] = {
306 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
307 #include "rte_pci_dev_ids.h"
309 { .vendor_id = 0, /* sentinel */ },
314 * The set of PCI devices this driver supports (for 82599 VF)
316 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
318 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
319 #include "rte_pci_dev_ids.h"
320 { .vendor_id = 0, /* sentinel */ },
324 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
325 .dev_configure = ixgbe_dev_configure,
326 .dev_start = ixgbe_dev_start,
327 .dev_stop = ixgbe_dev_stop,
328 .dev_set_link_up = ixgbe_dev_set_link_up,
329 .dev_set_link_down = ixgbe_dev_set_link_down,
330 .dev_close = ixgbe_dev_close,
331 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
332 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
333 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
334 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
335 .link_update = ixgbe_dev_link_update,
336 .stats_get = ixgbe_dev_stats_get,
337 .stats_reset = ixgbe_dev_stats_reset,
338 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
339 .dev_infos_get = ixgbe_dev_info_get,
340 .mtu_set = ixgbe_dev_mtu_set,
341 .vlan_filter_set = ixgbe_vlan_filter_set,
342 .vlan_tpid_set = ixgbe_vlan_tpid_set,
343 .vlan_offload_set = ixgbe_vlan_offload_set,
344 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
345 .rx_queue_start = ixgbe_dev_rx_queue_start,
346 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
347 .tx_queue_start = ixgbe_dev_tx_queue_start,
348 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
349 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
350 .rx_queue_release = ixgbe_dev_rx_queue_release,
351 .rx_queue_count = ixgbe_dev_rx_queue_count,
352 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
353 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
354 .tx_queue_release = ixgbe_dev_tx_queue_release,
355 .dev_led_on = ixgbe_dev_led_on,
356 .dev_led_off = ixgbe_dev_led_off,
357 .flow_ctrl_get = ixgbe_flow_ctrl_get,
358 .flow_ctrl_set = ixgbe_flow_ctrl_set,
359 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
360 .mac_addr_add = ixgbe_add_rar,
361 .mac_addr_remove = ixgbe_remove_rar,
362 .uc_hash_table_set = ixgbe_uc_hash_table_set,
363 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
364 .mirror_rule_set = ixgbe_mirror_rule_set,
365 .mirror_rule_reset = ixgbe_mirror_rule_reset,
366 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
367 .set_vf_rx = ixgbe_set_pool_rx,
368 .set_vf_tx = ixgbe_set_pool_tx,
369 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
370 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
371 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
372 .reta_update = ixgbe_dev_rss_reta_update,
373 .reta_query = ixgbe_dev_rss_reta_query,
374 #ifdef RTE_NIC_BYPASS
375 .bypass_init = ixgbe_bypass_init,
376 .bypass_state_set = ixgbe_bypass_state_store,
377 .bypass_state_show = ixgbe_bypass_state_show,
378 .bypass_event_set = ixgbe_bypass_event_store,
379 .bypass_event_show = ixgbe_bypass_event_show,
380 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
381 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
382 .bypass_ver_show = ixgbe_bypass_ver_show,
383 .bypass_wd_reset = ixgbe_bypass_wd_reset,
384 #endif /* RTE_NIC_BYPASS */
385 .rss_hash_update = ixgbe_dev_rss_hash_update,
386 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
387 .filter_ctrl = ixgbe_dev_filter_ctrl,
388 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
392 * dev_ops for virtual function, bare necessities for basic vf
393 * operation have been implemented
395 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
396 .dev_configure = ixgbevf_dev_configure,
397 .dev_start = ixgbevf_dev_start,
398 .dev_stop = ixgbevf_dev_stop,
399 .link_update = ixgbe_dev_link_update,
400 .stats_get = ixgbevf_dev_stats_get,
401 .stats_reset = ixgbevf_dev_stats_reset,
402 .dev_close = ixgbevf_dev_close,
403 .dev_infos_get = ixgbevf_dev_info_get,
404 .mtu_set = ixgbevf_dev_set_mtu,
405 .vlan_filter_set = ixgbevf_vlan_filter_set,
406 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
407 .vlan_offload_set = ixgbevf_vlan_offload_set,
408 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
409 .rx_queue_release = ixgbe_dev_rx_queue_release,
410 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
411 .tx_queue_release = ixgbe_dev_tx_queue_release,
412 .mac_addr_add = ixgbevf_add_mac_addr,
413 .mac_addr_remove = ixgbevf_remove_mac_addr,
414 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
418 * Atomically reads the link status information from global
419 * structure rte_eth_dev.
422 * - Pointer to the structure rte_eth_dev to read from.
423 * - Pointer to the buffer to be saved with the link status.
426 * - On success, zero.
427 * - On failure, negative value.
430 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
431 struct rte_eth_link *link)
433 struct rte_eth_link *dst = link;
434 struct rte_eth_link *src = &(dev->data->dev_link);
436 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
437 *(uint64_t *)src) == 0)
444 * Atomically writes the link status information into global
445 * structure rte_eth_dev.
448 * - Pointer to the structure rte_eth_dev to read from.
449 * - Pointer to the buffer to be saved with the link status.
452 * - On success, zero.
453 * - On failure, negative value.
456 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
457 struct rte_eth_link *link)
459 struct rte_eth_link *dst = &(dev->data->dev_link);
460 struct rte_eth_link *src = link;
462 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
463 *(uint64_t *)src) == 0)
470 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
473 ixgbe_is_sfp(struct ixgbe_hw *hw)
475 switch (hw->phy.type) {
476 case ixgbe_phy_sfp_avago:
477 case ixgbe_phy_sfp_ftl:
478 case ixgbe_phy_sfp_intel:
479 case ixgbe_phy_sfp_unknown:
480 case ixgbe_phy_sfp_passive_tyco:
481 case ixgbe_phy_sfp_passive_unknown:
488 static inline int32_t
489 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
494 status = ixgbe_reset_hw(hw);
496 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
497 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
498 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
499 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
500 IXGBE_WRITE_FLUSH(hw);
506 ixgbe_enable_intr(struct rte_eth_dev *dev)
508 struct ixgbe_interrupt *intr =
509 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
510 struct ixgbe_hw *hw =
511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
513 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
514 IXGBE_WRITE_FLUSH(hw);
518 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
521 ixgbe_disable_intr(struct ixgbe_hw *hw)
523 PMD_INIT_FUNC_TRACE();
525 if (hw->mac.type == ixgbe_mac_82598EB) {
526 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
528 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
529 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
530 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
532 IXGBE_WRITE_FLUSH(hw);
536 * This function resets queue statistics mapping registers.
537 * From Niantic datasheet, Initialization of Statistics section:
538 * "...if software requires the queue counters, the RQSMR and TQSM registers
539 * must be re-programmed following a device reset.
542 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
546 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
547 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
548 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
554 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
559 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
560 #define NB_QMAP_FIELDS_PER_QSM_REG 4
561 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
563 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
564 struct ixgbe_stat_mapping_registers *stat_mappings =
565 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
566 uint32_t qsmr_mask = 0;
567 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
571 if ((hw->mac.type != ixgbe_mac_82599EB) &&
572 (hw->mac.type != ixgbe_mac_X540) &&
573 (hw->mac.type != ixgbe_mac_X550) &&
574 (hw->mac.type != ixgbe_mac_X550EM_x))
577 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
578 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
581 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
582 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
583 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
586 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
588 /* Now clear any previous stat_idx set */
589 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
591 stat_mappings->tqsm[n] &= ~clearing_mask;
593 stat_mappings->rqsmr[n] &= ~clearing_mask;
595 q_map = (uint32_t)stat_idx;
596 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
597 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
599 stat_mappings->tqsm[n] |= qsmr_mask;
601 stat_mappings->rqsmr[n] |= qsmr_mask;
603 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
604 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
606 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
607 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
609 /* Now write the mapping in the appropriate register */
611 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
612 stat_mappings->rqsmr[n], n);
613 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
616 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
617 stat_mappings->tqsm[n], n);
618 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
624 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
626 struct ixgbe_stat_mapping_registers *stat_mappings =
627 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
628 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
631 /* write whatever was in stat mapping table to the NIC */
632 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
634 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
637 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
642 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
645 struct ixgbe_dcb_tc_config *tc;
646 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
648 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
649 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
650 for (i = 0; i < dcb_max_tc; i++) {
651 tc = &dcb_config->tc_config[i];
652 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
653 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
654 (uint8_t)(100/dcb_max_tc + (i & 1));
655 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
656 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
657 (uint8_t)(100/dcb_max_tc + (i & 1));
658 tc->pfc = ixgbe_dcb_pfc_disabled;
661 /* Initialize default user to priority mapping, UPx->TC0 */
662 tc = &dcb_config->tc_config[0];
663 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
664 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
665 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
666 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
667 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
669 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
670 dcb_config->pfc_mode_enable = false;
671 dcb_config->vt_mode = true;
672 dcb_config->round_robin_enable = false;
673 /* support all DCB capabilities in 82599 */
674 dcb_config->support.capabilities = 0xFF;
676 /*we only support 4 Tcs for X540, X550 */
677 if (hw->mac.type == ixgbe_mac_X540 ||
678 hw->mac.type == ixgbe_mac_X550 ||
679 hw->mac.type == ixgbe_mac_X550EM_x) {
680 dcb_config->num_tcs.pg_tcs = 4;
681 dcb_config->num_tcs.pfc_tcs = 4;
686 * Ensure that all locks are released before first NVM or PHY access
689 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
694 * Phy lock should not fail in this early stage. If this is the case,
695 * it is due to an improper exit of the application.
696 * So force the release of the faulty lock. Release of common lock
697 * is done automatically by swfw_sync function.
699 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
700 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
701 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
703 ixgbe_release_swfw_semaphore(hw, mask);
706 * These ones are more tricky since they are common to all ports; but
707 * swfw_sync retries last long enough (1s) to be almost sure that if
708 * lock can not be taken it is due to an improper lock of the
711 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
712 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
713 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
715 ixgbe_release_swfw_semaphore(hw, mask);
719 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
720 * It returns 0 on success.
723 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
725 struct rte_pci_device *pci_dev;
726 struct ixgbe_hw *hw =
727 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
728 struct ixgbe_vfta * shadow_vfta =
729 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
730 struct ixgbe_hwstrip *hwstrip =
731 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
732 struct ixgbe_dcb_config *dcb_config =
733 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
734 struct ixgbe_filter_info *filter_info =
735 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
740 PMD_INIT_FUNC_TRACE();
742 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
743 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
744 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
747 * For secondary processes, we don't initialise any further as primary
748 * has already done this work. Only check we don't need a different
749 * RX and TX function.
751 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
752 struct ixgbe_tx_queue *txq;
753 /* TX queue function in primary, set by last queue initialized
754 * Tx queue may not initialized by primary process */
755 if (eth_dev->data->tx_queues) {
756 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
757 ixgbe_set_tx_function(eth_dev, txq);
759 /* Use default TX function if we get here */
760 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
761 "Using default TX function.");
764 ixgbe_set_rx_function(eth_dev);
768 pci_dev = eth_dev->pci_dev;
770 /* Vendor and Device ID need to be set before init of shared code */
771 hw->device_id = pci_dev->id.device_id;
772 hw->vendor_id = pci_dev->id.vendor_id;
773 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
774 hw->allow_unsupported_sfp = 1;
776 /* Initialize the shared code (base driver) */
777 #ifdef RTE_NIC_BYPASS
778 diag = ixgbe_bypass_init_shared_code(hw);
780 diag = ixgbe_init_shared_code(hw);
781 #endif /* RTE_NIC_BYPASS */
783 if (diag != IXGBE_SUCCESS) {
784 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
788 /* pick up the PCI bus settings for reporting later */
789 ixgbe_get_bus_info(hw);
791 /* Unlock any pending hardware semaphore */
792 ixgbe_swfw_lock_reset(hw);
794 /* Initialize DCB configuration*/
795 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
796 ixgbe_dcb_init(hw,dcb_config);
797 /* Get Hardware Flow Control setting */
798 hw->fc.requested_mode = ixgbe_fc_full;
799 hw->fc.current_mode = ixgbe_fc_full;
800 hw->fc.pause_time = IXGBE_FC_PAUSE;
801 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
802 hw->fc.low_water[i] = IXGBE_FC_LO;
803 hw->fc.high_water[i] = IXGBE_FC_HI;
807 /* Make sure we have a good EEPROM before we read from it */
808 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
809 if (diag != IXGBE_SUCCESS) {
810 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
814 #ifdef RTE_NIC_BYPASS
815 diag = ixgbe_bypass_init_hw(hw);
817 diag = ixgbe_init_hw(hw);
818 #endif /* RTE_NIC_BYPASS */
821 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
822 * is called too soon after the kernel driver unbinding/binding occurs.
823 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
824 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
825 * also called. See ixgbe_identify_phy_82599(). The reason for the
826 * failure is not known, and only occuts when virtualisation features
827 * are disabled in the bios. A delay of 100ms was found to be enough by
828 * trial-and-error, and is doubled to be safe.
830 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
832 diag = ixgbe_init_hw(hw);
835 if (diag == IXGBE_ERR_EEPROM_VERSION) {
836 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
837 "LOM. Please be aware there may be issues associated "
838 "with your hardware.");
839 PMD_INIT_LOG(ERR, "If you are experiencing problems "
840 "please contact your Intel or hardware representative "
841 "who provided you with this hardware.");
842 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
843 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
845 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
849 /* disable interrupt */
850 ixgbe_disable_intr(hw);
852 /* reset mappings for queue statistics hw counters*/
853 ixgbe_reset_qstat_mappings(hw);
855 /* Allocate memory for storing MAC addresses */
856 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
857 hw->mac.num_rar_entries, 0);
858 if (eth_dev->data->mac_addrs == NULL) {
860 "Failed to allocate %u bytes needed to store "
862 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
865 /* Copy the permanent MAC address */
866 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
867 ð_dev->data->mac_addrs[0]);
869 /* Allocate memory for storing hash filter MAC addresses */
870 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
871 IXGBE_VMDQ_NUM_UC_MAC, 0);
872 if (eth_dev->data->hash_mac_addrs == NULL) {
874 "Failed to allocate %d bytes needed to store MAC addresses",
875 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
879 /* initialize the vfta */
880 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
882 /* initialize the hw strip bitmap*/
883 memset(hwstrip, 0, sizeof(*hwstrip));
885 /* initialize PF if max_vfs not zero */
886 ixgbe_pf_host_init(eth_dev);
888 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
889 /* let hardware know driver is loaded */
890 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
894 IXGBE_WRITE_FLUSH(hw);
896 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
897 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
898 (int) hw->mac.type, (int) hw->phy.type,
899 (int) hw->phy.sfp_type);
901 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
902 (int) hw->mac.type, (int) hw->phy.type);
904 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
905 eth_dev->data->port_id, pci_dev->id.vendor_id,
906 pci_dev->id.device_id);
908 rte_intr_callback_register(&(pci_dev->intr_handle),
909 ixgbe_dev_interrupt_handler, (void *)eth_dev);
911 /* enable uio intr after callback register */
912 rte_intr_enable(&(pci_dev->intr_handle));
914 /* enable support intr */
915 ixgbe_enable_intr(eth_dev);
917 /* initialize 5tuple filter list */
918 TAILQ_INIT(&filter_info->fivetuple_list);
919 memset(filter_info->fivetuple_mask, 0,
920 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
927 * Negotiate mailbox API version with the PF.
928 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
929 * Then we try to negotiate starting with the most recent one.
930 * If all negotiation attempts fail, then we will proceed with
931 * the default one (ixgbe_mbox_api_10).
934 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
938 /* start with highest supported, proceed down */
939 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
945 i != RTE_DIM(sup_ver) &&
946 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
952 generate_random_mac_addr(struct ether_addr *mac_addr)
956 /* Set Organizationally Unique Identifier (OUI) prefix. */
957 mac_addr->addr_bytes[0] = 0x00;
958 mac_addr->addr_bytes[1] = 0x09;
959 mac_addr->addr_bytes[2] = 0xC0;
960 /* Force indication of locally assigned MAC address. */
961 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
962 /* Generate the last 3 bytes of the MAC address with a random number. */
964 memcpy(&mac_addr->addr_bytes[3], &random, 3);
968 * Virtual Function device init
971 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
975 struct rte_pci_device *pci_dev;
976 struct ixgbe_hw *hw =
977 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
978 struct ixgbe_vfta * shadow_vfta =
979 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
980 struct ixgbe_hwstrip *hwstrip =
981 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
982 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
984 PMD_INIT_FUNC_TRACE();
986 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
987 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
988 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
990 /* for secondary processes, we don't initialise any further as primary
991 * has already done this work. Only check we don't need a different
993 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
994 if (eth_dev->data->scattered_rx)
995 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
999 pci_dev = eth_dev->pci_dev;
1001 hw->device_id = pci_dev->id.device_id;
1002 hw->vendor_id = pci_dev->id.vendor_id;
1003 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1005 /* initialize the vfta */
1006 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1008 /* initialize the hw strip bitmap*/
1009 memset(hwstrip, 0, sizeof(*hwstrip));
1011 /* Initialize the shared code (base driver) */
1012 diag = ixgbe_init_shared_code(hw);
1013 if (diag != IXGBE_SUCCESS) {
1014 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1018 /* init_mailbox_params */
1019 hw->mbx.ops.init_params(hw);
1021 /* Disable the interrupts for VF */
1022 ixgbevf_intr_disable(hw);
1024 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1025 diag = hw->mac.ops.reset_hw(hw);
1028 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1029 * the underlying PF driver has not assigned a MAC address to the VF.
1030 * In this case, assign a random MAC address.
1032 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1033 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1037 /* negotiate mailbox API version to use with the PF. */
1038 ixgbevf_negotiate_api(hw);
1040 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1041 ixgbevf_get_queues(hw, &tcs, &tc);
1043 /* Allocate memory for storing MAC addresses */
1044 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1045 hw->mac.num_rar_entries, 0);
1046 if (eth_dev->data->mac_addrs == NULL) {
1048 "Failed to allocate %u bytes needed to store "
1050 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1054 /* Generate a random MAC address, if none was assigned by PF. */
1055 if (is_zero_ether_addr(perm_addr)) {
1056 generate_random_mac_addr(perm_addr);
1057 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1059 rte_free(eth_dev->data->mac_addrs);
1060 eth_dev->data->mac_addrs = NULL;
1063 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1064 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1065 "%02x:%02x:%02x:%02x:%02x:%02x",
1066 perm_addr->addr_bytes[0],
1067 perm_addr->addr_bytes[1],
1068 perm_addr->addr_bytes[2],
1069 perm_addr->addr_bytes[3],
1070 perm_addr->addr_bytes[4],
1071 perm_addr->addr_bytes[5]);
1074 /* Copy the permanent MAC address */
1075 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1077 /* reset the hardware with the new settings */
1078 diag = hw->mac.ops.start_hw(hw);
1084 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1088 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1089 eth_dev->data->port_id, pci_dev->id.vendor_id,
1090 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1095 static struct eth_driver rte_ixgbe_pmd = {
1097 .name = "rte_ixgbe_pmd",
1098 .id_table = pci_id_ixgbe_map,
1099 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1101 .eth_dev_init = eth_ixgbe_dev_init,
1102 .dev_private_size = sizeof(struct ixgbe_adapter),
1106 * virtual function driver struct
1108 static struct eth_driver rte_ixgbevf_pmd = {
1110 .name = "rte_ixgbevf_pmd",
1111 .id_table = pci_id_ixgbevf_map,
1112 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1114 .eth_dev_init = eth_ixgbevf_dev_init,
1115 .dev_private_size = sizeof(struct ixgbe_adapter),
1119 * Driver initialization routine.
1120 * Invoked once at EAL init time.
1121 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1124 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1126 PMD_INIT_FUNC_TRACE();
1128 rte_eth_driver_register(&rte_ixgbe_pmd);
1133 * VF Driver initialization routine.
1134 * Invoked one at EAL init time.
1135 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1138 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1140 PMD_INIT_FUNC_TRACE();
1142 rte_eth_driver_register(&rte_ixgbevf_pmd);
1147 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1149 struct ixgbe_hw *hw =
1150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151 struct ixgbe_vfta * shadow_vfta =
1152 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1157 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1158 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1159 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1164 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1166 /* update local VFTA copy */
1167 shadow_vfta->vfta[vid_idx] = vfta;
1173 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1176 ixgbe_vlan_hw_strip_enable(dev, queue);
1178 ixgbe_vlan_hw_strip_disable(dev, queue);
1182 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1184 struct ixgbe_hw *hw =
1185 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1187 /* Only the high 16-bits is valid */
1188 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1192 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1194 struct ixgbe_hw *hw =
1195 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198 PMD_INIT_FUNC_TRACE();
1200 /* Filter Table Disable */
1201 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1202 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1204 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1208 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1210 struct ixgbe_hw *hw =
1211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212 struct ixgbe_vfta * shadow_vfta =
1213 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1217 PMD_INIT_FUNC_TRACE();
1219 /* Filter Table Enable */
1220 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1221 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1222 vlnctrl |= IXGBE_VLNCTRL_VFE;
1224 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1226 /* write whatever is in local vfta copy */
1227 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1228 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1232 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1234 struct ixgbe_hwstrip *hwstrip =
1235 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1237 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1241 IXGBE_SET_HWSTRIP(hwstrip, queue);
1243 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1247 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1249 struct ixgbe_hw *hw =
1250 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253 PMD_INIT_FUNC_TRACE();
1255 if (hw->mac.type == ixgbe_mac_82598EB) {
1256 /* No queue level support */
1257 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1261 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1262 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1263 ctrl &= ~IXGBE_RXDCTL_VME;
1264 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1266 /* record those setting for HW strip per queue */
1267 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1271 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1273 struct ixgbe_hw *hw =
1274 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277 PMD_INIT_FUNC_TRACE();
1279 if (hw->mac.type == ixgbe_mac_82598EB) {
1280 /* No queue level supported */
1281 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1285 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1286 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1287 ctrl |= IXGBE_RXDCTL_VME;
1288 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1290 /* record those setting for HW strip per queue */
1291 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1295 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1297 struct ixgbe_hw *hw =
1298 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302 PMD_INIT_FUNC_TRACE();
1304 if (hw->mac.type == ixgbe_mac_82598EB) {
1305 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306 ctrl &= ~IXGBE_VLNCTRL_VME;
1307 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1310 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313 ctrl &= ~IXGBE_RXDCTL_VME;
1314 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1316 /* record those setting for HW strip per queue */
1317 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1323 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1325 struct ixgbe_hw *hw =
1326 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1330 PMD_INIT_FUNC_TRACE();
1332 if (hw->mac.type == ixgbe_mac_82598EB) {
1333 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1334 ctrl |= IXGBE_VLNCTRL_VME;
1335 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1338 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1339 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1340 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1341 ctrl |= IXGBE_RXDCTL_VME;
1342 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1344 /* record those setting for HW strip per queue */
1345 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1351 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1353 struct ixgbe_hw *hw =
1354 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 PMD_INIT_FUNC_TRACE();
1359 /* DMATXCTRL: Geric Double VLAN Disable */
1360 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1361 ctrl &= ~IXGBE_DMATXCTL_GDV;
1362 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1364 /* CTRL_EXT: Global Double VLAN Disable */
1365 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1366 ctrl &= ~IXGBE_EXTENDED_VLAN;
1367 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1372 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1374 struct ixgbe_hw *hw =
1375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 PMD_INIT_FUNC_TRACE();
1380 /* DMATXCTRL: Geric Double VLAN Enable */
1381 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1382 ctrl |= IXGBE_DMATXCTL_GDV;
1383 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1385 /* CTRL_EXT: Global Double VLAN Enable */
1386 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1387 ctrl |= IXGBE_EXTENDED_VLAN;
1388 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1391 * VET EXT field in the EXVET register = 0x8100 by default
1392 * So no need to change. Same to VT field of DMATXCTL register
1397 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1399 if(mask & ETH_VLAN_STRIP_MASK){
1400 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401 ixgbe_vlan_hw_strip_enable_all(dev);
1403 ixgbe_vlan_hw_strip_disable_all(dev);
1406 if(mask & ETH_VLAN_FILTER_MASK){
1407 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1408 ixgbe_vlan_hw_filter_enable(dev);
1410 ixgbe_vlan_hw_filter_disable(dev);
1413 if(mask & ETH_VLAN_EXTEND_MASK){
1414 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1415 ixgbe_vlan_hw_extend_enable(dev);
1417 ixgbe_vlan_hw_extend_disable(dev);
1422 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1424 struct ixgbe_hw *hw =
1425 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1427 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1428 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1429 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1433 ixgbe_dev_configure(struct rte_eth_dev *dev)
1435 struct ixgbe_interrupt *intr =
1436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437 struct ixgbe_adapter *adapter =
1438 (struct ixgbe_adapter *)dev->data->dev_private;
1440 PMD_INIT_FUNC_TRACE();
1442 /* set flag to update link status after init */
1443 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1446 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1447 * allocation or vector Rx preconditions we will reset it.
1449 adapter->rx_bulk_alloc_allowed = true;
1450 adapter->rx_vec_allowed = true;
1456 * Configure device link speed and setup link.
1457 * It returns 0 on success.
1460 ixgbe_dev_start(struct rte_eth_dev *dev)
1462 struct ixgbe_hw *hw =
1463 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464 struct ixgbe_vf_info *vfinfo =
1465 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1466 int err, link_up = 0, negotiate = 0;
1472 PMD_INIT_FUNC_TRACE();
1474 /* IXGBE devices don't support half duplex */
1475 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1476 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1477 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1478 dev->data->dev_conf.link_duplex,
1479 dev->data->port_id);
1484 hw->adapter_stopped = FALSE;
1485 ixgbe_stop_adapter(hw);
1487 /* reinitialize adapter
1488 * this calls reset and start */
1489 status = ixgbe_pf_reset_hw(hw);
1492 hw->mac.ops.start_hw(hw);
1493 hw->mac.get_link_status = true;
1495 /* configure PF module if SRIOV enabled */
1496 ixgbe_pf_host_configure(dev);
1498 /* initialize transmission unit */
1499 ixgbe_dev_tx_init(dev);
1501 /* This can fail when allocating mbufs for descriptor rings */
1502 err = ixgbe_dev_rx_init(dev);
1504 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1508 err = ixgbe_dev_rxtx_start(dev);
1510 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1514 /* Skip link setup if loopback mode is enabled for 82599. */
1515 if (hw->mac.type == ixgbe_mac_82599EB &&
1516 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1517 goto skip_link_setup;
1519 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1520 err = hw->mac.ops.setup_sfp(hw);
1525 /* Turn on the laser */
1526 ixgbe_enable_tx_laser(hw);
1528 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1531 dev->data->dev_link.link_status = link_up;
1533 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1537 switch(dev->data->dev_conf.link_speed) {
1538 case ETH_LINK_SPEED_AUTONEG:
1539 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1540 IXGBE_LINK_SPEED_82599_AUTONEG :
1541 IXGBE_LINK_SPEED_82598_AUTONEG;
1543 case ETH_LINK_SPEED_100:
1545 * Invalid for 82598 but error will be detected by
1546 * ixgbe_setup_link()
1548 speed = IXGBE_LINK_SPEED_100_FULL;
1550 case ETH_LINK_SPEED_1000:
1551 speed = IXGBE_LINK_SPEED_1GB_FULL;
1553 case ETH_LINK_SPEED_10000:
1554 speed = IXGBE_LINK_SPEED_10GB_FULL;
1557 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1558 dev->data->dev_conf.link_speed,
1559 dev->data->port_id);
1563 err = ixgbe_setup_link(hw, speed, link_up);
1569 /* check if lsc interrupt is enabled */
1570 if (dev->data->dev_conf.intr_conf.lsc != 0)
1571 ixgbe_dev_lsc_interrupt_setup(dev);
1573 /* resume enabled intr since hw reset */
1574 ixgbe_enable_intr(dev);
1576 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1577 ETH_VLAN_EXTEND_MASK;
1578 ixgbe_vlan_offload_set(dev, mask);
1580 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1581 /* Enable vlan filtering for VMDq */
1582 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1585 /* Configure DCB hw */
1586 ixgbe_configure_dcb(dev);
1588 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1589 err = ixgbe_fdir_configure(dev);
1594 /* Restore vf rate limit */
1595 if (vfinfo != NULL) {
1596 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1597 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1598 if (vfinfo[vf].tx_rate[idx] != 0)
1599 ixgbe_set_vf_rate_limit(dev, vf,
1600 vfinfo[vf].tx_rate[idx],
1604 ixgbe_restore_statistics_mapping(dev);
1609 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1610 ixgbe_dev_clear_queues(dev);
1615 * Stop device: disable rx and tx functions to allow for reconfiguring.
1618 ixgbe_dev_stop(struct rte_eth_dev *dev)
1620 struct rte_eth_link link;
1621 struct ixgbe_hw *hw =
1622 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623 struct ixgbe_vf_info *vfinfo =
1624 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1625 struct ixgbe_filter_info *filter_info =
1626 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1627 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1630 PMD_INIT_FUNC_TRACE();
1632 /* disable interrupts */
1633 ixgbe_disable_intr(hw);
1636 ixgbe_pf_reset_hw(hw);
1637 hw->adapter_stopped = FALSE;
1640 ixgbe_stop_adapter(hw);
1642 for (vf = 0; vfinfo != NULL &&
1643 vf < dev->pci_dev->max_vfs; vf++)
1644 vfinfo[vf].clear_to_send = false;
1646 /* Turn off the laser */
1647 ixgbe_disable_tx_laser(hw);
1649 ixgbe_dev_clear_queues(dev);
1651 /* Clear stored conf */
1652 dev->data->scattered_rx = 0;
1655 /* Clear recorded link status */
1656 memset(&link, 0, sizeof(link));
1657 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1659 /* Remove all ntuple filters of the device */
1660 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1661 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1662 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1663 TAILQ_REMOVE(&filter_info->fivetuple_list,
1667 memset(filter_info->fivetuple_mask, 0,
1668 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1673 * Set device link up: enable tx laser.
1676 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1678 struct ixgbe_hw *hw =
1679 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 if (hw->mac.type == ixgbe_mac_82599EB) {
1681 #ifdef RTE_NIC_BYPASS
1682 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1683 /* Not suported in bypass mode */
1684 PMD_INIT_LOG(ERR, "Set link up is not supported "
1685 "by device id 0x%x", hw->device_id);
1689 /* Turn on the laser */
1690 ixgbe_enable_tx_laser(hw);
1694 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1700 * Set device link down: disable tx laser.
1703 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1705 struct ixgbe_hw *hw =
1706 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707 if (hw->mac.type == ixgbe_mac_82599EB) {
1708 #ifdef RTE_NIC_BYPASS
1709 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1710 /* Not suported in bypass mode */
1711 PMD_INIT_LOG(ERR, "Set link down is not supported "
1712 "by device id 0x%x", hw->device_id);
1716 /* Turn off the laser */
1717 ixgbe_disable_tx_laser(hw);
1721 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1727 * Reest and stop device.
1730 ixgbe_dev_close(struct rte_eth_dev *dev)
1732 struct ixgbe_hw *hw =
1733 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735 PMD_INIT_FUNC_TRACE();
1737 ixgbe_pf_reset_hw(hw);
1739 ixgbe_dev_stop(dev);
1740 hw->adapter_stopped = 1;
1742 ixgbe_disable_pcie_master(hw);
1744 /* reprogram the RAR[0] in case user changed it. */
1745 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1749 * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1752 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1754 struct ixgbe_hw *hw =
1755 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 struct ixgbe_hw_stats *hw_stats =
1757 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1758 uint32_t bprc, lxon, lxoff, total;
1759 uint64_t total_missed_rx, total_qbrc, total_qprc;
1762 total_missed_rx = 0;
1766 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1767 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1768 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1769 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1771 for (i = 0; i < 8; i++) {
1773 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1774 /* global total per queue */
1775 hw_stats->mpc[i] += mp;
1776 /* Running comprehensive total for stats display */
1777 total_missed_rx += hw_stats->mpc[i];
1778 if (hw->mac.type == ixgbe_mac_82598EB)
1779 hw_stats->rnbc[i] +=
1780 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1781 hw_stats->pxontxc[i] +=
1782 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1783 hw_stats->pxonrxc[i] +=
1784 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1785 hw_stats->pxofftxc[i] +=
1786 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1787 hw_stats->pxoffrxc[i] +=
1788 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1789 hw_stats->pxon2offc[i] +=
1790 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1792 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1793 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1794 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1795 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1796 hw_stats->qbrc[i] +=
1797 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1798 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1799 hw_stats->qbtc[i] +=
1800 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1801 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1803 total_qprc += hw_stats->qprc[i];
1804 total_qbrc += hw_stats->qbrc[i];
1806 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1807 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1808 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1810 /* Note that gprc counts missed packets */
1811 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1813 if (hw->mac.type != ixgbe_mac_82598EB) {
1814 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1815 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1816 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1817 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1818 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1819 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1820 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1821 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1823 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1824 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1825 /* 82598 only has a counter in the high register */
1826 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1827 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1828 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1832 * Workaround: mprc hardware is incorrectly counting
1833 * broadcasts, so for now we subtract those.
1835 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1836 hw_stats->bprc += bprc;
1837 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1838 if (hw->mac.type == ixgbe_mac_82598EB)
1839 hw_stats->mprc -= bprc;
1841 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1842 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1843 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1844 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1845 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1846 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1848 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1849 hw_stats->lxontxc += lxon;
1850 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1851 hw_stats->lxofftxc += lxoff;
1852 total = lxon + lxoff;
1854 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1855 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1856 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1857 hw_stats->gptc -= total;
1858 hw_stats->mptc -= total;
1859 hw_stats->ptc64 -= total;
1860 hw_stats->gotc -= total * ETHER_MIN_LEN;
1862 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1863 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1864 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1865 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1866 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1867 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1868 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1869 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1870 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1871 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1872 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1873 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1874 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1875 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1876 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1877 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1878 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1879 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1880 /* Only read FCOE on 82599 */
1881 if (hw->mac.type != ixgbe_mac_82598EB) {
1882 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1883 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1884 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1885 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1886 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1892 /* Fill out the rte_eth_stats statistics structure */
1893 stats->ipackets = total_qprc;
1894 stats->ibytes = total_qbrc;
1895 stats->opackets = hw_stats->gptc;
1896 stats->obytes = hw_stats->gotc;
1897 stats->imcasts = hw_stats->mprc;
1899 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1900 stats->q_ipackets[i] = hw_stats->qprc[i];
1901 stats->q_opackets[i] = hw_stats->qptc[i];
1902 stats->q_ibytes[i] = hw_stats->qbrc[i];
1903 stats->q_obytes[i] = hw_stats->qbtc[i];
1904 stats->q_errors[i] = hw_stats->qprdc[i];
1908 stats->ibadcrc = hw_stats->crcerrs;
1909 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1910 stats->imissed = total_missed_rx;
1911 stats->ierrors = stats->ibadcrc +
1914 hw_stats->illerrc + hw_stats->errbc;
1919 /* XON/XOFF pause frames */
1920 stats->tx_pause_xon = hw_stats->lxontxc;
1921 stats->rx_pause_xon = hw_stats->lxonrxc;
1922 stats->tx_pause_xoff = hw_stats->lxofftxc;
1923 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1925 /* Flow Director Stats registers */
1926 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1927 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1928 stats->fdirmatch = hw_stats->fdirmatch;
1929 stats->fdirmiss = hw_stats->fdirmiss;
1933 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1935 struct ixgbe_hw_stats *stats =
1936 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1938 /* HW registers are cleared on read */
1939 ixgbe_dev_stats_get(dev, NULL);
1941 /* Reset software totals */
1942 memset(stats, 0, sizeof(*stats));
1946 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1948 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1950 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1952 /* Good Rx packet, include VF loopback */
1953 UPDATE_VF_STAT(IXGBE_VFGPRC,
1954 hw_stats->last_vfgprc, hw_stats->vfgprc);
1956 /* Good Rx octets, include VF loopback */
1957 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1958 hw_stats->last_vfgorc, hw_stats->vfgorc);
1960 /* Good Tx packet, include VF loopback */
1961 UPDATE_VF_STAT(IXGBE_VFGPTC,
1962 hw_stats->last_vfgptc, hw_stats->vfgptc);
1964 /* Good Tx octets, include VF loopback */
1965 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1966 hw_stats->last_vfgotc, hw_stats->vfgotc);
1968 /* Rx Multicst Packet */
1969 UPDATE_VF_STAT(IXGBE_VFMPRC,
1970 hw_stats->last_vfmprc, hw_stats->vfmprc);
1975 stats->ipackets = hw_stats->vfgprc;
1976 stats->ibytes = hw_stats->vfgorc;
1977 stats->opackets = hw_stats->vfgptc;
1978 stats->obytes = hw_stats->vfgotc;
1979 stats->imcasts = hw_stats->vfmprc;
1983 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1985 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1986 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1988 /* Sync HW register to the last stats */
1989 ixgbevf_dev_stats_get(dev, NULL);
1991 /* reset HW current stats*/
1992 hw_stats->vfgprc = 0;
1993 hw_stats->vfgorc = 0;
1994 hw_stats->vfgptc = 0;
1995 hw_stats->vfgotc = 0;
1996 hw_stats->vfmprc = 0;
2001 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2003 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2006 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2007 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2008 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2009 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2010 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2011 dev_info->max_vfs = dev->pci_dev->max_vfs;
2012 if (hw->mac.type == ixgbe_mac_82598EB)
2013 dev_info->max_vmdq_pools = ETH_16_POOLS;
2015 dev_info->max_vmdq_pools = ETH_64_POOLS;
2016 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2017 dev_info->rx_offload_capa =
2018 DEV_RX_OFFLOAD_VLAN_STRIP |
2019 DEV_RX_OFFLOAD_IPV4_CKSUM |
2020 DEV_RX_OFFLOAD_UDP_CKSUM |
2021 DEV_RX_OFFLOAD_TCP_CKSUM;
2024 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2027 if ((hw->mac.type == ixgbe_mac_82599EB ||
2028 hw->mac.type == ixgbe_mac_X540) &&
2029 !RTE_ETH_DEV_SRIOV(dev).active)
2030 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2032 dev_info->tx_offload_capa =
2033 DEV_TX_OFFLOAD_VLAN_INSERT |
2034 DEV_TX_OFFLOAD_IPV4_CKSUM |
2035 DEV_TX_OFFLOAD_UDP_CKSUM |
2036 DEV_TX_OFFLOAD_TCP_CKSUM |
2037 DEV_TX_OFFLOAD_SCTP_CKSUM |
2038 DEV_TX_OFFLOAD_TCP_TSO;
2040 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2042 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2043 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2044 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2046 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2050 dev_info->default_txconf = (struct rte_eth_txconf) {
2052 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2053 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2054 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2056 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2057 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2058 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2059 ETH_TXQ_FLAGS_NOOFFLOADS,
2061 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2062 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2066 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2067 struct rte_eth_dev_info *dev_info)
2069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2072 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2073 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2074 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2075 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2076 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2077 dev_info->max_vfs = dev->pci_dev->max_vfs;
2078 if (hw->mac.type == ixgbe_mac_82598EB)
2079 dev_info->max_vmdq_pools = ETH_16_POOLS;
2081 dev_info->max_vmdq_pools = ETH_64_POOLS;
2082 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2083 DEV_RX_OFFLOAD_IPV4_CKSUM |
2084 DEV_RX_OFFLOAD_UDP_CKSUM |
2085 DEV_RX_OFFLOAD_TCP_CKSUM;
2086 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2087 DEV_TX_OFFLOAD_IPV4_CKSUM |
2088 DEV_TX_OFFLOAD_UDP_CKSUM |
2089 DEV_TX_OFFLOAD_TCP_CKSUM |
2090 DEV_TX_OFFLOAD_SCTP_CKSUM;
2092 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2094 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2095 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2096 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2098 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2102 dev_info->default_txconf = (struct rte_eth_txconf) {
2104 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2105 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2106 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2108 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2109 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2110 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2111 ETH_TXQ_FLAGS_NOOFFLOADS,
2115 /* return 0 means link status changed, -1 means not changed */
2117 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2119 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 struct rte_eth_link link, old;
2121 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2125 link.link_status = 0;
2126 link.link_speed = 0;
2127 link.link_duplex = 0;
2128 memset(&old, 0, sizeof(old));
2129 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2131 hw->mac.get_link_status = true;
2133 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2134 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2135 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2137 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2140 link.link_speed = ETH_LINK_SPEED_100;
2141 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2142 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2143 if (link.link_status == old.link_status)
2149 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2150 if (link.link_status == old.link_status)
2154 link.link_status = 1;
2155 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2157 switch (link_speed) {
2159 case IXGBE_LINK_SPEED_UNKNOWN:
2160 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2161 link.link_speed = ETH_LINK_SPEED_100;
2164 case IXGBE_LINK_SPEED_100_FULL:
2165 link.link_speed = ETH_LINK_SPEED_100;
2168 case IXGBE_LINK_SPEED_1GB_FULL:
2169 link.link_speed = ETH_LINK_SPEED_1000;
2172 case IXGBE_LINK_SPEED_10GB_FULL:
2173 link.link_speed = ETH_LINK_SPEED_10000;
2176 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2178 if (link.link_status == old.link_status)
2185 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2191 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2192 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2196 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2198 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2202 fctrl &= (~IXGBE_FCTRL_UPE);
2203 if (dev->data->all_multicast == 1)
2204 fctrl |= IXGBE_FCTRL_MPE;
2206 fctrl &= (~IXGBE_FCTRL_MPE);
2207 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2211 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2213 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2217 fctrl |= IXGBE_FCTRL_MPE;
2218 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2222 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 if (dev->data->promiscuous == 1)
2228 return; /* must remain in all_multicast mode */
2230 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2231 fctrl &= (~IXGBE_FCTRL_MPE);
2232 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2236 * It clears the interrupt causes and enables the interrupt.
2237 * It will be called once only during nic initialized.
2240 * Pointer to struct rte_eth_dev.
2243 * - On success, zero.
2244 * - On failure, a negative value.
2247 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2249 struct ixgbe_interrupt *intr =
2250 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2252 ixgbe_dev_link_status_print(dev);
2253 intr->mask |= IXGBE_EICR_LSC;
2259 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2262 * Pointer to struct rte_eth_dev.
2265 * - On success, zero.
2266 * - On failure, a negative value.
2269 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2272 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273 struct ixgbe_interrupt *intr =
2274 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2276 /* clear all cause mask */
2277 ixgbe_disable_intr(hw);
2279 /* read-on-clear nic registers here */
2280 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2281 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2284 if (eicr & IXGBE_EICR_LSC) {
2285 /* set flag for async link update */
2286 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2289 if (eicr & IXGBE_EICR_MAILBOX)
2290 intr->flags |= IXGBE_FLAG_MAILBOX;
2296 * It gets and then prints the link status.
2299 * Pointer to struct rte_eth_dev.
2302 * - On success, zero.
2303 * - On failure, a negative value.
2306 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2308 struct rte_eth_link link;
2310 memset(&link, 0, sizeof(link));
2311 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2312 if (link.link_status) {
2313 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2314 (int)(dev->data->port_id),
2315 (unsigned)link.link_speed,
2316 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2317 "full-duplex" : "half-duplex");
2319 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2320 (int)(dev->data->port_id));
2322 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2323 dev->pci_dev->addr.domain,
2324 dev->pci_dev->addr.bus,
2325 dev->pci_dev->addr.devid,
2326 dev->pci_dev->addr.function);
2330 * It executes link_update after knowing an interrupt occurred.
2333 * Pointer to struct rte_eth_dev.
2336 * - On success, zero.
2337 * - On failure, a negative value.
2340 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2342 struct ixgbe_interrupt *intr =
2343 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2345 struct rte_eth_link link;
2346 int intr_enable_delay = false;
2348 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2350 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2351 ixgbe_pf_mbx_process(dev);
2352 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2355 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2356 /* get the link status before link update, for predicting later */
2357 memset(&link, 0, sizeof(link));
2358 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2360 ixgbe_dev_link_update(dev, 0);
2363 if (!link.link_status)
2364 /* handle it 1 sec later, wait it being stable */
2365 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2366 /* likely to down */
2368 /* handle it 4 sec later, wait it being stable */
2369 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2371 ixgbe_dev_link_status_print(dev);
2373 intr_enable_delay = true;
2376 if (intr_enable_delay) {
2377 if (rte_eal_alarm_set(timeout * 1000,
2378 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2379 PMD_DRV_LOG(ERR, "Error setting alarm");
2381 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2382 ixgbe_enable_intr(dev);
2383 rte_intr_enable(&(dev->pci_dev->intr_handle));
2391 * Interrupt handler which shall be registered for alarm callback for delayed
2392 * handling specific interrupt to wait for the stable nic state. As the
2393 * NIC interrupt state is not stable for ixgbe after link is just down,
2394 * it needs to wait 4 seconds to get the stable status.
2397 * Pointer to interrupt handle.
2399 * The address of parameter (struct rte_eth_dev *) regsitered before.
2405 ixgbe_dev_interrupt_delayed_handler(void *param)
2407 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2408 struct ixgbe_interrupt *intr =
2409 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2410 struct ixgbe_hw *hw =
2411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2415 if (eicr & IXGBE_EICR_MAILBOX)
2416 ixgbe_pf_mbx_process(dev);
2418 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2419 ixgbe_dev_link_update(dev, 0);
2420 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2421 ixgbe_dev_link_status_print(dev);
2422 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2425 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2426 ixgbe_enable_intr(dev);
2427 rte_intr_enable(&(dev->pci_dev->intr_handle));
2431 * Interrupt handler triggered by NIC for handling
2432 * specific interrupt.
2435 * Pointer to interrupt handle.
2437 * The address of parameter (struct rte_eth_dev *) regsitered before.
2443 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2446 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2447 ixgbe_dev_interrupt_get_status(dev);
2448 ixgbe_dev_interrupt_action(dev);
2452 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2454 struct ixgbe_hw *hw;
2456 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2461 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2463 struct ixgbe_hw *hw;
2465 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2470 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2472 struct ixgbe_hw *hw;
2478 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480 fc_conf->pause_time = hw->fc.pause_time;
2481 fc_conf->high_water = hw->fc.high_water[0];
2482 fc_conf->low_water = hw->fc.low_water[0];
2483 fc_conf->send_xon = hw->fc.send_xon;
2484 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2487 * Return rx_pause status according to actual setting of
2490 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2491 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2497 * Return tx_pause status according to actual setting of
2500 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2501 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2506 if (rx_pause && tx_pause)
2507 fc_conf->mode = RTE_FC_FULL;
2509 fc_conf->mode = RTE_FC_RX_PAUSE;
2511 fc_conf->mode = RTE_FC_TX_PAUSE;
2513 fc_conf->mode = RTE_FC_NONE;
2519 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2521 struct ixgbe_hw *hw;
2523 uint32_t rx_buf_size;
2524 uint32_t max_high_water;
2526 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2533 PMD_INIT_FUNC_TRACE();
2535 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2538 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2539 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2542 * At least reserve one Ethernet frame for watermark
2543 * high_water/low_water in kilo bytes for ixgbe
2545 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2546 if ((fc_conf->high_water > max_high_water) ||
2547 (fc_conf->high_water < fc_conf->low_water)) {
2548 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2549 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2553 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2554 hw->fc.pause_time = fc_conf->pause_time;
2555 hw->fc.high_water[0] = fc_conf->high_water;
2556 hw->fc.low_water[0] = fc_conf->low_water;
2557 hw->fc.send_xon = fc_conf->send_xon;
2559 err = ixgbe_fc_enable(hw);
2561 /* Not negotiated is not an error case */
2562 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2564 /* check if we want to forward MAC frames - driver doesn't have native
2565 * capability to do that, so we'll write the registers ourselves */
2567 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2569 /* set or clear MFLCN.PMCF bit depending on configuration */
2570 if (fc_conf->mac_ctrl_frame_fwd != 0)
2571 mflcn |= IXGBE_MFLCN_PMCF;
2573 mflcn &= ~IXGBE_MFLCN_PMCF;
2575 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2576 IXGBE_WRITE_FLUSH(hw);
2581 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2586 * ixgbe_pfc_enable_generic - Enable flow control
2587 * @hw: pointer to hardware structure
2588 * @tc_num: traffic class number
2589 * Enable flow control according to the current settings.
2592 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2595 uint32_t mflcn_reg, fccfg_reg;
2597 uint32_t fcrtl, fcrth;
2601 /* Validate the water mark configuration */
2602 if (!hw->fc.pause_time) {
2603 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2607 /* Low water mark of zero causes XOFF floods */
2608 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2609 /* High/Low water can not be 0 */
2610 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2611 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2612 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2616 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2617 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2618 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2622 /* Negotiate the fc mode to use */
2623 ixgbe_fc_autoneg(hw);
2625 /* Disable any previous flow control settings */
2626 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2627 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2629 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2630 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2632 switch (hw->fc.current_mode) {
2635 * If the count of enabled RX Priority Flow control >1,
2636 * and the TX pause can not be disabled
2639 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2640 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2641 if (reg & IXGBE_FCRTH_FCEN)
2645 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2647 case ixgbe_fc_rx_pause:
2649 * Rx Flow control is enabled and Tx Flow control is
2650 * disabled by software override. Since there really
2651 * isn't a way to advertise that we are capable of RX
2652 * Pause ONLY, we will advertise that we support both
2653 * symmetric and asymmetric Rx PAUSE. Later, we will
2654 * disable the adapter's ability to send PAUSE frames.
2656 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2658 * If the count of enabled RX Priority Flow control >1,
2659 * and the TX pause can not be disabled
2662 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2663 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2664 if (reg & IXGBE_FCRTH_FCEN)
2668 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2670 case ixgbe_fc_tx_pause:
2672 * Tx Flow control is enabled, and Rx Flow control is
2673 * disabled by software override.
2675 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2678 /* Flow control (both Rx and Tx) is enabled by SW override. */
2679 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2680 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2683 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2684 ret_val = IXGBE_ERR_CONFIG;
2689 /* Set 802.3x based flow control settings. */
2690 mflcn_reg |= IXGBE_MFLCN_DPF;
2691 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2692 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2694 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2695 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2696 hw->fc.high_water[tc_num]) {
2697 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2698 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2699 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2701 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2703 * In order to prevent Tx hangs when the internal Tx
2704 * switch is enabled we must set the high water mark
2705 * to the maximum FCRTH value. This allows the Tx
2706 * switch to function even under heavy Rx workloads.
2708 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2710 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2712 /* Configure pause time (2 TCs per register) */
2713 reg = hw->fc.pause_time * 0x00010001;
2714 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2715 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2717 /* Configure flow control refresh threshold value */
2718 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2725 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2727 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2730 if(hw->mac.type != ixgbe_mac_82598EB) {
2731 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2737 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2740 uint32_t rx_buf_size;
2741 uint32_t max_high_water;
2743 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2744 struct ixgbe_hw *hw =
2745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746 struct ixgbe_dcb_config *dcb_config =
2747 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2749 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2756 PMD_INIT_FUNC_TRACE();
2758 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2759 tc_num = map[pfc_conf->priority];
2760 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2761 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2763 * At least reserve one Ethernet frame for watermark
2764 * high_water/low_water in kilo bytes for ixgbe
2766 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2767 if ((pfc_conf->fc.high_water > max_high_water) ||
2768 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2769 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2770 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2774 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2775 hw->fc.pause_time = pfc_conf->fc.pause_time;
2776 hw->fc.send_xon = pfc_conf->fc.send_xon;
2777 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2778 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2780 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2782 /* Not negotiated is not an error case */
2783 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2786 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2791 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2792 struct rte_eth_rss_reta_entry64 *reta_conf,
2797 uint16_t idx, shift;
2798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 PMD_INIT_FUNC_TRACE();
2801 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2802 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2803 "(%d) doesn't match the number hardware can supported "
2804 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2808 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2809 idx = i / RTE_RETA_GROUP_SIZE;
2810 shift = i % RTE_RETA_GROUP_SIZE;
2811 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2815 if (mask == IXGBE_4_BIT_MASK)
2818 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2819 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2820 if (mask & (0x1 << j))
2821 reta |= reta_conf[idx].reta[shift + j] <<
2824 reta |= r & (IXGBE_8_BIT_MASK <<
2827 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2834 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2835 struct rte_eth_rss_reta_entry64 *reta_conf,
2840 uint16_t idx, shift;
2841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 PMD_INIT_FUNC_TRACE();
2844 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2845 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2846 "(%d) doesn't match the number hardware can supported "
2847 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2851 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2852 idx = i / RTE_RETA_GROUP_SIZE;
2853 shift = i % RTE_RETA_GROUP_SIZE;
2854 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2859 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2860 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2861 if (mask & (0x1 << j))
2862 reta_conf[idx].reta[shift + j] =
2863 ((reta >> (CHAR_BIT * j)) &
2872 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2873 uint32_t index, uint32_t pool)
2875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 uint32_t enable_addr = 1;
2878 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2882 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886 ixgbe_clear_rar(hw, index);
2890 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2894 struct ixgbe_hw *hw;
2895 struct rte_eth_dev_info dev_info;
2896 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2898 ixgbe_dev_info_get(dev, &dev_info);
2900 /* check that mtu is within the allowed range */
2901 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2904 /* refuse mtu that requires the support of scattered packets when this
2905 * feature has not been enabled before. */
2906 if (!dev->data->scattered_rx &&
2907 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2908 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2911 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2914 /* switch to jumbo mode if needed */
2915 if (frame_size > ETHER_MAX_LEN) {
2916 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2917 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2919 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2920 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2922 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2924 /* update max frame size */
2925 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2927 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2928 maxfrs &= 0x0000FFFF;
2929 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2930 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2936 * Virtual Function operations
2939 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2941 PMD_INIT_FUNC_TRACE();
2943 /* Clear interrupt mask to stop from interrupts being generated */
2944 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2946 IXGBE_WRITE_FLUSH(hw);
2950 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2952 struct rte_eth_conf* conf = &dev->data->dev_conf;
2953 struct ixgbe_adapter *adapter =
2954 (struct ixgbe_adapter *)dev->data->dev_private;
2956 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2957 dev->data->port_id);
2960 * VF has no ability to enable/disable HW CRC
2961 * Keep the persistent behavior the same as Host PF
2963 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2964 if (!conf->rxmode.hw_strip_crc) {
2965 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2966 conf->rxmode.hw_strip_crc = 1;
2969 if (conf->rxmode.hw_strip_crc) {
2970 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2971 conf->rxmode.hw_strip_crc = 0;
2976 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2977 * allocation or vector Rx preconditions we will reset it.
2979 adapter->rx_bulk_alloc_allowed = true;
2980 adapter->rx_vec_allowed = true;
2986 ixgbevf_dev_start(struct rte_eth_dev *dev)
2988 struct ixgbe_hw *hw =
2989 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992 PMD_INIT_FUNC_TRACE();
2994 hw->mac.ops.reset_hw(hw);
2995 hw->mac.get_link_status = true;
2997 /* negotiate mailbox API version to use with the PF. */
2998 ixgbevf_negotiate_api(hw);
3000 ixgbevf_dev_tx_init(dev);
3002 /* This can fail when allocating mbufs for descriptor rings */
3003 err = ixgbevf_dev_rx_init(dev);
3005 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3006 ixgbe_dev_clear_queues(dev);
3011 ixgbevf_set_vfta_all(dev,1);
3014 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3015 ETH_VLAN_EXTEND_MASK;
3016 ixgbevf_vlan_offload_set(dev, mask);
3018 ixgbevf_dev_rxtx_start(dev);
3024 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 PMD_INIT_FUNC_TRACE();
3030 hw->adapter_stopped = TRUE;
3031 ixgbe_stop_adapter(hw);
3034 * Clear what we set, but we still keep shadow_vfta to
3035 * restore after device starts
3037 ixgbevf_set_vfta_all(dev,0);
3039 /* Clear stored conf */
3040 dev->data->scattered_rx = 0;
3042 ixgbe_dev_clear_queues(dev);
3046 ixgbevf_dev_close(struct rte_eth_dev *dev)
3048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050 PMD_INIT_FUNC_TRACE();
3054 ixgbevf_dev_stop(dev);
3056 /* reprogram the RAR[0] in case user changed it. */
3057 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3060 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063 struct ixgbe_vfta * shadow_vfta =
3064 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3065 int i = 0, j = 0, vfta = 0, mask = 1;
3067 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3068 vfta = shadow_vfta->vfta[i];
3071 for (j = 0; j < 32; j++){
3073 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3082 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3084 struct ixgbe_hw *hw =
3085 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086 struct ixgbe_vfta * shadow_vfta =
3087 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3088 uint32_t vid_idx = 0;
3089 uint32_t vid_bit = 0;
3092 PMD_INIT_FUNC_TRACE();
3094 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3095 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3097 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3100 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3101 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3103 /* Save what we set and retore it after device reset */
3105 shadow_vfta->vfta[vid_idx] |= vid_bit;
3107 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3113 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3115 struct ixgbe_hw *hw =
3116 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119 PMD_INIT_FUNC_TRACE();
3121 if(queue >= hw->mac.max_rx_queues)
3124 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3126 ctrl |= IXGBE_RXDCTL_VME;
3128 ctrl &= ~IXGBE_RXDCTL_VME;
3129 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3131 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3135 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3137 struct ixgbe_hw *hw =
3138 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142 /* VF function only support hw strip feature, others are not support */
3143 if(mask & ETH_VLAN_STRIP_MASK){
3144 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3146 for(i=0; i < hw->mac.max_rx_queues; i++)
3147 ixgbevf_vlan_strip_queue_set(dev,i,on);
3152 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3156 /* we only need to do this if VMDq is enabled */
3157 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3158 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3159 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3167 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3169 uint32_t vector = 0;
3170 switch (hw->mac.mc_filter_type) {
3171 case 0: /* use bits [47:36] of the address */
3172 vector = ((uc_addr->addr_bytes[4] >> 4) |
3173 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3175 case 1: /* use bits [46:35] of the address */
3176 vector = ((uc_addr->addr_bytes[4] >> 3) |
3177 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3179 case 2: /* use bits [45:34] of the address */
3180 vector = ((uc_addr->addr_bytes[4] >> 2) |
3181 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3183 case 3: /* use bits [43:32] of the address */
3184 vector = ((uc_addr->addr_bytes[4]) |
3185 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3187 default: /* Invalid mc_filter_type */
3191 /* vector can only be 12-bits or boundary will be exceeded */
3197 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3205 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3206 const uint32_t ixgbe_uta_bit_shift = 5;
3207 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3208 const uint32_t bit1 = 0x1;
3210 struct ixgbe_hw *hw =
3211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212 struct ixgbe_uta_info *uta_info =
3213 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3215 /* The UTA table only exists on 82599 hardware and newer */
3216 if (hw->mac.type < ixgbe_mac_82599EB)
3219 vector = ixgbe_uta_vector(hw,mac_addr);
3220 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3221 uta_shift = vector & ixgbe_uta_bit_mask;
3223 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3227 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3229 uta_info->uta_in_use++;
3230 reg_val |= (bit1 << uta_shift);
3231 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3233 uta_info->uta_in_use--;
3234 reg_val &= ~(bit1 << uta_shift);
3235 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3238 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3240 if (uta_info->uta_in_use > 0)
3241 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3242 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3244 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3250 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3253 struct ixgbe_hw *hw =
3254 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3255 struct ixgbe_uta_info *uta_info =
3256 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3258 /* The UTA table only exists on 82599 hardware and newer */
3259 if (hw->mac.type < ixgbe_mac_82599EB)
3263 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3264 uta_info->uta_shadow[i] = ~0;
3265 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3268 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3269 uta_info->uta_shadow[i] = 0;
3270 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3278 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3280 uint32_t new_val = orig_val;
3282 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3283 new_val |= IXGBE_VMOLR_AUPE;
3284 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3285 new_val |= IXGBE_VMOLR_ROMPE;
3286 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3287 new_val |= IXGBE_VMOLR_ROPE;
3288 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3289 new_val |= IXGBE_VMOLR_BAM;
3290 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3291 new_val |= IXGBE_VMOLR_MPE;
3297 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3298 uint16_t rx_mask, uint8_t on)
3302 struct ixgbe_hw *hw =
3303 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3306 if (hw->mac.type == ixgbe_mac_82598EB) {
3307 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3308 " on 82599 hardware and newer");
3311 if (ixgbe_vmdq_mode_check(hw) < 0)
3314 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3321 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3327 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3331 const uint8_t bit1 = 0x1;
3333 struct ixgbe_hw *hw =
3334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336 if (ixgbe_vmdq_mode_check(hw) < 0)
3339 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3340 reg = IXGBE_READ_REG(hw, addr);
3348 IXGBE_WRITE_REG(hw, addr,reg);
3354 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3358 const uint8_t bit1 = 0x1;
3360 struct ixgbe_hw *hw =
3361 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363 if (ixgbe_vmdq_mode_check(hw) < 0)
3366 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3367 reg = IXGBE_READ_REG(hw, addr);
3375 IXGBE_WRITE_REG(hw, addr,reg);
3381 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3382 uint64_t pool_mask, uint8_t vlan_on)
3386 struct ixgbe_hw *hw =
3387 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389 if (ixgbe_vmdq_mode_check(hw) < 0)
3391 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3392 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3393 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3402 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3403 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3404 uint8_t rule_id, uint8_t on)
3406 uint32_t mr_ctl,vlvf;
3407 uint32_t mp_lsb = 0;
3408 uint32_t mv_msb = 0;
3409 uint32_t mv_lsb = 0;
3410 uint32_t mp_msb = 0;
3413 uint64_t vlan_mask = 0;
3415 const uint8_t pool_mask_offset = 32;
3416 const uint8_t vlan_mask_offset = 32;
3417 const uint8_t dst_pool_offset = 8;
3418 const uint8_t rule_mr_offset = 4;
3419 const uint8_t mirror_rule_mask= 0x0F;
3421 struct ixgbe_mirror_info *mr_info =
3422 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3423 struct ixgbe_hw *hw =
3424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3426 if (ixgbe_vmdq_mode_check(hw) < 0)
3429 /* Check if vlan mask is valid */
3430 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3431 if (mirror_conf->vlan.vlan_mask == 0)
3435 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3436 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3437 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3438 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3439 /* search vlan id related pool vlan filter index */
3440 reg_index = ixgbe_find_vlvf_slot(hw,
3441 mirror_conf->vlan.vlan_id[i]);
3444 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3445 if ((vlvf & IXGBE_VLVF_VIEN) &&
3446 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3447 == mirror_conf->vlan.vlan_id[i]))
3448 vlan_mask |= (1ULL << reg_index);
3455 mv_lsb = vlan_mask & 0xFFFFFFFF;
3456 mv_msb = vlan_mask >> vlan_mask_offset;
3458 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3459 mirror_conf->vlan.vlan_mask;
3460 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3461 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3462 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3463 mirror_conf->vlan.vlan_id[i];
3468 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3469 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3470 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3475 * if enable pool mirror, write related pool mask register,if disable
3476 * pool mirror, clear PFMRVM register
3478 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3480 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3481 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3482 mr_info->mr_conf[rule_id].pool_mask =
3483 mirror_conf->pool_mask;
3488 mr_info->mr_conf[rule_id].pool_mask = 0;
3492 /* read mirror control register and recalculate it */
3493 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3496 mr_ctl |= mirror_conf->rule_type_mask;
3497 mr_ctl &= mirror_rule_mask;
3498 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3500 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3502 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3503 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3505 /* write mirrror control register */
3506 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3508 /* write pool mirrror control register */
3509 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3510 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3511 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3514 /* write VLAN mirrror control register */
3515 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3516 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3517 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3525 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3528 uint32_t lsb_val = 0;
3529 uint32_t msb_val = 0;
3530 const uint8_t rule_mr_offset = 4;
3532 struct ixgbe_hw *hw =
3533 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534 struct ixgbe_mirror_info *mr_info =
3535 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3537 if (ixgbe_vmdq_mode_check(hw) < 0)
3540 memset(&mr_info->mr_conf[rule_id], 0,
3541 sizeof(struct rte_eth_vmdq_mirror_conf));
3543 /* clear PFVMCTL register */
3544 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3546 /* clear pool mask register */
3547 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3548 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3550 /* clear vlan mask register */
3551 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3552 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3557 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3558 uint16_t queue_idx, uint16_t tx_rate)
3560 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561 uint32_t rf_dec, rf_int;
3563 uint16_t link_speed = dev->data->dev_link.link_speed;
3565 if (queue_idx >= hw->mac.max_tx_queues)
3569 /* Calculate the rate factor values to set */
3570 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3571 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3572 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3574 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3575 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3576 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3577 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3583 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3584 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3587 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3588 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3589 IXGBE_MAX_JUMBO_FRAME_SIZE))
3590 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3591 IXGBE_MMW_SIZE_JUMBO_FRAME);
3593 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3594 IXGBE_MMW_SIZE_DEFAULT);
3596 /* Set RTTBCNRC of queue X */
3597 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3598 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3599 IXGBE_WRITE_FLUSH(hw);
3604 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3605 uint16_t tx_rate, uint64_t q_msk)
3607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608 struct ixgbe_vf_info *vfinfo =
3609 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3610 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3611 uint32_t queue_stride =
3612 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3613 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3614 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3615 uint16_t total_rate = 0;
3617 if (queue_end >= hw->mac.max_tx_queues)
3620 if (vfinfo != NULL) {
3621 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3624 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3626 total_rate += vfinfo[vf_idx].tx_rate[idx];
3631 /* Store tx_rate for this vf. */
3632 for (idx = 0; idx < nb_q_per_pool; idx++) {
3633 if (((uint64_t)0x1 << idx) & q_msk) {
3634 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3635 vfinfo[vf].tx_rate[idx] = tx_rate;
3636 total_rate += tx_rate;
3640 if (total_rate > dev->data->dev_link.link_speed) {
3642 * Reset stored TX rate of the VF if it causes exceed
3645 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3649 /* Set RTTBCNRC of each queue/pool for vf X */
3650 for (; queue_idx <= queue_end; queue_idx++) {
3652 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3660 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3661 __attribute__((unused)) uint32_t index,
3662 __attribute__((unused)) uint32_t pool)
3664 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3669 * operation. Trap this case to avoid exhausting the [very limited]
3670 * set of PF resources used to store VF MAC addresses.
3672 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3674 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3677 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3681 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3683 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3685 struct ether_addr *mac_addr;
3690 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3691 * not support the deletion of a given MAC address.
3692 * Instead, it imposes to delete all MAC addresses, then to add again
3693 * all MAC addresses with the exception of the one to be deleted.
3695 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3698 * Add again all MAC addresses, with the exception of the deleted one
3699 * and of the permanent MAC address.
3701 for (i = 0, mac_addr = dev->data->mac_addrs;
3702 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3703 /* Skip the deleted MAC address */
3706 /* Skip NULL MAC addresses */
3707 if (is_zero_ether_addr(mac_addr))
3709 /* Skip the permanent MAC address */
3710 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3712 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3715 "Adding again MAC address "
3716 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3718 mac_addr->addr_bytes[0],
3719 mac_addr->addr_bytes[1],
3720 mac_addr->addr_bytes[2],
3721 mac_addr->addr_bytes[3],
3722 mac_addr->addr_bytes[4],
3723 mac_addr->addr_bytes[5],
3728 #define MAC_TYPE_FILTER_SUP(type) do {\
3729 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3730 (type) != ixgbe_mac_X550)\
3735 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3736 struct rte_eth_syn_filter *filter,
3739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3745 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3748 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3750 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3751 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3753 if (filter->hig_pri)
3754 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3756 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3758 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3760 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3762 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3763 IXGBE_WRITE_FLUSH(hw);
3768 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3769 struct rte_eth_syn_filter *filter)
3771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3774 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3775 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3776 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3783 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3784 enum rte_filter_op filter_op,
3787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790 MAC_TYPE_FILTER_SUP(hw->mac.type);
3792 if (filter_op == RTE_ETH_FILTER_NOP)
3796 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3801 switch (filter_op) {
3802 case RTE_ETH_FILTER_ADD:
3803 ret = ixgbe_syn_filter_set(dev,
3804 (struct rte_eth_syn_filter *)arg,
3807 case RTE_ETH_FILTER_DELETE:
3808 ret = ixgbe_syn_filter_set(dev,
3809 (struct rte_eth_syn_filter *)arg,
3812 case RTE_ETH_FILTER_GET:
3813 ret = ixgbe_syn_filter_get(dev,
3814 (struct rte_eth_syn_filter *)arg);
3817 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3826 static inline enum ixgbe_5tuple_protocol
3827 convert_protocol_type(uint8_t protocol_value)
3829 if (protocol_value == IPPROTO_TCP)
3830 return IXGBE_FILTER_PROTOCOL_TCP;
3831 else if (protocol_value == IPPROTO_UDP)
3832 return IXGBE_FILTER_PROTOCOL_UDP;
3833 else if (protocol_value == IPPROTO_SCTP)
3834 return IXGBE_FILTER_PROTOCOL_SCTP;
3836 return IXGBE_FILTER_PROTOCOL_NONE;
3840 * add a 5tuple filter
3843 * dev: Pointer to struct rte_eth_dev.
3844 * index: the index the filter allocates.
3845 * filter: ponter to the filter that will be added.
3846 * rx_queue: the queue id the filter assigned to.
3849 * - On success, zero.
3850 * - On failure, a negative value.
3853 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3854 struct ixgbe_5tuple_filter *filter)
3856 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 struct ixgbe_filter_info *filter_info =
3858 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3860 uint32_t ftqf, sdpqf;
3861 uint32_t l34timir = 0;
3862 uint8_t mask = 0xff;
3865 * look for an unused 5tuple filter index,
3866 * and insert the filter to list.
3868 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3869 idx = i / (sizeof(uint32_t) * NBBY);
3870 shift = i % (sizeof(uint32_t) * NBBY);
3871 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3872 filter_info->fivetuple_mask[idx] |= 1 << shift;
3874 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3880 if (i >= IXGBE_MAX_FTQF_FILTERS) {
3881 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3885 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3886 IXGBE_SDPQF_DSTPORT_SHIFT);
3887 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3889 ftqf = (uint32_t)(filter->filter_info.proto &
3890 IXGBE_FTQF_PROTOCOL_MASK);
3891 ftqf |= (uint32_t)((filter->filter_info.priority &
3892 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3893 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3894 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3895 if (filter->filter_info.dst_ip_mask == 0)
3896 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3897 if (filter->filter_info.src_port_mask == 0)
3898 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3899 if (filter->filter_info.dst_port_mask == 0)
3900 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3901 if (filter->filter_info.proto_mask == 0)
3902 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3903 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3904 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3905 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3907 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3908 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3909 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3910 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3912 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3913 l34timir |= (uint32_t)(filter->queue <<
3914 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3915 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3920 * remove a 5tuple filter
3923 * dev: Pointer to struct rte_eth_dev.
3924 * filter: the pointer of the filter will be removed.
3927 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3928 struct ixgbe_5tuple_filter *filter)
3930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931 struct ixgbe_filter_info *filter_info =
3932 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3933 uint16_t index = filter->index;
3935 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3936 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3937 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3940 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3941 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3942 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3943 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3944 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3948 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3950 struct ixgbe_hw *hw;
3951 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3953 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3958 /* refuse mtu that requires the support of scattered packets when this
3959 * feature has not been enabled before. */
3960 if (!dev->data->scattered_rx &&
3961 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3962 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3966 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3967 * request of the version 2.0 of the mailbox API.
3968 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3969 * of the mailbox API.
3970 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3971 * prior to 3.11.33 which contains the following change:
3972 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3974 ixgbevf_rlpml_set_vf(hw, max_frame);
3976 /* update max frame size */
3977 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3981 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3982 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3986 static inline struct ixgbe_5tuple_filter *
3987 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3988 struct ixgbe_5tuple_filter_info *key)
3990 struct ixgbe_5tuple_filter *it;
3992 TAILQ_FOREACH(it, filter_list, entries) {
3993 if (memcmp(key, &it->filter_info,
3994 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4001 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4003 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4004 struct ixgbe_5tuple_filter_info *filter_info)
4006 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4007 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4008 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4011 switch (filter->dst_ip_mask) {
4013 filter_info->dst_ip_mask = 0;
4014 filter_info->dst_ip = filter->dst_ip;
4017 filter_info->dst_ip_mask = 1;
4020 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4024 switch (filter->src_ip_mask) {
4026 filter_info->src_ip_mask = 0;
4027 filter_info->src_ip = filter->src_ip;
4030 filter_info->src_ip_mask = 1;
4033 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4037 switch (filter->dst_port_mask) {
4039 filter_info->dst_port_mask = 0;
4040 filter_info->dst_port = filter->dst_port;
4043 filter_info->dst_port_mask = 1;
4046 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4050 switch (filter->src_port_mask) {
4052 filter_info->src_port_mask = 0;
4053 filter_info->src_port = filter->src_port;
4056 filter_info->src_port_mask = 1;
4059 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4063 switch (filter->proto_mask) {
4065 filter_info->proto_mask = 0;
4066 filter_info->proto =
4067 convert_protocol_type(filter->proto);
4070 filter_info->proto_mask = 1;
4073 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4077 filter_info->priority = (uint8_t)filter->priority;
4082 * add or delete a ntuple filter
4085 * dev: Pointer to struct rte_eth_dev.
4086 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4087 * add: if true, add filter, if false, remove filter
4090 * - On success, zero.
4091 * - On failure, a negative value.
4094 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4095 struct rte_eth_ntuple_filter *ntuple_filter,
4098 struct ixgbe_filter_info *filter_info =
4099 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4100 struct ixgbe_5tuple_filter_info filter_5tuple;
4101 struct ixgbe_5tuple_filter *filter;
4104 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4105 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4109 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4110 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4114 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4116 if (filter != NULL && add) {
4117 PMD_DRV_LOG(ERR, "filter exists.");
4120 if (filter == NULL && !add) {
4121 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4126 filter = rte_zmalloc("ixgbe_5tuple_filter",
4127 sizeof(struct ixgbe_5tuple_filter), 0);
4130 (void)rte_memcpy(&filter->filter_info,
4132 sizeof(struct ixgbe_5tuple_filter_info));
4133 filter->queue = ntuple_filter->queue;
4134 ret = ixgbe_add_5tuple_filter(dev, filter);
4140 ixgbe_remove_5tuple_filter(dev, filter);
4146 * get a ntuple filter
4149 * dev: Pointer to struct rte_eth_dev.
4150 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4153 * - On success, zero.
4154 * - On failure, a negative value.
4157 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4158 struct rte_eth_ntuple_filter *ntuple_filter)
4160 struct ixgbe_filter_info *filter_info =
4161 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4162 struct ixgbe_5tuple_filter_info filter_5tuple;
4163 struct ixgbe_5tuple_filter *filter;
4166 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4167 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4171 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4172 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4176 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4178 if (filter == NULL) {
4179 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4182 ntuple_filter->queue = filter->queue;
4187 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4188 * @dev: pointer to rte_eth_dev structure
4189 * @filter_op:operation will be taken.
4190 * @arg: a pointer to specific structure corresponding to the filter_op
4193 * - On success, zero.
4194 * - On failure, a negative value.
4197 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4198 enum rte_filter_op filter_op,
4201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4206 if (filter_op == RTE_ETH_FILTER_NOP)
4210 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4215 switch (filter_op) {
4216 case RTE_ETH_FILTER_ADD:
4217 ret = ixgbe_add_del_ntuple_filter(dev,
4218 (struct rte_eth_ntuple_filter *)arg,
4221 case RTE_ETH_FILTER_DELETE:
4222 ret = ixgbe_add_del_ntuple_filter(dev,
4223 (struct rte_eth_ntuple_filter *)arg,
4226 case RTE_ETH_FILTER_GET:
4227 ret = ixgbe_get_ntuple_filter(dev,
4228 (struct rte_eth_ntuple_filter *)arg);
4231 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4239 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4244 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4245 if (filter_info->ethertype_filters[i] == ethertype &&
4246 (filter_info->ethertype_mask & (1 << i)))
4253 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4258 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4259 if (!(filter_info->ethertype_mask & (1 << i))) {
4260 filter_info->ethertype_mask |= 1 << i;
4261 filter_info->ethertype_filters[i] = ethertype;
4269 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4272 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4274 filter_info->ethertype_mask &= ~(1 << idx);
4275 filter_info->ethertype_filters[idx] = 0;
4280 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4281 struct rte_eth_ethertype_filter *filter,
4284 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285 struct ixgbe_filter_info *filter_info =
4286 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4291 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4294 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4295 filter->ether_type == ETHER_TYPE_IPv6) {
4296 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4297 " ethertype filter.", filter->ether_type);
4301 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4302 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4305 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4306 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4310 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4311 if (ret >= 0 && add) {
4312 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4313 filter->ether_type);
4316 if (ret < 0 && !add) {
4317 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4318 filter->ether_type);
4323 ret = ixgbe_ethertype_filter_insert(filter_info,
4324 filter->ether_type);
4326 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4329 etqf = IXGBE_ETQF_FILTER_EN;
4330 etqf |= (uint32_t)filter->ether_type;
4331 etqs |= (uint32_t)((filter->queue <<
4332 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4333 IXGBE_ETQS_RX_QUEUE);
4334 etqs |= IXGBE_ETQS_QUEUE_EN;
4336 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4340 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4341 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4342 IXGBE_WRITE_FLUSH(hw);
4348 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4349 struct rte_eth_ethertype_filter *filter)
4351 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352 struct ixgbe_filter_info *filter_info =
4353 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4354 uint32_t etqf, etqs;
4357 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4359 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4360 filter->ether_type);
4364 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4365 if (etqf & IXGBE_ETQF_FILTER_EN) {
4366 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4367 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4369 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4370 IXGBE_ETQS_RX_QUEUE_SHIFT;
4377 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4378 * @dev: pointer to rte_eth_dev structure
4379 * @filter_op:operation will be taken.
4380 * @arg: a pointer to specific structure corresponding to the filter_op
4383 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4384 enum rte_filter_op filter_op,
4387 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4390 MAC_TYPE_FILTER_SUP(hw->mac.type);
4392 if (filter_op == RTE_ETH_FILTER_NOP)
4396 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4401 switch (filter_op) {
4402 case RTE_ETH_FILTER_ADD:
4403 ret = ixgbe_add_del_ethertype_filter(dev,
4404 (struct rte_eth_ethertype_filter *)arg,
4407 case RTE_ETH_FILTER_DELETE:
4408 ret = ixgbe_add_del_ethertype_filter(dev,
4409 (struct rte_eth_ethertype_filter *)arg,
4412 case RTE_ETH_FILTER_GET:
4413 ret = ixgbe_get_ethertype_filter(dev,
4414 (struct rte_eth_ethertype_filter *)arg);
4417 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4425 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4426 enum rte_filter_type filter_type,
4427 enum rte_filter_op filter_op,
4432 switch (filter_type) {
4433 case RTE_ETH_FILTER_NTUPLE:
4434 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4436 case RTE_ETH_FILTER_ETHERTYPE:
4437 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4439 case RTE_ETH_FILTER_SYN:
4440 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4442 case RTE_ETH_FILTER_FDIR:
4443 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4446 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4455 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4456 u8 **mc_addr_ptr, u32 *vmdq)
4461 mc_addr = *mc_addr_ptr;
4462 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4467 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4468 struct ether_addr *mc_addr_set,
4469 uint32_t nb_mc_addr)
4471 struct ixgbe_hw *hw;
4474 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475 mc_addr_list = (u8 *)mc_addr_set;
4476 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4477 ixgbe_dev_addr_list_itr, TRUE);
4480 static struct rte_driver rte_ixgbe_driver = {
4482 .init = rte_ixgbe_pmd_init,
4485 static struct rte_driver rte_ixgbevf_driver = {
4487 .init = rte_ixgbevf_pmd_init,
4490 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4491 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);