4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define IXGBE_TIMINCA_16NS_SHIFT 24
130 #define IXGBE_TIMINCA_INCVALUE 16000000
131 #define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
132 | IXGBE_TIMINCA_INCVALUE)
134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
147 int wait_to_complete);
148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
149 struct rte_eth_stats *stats);
150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
151 struct rte_eth_xstats *xstats, unsigned n);
152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstats *xstats, unsigned n);
154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *dev_info);
162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
163 struct rte_eth_dev_info *dev_info);
164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
167 uint16_t vlan_id, int on);
168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
170 uint16_t queue, bool on);
171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
182 struct rte_eth_fc_conf *fc_conf);
183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
184 struct rte_eth_fc_conf *fc_conf);
185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
186 struct rte_eth_pfc_conf *pfc_conf);
187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
188 struct rte_eth_rss_reta_entry64 *reta_conf,
190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
191 struct rte_eth_rss_reta_entry64 *reta_conf,
193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
202 uint32_t index, uint32_t pool);
203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
205 struct ether_addr *mac_addr);
206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
208 /* For Virtual Function support */
209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
213 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
214 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
220 struct rte_eth_stats *stats);
221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
223 uint16_t vlan_id, int on);
224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
225 uint16_t queue, int on);
226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
235 uint8_t queue, uint8_t msix_vector);
236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
238 /* For Eth VMDQ APIs support */
239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
240 ether_addr* mac_addr,uint8_t on);
241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
242 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
243 uint16_t rx_mask, uint8_t on);
244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
247 uint64_t pool_mask,uint8_t vlan_on);
248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
249 struct rte_eth_mirror_conf *mirror_conf,
250 uint8_t rule_id, uint8_t on);
251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
258 uint8_t queue, uint8_t msix_vector);
259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
262 uint16_t queue_idx, uint16_t tx_rate);
263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
264 uint16_t tx_rate, uint64_t q_msk);
266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
267 struct ether_addr *mac_addr,
268 uint32_t index, uint32_t pool);
269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
271 struct ether_addr *mac_addr);
272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
273 struct rte_eth_syn_filter *filter,
275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
276 struct rte_eth_syn_filter *filter);
277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
278 enum rte_filter_op filter_op,
280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
281 struct ixgbe_5tuple_filter *filter);
282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
283 struct ixgbe_5tuple_filter *filter);
284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
285 struct rte_eth_ntuple_filter *filter,
287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
288 enum rte_filter_op filter_op,
290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
291 struct rte_eth_ntuple_filter *filter);
292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
293 struct rte_eth_ethertype_filter *filter,
295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
296 enum rte_filter_op filter_op,
298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
299 struct rte_eth_ethertype_filter *filter);
300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
301 enum rte_filter_type filter_type,
302 enum rte_filter_op filter_op,
304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
307 struct ether_addr *mc_addr_set,
308 uint32_t nb_mc_addr);
309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
310 struct rte_eth_dcb_info *dcb_info);
312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
314 struct rte_dev_reg_info *regs);
315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
317 struct rte_dev_eeprom_info *eeprom);
318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
319 struct rte_dev_eeprom_info *eeprom);
321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
323 struct rte_dev_reg_info *regs);
325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
328 struct timespec *timestamp,
330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
331 struct timespec *timestamp);
334 * Define VF Stats MACRO for Non "cleared on read" register
336 #define UPDATE_VF_STAT(reg, last, cur) \
338 uint32_t latest = IXGBE_READ_REG(hw, reg); \
339 cur += (latest - last) & UINT_MAX; \
343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
345 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
346 u64 new_msb = IXGBE_READ_REG(hw, msb); \
347 u64 latest = ((new_msb << 32) | new_lsb); \
348 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
352 #define IXGBE_SET_HWSTRIP(h, q) do{\
353 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
354 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
355 (h)->bitmap[idx] |= 1 << bit;\
358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
359 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
360 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
361 (h)->bitmap[idx] &= ~(1 << bit);\
364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
365 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
366 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
367 (r) = (h)->bitmap[idx] >> bit & 1;\
371 * The set of PCI devices this driver supports
373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
376 #include "rte_pci_dev_ids.h"
378 { .vendor_id = 0, /* sentinel */ },
383 * The set of PCI devices this driver supports (for 82599 VF)
385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
388 #include "rte_pci_dev_ids.h"
389 { .vendor_id = 0, /* sentinel */ },
393 static const struct rte_eth_desc_lim rx_desc_lim = {
394 .nb_max = IXGBE_MAX_RING_DESC,
395 .nb_min = IXGBE_MIN_RING_DESC,
396 .nb_align = IXGBE_RXD_ALIGN,
399 static const struct rte_eth_desc_lim tx_desc_lim = {
400 .nb_max = IXGBE_MAX_RING_DESC,
401 .nb_min = IXGBE_MIN_RING_DESC,
402 .nb_align = IXGBE_TXD_ALIGN,
405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
406 .dev_configure = ixgbe_dev_configure,
407 .dev_start = ixgbe_dev_start,
408 .dev_stop = ixgbe_dev_stop,
409 .dev_set_link_up = ixgbe_dev_set_link_up,
410 .dev_set_link_down = ixgbe_dev_set_link_down,
411 .dev_close = ixgbe_dev_close,
412 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
413 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
414 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
415 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
416 .link_update = ixgbe_dev_link_update,
417 .stats_get = ixgbe_dev_stats_get,
418 .xstats_get = ixgbe_dev_xstats_get,
419 .stats_reset = ixgbe_dev_stats_reset,
420 .xstats_reset = ixgbe_dev_xstats_reset,
421 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
422 .dev_infos_get = ixgbe_dev_info_get,
423 .mtu_set = ixgbe_dev_mtu_set,
424 .vlan_filter_set = ixgbe_vlan_filter_set,
425 .vlan_tpid_set = ixgbe_vlan_tpid_set,
426 .vlan_offload_set = ixgbe_vlan_offload_set,
427 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
428 .rx_queue_start = ixgbe_dev_rx_queue_start,
429 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
430 .tx_queue_start = ixgbe_dev_tx_queue_start,
431 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
432 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
433 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
434 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
435 .rx_queue_release = ixgbe_dev_rx_queue_release,
436 .rx_queue_count = ixgbe_dev_rx_queue_count,
437 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
438 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
439 .tx_queue_release = ixgbe_dev_tx_queue_release,
440 .dev_led_on = ixgbe_dev_led_on,
441 .dev_led_off = ixgbe_dev_led_off,
442 .flow_ctrl_get = ixgbe_flow_ctrl_get,
443 .flow_ctrl_set = ixgbe_flow_ctrl_set,
444 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
445 .mac_addr_add = ixgbe_add_rar,
446 .mac_addr_remove = ixgbe_remove_rar,
447 .mac_addr_set = ixgbe_set_default_mac_addr,
448 .uc_hash_table_set = ixgbe_uc_hash_table_set,
449 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
450 .mirror_rule_set = ixgbe_mirror_rule_set,
451 .mirror_rule_reset = ixgbe_mirror_rule_reset,
452 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
453 .set_vf_rx = ixgbe_set_pool_rx,
454 .set_vf_tx = ixgbe_set_pool_tx,
455 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
456 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
457 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
458 .reta_update = ixgbe_dev_rss_reta_update,
459 .reta_query = ixgbe_dev_rss_reta_query,
460 #ifdef RTE_NIC_BYPASS
461 .bypass_init = ixgbe_bypass_init,
462 .bypass_state_set = ixgbe_bypass_state_store,
463 .bypass_state_show = ixgbe_bypass_state_show,
464 .bypass_event_set = ixgbe_bypass_event_store,
465 .bypass_event_show = ixgbe_bypass_event_show,
466 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
467 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
468 .bypass_ver_show = ixgbe_bypass_ver_show,
469 .bypass_wd_reset = ixgbe_bypass_wd_reset,
470 #endif /* RTE_NIC_BYPASS */
471 .rss_hash_update = ixgbe_dev_rss_hash_update,
472 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
473 .filter_ctrl = ixgbe_dev_filter_ctrl,
474 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
475 .rxq_info_get = ixgbe_rxq_info_get,
476 .txq_info_get = ixgbe_txq_info_get,
477 .timesync_enable = ixgbe_timesync_enable,
478 .timesync_disable = ixgbe_timesync_disable,
479 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
480 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
481 .get_reg_length = ixgbe_get_reg_length,
482 .get_reg = ixgbe_get_regs,
483 .get_eeprom_length = ixgbe_get_eeprom_length,
484 .get_eeprom = ixgbe_get_eeprom,
485 .set_eeprom = ixgbe_set_eeprom,
486 .get_dcb_info = ixgbe_dev_get_dcb_info,
490 * dev_ops for virtual function, bare necessities for basic vf
491 * operation have been implemented
493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
494 .dev_configure = ixgbevf_dev_configure,
495 .dev_start = ixgbevf_dev_start,
496 .dev_stop = ixgbevf_dev_stop,
497 .link_update = ixgbe_dev_link_update,
498 .stats_get = ixgbevf_dev_stats_get,
499 .xstats_get = ixgbevf_dev_xstats_get,
500 .stats_reset = ixgbevf_dev_stats_reset,
501 .xstats_reset = ixgbevf_dev_stats_reset,
502 .dev_close = ixgbevf_dev_close,
503 .dev_infos_get = ixgbevf_dev_info_get,
504 .mtu_set = ixgbevf_dev_set_mtu,
505 .vlan_filter_set = ixgbevf_vlan_filter_set,
506 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
507 .vlan_offload_set = ixgbevf_vlan_offload_set,
508 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
509 .rx_queue_release = ixgbe_dev_rx_queue_release,
510 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
511 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
512 .tx_queue_release = ixgbe_dev_tx_queue_release,
513 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
514 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
515 .mac_addr_add = ixgbevf_add_mac_addr,
516 .mac_addr_remove = ixgbevf_remove_mac_addr,
517 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
518 .rxq_info_get = ixgbe_rxq_info_get,
519 .txq_info_get = ixgbe_txq_info_get,
520 .mac_addr_set = ixgbevf_set_default_mac_addr,
521 .get_reg_length = ixgbevf_get_reg_length,
522 .get_reg = ixgbevf_get_regs,
523 .reta_update = ixgbe_dev_rss_reta_update,
524 .reta_query = ixgbe_dev_rss_reta_query,
525 .rss_hash_update = ixgbe_dev_rss_hash_update,
526 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_ixgbe_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
536 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
537 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
538 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
539 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
540 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
541 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
542 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
543 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
544 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
545 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
546 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
547 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
548 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
549 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
550 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
552 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
554 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
555 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
556 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
557 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
558 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
559 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
560 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
561 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
562 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
563 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
564 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
565 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
566 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
567 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
568 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
569 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
570 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
572 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
574 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
575 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
576 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
577 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
579 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
581 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
583 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
585 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
587 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
589 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
592 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
593 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
594 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
596 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
597 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
598 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
599 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
600 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
602 {"rx_fcoe_no_direct_data_placement_ext_buff",
603 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
605 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
607 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
609 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
617 sizeof(rte_ixgbe_stats_strings[0]))
619 /* Per-queue statistics */
620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
627 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
631 sizeof(rte_ixgbevf_stats_strings[0]))
634 * Atomically reads the link status information from global
635 * structure rte_eth_dev.
638 * - Pointer to the structure rte_eth_dev to read from.
639 * - Pointer to the buffer to be saved with the link status.
642 * - On success, zero.
643 * - On failure, negative value.
646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = link;
650 struct rte_eth_link *src = &(dev->data->dev_link);
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
660 * Atomically writes the link status information into global
661 * structure rte_eth_dev.
664 * - Pointer to the structure rte_eth_dev to read from.
665 * - Pointer to the buffer to be saved with the link status.
668 * - On success, zero.
669 * - On failure, negative value.
672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
686 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
689 ixgbe_is_sfp(struct ixgbe_hw *hw)
691 switch (hw->phy.type) {
692 case ixgbe_phy_sfp_avago:
693 case ixgbe_phy_sfp_ftl:
694 case ixgbe_phy_sfp_intel:
695 case ixgbe_phy_sfp_unknown:
696 case ixgbe_phy_sfp_passive_tyco:
697 case ixgbe_phy_sfp_passive_unknown:
704 static inline int32_t
705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
710 status = ixgbe_reset_hw(hw);
712 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
713 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
714 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
715 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
716 IXGBE_WRITE_FLUSH(hw);
722 ixgbe_enable_intr(struct rte_eth_dev *dev)
724 struct ixgbe_interrupt *intr =
725 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
726 struct ixgbe_hw *hw =
727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
729 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
730 IXGBE_WRITE_FLUSH(hw);
734 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
737 ixgbe_disable_intr(struct ixgbe_hw *hw)
739 PMD_INIT_FUNC_TRACE();
741 if (hw->mac.type == ixgbe_mac_82598EB) {
742 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
744 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
745 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
746 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
748 IXGBE_WRITE_FLUSH(hw);
752 * This function resets queue statistics mapping registers.
753 * From Niantic datasheet, Initialization of Statistics section:
754 * "...if software requires the queue counters, the RQSMR and TQSM registers
755 * must be re-programmed following a device reset.
758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
762 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
763 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
764 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
780 struct ixgbe_stat_mapping_registers *stat_mappings =
781 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
782 uint32_t qsmr_mask = 0;
783 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
787 if ((hw->mac.type != ixgbe_mac_82599EB) &&
788 (hw->mac.type != ixgbe_mac_X540) &&
789 (hw->mac.type != ixgbe_mac_X550) &&
790 (hw->mac.type != ixgbe_mac_X550EM_x))
793 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
794 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
797 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
798 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
799 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
802 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
804 /* Now clear any previous stat_idx set */
805 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
807 stat_mappings->tqsm[n] &= ~clearing_mask;
809 stat_mappings->rqsmr[n] &= ~clearing_mask;
811 q_map = (uint32_t)stat_idx;
812 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
813 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
815 stat_mappings->tqsm[n] |= qsmr_mask;
817 stat_mappings->rqsmr[n] |= qsmr_mask;
819 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
820 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
822 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
823 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
825 /* Now write the mapping in the appropriate register */
827 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
828 stat_mappings->rqsmr[n], n);
829 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
832 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
833 stat_mappings->tqsm[n], n);
834 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
842 struct ixgbe_stat_mapping_registers *stat_mappings =
843 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 /* write whatever was in stat mapping table to the NIC */
848 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
850 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
853 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
861 struct ixgbe_dcb_tc_config *tc;
862 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
864 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
865 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
866 for (i = 0; i < dcb_max_tc; i++) {
867 tc = &dcb_config->tc_config[i];
868 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
869 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
870 (uint8_t)(100/dcb_max_tc + (i & 1));
871 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
872 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
873 (uint8_t)(100/dcb_max_tc + (i & 1));
874 tc->pfc = ixgbe_dcb_pfc_disabled;
877 /* Initialize default user to priority mapping, UPx->TC0 */
878 tc = &dcb_config->tc_config[0];
879 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
880 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
881 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
882 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
883 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
885 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
886 dcb_config->pfc_mode_enable = false;
887 dcb_config->vt_mode = true;
888 dcb_config->round_robin_enable = false;
889 /* support all DCB capabilities in 82599 */
890 dcb_config->support.capabilities = 0xFF;
892 /*we only support 4 Tcs for X540, X550 */
893 if (hw->mac.type == ixgbe_mac_X540 ||
894 hw->mac.type == ixgbe_mac_X550 ||
895 hw->mac.type == ixgbe_mac_X550EM_x) {
896 dcb_config->num_tcs.pg_tcs = 4;
897 dcb_config->num_tcs.pfc_tcs = 4;
902 * Ensure that all locks are released before first NVM or PHY access
905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
910 * Phy lock should not fail in this early stage. If this is the case,
911 * it is due to an improper exit of the application.
912 * So force the release of the faulty lock. Release of common lock
913 * is done automatically by swfw_sync function.
915 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
916 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
917 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
919 ixgbe_release_swfw_semaphore(hw, mask);
922 * These ones are more tricky since they are common to all ports; but
923 * swfw_sync retries last long enough (1s) to be almost sure that if
924 * lock can not be taken it is due to an improper lock of the
927 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
928 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
929 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
931 ixgbe_release_swfw_semaphore(hw, mask);
935 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
936 * It returns 0 on success.
939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
941 struct rte_pci_device *pci_dev;
942 struct ixgbe_hw *hw =
943 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
944 struct ixgbe_vfta * shadow_vfta =
945 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
946 struct ixgbe_hwstrip *hwstrip =
947 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
948 struct ixgbe_dcb_config *dcb_config =
949 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
950 struct ixgbe_filter_info *filter_info =
951 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
956 PMD_INIT_FUNC_TRACE();
958 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
959 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
960 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
963 * For secondary processes, we don't initialise any further as primary
964 * has already done this work. Only check we don't need a different
965 * RX and TX function.
967 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
968 struct ixgbe_tx_queue *txq;
969 /* TX queue function in primary, set by last queue initialized
970 * Tx queue may not initialized by primary process */
971 if (eth_dev->data->tx_queues) {
972 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
973 ixgbe_set_tx_function(eth_dev, txq);
975 /* Use default TX function if we get here */
976 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
977 "Using default TX function.");
980 ixgbe_set_rx_function(eth_dev);
984 pci_dev = eth_dev->pci_dev;
986 rte_eth_copy_pci_info(eth_dev, pci_dev);
988 /* Vendor and Device ID need to be set before init of shared code */
989 hw->device_id = pci_dev->id.device_id;
990 hw->vendor_id = pci_dev->id.vendor_id;
991 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
992 hw->allow_unsupported_sfp = 1;
994 /* Initialize the shared code (base driver) */
995 #ifdef RTE_NIC_BYPASS
996 diag = ixgbe_bypass_init_shared_code(hw);
998 diag = ixgbe_init_shared_code(hw);
999 #endif /* RTE_NIC_BYPASS */
1001 if (diag != IXGBE_SUCCESS) {
1002 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1006 /* pick up the PCI bus settings for reporting later */
1007 ixgbe_get_bus_info(hw);
1009 /* Unlock any pending hardware semaphore */
1010 ixgbe_swfw_lock_reset(hw);
1012 /* Initialize DCB configuration*/
1013 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1014 ixgbe_dcb_init(hw,dcb_config);
1015 /* Get Hardware Flow Control setting */
1016 hw->fc.requested_mode = ixgbe_fc_full;
1017 hw->fc.current_mode = ixgbe_fc_full;
1018 hw->fc.pause_time = IXGBE_FC_PAUSE;
1019 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1020 hw->fc.low_water[i] = IXGBE_FC_LO;
1021 hw->fc.high_water[i] = IXGBE_FC_HI;
1023 hw->fc.send_xon = 1;
1025 /* Make sure we have a good EEPROM before we read from it */
1026 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1027 if (diag != IXGBE_SUCCESS) {
1028 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1032 #ifdef RTE_NIC_BYPASS
1033 diag = ixgbe_bypass_init_hw(hw);
1035 diag = ixgbe_init_hw(hw);
1036 #endif /* RTE_NIC_BYPASS */
1039 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1040 * is called too soon after the kernel driver unbinding/binding occurs.
1041 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1042 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1043 * also called. See ixgbe_identify_phy_82599(). The reason for the
1044 * failure is not known, and only occuts when virtualisation features
1045 * are disabled in the bios. A delay of 100ms was found to be enough by
1046 * trial-and-error, and is doubled to be safe.
1048 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1050 diag = ixgbe_init_hw(hw);
1053 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1054 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1055 "LOM. Please be aware there may be issues associated "
1056 "with your hardware.");
1057 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1058 "please contact your Intel or hardware representative "
1059 "who provided you with this hardware.");
1060 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1061 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1063 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1067 /* Reset the hw statistics */
1068 ixgbe_dev_stats_reset(eth_dev);
1070 /* disable interrupt */
1071 ixgbe_disable_intr(hw);
1073 /* reset mappings for queue statistics hw counters*/
1074 ixgbe_reset_qstat_mappings(hw);
1076 /* Allocate memory for storing MAC addresses */
1077 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1078 hw->mac.num_rar_entries, 0);
1079 if (eth_dev->data->mac_addrs == NULL) {
1081 "Failed to allocate %u bytes needed to store "
1083 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1086 /* Copy the permanent MAC address */
1087 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1088 ð_dev->data->mac_addrs[0]);
1090 /* Allocate memory for storing hash filter MAC addresses */
1091 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1092 IXGBE_VMDQ_NUM_UC_MAC, 0);
1093 if (eth_dev->data->hash_mac_addrs == NULL) {
1095 "Failed to allocate %d bytes needed to store MAC addresses",
1096 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1100 /* initialize the vfta */
1101 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1103 /* initialize the hw strip bitmap*/
1104 memset(hwstrip, 0, sizeof(*hwstrip));
1106 /* initialize PF if max_vfs not zero */
1107 ixgbe_pf_host_init(eth_dev);
1109 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1110 /* let hardware know driver is loaded */
1111 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1112 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1113 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1114 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1115 IXGBE_WRITE_FLUSH(hw);
1117 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1118 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1119 (int) hw->mac.type, (int) hw->phy.type,
1120 (int) hw->phy.sfp_type);
1122 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1123 (int) hw->mac.type, (int) hw->phy.type);
1125 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1126 eth_dev->data->port_id, pci_dev->id.vendor_id,
1127 pci_dev->id.device_id);
1129 rte_intr_callback_register(&pci_dev->intr_handle,
1130 ixgbe_dev_interrupt_handler,
1133 /* enable uio/vfio intr/eventfd mapping */
1134 rte_intr_enable(&pci_dev->intr_handle);
1136 /* enable support intr */
1137 ixgbe_enable_intr(eth_dev);
1139 /* initialize 5tuple filter list */
1140 TAILQ_INIT(&filter_info->fivetuple_list);
1141 memset(filter_info->fivetuple_mask, 0,
1142 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1148 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1150 struct rte_pci_device *pci_dev;
1151 struct ixgbe_hw *hw;
1153 PMD_INIT_FUNC_TRACE();
1155 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1158 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1159 pci_dev = eth_dev->pci_dev;
1161 if (hw->adapter_stopped == 0)
1162 ixgbe_dev_close(eth_dev);
1164 eth_dev->dev_ops = NULL;
1165 eth_dev->rx_pkt_burst = NULL;
1166 eth_dev->tx_pkt_burst = NULL;
1168 /* Unlock any pending hardware semaphore */
1169 ixgbe_swfw_lock_reset(hw);
1171 /* disable uio intr before callback unregister */
1172 rte_intr_disable(&(pci_dev->intr_handle));
1173 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1174 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1176 /* uninitialize PF if max_vfs not zero */
1177 ixgbe_pf_host_uninit(eth_dev);
1179 rte_free(eth_dev->data->mac_addrs);
1180 eth_dev->data->mac_addrs = NULL;
1182 rte_free(eth_dev->data->hash_mac_addrs);
1183 eth_dev->data->hash_mac_addrs = NULL;
1189 * Negotiate mailbox API version with the PF.
1190 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1191 * Then we try to negotiate starting with the most recent one.
1192 * If all negotiation attempts fail, then we will proceed with
1193 * the default one (ixgbe_mbox_api_10).
1196 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1200 /* start with highest supported, proceed down */
1201 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1207 i != RTE_DIM(sup_ver) &&
1208 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1214 generate_random_mac_addr(struct ether_addr *mac_addr)
1218 /* Set Organizationally Unique Identifier (OUI) prefix. */
1219 mac_addr->addr_bytes[0] = 0x00;
1220 mac_addr->addr_bytes[1] = 0x09;
1221 mac_addr->addr_bytes[2] = 0xC0;
1222 /* Force indication of locally assigned MAC address. */
1223 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1224 /* Generate the last 3 bytes of the MAC address with a random number. */
1225 random = rte_rand();
1226 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1230 * Virtual Function device init
1233 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1237 struct rte_pci_device *pci_dev;
1238 struct ixgbe_hw *hw =
1239 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1240 struct ixgbe_vfta * shadow_vfta =
1241 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1242 struct ixgbe_hwstrip *hwstrip =
1243 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1244 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1246 PMD_INIT_FUNC_TRACE();
1248 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1249 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1250 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1252 /* for secondary processes, we don't initialise any further as primary
1253 * has already done this work. Only check we don't need a different
1255 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1256 if (eth_dev->data->scattered_rx)
1257 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1261 pci_dev = eth_dev->pci_dev;
1263 rte_eth_copy_pci_info(eth_dev, pci_dev);
1265 hw->device_id = pci_dev->id.device_id;
1266 hw->vendor_id = pci_dev->id.vendor_id;
1267 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1269 /* initialize the vfta */
1270 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1272 /* initialize the hw strip bitmap*/
1273 memset(hwstrip, 0, sizeof(*hwstrip));
1275 /* Initialize the shared code (base driver) */
1276 diag = ixgbe_init_shared_code(hw);
1277 if (diag != IXGBE_SUCCESS) {
1278 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1282 /* init_mailbox_params */
1283 hw->mbx.ops.init_params(hw);
1285 /* Reset the hw statistics */
1286 ixgbevf_dev_stats_reset(eth_dev);
1288 /* Disable the interrupts for VF */
1289 ixgbevf_intr_disable(hw);
1291 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1292 diag = hw->mac.ops.reset_hw(hw);
1295 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1296 * the underlying PF driver has not assigned a MAC address to the VF.
1297 * In this case, assign a random MAC address.
1299 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1300 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1304 /* negotiate mailbox API version to use with the PF. */
1305 ixgbevf_negotiate_api(hw);
1307 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1308 ixgbevf_get_queues(hw, &tcs, &tc);
1310 /* Allocate memory for storing MAC addresses */
1311 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1312 hw->mac.num_rar_entries, 0);
1313 if (eth_dev->data->mac_addrs == NULL) {
1315 "Failed to allocate %u bytes needed to store "
1317 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1321 /* Generate a random MAC address, if none was assigned by PF. */
1322 if (is_zero_ether_addr(perm_addr)) {
1323 generate_random_mac_addr(perm_addr);
1324 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1326 rte_free(eth_dev->data->mac_addrs);
1327 eth_dev->data->mac_addrs = NULL;
1330 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1331 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1332 "%02x:%02x:%02x:%02x:%02x:%02x",
1333 perm_addr->addr_bytes[0],
1334 perm_addr->addr_bytes[1],
1335 perm_addr->addr_bytes[2],
1336 perm_addr->addr_bytes[3],
1337 perm_addr->addr_bytes[4],
1338 perm_addr->addr_bytes[5]);
1341 /* Copy the permanent MAC address */
1342 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1344 /* reset the hardware with the new settings */
1345 diag = hw->mac.ops.start_hw(hw);
1351 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1355 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1356 eth_dev->data->port_id, pci_dev->id.vendor_id,
1357 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1362 /* Virtual Function device uninit */
1365 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1367 struct ixgbe_hw *hw;
1370 PMD_INIT_FUNC_TRACE();
1372 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1375 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1377 if (hw->adapter_stopped == 0)
1378 ixgbevf_dev_close(eth_dev);
1380 eth_dev->dev_ops = NULL;
1381 eth_dev->rx_pkt_burst = NULL;
1382 eth_dev->tx_pkt_burst = NULL;
1384 /* Disable the interrupts for VF */
1385 ixgbevf_intr_disable(hw);
1387 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1388 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1389 eth_dev->data->rx_queues[i] = NULL;
1391 eth_dev->data->nb_rx_queues = 0;
1393 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1394 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1395 eth_dev->data->tx_queues[i] = NULL;
1397 eth_dev->data->nb_tx_queues = 0;
1399 rte_free(eth_dev->data->mac_addrs);
1400 eth_dev->data->mac_addrs = NULL;
1405 static struct eth_driver rte_ixgbe_pmd = {
1407 .name = "rte_ixgbe_pmd",
1408 .id_table = pci_id_ixgbe_map,
1409 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1410 RTE_PCI_DRV_DETACHABLE,
1412 .eth_dev_init = eth_ixgbe_dev_init,
1413 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1414 .dev_private_size = sizeof(struct ixgbe_adapter),
1418 * virtual function driver struct
1420 static struct eth_driver rte_ixgbevf_pmd = {
1422 .name = "rte_ixgbevf_pmd",
1423 .id_table = pci_id_ixgbevf_map,
1424 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1426 .eth_dev_init = eth_ixgbevf_dev_init,
1427 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1428 .dev_private_size = sizeof(struct ixgbe_adapter),
1432 * Driver initialization routine.
1433 * Invoked once at EAL init time.
1434 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1437 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1439 PMD_INIT_FUNC_TRACE();
1441 rte_eth_driver_register(&rte_ixgbe_pmd);
1446 * VF Driver initialization routine.
1447 * Invoked one at EAL init time.
1448 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1451 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1453 PMD_INIT_FUNC_TRACE();
1455 rte_eth_driver_register(&rte_ixgbevf_pmd);
1460 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1462 struct ixgbe_hw *hw =
1463 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464 struct ixgbe_vfta * shadow_vfta =
1465 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1470 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1471 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1472 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1477 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1479 /* update local VFTA copy */
1480 shadow_vfta->vfta[vid_idx] = vfta;
1486 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1489 ixgbe_vlan_hw_strip_enable(dev, queue);
1491 ixgbe_vlan_hw_strip_disable(dev, queue);
1495 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1497 struct ixgbe_hw *hw =
1498 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500 /* Only the high 16-bits is valid */
1501 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1505 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1507 struct ixgbe_hw *hw =
1508 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511 PMD_INIT_FUNC_TRACE();
1513 /* Filter Table Disable */
1514 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1515 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1517 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1521 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1523 struct ixgbe_hw *hw =
1524 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525 struct ixgbe_vfta * shadow_vfta =
1526 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1530 PMD_INIT_FUNC_TRACE();
1532 /* Filter Table Enable */
1533 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1534 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1535 vlnctrl |= IXGBE_VLNCTRL_VFE;
1537 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1539 /* write whatever is in local vfta copy */
1540 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1541 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1545 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1547 struct ixgbe_hwstrip *hwstrip =
1548 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1550 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1554 IXGBE_SET_HWSTRIP(hwstrip, queue);
1556 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1560 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1562 struct ixgbe_hw *hw =
1563 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 PMD_INIT_FUNC_TRACE();
1568 if (hw->mac.type == ixgbe_mac_82598EB) {
1569 /* No queue level support */
1570 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1574 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1575 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1576 ctrl &= ~IXGBE_RXDCTL_VME;
1577 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1579 /* record those setting for HW strip per queue */
1580 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1584 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1586 struct ixgbe_hw *hw =
1587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590 PMD_INIT_FUNC_TRACE();
1592 if (hw->mac.type == ixgbe_mac_82598EB) {
1593 /* No queue level supported */
1594 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1598 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1599 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1600 ctrl |= IXGBE_RXDCTL_VME;
1601 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1603 /* record those setting for HW strip per queue */
1604 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1608 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1610 struct ixgbe_hw *hw =
1611 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615 PMD_INIT_FUNC_TRACE();
1617 if (hw->mac.type == ixgbe_mac_82598EB) {
1618 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1619 ctrl &= ~IXGBE_VLNCTRL_VME;
1620 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1623 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1624 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1625 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1626 ctrl &= ~IXGBE_RXDCTL_VME;
1627 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1629 /* record those setting for HW strip per queue */
1630 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1636 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1638 struct ixgbe_hw *hw =
1639 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643 PMD_INIT_FUNC_TRACE();
1645 if (hw->mac.type == ixgbe_mac_82598EB) {
1646 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1647 ctrl |= IXGBE_VLNCTRL_VME;
1648 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1651 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1652 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1653 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1654 ctrl |= IXGBE_RXDCTL_VME;
1655 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1657 /* record those setting for HW strip per queue */
1658 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1664 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1666 struct ixgbe_hw *hw =
1667 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670 PMD_INIT_FUNC_TRACE();
1672 /* DMATXCTRL: Geric Double VLAN Disable */
1673 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1674 ctrl &= ~IXGBE_DMATXCTL_GDV;
1675 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1677 /* CTRL_EXT: Global Double VLAN Disable */
1678 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1679 ctrl &= ~IXGBE_EXTENDED_VLAN;
1680 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1685 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1687 struct ixgbe_hw *hw =
1688 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 PMD_INIT_FUNC_TRACE();
1693 /* DMATXCTRL: Geric Double VLAN Enable */
1694 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1695 ctrl |= IXGBE_DMATXCTL_GDV;
1696 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1698 /* CTRL_EXT: Global Double VLAN Enable */
1699 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1700 ctrl |= IXGBE_EXTENDED_VLAN;
1701 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1704 * VET EXT field in the EXVET register = 0x8100 by default
1705 * So no need to change. Same to VT field of DMATXCTL register
1710 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1712 if(mask & ETH_VLAN_STRIP_MASK){
1713 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1714 ixgbe_vlan_hw_strip_enable_all(dev);
1716 ixgbe_vlan_hw_strip_disable_all(dev);
1719 if(mask & ETH_VLAN_FILTER_MASK){
1720 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1721 ixgbe_vlan_hw_filter_enable(dev);
1723 ixgbe_vlan_hw_filter_disable(dev);
1726 if(mask & ETH_VLAN_EXTEND_MASK){
1727 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1728 ixgbe_vlan_hw_extend_enable(dev);
1730 ixgbe_vlan_hw_extend_disable(dev);
1735 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1737 struct ixgbe_hw *hw =
1738 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1740 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1741 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1742 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1746 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1751 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1754 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1760 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1761 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1767 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1769 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1770 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1771 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1773 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1774 /* check multi-queue mode */
1775 switch (dev_conf->rxmode.mq_mode) {
1776 case ETH_MQ_RX_VMDQ_DCB:
1777 case ETH_MQ_RX_VMDQ_DCB_RSS:
1778 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1779 PMD_INIT_LOG(ERR, "SRIOV active,"
1780 " unsupported mq_mode rx %d.",
1781 dev_conf->rxmode.mq_mode);
1784 case ETH_MQ_RX_VMDQ_RSS:
1785 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1786 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1787 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1788 PMD_INIT_LOG(ERR, "SRIOV is active,"
1789 " invalid queue number"
1790 " for VMDQ RSS, allowed"
1791 " value are 1, 2 or 4.");
1795 case ETH_MQ_RX_VMDQ_ONLY:
1796 case ETH_MQ_RX_NONE:
1797 /* if nothing mq mode configure, use default scheme */
1798 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1799 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1800 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1802 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1803 /* SRIOV only works in VMDq enable mode */
1804 PMD_INIT_LOG(ERR, "SRIOV is active,"
1805 " wrong mq_mode rx %d.",
1806 dev_conf->rxmode.mq_mode);
1810 switch (dev_conf->txmode.mq_mode) {
1811 case ETH_MQ_TX_VMDQ_DCB:
1812 /* DCB VMDQ in SRIOV mode, not implement yet */
1813 PMD_INIT_LOG(ERR, "SRIOV is active,"
1814 " unsupported VMDQ mq_mode tx %d.",
1815 dev_conf->txmode.mq_mode);
1817 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1818 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1822 /* check valid queue number */
1823 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1824 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1825 PMD_INIT_LOG(ERR, "SRIOV is active,"
1826 " queue number must less equal to %d.",
1827 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1831 /* check configuration for vmdb+dcb mode */
1832 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1833 const struct rte_eth_vmdq_dcb_conf *conf;
1835 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1836 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1837 IXGBE_VMDQ_DCB_NB_QUEUES);
1840 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1841 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1842 conf->nb_queue_pools == ETH_32_POOLS)) {
1843 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1844 " nb_queue_pools must be %d or %d.",
1845 ETH_16_POOLS, ETH_32_POOLS);
1849 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1850 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1852 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1853 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1854 IXGBE_VMDQ_DCB_NB_QUEUES);
1857 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1858 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1859 conf->nb_queue_pools == ETH_32_POOLS)) {
1860 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1861 " nb_queue_pools != %d and"
1862 " nb_queue_pools != %d.",
1863 ETH_16_POOLS, ETH_32_POOLS);
1868 /* For DCB mode check our configuration before we go further */
1869 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1870 const struct rte_eth_dcb_rx_conf *conf;
1872 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1873 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1874 IXGBE_DCB_NB_QUEUES);
1877 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1878 if (!(conf->nb_tcs == ETH_4_TCS ||
1879 conf->nb_tcs == ETH_8_TCS)) {
1880 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1881 " and nb_tcs != %d.",
1882 ETH_4_TCS, ETH_8_TCS);
1887 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1888 const struct rte_eth_dcb_tx_conf *conf;
1890 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1891 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1892 IXGBE_DCB_NB_QUEUES);
1895 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1896 if (!(conf->nb_tcs == ETH_4_TCS ||
1897 conf->nb_tcs == ETH_8_TCS)) {
1898 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1899 " and nb_tcs != %d.",
1900 ETH_4_TCS, ETH_8_TCS);
1909 ixgbe_dev_configure(struct rte_eth_dev *dev)
1911 struct ixgbe_interrupt *intr =
1912 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1913 struct ixgbe_adapter *adapter =
1914 (struct ixgbe_adapter *)dev->data->dev_private;
1917 PMD_INIT_FUNC_TRACE();
1918 /* multipe queue mode checking */
1919 ret = ixgbe_check_mq_mode(dev);
1921 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1926 /* set flag to update link status after init */
1927 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1930 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1931 * allocation or vector Rx preconditions we will reset it.
1933 adapter->rx_bulk_alloc_allowed = true;
1934 adapter->rx_vec_allowed = true;
1940 * Configure device link speed and setup link.
1941 * It returns 0 on success.
1944 ixgbe_dev_start(struct rte_eth_dev *dev)
1946 struct ixgbe_hw *hw =
1947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948 struct ixgbe_vf_info *vfinfo =
1949 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1950 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1951 uint32_t intr_vector = 0;
1952 int err, link_up = 0, negotiate = 0;
1958 PMD_INIT_FUNC_TRACE();
1960 /* IXGBE devices don't support half duplex */
1961 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1962 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1963 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1964 dev->data->dev_conf.link_duplex,
1965 dev->data->port_id);
1970 hw->adapter_stopped = 0;
1971 ixgbe_stop_adapter(hw);
1973 /* reinitialize adapter
1974 * this calls reset and start */
1975 status = ixgbe_pf_reset_hw(hw);
1978 hw->mac.ops.start_hw(hw);
1979 hw->mac.get_link_status = true;
1981 /* configure PF module if SRIOV enabled */
1982 ixgbe_pf_host_configure(dev);
1984 /* check and configure queue intr-vector mapping */
1985 if ((rte_intr_cap_multiple(intr_handle) ||
1986 !RTE_ETH_DEV_SRIOV(dev).active) &&
1987 dev->data->dev_conf.intr_conf.rxq != 0) {
1988 intr_vector = dev->data->nb_rx_queues;
1989 if (rte_intr_efd_enable(intr_handle, intr_vector))
1993 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1994 intr_handle->intr_vec =
1995 rte_zmalloc("intr_vec",
1996 dev->data->nb_rx_queues * sizeof(int), 0);
1997 if (intr_handle->intr_vec == NULL) {
1998 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1999 " intr_vec\n", dev->data->nb_rx_queues);
2004 /* confiugre msix for sleep until rx interrupt */
2005 ixgbe_configure_msix(dev);
2007 /* initialize transmission unit */
2008 ixgbe_dev_tx_init(dev);
2010 /* This can fail when allocating mbufs for descriptor rings */
2011 err = ixgbe_dev_rx_init(dev);
2013 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2017 err = ixgbe_dev_rxtx_start(dev);
2019 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2023 /* Skip link setup if loopback mode is enabled for 82599. */
2024 if (hw->mac.type == ixgbe_mac_82599EB &&
2025 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2026 goto skip_link_setup;
2028 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2029 err = hw->mac.ops.setup_sfp(hw);
2034 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2035 /* Turn on the copper */
2036 ixgbe_set_phy_power(hw, true);
2038 /* Turn on the laser */
2039 ixgbe_enable_tx_laser(hw);
2042 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2045 dev->data->dev_link.link_status = link_up;
2047 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2051 switch(dev->data->dev_conf.link_speed) {
2052 case ETH_LINK_SPEED_AUTONEG:
2053 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2054 IXGBE_LINK_SPEED_82599_AUTONEG :
2055 IXGBE_LINK_SPEED_82598_AUTONEG;
2057 case ETH_LINK_SPEED_100:
2059 * Invalid for 82598 but error will be detected by
2060 * ixgbe_setup_link()
2062 speed = IXGBE_LINK_SPEED_100_FULL;
2064 case ETH_LINK_SPEED_1000:
2065 speed = IXGBE_LINK_SPEED_1GB_FULL;
2067 case ETH_LINK_SPEED_10000:
2068 speed = IXGBE_LINK_SPEED_10GB_FULL;
2071 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2072 dev->data->dev_conf.link_speed,
2073 dev->data->port_id);
2077 err = ixgbe_setup_link(hw, speed, link_up);
2083 if (rte_intr_allow_others(intr_handle)) {
2084 /* check if lsc interrupt is enabled */
2085 if (dev->data->dev_conf.intr_conf.lsc != 0)
2086 ixgbe_dev_lsc_interrupt_setup(dev);
2088 rte_intr_callback_unregister(intr_handle,
2089 ixgbe_dev_interrupt_handler,
2091 if (dev->data->dev_conf.intr_conf.lsc != 0)
2092 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2093 " no intr multiplex\n");
2096 /* check if rxq interrupt is enabled */
2097 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2098 rte_intr_dp_is_en(intr_handle))
2099 ixgbe_dev_rxq_interrupt_setup(dev);
2101 /* enable uio/vfio intr/eventfd mapping */
2102 rte_intr_enable(intr_handle);
2104 /* resume enabled intr since hw reset */
2105 ixgbe_enable_intr(dev);
2107 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2108 ETH_VLAN_EXTEND_MASK;
2109 ixgbe_vlan_offload_set(dev, mask);
2111 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2112 /* Enable vlan filtering for VMDq */
2113 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2116 /* Configure DCB hw */
2117 ixgbe_configure_dcb(dev);
2119 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2120 err = ixgbe_fdir_configure(dev);
2125 /* Restore vf rate limit */
2126 if (vfinfo != NULL) {
2127 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2128 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2129 if (vfinfo[vf].tx_rate[idx] != 0)
2130 ixgbe_set_vf_rate_limit(dev, vf,
2131 vfinfo[vf].tx_rate[idx],
2135 ixgbe_restore_statistics_mapping(dev);
2140 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2141 ixgbe_dev_clear_queues(dev);
2146 * Stop device: disable rx and tx functions to allow for reconfiguring.
2149 ixgbe_dev_stop(struct rte_eth_dev *dev)
2151 struct rte_eth_link link;
2152 struct ixgbe_hw *hw =
2153 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154 struct ixgbe_vf_info *vfinfo =
2155 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2156 struct ixgbe_filter_info *filter_info =
2157 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2158 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2159 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2162 PMD_INIT_FUNC_TRACE();
2164 /* disable interrupts */
2165 ixgbe_disable_intr(hw);
2167 /* disable intr eventfd mapping */
2168 rte_intr_disable(intr_handle);
2171 ixgbe_pf_reset_hw(hw);
2172 hw->adapter_stopped = 0;
2175 ixgbe_stop_adapter(hw);
2177 for (vf = 0; vfinfo != NULL &&
2178 vf < dev->pci_dev->max_vfs; vf++)
2179 vfinfo[vf].clear_to_send = false;
2181 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2182 /* Turn off the copper */
2183 ixgbe_set_phy_power(hw, false);
2185 /* Turn off the laser */
2186 ixgbe_disable_tx_laser(hw);
2189 ixgbe_dev_clear_queues(dev);
2191 /* Clear stored conf */
2192 dev->data->scattered_rx = 0;
2195 /* Clear recorded link status */
2196 memset(&link, 0, sizeof(link));
2197 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2199 /* Remove all ntuple filters of the device */
2200 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2201 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2202 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2203 TAILQ_REMOVE(&filter_info->fivetuple_list,
2207 memset(filter_info->fivetuple_mask, 0,
2208 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2210 if (!rte_intr_allow_others(intr_handle))
2211 /* resume to the default handler */
2212 rte_intr_callback_register(intr_handle,
2213 ixgbe_dev_interrupt_handler,
2216 /* Clean datapath event and queue/vec mapping */
2217 rte_intr_efd_disable(intr_handle);
2218 if (intr_handle->intr_vec != NULL) {
2219 rte_free(intr_handle->intr_vec);
2220 intr_handle->intr_vec = NULL;
2225 * Set device link up: enable tx.
2228 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2230 struct ixgbe_hw *hw =
2231 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232 if (hw->mac.type == ixgbe_mac_82599EB) {
2233 #ifdef RTE_NIC_BYPASS
2234 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2235 /* Not suported in bypass mode */
2236 PMD_INIT_LOG(ERR, "Set link up is not supported "
2237 "by device id 0x%x", hw->device_id);
2243 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2244 /* Turn on the copper */
2245 ixgbe_set_phy_power(hw, true);
2247 /* Turn on the laser */
2248 ixgbe_enable_tx_laser(hw);
2255 * Set device link down: disable tx.
2258 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2260 struct ixgbe_hw *hw =
2261 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262 if (hw->mac.type == ixgbe_mac_82599EB) {
2263 #ifdef RTE_NIC_BYPASS
2264 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2265 /* Not suported in bypass mode */
2266 PMD_INIT_LOG(ERR, "Set link down is not supported "
2267 "by device id 0x%x", hw->device_id);
2273 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2274 /* Turn off the copper */
2275 ixgbe_set_phy_power(hw, false);
2277 /* Turn off the laser */
2278 ixgbe_disable_tx_laser(hw);
2285 * Reest and stop device.
2288 ixgbe_dev_close(struct rte_eth_dev *dev)
2290 struct ixgbe_hw *hw =
2291 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293 PMD_INIT_FUNC_TRACE();
2295 ixgbe_pf_reset_hw(hw);
2297 ixgbe_dev_stop(dev);
2298 hw->adapter_stopped = 1;
2300 ixgbe_dev_free_queues(dev);
2302 ixgbe_disable_pcie_master(hw);
2304 /* reprogram the RAR[0] in case user changed it. */
2305 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2309 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2310 *hw_stats, uint64_t *total_missed_rx,
2311 uint64_t *total_qbrc, uint64_t *total_qprc,
2312 uint64_t *total_qprdc)
2314 uint32_t bprc, lxon, lxoff, total;
2317 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2318 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2319 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2320 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2322 for (i = 0; i < 8; i++) {
2324 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2325 /* global total per queue */
2326 hw_stats->mpc[i] += mp;
2327 /* Running comprehensive total for stats display */
2328 *total_missed_rx += hw_stats->mpc[i];
2329 if (hw->mac.type == ixgbe_mac_82598EB) {
2330 hw_stats->rnbc[i] +=
2331 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2332 hw_stats->pxonrxc[i] +=
2333 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2334 hw_stats->pxoffrxc[i] +=
2335 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2337 hw_stats->pxonrxc[i] +=
2338 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2339 hw_stats->pxoffrxc[i] +=
2340 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2341 hw_stats->pxon2offc[i] +=
2342 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2344 hw_stats->pxontxc[i] +=
2345 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2346 hw_stats->pxofftxc[i] +=
2347 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2349 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2350 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2351 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2352 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2353 hw_stats->qbrc[i] +=
2354 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2355 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2356 hw_stats->qbtc[i] +=
2357 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2358 *total_qprdc += hw_stats->qprdc[i] +=
2359 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2361 *total_qprc += hw_stats->qprc[i];
2362 *total_qbrc += hw_stats->qbrc[i];
2364 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2365 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2366 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2368 /* Note that gprc counts missed packets */
2369 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2371 if (hw->mac.type != ixgbe_mac_82598EB) {
2372 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2373 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2374 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2375 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2376 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2377 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2378 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2379 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2381 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2382 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2383 /* 82598 only has a counter in the high register */
2384 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2385 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2386 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2390 * Workaround: mprc hardware is incorrectly counting
2391 * broadcasts, so for now we subtract those.
2393 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2394 hw_stats->bprc += bprc;
2395 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2396 if (hw->mac.type == ixgbe_mac_82598EB)
2397 hw_stats->mprc -= bprc;
2399 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2400 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2401 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2402 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2403 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2404 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2406 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2407 hw_stats->lxontxc += lxon;
2408 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2409 hw_stats->lxofftxc += lxoff;
2410 total = lxon + lxoff;
2412 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2413 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2414 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2415 hw_stats->gptc -= total;
2416 hw_stats->mptc -= total;
2417 hw_stats->ptc64 -= total;
2418 hw_stats->gotc -= total * ETHER_MIN_LEN;
2420 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2421 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2422 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2423 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2424 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2425 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2426 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2427 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2428 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2429 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2430 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2431 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2432 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2433 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2434 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2435 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2436 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2437 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2438 /* Only read FCOE on 82599 */
2439 if (hw->mac.type != ixgbe_mac_82598EB) {
2440 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2441 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2442 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2443 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2444 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2447 /* Flow Director Stats registers */
2448 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2449 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2453 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2456 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2458 struct ixgbe_hw *hw =
2459 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460 struct ixgbe_hw_stats *hw_stats =
2461 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2462 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2465 total_missed_rx = 0;
2470 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2471 &total_qprc, &total_qprdc);
2476 /* Fill out the rte_eth_stats statistics structure */
2477 stats->ipackets = total_qprc;
2478 stats->ibytes = total_qbrc;
2479 stats->opackets = hw_stats->gptc;
2480 stats->obytes = hw_stats->gotc;
2482 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2483 stats->q_ipackets[i] = hw_stats->qprc[i];
2484 stats->q_opackets[i] = hw_stats->qptc[i];
2485 stats->q_ibytes[i] = hw_stats->qbrc[i];
2486 stats->q_obytes[i] = hw_stats->qbtc[i];
2487 stats->q_errors[i] = hw_stats->qprdc[i];
2491 stats->ierrors = hw_stats->crcerrs +
2509 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2511 struct ixgbe_hw_stats *stats =
2512 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2514 /* HW registers are cleared on read */
2515 ixgbe_dev_stats_get(dev, NULL);
2517 /* Reset software totals */
2518 memset(stats, 0, sizeof(*stats));
2522 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2525 struct ixgbe_hw *hw =
2526 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 struct ixgbe_hw_stats *hw_stats =
2528 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2529 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2530 unsigned i, count = IXGBE_NB_XSTATS;
2535 total_missed_rx = 0;
2540 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2541 &total_qprc, &total_qprdc);
2543 /* If this is a reset xstats is NULL, and we have cleared the
2544 * registers by reading them.
2549 /* Extended stats from ixgbe_hw_stats */
2551 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2552 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2553 rte_ixgbe_stats_strings[i].name);
2554 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2555 rte_ixgbe_stats_strings[i].offset);
2559 /* Per-Q stats, with 8 queues available */
2560 for (i = 0; i < 8; i++) {
2561 snprintf(xstats[count].name, sizeof(xstats[count].name),
2562 "rx_q%u_mbuf_allocation_errors", i);
2563 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2564 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2567 snprintf(xstats[count].name, sizeof(xstats[count].name),
2568 "rx_q%u_missed_packets", i);
2569 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2570 offsetof(struct ixgbe_hw_stats, mpc[i]));
2573 snprintf(xstats[count].name, sizeof(xstats[count].name),
2574 "rx_q%u_xon_priority_packets", i);
2575 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2576 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2579 snprintf(xstats[count].name, sizeof(xstats[count].name),
2580 "tx_q%u_xon_priority_packets", i);
2581 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2582 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2585 snprintf(xstats[count].name, sizeof(xstats[count].name),
2586 "rx_q%u_xoff_priority_packets", i);
2587 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2588 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2591 snprintf(xstats[count].name, sizeof(xstats[count].name),
2592 "tx_q%u_xoff_priority_packets", i);
2593 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2594 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2597 snprintf(xstats[count].name, sizeof(xstats[count].name),
2598 "xx_q%u_xon_to_xoff_priority_packets", i);
2599 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2600 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2604 for (i = 0; i < 16; i++) {
2605 snprintf(xstats[count].name, sizeof(xstats[count].name),
2606 "rx_q%u_packets", i);
2607 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2608 offsetof(struct ixgbe_hw_stats, qprc[i]));
2611 snprintf(xstats[count].name, sizeof(xstats[count].name),
2613 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2614 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2617 snprintf(xstats[count].name, sizeof(xstats[count].name),
2618 "tx_q%u_packets", i);
2619 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2620 offsetof(struct ixgbe_hw_stats, qptc[i]));
2623 snprintf(xstats[count].name, sizeof(xstats[count].name),
2625 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2626 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2629 snprintf(xstats[count].name, sizeof(xstats[count].name),
2630 "rx_q%u_dropped", i);
2631 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2632 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2640 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2642 struct ixgbe_hw_stats *stats =
2643 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2645 /* HW registers are cleared on read */
2646 ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2648 /* Reset software totals */
2649 memset(stats, 0, sizeof(*stats));
2653 ixgbevf_update_stats(struct rte_eth_dev *dev)
2655 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2657 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2659 /* Good Rx packet, include VF loopback */
2660 UPDATE_VF_STAT(IXGBE_VFGPRC,
2661 hw_stats->last_vfgprc, hw_stats->vfgprc);
2663 /* Good Rx octets, include VF loopback */
2664 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2665 hw_stats->last_vfgorc, hw_stats->vfgorc);
2667 /* Good Tx packet, include VF loopback */
2668 UPDATE_VF_STAT(IXGBE_VFGPTC,
2669 hw_stats->last_vfgptc, hw_stats->vfgptc);
2671 /* Good Tx octets, include VF loopback */
2672 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2673 hw_stats->last_vfgotc, hw_stats->vfgotc);
2675 /* Rx Multicst Packet */
2676 UPDATE_VF_STAT(IXGBE_VFMPRC,
2677 hw_stats->last_vfmprc, hw_stats->vfmprc);
2681 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2684 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2685 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2688 if (n < IXGBEVF_NB_XSTATS)
2689 return IXGBEVF_NB_XSTATS;
2691 ixgbevf_update_stats(dev);
2696 /* Extended stats */
2697 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2698 snprintf(xstats[i].name, sizeof(xstats[i].name),
2699 "%s", rte_ixgbevf_stats_strings[i].name);
2700 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2701 rte_ixgbevf_stats_strings[i].offset);
2704 return IXGBEVF_NB_XSTATS;
2708 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2710 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2711 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2713 ixgbevf_update_stats(dev);
2718 stats->ipackets = hw_stats->vfgprc;
2719 stats->ibytes = hw_stats->vfgorc;
2720 stats->opackets = hw_stats->vfgptc;
2721 stats->obytes = hw_stats->vfgotc;
2722 stats->imcasts = hw_stats->vfmprc;
2723 /* stats->imcasts should be removed as imcasts is deprecated */
2727 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2729 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2730 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2732 /* Sync HW register to the last stats */
2733 ixgbevf_dev_stats_get(dev, NULL);
2735 /* reset HW current stats*/
2736 hw_stats->vfgprc = 0;
2737 hw_stats->vfgorc = 0;
2738 hw_stats->vfgptc = 0;
2739 hw_stats->vfgotc = 0;
2740 hw_stats->vfmprc = 0;
2745 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2750 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2751 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2752 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2753 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2754 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2755 dev_info->max_vfs = dev->pci_dev->max_vfs;
2756 if (hw->mac.type == ixgbe_mac_82598EB)
2757 dev_info->max_vmdq_pools = ETH_16_POOLS;
2759 dev_info->max_vmdq_pools = ETH_64_POOLS;
2760 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2761 dev_info->rx_offload_capa =
2762 DEV_RX_OFFLOAD_VLAN_STRIP |
2763 DEV_RX_OFFLOAD_IPV4_CKSUM |
2764 DEV_RX_OFFLOAD_UDP_CKSUM |
2765 DEV_RX_OFFLOAD_TCP_CKSUM;
2768 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2771 if ((hw->mac.type == ixgbe_mac_82599EB ||
2772 hw->mac.type == ixgbe_mac_X540) &&
2773 !RTE_ETH_DEV_SRIOV(dev).active)
2774 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2776 dev_info->tx_offload_capa =
2777 DEV_TX_OFFLOAD_VLAN_INSERT |
2778 DEV_TX_OFFLOAD_IPV4_CKSUM |
2779 DEV_TX_OFFLOAD_UDP_CKSUM |
2780 DEV_TX_OFFLOAD_TCP_CKSUM |
2781 DEV_TX_OFFLOAD_SCTP_CKSUM |
2782 DEV_TX_OFFLOAD_TCP_TSO;
2784 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2786 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2787 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2788 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2790 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2794 dev_info->default_txconf = (struct rte_eth_txconf) {
2796 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2797 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2798 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2800 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2801 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2802 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2803 ETH_TXQ_FLAGS_NOOFFLOADS,
2806 dev_info->rx_desc_lim = rx_desc_lim;
2807 dev_info->tx_desc_lim = tx_desc_lim;
2809 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2810 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2811 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2815 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2816 struct rte_eth_dev_info *dev_info)
2818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2821 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2822 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2823 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2824 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2825 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2826 dev_info->max_vfs = dev->pci_dev->max_vfs;
2827 if (hw->mac.type == ixgbe_mac_82598EB)
2828 dev_info->max_vmdq_pools = ETH_16_POOLS;
2830 dev_info->max_vmdq_pools = ETH_64_POOLS;
2831 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2832 DEV_RX_OFFLOAD_IPV4_CKSUM |
2833 DEV_RX_OFFLOAD_UDP_CKSUM |
2834 DEV_RX_OFFLOAD_TCP_CKSUM;
2835 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2836 DEV_TX_OFFLOAD_IPV4_CKSUM |
2837 DEV_TX_OFFLOAD_UDP_CKSUM |
2838 DEV_TX_OFFLOAD_TCP_CKSUM |
2839 DEV_TX_OFFLOAD_SCTP_CKSUM |
2840 DEV_TX_OFFLOAD_TCP_TSO;
2842 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2844 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2845 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2846 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2848 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2852 dev_info->default_txconf = (struct rte_eth_txconf) {
2854 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2855 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2856 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2858 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2859 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2860 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2861 ETH_TXQ_FLAGS_NOOFFLOADS,
2864 dev_info->rx_desc_lim = rx_desc_lim;
2865 dev_info->tx_desc_lim = tx_desc_lim;
2868 /* return 0 means link status changed, -1 means not changed */
2870 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 struct rte_eth_link link, old;
2874 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2878 link.link_status = 0;
2879 link.link_speed = 0;
2880 link.link_duplex = 0;
2881 memset(&old, 0, sizeof(old));
2882 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2884 hw->mac.get_link_status = true;
2886 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2887 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2888 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2890 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2893 link.link_speed = ETH_LINK_SPEED_100;
2894 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2895 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2896 if (link.link_status == old.link_status)
2902 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2903 if (link.link_status == old.link_status)
2907 link.link_status = 1;
2908 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2910 switch (link_speed) {
2912 case IXGBE_LINK_SPEED_UNKNOWN:
2913 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2914 link.link_speed = ETH_LINK_SPEED_100;
2917 case IXGBE_LINK_SPEED_100_FULL:
2918 link.link_speed = ETH_LINK_SPEED_100;
2921 case IXGBE_LINK_SPEED_1GB_FULL:
2922 link.link_speed = ETH_LINK_SPEED_1000;
2925 case IXGBE_LINK_SPEED_10GB_FULL:
2926 link.link_speed = ETH_LINK_SPEED_10000;
2929 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2931 if (link.link_status == old.link_status)
2938 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2944 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2945 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2949 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2951 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2955 fctrl &= (~IXGBE_FCTRL_UPE);
2956 if (dev->data->all_multicast == 1)
2957 fctrl |= IXGBE_FCTRL_MPE;
2959 fctrl &= (~IXGBE_FCTRL_MPE);
2960 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2964 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2970 fctrl |= IXGBE_FCTRL_MPE;
2971 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2975 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2977 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980 if (dev->data->promiscuous == 1)
2981 return; /* must remain in all_multicast mode */
2983 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2984 fctrl &= (~IXGBE_FCTRL_MPE);
2985 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2989 * It clears the interrupt causes and enables the interrupt.
2990 * It will be called once only during nic initialized.
2993 * Pointer to struct rte_eth_dev.
2996 * - On success, zero.
2997 * - On failure, a negative value.
3000 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3002 struct ixgbe_interrupt *intr =
3003 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3005 ixgbe_dev_link_status_print(dev);
3006 intr->mask |= IXGBE_EICR_LSC;
3012 * It clears the interrupt causes and enables the interrupt.
3013 * It will be called once only during nic initialized.
3016 * Pointer to struct rte_eth_dev.
3019 * - On success, zero.
3020 * - On failure, a negative value.
3023 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3025 struct ixgbe_interrupt *intr =
3026 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3028 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3034 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3037 * Pointer to struct rte_eth_dev.
3040 * - On success, zero.
3041 * - On failure, a negative value.
3044 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048 struct ixgbe_interrupt *intr =
3049 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3051 /* clear all cause mask */
3052 ixgbe_disable_intr(hw);
3054 /* read-on-clear nic registers here */
3055 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3056 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3060 /* set flag for async link update */
3061 if (eicr & IXGBE_EICR_LSC)
3062 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3064 if (eicr & IXGBE_EICR_MAILBOX)
3065 intr->flags |= IXGBE_FLAG_MAILBOX;
3071 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3075 struct ixgbe_interrupt *intr =
3076 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3078 /* clear all cause mask */
3079 ixgbevf_intr_disable(hw);
3081 /* read-on-clear nic registers here */
3082 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3083 PMD_DRV_LOG(INFO, "eicr %x", eicr);
3087 /* set flag for async link update */
3088 if (eicr & IXGBE_EICR_LSC)
3089 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3095 * It gets and then prints the link status.
3098 * Pointer to struct rte_eth_dev.
3101 * - On success, zero.
3102 * - On failure, a negative value.
3105 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3107 struct rte_eth_link link;
3109 memset(&link, 0, sizeof(link));
3110 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3111 if (link.link_status) {
3112 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3113 (int)(dev->data->port_id),
3114 (unsigned)link.link_speed,
3115 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3116 "full-duplex" : "half-duplex");
3118 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3119 (int)(dev->data->port_id));
3121 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3122 dev->pci_dev->addr.domain,
3123 dev->pci_dev->addr.bus,
3124 dev->pci_dev->addr.devid,
3125 dev->pci_dev->addr.function);
3129 * It executes link_update after knowing an interrupt occurred.
3132 * Pointer to struct rte_eth_dev.
3135 * - On success, zero.
3136 * - On failure, a negative value.
3139 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3141 struct ixgbe_interrupt *intr =
3142 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3144 struct rte_eth_link link;
3145 int intr_enable_delay = false;
3147 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3149 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3150 ixgbe_pf_mbx_process(dev);
3151 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3154 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3155 /* get the link status before link update, for predicting later */
3156 memset(&link, 0, sizeof(link));
3157 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3159 ixgbe_dev_link_update(dev, 0);
3162 if (!link.link_status)
3163 /* handle it 1 sec later, wait it being stable */
3164 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3165 /* likely to down */
3167 /* handle it 4 sec later, wait it being stable */
3168 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3170 ixgbe_dev_link_status_print(dev);
3172 intr_enable_delay = true;
3175 if (intr_enable_delay) {
3176 if (rte_eal_alarm_set(timeout * 1000,
3177 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3178 PMD_DRV_LOG(ERR, "Error setting alarm");
3180 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3181 ixgbe_enable_intr(dev);
3182 rte_intr_enable(&(dev->pci_dev->intr_handle));
3190 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3192 struct ixgbe_hw *hw =
3193 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3196 ixgbevf_intr_enable(hw);
3197 rte_intr_enable(&dev->pci_dev->intr_handle);
3202 * Interrupt handler which shall be registered for alarm callback for delayed
3203 * handling specific interrupt to wait for the stable nic state. As the
3204 * NIC interrupt state is not stable for ixgbe after link is just down,
3205 * it needs to wait 4 seconds to get the stable status.
3208 * Pointer to interrupt handle.
3210 * The address of parameter (struct rte_eth_dev *) regsitered before.
3216 ixgbe_dev_interrupt_delayed_handler(void *param)
3218 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3219 struct ixgbe_interrupt *intr =
3220 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3221 struct ixgbe_hw *hw =
3222 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3226 if (eicr & IXGBE_EICR_MAILBOX)
3227 ixgbe_pf_mbx_process(dev);
3229 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3230 ixgbe_dev_link_update(dev, 0);
3231 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3232 ixgbe_dev_link_status_print(dev);
3233 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3236 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3237 ixgbe_enable_intr(dev);
3238 rte_intr_enable(&(dev->pci_dev->intr_handle));
3242 * Interrupt handler triggered by NIC for handling
3243 * specific interrupt.
3246 * Pointer to interrupt handle.
3248 * The address of parameter (struct rte_eth_dev *) regsitered before.
3254 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3257 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3259 ixgbe_dev_interrupt_get_status(dev);
3260 ixgbe_dev_interrupt_action(dev);
3264 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3267 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3269 ixgbevf_dev_interrupt_get_status(dev);
3270 ixgbevf_dev_interrupt_action(dev);
3274 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3276 struct ixgbe_hw *hw;
3278 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3283 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3285 struct ixgbe_hw *hw;
3287 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3292 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3294 struct ixgbe_hw *hw;
3300 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302 fc_conf->pause_time = hw->fc.pause_time;
3303 fc_conf->high_water = hw->fc.high_water[0];
3304 fc_conf->low_water = hw->fc.low_water[0];
3305 fc_conf->send_xon = hw->fc.send_xon;
3306 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3309 * Return rx_pause status according to actual setting of
3312 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3313 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3319 * Return tx_pause status according to actual setting of
3322 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3323 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3328 if (rx_pause && tx_pause)
3329 fc_conf->mode = RTE_FC_FULL;
3331 fc_conf->mode = RTE_FC_RX_PAUSE;
3333 fc_conf->mode = RTE_FC_TX_PAUSE;
3335 fc_conf->mode = RTE_FC_NONE;
3341 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3343 struct ixgbe_hw *hw;
3345 uint32_t rx_buf_size;
3346 uint32_t max_high_water;
3348 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3355 PMD_INIT_FUNC_TRACE();
3357 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3359 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3362 * At least reserve one Ethernet frame for watermark
3363 * high_water/low_water in kilo bytes for ixgbe
3365 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3366 if ((fc_conf->high_water > max_high_water) ||
3367 (fc_conf->high_water < fc_conf->low_water)) {
3368 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3369 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3373 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3374 hw->fc.pause_time = fc_conf->pause_time;
3375 hw->fc.high_water[0] = fc_conf->high_water;
3376 hw->fc.low_water[0] = fc_conf->low_water;
3377 hw->fc.send_xon = fc_conf->send_xon;
3378 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3380 err = ixgbe_fc_enable(hw);
3382 /* Not negotiated is not an error case */
3383 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3385 /* check if we want to forward MAC frames - driver doesn't have native
3386 * capability to do that, so we'll write the registers ourselves */
3388 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3390 /* set or clear MFLCN.PMCF bit depending on configuration */
3391 if (fc_conf->mac_ctrl_frame_fwd != 0)
3392 mflcn |= IXGBE_MFLCN_PMCF;
3394 mflcn &= ~IXGBE_MFLCN_PMCF;
3396 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3397 IXGBE_WRITE_FLUSH(hw);
3402 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3407 * ixgbe_pfc_enable_generic - Enable flow control
3408 * @hw: pointer to hardware structure
3409 * @tc_num: traffic class number
3410 * Enable flow control according to the current settings.
3413 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3416 uint32_t mflcn_reg, fccfg_reg;
3418 uint32_t fcrtl, fcrth;
3422 /* Validate the water mark configuration */
3423 if (!hw->fc.pause_time) {
3424 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3428 /* Low water mark of zero causes XOFF floods */
3429 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3430 /* High/Low water can not be 0 */
3431 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3432 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3433 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3437 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3438 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3439 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3443 /* Negotiate the fc mode to use */
3444 ixgbe_fc_autoneg(hw);
3446 /* Disable any previous flow control settings */
3447 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3448 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3450 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3451 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3453 switch (hw->fc.current_mode) {
3456 * If the count of enabled RX Priority Flow control >1,
3457 * and the TX pause can not be disabled
3460 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3461 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3462 if (reg & IXGBE_FCRTH_FCEN)
3466 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3468 case ixgbe_fc_rx_pause:
3470 * Rx Flow control is enabled and Tx Flow control is
3471 * disabled by software override. Since there really
3472 * isn't a way to advertise that we are capable of RX
3473 * Pause ONLY, we will advertise that we support both
3474 * symmetric and asymmetric Rx PAUSE. Later, we will
3475 * disable the adapter's ability to send PAUSE frames.
3477 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3479 * If the count of enabled RX Priority Flow control >1,
3480 * and the TX pause can not be disabled
3483 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3484 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3485 if (reg & IXGBE_FCRTH_FCEN)
3489 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3491 case ixgbe_fc_tx_pause:
3493 * Tx Flow control is enabled, and Rx Flow control is
3494 * disabled by software override.
3496 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3499 /* Flow control (both Rx and Tx) is enabled by SW override. */
3500 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3501 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3504 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3505 ret_val = IXGBE_ERR_CONFIG;
3510 /* Set 802.3x based flow control settings. */
3511 mflcn_reg |= IXGBE_MFLCN_DPF;
3512 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3513 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3515 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3516 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3517 hw->fc.high_water[tc_num]) {
3518 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3519 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3520 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3522 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3524 * In order to prevent Tx hangs when the internal Tx
3525 * switch is enabled we must set the high water mark
3526 * to the maximum FCRTH value. This allows the Tx
3527 * switch to function even under heavy Rx workloads.
3529 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3531 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3533 /* Configure pause time (2 TCs per register) */
3534 reg = hw->fc.pause_time * 0x00010001;
3535 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3536 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3538 /* Configure flow control refresh threshold value */
3539 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3546 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3548 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3551 if(hw->mac.type != ixgbe_mac_82598EB) {
3552 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3558 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3561 uint32_t rx_buf_size;
3562 uint32_t max_high_water;
3564 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3565 struct ixgbe_hw *hw =
3566 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567 struct ixgbe_dcb_config *dcb_config =
3568 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3570 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3577 PMD_INIT_FUNC_TRACE();
3579 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3580 tc_num = map[pfc_conf->priority];
3581 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3582 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3584 * At least reserve one Ethernet frame for watermark
3585 * high_water/low_water in kilo bytes for ixgbe
3587 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3588 if ((pfc_conf->fc.high_water > max_high_water) ||
3589 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3590 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3591 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3595 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3596 hw->fc.pause_time = pfc_conf->fc.pause_time;
3597 hw->fc.send_xon = pfc_conf->fc.send_xon;
3598 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3599 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3601 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3603 /* Not negotiated is not an error case */
3604 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3607 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3612 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3613 struct rte_eth_rss_reta_entry64 *reta_conf,
3618 uint16_t idx, shift;
3619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 uint16_t sp_reta_size;
3623 PMD_INIT_FUNC_TRACE();
3625 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3626 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3631 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3632 if (reta_size != sp_reta_size) {
3633 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3634 "(%d) doesn't match the number hardware can supported "
3635 "(%d)\n", reta_size, sp_reta_size);
3639 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3640 idx = i / RTE_RETA_GROUP_SIZE;
3641 shift = i % RTE_RETA_GROUP_SIZE;
3642 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3646 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3647 if (mask == IXGBE_4_BIT_MASK)
3650 r = IXGBE_READ_REG(hw, reta_reg);
3651 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3652 if (mask & (0x1 << j))
3653 reta |= reta_conf[idx].reta[shift + j] <<
3656 reta |= r & (IXGBE_8_BIT_MASK <<
3659 IXGBE_WRITE_REG(hw, reta_reg, reta);
3666 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3667 struct rte_eth_rss_reta_entry64 *reta_conf,
3672 uint16_t idx, shift;
3673 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3674 uint16_t sp_reta_size;
3677 PMD_INIT_FUNC_TRACE();
3678 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3679 if (reta_size != sp_reta_size) {
3680 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3681 "(%d) doesn't match the number hardware can supported "
3682 "(%d)\n", reta_size, sp_reta_size);
3686 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3687 idx = i / RTE_RETA_GROUP_SIZE;
3688 shift = i % RTE_RETA_GROUP_SIZE;
3689 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3694 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3695 reta = IXGBE_READ_REG(hw, reta_reg);
3696 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3697 if (mask & (0x1 << j))
3698 reta_conf[idx].reta[shift + j] =
3699 ((reta >> (CHAR_BIT * j)) &
3708 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3709 uint32_t index, uint32_t pool)
3711 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3712 uint32_t enable_addr = 1;
3714 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3718 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722 ixgbe_clear_rar(hw, index);
3726 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3728 ixgbe_remove_rar(dev, 0);
3730 ixgbe_add_rar(dev, addr, 0, 0);
3734 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3738 struct ixgbe_hw *hw;
3739 struct rte_eth_dev_info dev_info;
3740 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3742 ixgbe_dev_info_get(dev, &dev_info);
3744 /* check that mtu is within the allowed range */
3745 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3748 /* refuse mtu that requires the support of scattered packets when this
3749 * feature has not been enabled before. */
3750 if (!dev->data->scattered_rx &&
3751 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3752 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3755 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3758 /* switch to jumbo mode if needed */
3759 if (frame_size > ETHER_MAX_LEN) {
3760 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3761 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3763 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3764 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3766 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3768 /* update max frame size */
3769 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3771 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3772 maxfrs &= 0x0000FFFF;
3773 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3774 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3780 * Virtual Function operations
3783 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3785 PMD_INIT_FUNC_TRACE();
3787 /* Clear interrupt mask to stop from interrupts being generated */
3788 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3790 IXGBE_WRITE_FLUSH(hw);
3794 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3796 PMD_INIT_FUNC_TRACE();
3798 /* VF enable interrupt autoclean */
3799 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3800 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3801 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3803 IXGBE_WRITE_FLUSH(hw);
3807 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3809 struct rte_eth_conf* conf = &dev->data->dev_conf;
3810 struct ixgbe_adapter *adapter =
3811 (struct ixgbe_adapter *)dev->data->dev_private;
3813 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3814 dev->data->port_id);
3817 * VF has no ability to enable/disable HW CRC
3818 * Keep the persistent behavior the same as Host PF
3820 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3821 if (!conf->rxmode.hw_strip_crc) {
3822 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3823 conf->rxmode.hw_strip_crc = 1;
3826 if (conf->rxmode.hw_strip_crc) {
3827 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3828 conf->rxmode.hw_strip_crc = 0;
3833 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3834 * allocation or vector Rx preconditions we will reset it.
3836 adapter->rx_bulk_alloc_allowed = true;
3837 adapter->rx_vec_allowed = true;
3843 ixgbevf_dev_start(struct rte_eth_dev *dev)
3845 struct ixgbe_hw *hw =
3846 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847 uint32_t intr_vector = 0;
3848 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3852 PMD_INIT_FUNC_TRACE();
3854 hw->mac.ops.reset_hw(hw);
3855 hw->mac.get_link_status = true;
3857 /* negotiate mailbox API version to use with the PF. */
3858 ixgbevf_negotiate_api(hw);
3860 ixgbevf_dev_tx_init(dev);
3862 /* This can fail when allocating mbufs for descriptor rings */
3863 err = ixgbevf_dev_rx_init(dev);
3865 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3866 ixgbe_dev_clear_queues(dev);
3871 ixgbevf_set_vfta_all(dev,1);
3874 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3875 ETH_VLAN_EXTEND_MASK;
3876 ixgbevf_vlan_offload_set(dev, mask);
3878 ixgbevf_dev_rxtx_start(dev);
3880 /* check and configure queue intr-vector mapping */
3881 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3882 intr_vector = dev->data->nb_rx_queues;
3883 if (rte_intr_efd_enable(intr_handle, intr_vector))
3887 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3888 intr_handle->intr_vec =
3889 rte_zmalloc("intr_vec",
3890 dev->data->nb_rx_queues * sizeof(int), 0);
3891 if (intr_handle->intr_vec == NULL) {
3892 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3893 " intr_vec\n", dev->data->nb_rx_queues);
3897 ixgbevf_configure_msix(dev);
3899 if (dev->data->dev_conf.intr_conf.lsc != 0) {
3900 if (rte_intr_allow_others(intr_handle))
3901 rte_intr_callback_register(intr_handle,
3902 ixgbevf_dev_interrupt_handler,
3905 PMD_INIT_LOG(INFO, "lsc won't enable because of"
3906 " no intr multiplex\n");
3909 rte_intr_enable(intr_handle);
3911 /* Re-enable interrupt for VF */
3912 ixgbevf_intr_enable(hw);
3918 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3923 PMD_INIT_FUNC_TRACE();
3925 hw->adapter_stopped = 1;
3926 ixgbe_stop_adapter(hw);
3929 * Clear what we set, but we still keep shadow_vfta to
3930 * restore after device starts
3932 ixgbevf_set_vfta_all(dev,0);
3934 /* Clear stored conf */
3935 dev->data->scattered_rx = 0;
3937 ixgbe_dev_clear_queues(dev);
3939 /* disable intr eventfd mapping */
3940 rte_intr_disable(intr_handle);
3942 /* Clean datapath event and queue/vec mapping */
3943 rte_intr_efd_disable(intr_handle);
3944 if (intr_handle->intr_vec != NULL) {
3945 rte_free(intr_handle->intr_vec);
3946 intr_handle->intr_vec = NULL;
3951 ixgbevf_dev_close(struct rte_eth_dev *dev)
3953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955 PMD_INIT_FUNC_TRACE();
3959 ixgbevf_dev_stop(dev);
3961 ixgbe_dev_free_queues(dev);
3963 /* reprogram the RAR[0] in case user changed it. */
3964 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3967 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970 struct ixgbe_vfta * shadow_vfta =
3971 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3972 int i = 0, j = 0, vfta = 0, mask = 1;
3974 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3975 vfta = shadow_vfta->vfta[i];
3978 for (j = 0; j < 32; j++){
3980 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3989 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3991 struct ixgbe_hw *hw =
3992 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 struct ixgbe_vfta * shadow_vfta =
3994 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3995 uint32_t vid_idx = 0;
3996 uint32_t vid_bit = 0;
3999 PMD_INIT_FUNC_TRACE();
4001 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4002 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4004 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4007 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4008 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4010 /* Save what we set and retore it after device reset */
4012 shadow_vfta->vfta[vid_idx] |= vid_bit;
4014 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4020 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4022 struct ixgbe_hw *hw =
4023 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026 PMD_INIT_FUNC_TRACE();
4028 if(queue >= hw->mac.max_rx_queues)
4031 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4033 ctrl |= IXGBE_RXDCTL_VME;
4035 ctrl &= ~IXGBE_RXDCTL_VME;
4036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4038 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4042 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4044 struct ixgbe_hw *hw =
4045 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4049 /* VF function only support hw strip feature, others are not support */
4050 if(mask & ETH_VLAN_STRIP_MASK){
4051 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4053 for(i=0; i < hw->mac.max_rx_queues; i++)
4054 ixgbevf_vlan_strip_queue_set(dev,i,on);
4059 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4063 /* we only need to do this if VMDq is enabled */
4064 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4065 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4066 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4074 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4076 uint32_t vector = 0;
4077 switch (hw->mac.mc_filter_type) {
4078 case 0: /* use bits [47:36] of the address */
4079 vector = ((uc_addr->addr_bytes[4] >> 4) |
4080 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4082 case 1: /* use bits [46:35] of the address */
4083 vector = ((uc_addr->addr_bytes[4] >> 3) |
4084 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4086 case 2: /* use bits [45:34] of the address */
4087 vector = ((uc_addr->addr_bytes[4] >> 2) |
4088 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4090 case 3: /* use bits [43:32] of the address */
4091 vector = ((uc_addr->addr_bytes[4]) |
4092 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4094 default: /* Invalid mc_filter_type */
4098 /* vector can only be 12-bits or boundary will be exceeded */
4104 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4112 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4113 const uint32_t ixgbe_uta_bit_shift = 5;
4114 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4115 const uint32_t bit1 = 0x1;
4117 struct ixgbe_hw *hw =
4118 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4119 struct ixgbe_uta_info *uta_info =
4120 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4122 /* The UTA table only exists on 82599 hardware and newer */
4123 if (hw->mac.type < ixgbe_mac_82599EB)
4126 vector = ixgbe_uta_vector(hw,mac_addr);
4127 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4128 uta_shift = vector & ixgbe_uta_bit_mask;
4130 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4134 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4136 uta_info->uta_in_use++;
4137 reg_val |= (bit1 << uta_shift);
4138 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4140 uta_info->uta_in_use--;
4141 reg_val &= ~(bit1 << uta_shift);
4142 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4145 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4147 if (uta_info->uta_in_use > 0)
4148 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4149 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4151 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4157 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4160 struct ixgbe_hw *hw =
4161 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4162 struct ixgbe_uta_info *uta_info =
4163 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4165 /* The UTA table only exists on 82599 hardware and newer */
4166 if (hw->mac.type < ixgbe_mac_82599EB)
4170 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4171 uta_info->uta_shadow[i] = ~0;
4172 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4175 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4176 uta_info->uta_shadow[i] = 0;
4177 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4185 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4187 uint32_t new_val = orig_val;
4189 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4190 new_val |= IXGBE_VMOLR_AUPE;
4191 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4192 new_val |= IXGBE_VMOLR_ROMPE;
4193 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4194 new_val |= IXGBE_VMOLR_ROPE;
4195 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4196 new_val |= IXGBE_VMOLR_BAM;
4197 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4198 new_val |= IXGBE_VMOLR_MPE;
4204 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4205 uint16_t rx_mask, uint8_t on)
4209 struct ixgbe_hw *hw =
4210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4213 if (hw->mac.type == ixgbe_mac_82598EB) {
4214 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4215 " on 82599 hardware and newer");
4218 if (ixgbe_vmdq_mode_check(hw) < 0)
4221 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4228 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4234 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4238 const uint8_t bit1 = 0x1;
4240 struct ixgbe_hw *hw =
4241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4243 if (ixgbe_vmdq_mode_check(hw) < 0)
4246 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4247 reg = IXGBE_READ_REG(hw, addr);
4255 IXGBE_WRITE_REG(hw, addr,reg);
4261 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4265 const uint8_t bit1 = 0x1;
4267 struct ixgbe_hw *hw =
4268 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270 if (ixgbe_vmdq_mode_check(hw) < 0)
4273 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4274 reg = IXGBE_READ_REG(hw, addr);
4282 IXGBE_WRITE_REG(hw, addr,reg);
4288 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4289 uint64_t pool_mask, uint8_t vlan_on)
4293 struct ixgbe_hw *hw =
4294 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4296 if (ixgbe_vmdq_mode_check(hw) < 0)
4298 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4299 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4300 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4308 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4309 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4310 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4311 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4312 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4313 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4314 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4317 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4318 struct rte_eth_mirror_conf *mirror_conf,
4319 uint8_t rule_id, uint8_t on)
4321 uint32_t mr_ctl,vlvf;
4322 uint32_t mp_lsb = 0;
4323 uint32_t mv_msb = 0;
4324 uint32_t mv_lsb = 0;
4325 uint32_t mp_msb = 0;
4328 uint64_t vlan_mask = 0;
4330 const uint8_t pool_mask_offset = 32;
4331 const uint8_t vlan_mask_offset = 32;
4332 const uint8_t dst_pool_offset = 8;
4333 const uint8_t rule_mr_offset = 4;
4334 const uint8_t mirror_rule_mask= 0x0F;
4336 struct ixgbe_mirror_info *mr_info =
4337 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4338 struct ixgbe_hw *hw =
4339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340 uint8_t mirror_type = 0;
4342 if (ixgbe_vmdq_mode_check(hw) < 0)
4345 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4348 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4349 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4350 mirror_conf->rule_type);
4354 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4355 mirror_type |= IXGBE_MRCTL_VLME;
4356 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4357 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4358 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4359 /* search vlan id related pool vlan filter index */
4360 reg_index = ixgbe_find_vlvf_slot(hw,
4361 mirror_conf->vlan.vlan_id[i]);
4364 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4365 if ((vlvf & IXGBE_VLVF_VIEN) &&
4366 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4367 mirror_conf->vlan.vlan_id[i]))
4368 vlan_mask |= (1ULL << reg_index);
4375 mv_lsb = vlan_mask & 0xFFFFFFFF;
4376 mv_msb = vlan_mask >> vlan_mask_offset;
4378 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4379 mirror_conf->vlan.vlan_mask;
4380 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4381 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4382 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4383 mirror_conf->vlan.vlan_id[i];
4388 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4389 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4390 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4395 * if enable pool mirror, write related pool mask register,if disable
4396 * pool mirror, clear PFMRVM register
4398 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4399 mirror_type |= IXGBE_MRCTL_VPME;
4401 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4402 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4403 mr_info->mr_conf[rule_id].pool_mask =
4404 mirror_conf->pool_mask;
4409 mr_info->mr_conf[rule_id].pool_mask = 0;
4412 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4413 mirror_type |= IXGBE_MRCTL_UPME;
4414 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4415 mirror_type |= IXGBE_MRCTL_DPME;
4417 /* read mirror control register and recalculate it */
4418 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4421 mr_ctl |= mirror_type;
4422 mr_ctl &= mirror_rule_mask;
4423 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4425 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4427 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4428 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4430 /* write mirrror control register */
4431 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4433 /* write pool mirrror control register */
4434 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4435 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4436 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4439 /* write VLAN mirrror control register */
4440 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4441 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4442 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4450 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4453 uint32_t lsb_val = 0;
4454 uint32_t msb_val = 0;
4455 const uint8_t rule_mr_offset = 4;
4457 struct ixgbe_hw *hw =
4458 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459 struct ixgbe_mirror_info *mr_info =
4460 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4462 if (ixgbe_vmdq_mode_check(hw) < 0)
4465 memset(&mr_info->mr_conf[rule_id], 0,
4466 sizeof(struct rte_eth_mirror_conf));
4468 /* clear PFVMCTL register */
4469 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4471 /* clear pool mask register */
4472 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4473 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4475 /* clear vlan mask register */
4476 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4477 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4483 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4486 struct ixgbe_hw *hw =
4487 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4489 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4490 mask |= (1 << IXGBE_MISC_VEC_ID);
4491 RTE_SET_USED(queue_id);
4492 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4494 rte_intr_enable(&dev->pci_dev->intr_handle);
4500 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4503 struct ixgbe_hw *hw =
4504 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4506 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4507 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4508 RTE_SET_USED(queue_id);
4509 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4515 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4518 struct ixgbe_hw *hw =
4519 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4520 struct ixgbe_interrupt *intr =
4521 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4523 if (queue_id < 16) {
4524 ixgbe_disable_intr(hw);
4525 intr->mask |= (1 << queue_id);
4526 ixgbe_enable_intr(dev);
4527 } else if (queue_id < 32) {
4528 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4529 mask &= (1 << queue_id);
4530 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4531 } else if (queue_id < 64) {
4532 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4533 mask &= (1 << (queue_id - 32));
4534 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4536 rte_intr_enable(&dev->pci_dev->intr_handle);
4542 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4545 struct ixgbe_hw *hw =
4546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4547 struct ixgbe_interrupt *intr =
4548 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4550 if (queue_id < 16) {
4551 ixgbe_disable_intr(hw);
4552 intr->mask &= ~(1 << queue_id);
4553 ixgbe_enable_intr(dev);
4554 } else if (queue_id < 32) {
4555 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4556 mask &= ~(1 << queue_id);
4557 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4558 } else if (queue_id < 64) {
4559 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4560 mask &= ~(1 << (queue_id - 32));
4561 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4568 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4569 uint8_t queue, uint8_t msix_vector)
4573 if (direction == -1) {
4575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4576 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4579 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4581 /* rx or tx cause */
4582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4583 idx = ((16 * (queue & 1)) + (8 * direction));
4584 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4585 tmp &= ~(0xFF << idx);
4586 tmp |= (msix_vector << idx);
4587 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4592 * set the IVAR registers, mapping interrupt causes to vectors
4594 * pointer to ixgbe_hw struct
4596 * 0 for Rx, 1 for Tx, -1 for other causes
4598 * queue to map the corresponding interrupt to
4600 * the vector to map to the corresponding queue
4603 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4604 uint8_t queue, uint8_t msix_vector)
4608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4609 if (hw->mac.type == ixgbe_mac_82598EB) {
4610 if (direction == -1)
4612 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4613 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4614 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4615 tmp |= (msix_vector << (8 * (queue & 0x3)));
4616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4617 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4618 (hw->mac.type == ixgbe_mac_X540)) {
4619 if (direction == -1) {
4621 idx = ((queue & 1) * 8);
4622 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4623 tmp &= ~(0xFF << idx);
4624 tmp |= (msix_vector << idx);
4625 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4627 /* rx or tx causes */
4628 idx = ((16 * (queue & 1)) + (8 * direction));
4629 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4630 tmp &= ~(0xFF << idx);
4631 tmp |= (msix_vector << idx);
4632 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4638 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4640 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4641 struct ixgbe_hw *hw =
4642 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4646 /* won't configure msix register if no mapping is done
4647 * between intr vector and event fd.
4649 if (!rte_intr_dp_is_en(intr_handle))
4652 /* Configure all RX queues of VF */
4653 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4654 /* Force all queue use vector 0,
4655 * as IXGBE_VF_MAXMSIVECOTR = 1
4657 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4658 intr_handle->intr_vec[q_idx] = vector_idx;
4661 /* Configure VF Rx queue ivar */
4662 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4666 * Sets up the hardware to properly generate MSI-X interrupts
4668 * board private structure
4671 ixgbe_configure_msix(struct rte_eth_dev *dev)
4673 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4674 struct ixgbe_hw *hw =
4675 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4677 uint32_t vec = IXGBE_MISC_VEC_ID;
4681 /* won't configure msix register if no mapping is done
4682 * between intr vector and event fd
4684 if (!rte_intr_dp_is_en(intr_handle))
4687 if (rte_intr_allow_others(intr_handle))
4688 vec = base = IXGBE_RX_VEC_START;
4690 /* setup GPIE for MSI-x mode */
4691 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4692 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4693 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4694 /* auto clearing and auto setting corresponding bits in EIMS
4695 * when MSI-X interrupt is triggered
4697 if (hw->mac.type == ixgbe_mac_82598EB) {
4698 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4700 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4701 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4703 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4705 /* Populate the IVAR table and set the ITR values to the
4706 * corresponding register.
4708 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4710 /* by default, 1:1 mapping */
4711 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4712 intr_handle->intr_vec[queue_id] = vec;
4713 if (vec < base + intr_handle->nb_efd - 1)
4717 switch (hw->mac.type) {
4718 case ixgbe_mac_82598EB:
4719 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4722 case ixgbe_mac_82599EB:
4723 case ixgbe_mac_X540:
4724 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4729 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4730 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4732 /* set up to autoclear timer, and the vectors */
4733 mask = IXGBE_EIMS_ENABLE_MASK;
4734 mask &= ~(IXGBE_EIMS_OTHER |
4735 IXGBE_EIMS_MAILBOX |
4738 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4741 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4742 uint16_t queue_idx, uint16_t tx_rate)
4744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745 uint32_t rf_dec, rf_int;
4747 uint16_t link_speed = dev->data->dev_link.link_speed;
4749 if (queue_idx >= hw->mac.max_tx_queues)
4753 /* Calculate the rate factor values to set */
4754 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4755 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4756 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4758 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4759 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4760 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4761 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4767 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4768 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4771 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4772 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4773 IXGBE_MAX_JUMBO_FRAME_SIZE))
4774 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4775 IXGBE_MMW_SIZE_JUMBO_FRAME);
4777 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4778 IXGBE_MMW_SIZE_DEFAULT);
4780 /* Set RTTBCNRC of queue X */
4781 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4782 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4783 IXGBE_WRITE_FLUSH(hw);
4788 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4789 uint16_t tx_rate, uint64_t q_msk)
4791 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 struct ixgbe_vf_info *vfinfo =
4793 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4794 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4795 uint32_t queue_stride =
4796 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4797 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4798 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4799 uint16_t total_rate = 0;
4801 if (queue_end >= hw->mac.max_tx_queues)
4804 if (vfinfo != NULL) {
4805 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4808 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4810 total_rate += vfinfo[vf_idx].tx_rate[idx];
4815 /* Store tx_rate for this vf. */
4816 for (idx = 0; idx < nb_q_per_pool; idx++) {
4817 if (((uint64_t)0x1 << idx) & q_msk) {
4818 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4819 vfinfo[vf].tx_rate[idx] = tx_rate;
4820 total_rate += tx_rate;
4824 if (total_rate > dev->data->dev_link.link_speed) {
4826 * Reset stored TX rate of the VF if it causes exceed
4829 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4833 /* Set RTTBCNRC of each queue/pool for vf X */
4834 for (; queue_idx <= queue_end; queue_idx++) {
4836 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4844 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4845 __attribute__((unused)) uint32_t index,
4846 __attribute__((unused)) uint32_t pool)
4848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4853 * operation. Trap this case to avoid exhausting the [very limited]
4854 * set of PF resources used to store VF MAC addresses.
4856 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4858 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4861 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4865 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4868 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4869 struct ether_addr *mac_addr;
4874 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4875 * not support the deletion of a given MAC address.
4876 * Instead, it imposes to delete all MAC addresses, then to add again
4877 * all MAC addresses with the exception of the one to be deleted.
4879 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4882 * Add again all MAC addresses, with the exception of the deleted one
4883 * and of the permanent MAC address.
4885 for (i = 0, mac_addr = dev->data->mac_addrs;
4886 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4887 /* Skip the deleted MAC address */
4890 /* Skip NULL MAC addresses */
4891 if (is_zero_ether_addr(mac_addr))
4893 /* Skip the permanent MAC address */
4894 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4896 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4899 "Adding again MAC address "
4900 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4902 mac_addr->addr_bytes[0],
4903 mac_addr->addr_bytes[1],
4904 mac_addr->addr_bytes[2],
4905 mac_addr->addr_bytes[3],
4906 mac_addr->addr_bytes[4],
4907 mac_addr->addr_bytes[5],
4913 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4920 #define MAC_TYPE_FILTER_SUP(type) do {\
4921 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4922 (type) != ixgbe_mac_X550)\
4927 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4928 struct rte_eth_syn_filter *filter,
4931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4934 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4937 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4940 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4942 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4943 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4945 if (filter->hig_pri)
4946 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4948 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4950 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4952 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4954 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4955 IXGBE_WRITE_FLUSH(hw);
4960 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4961 struct rte_eth_syn_filter *filter)
4963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4964 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4966 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4967 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4968 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4975 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4976 enum rte_filter_op filter_op,
4979 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982 MAC_TYPE_FILTER_SUP(hw->mac.type);
4984 if (filter_op == RTE_ETH_FILTER_NOP)
4988 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4993 switch (filter_op) {
4994 case RTE_ETH_FILTER_ADD:
4995 ret = ixgbe_syn_filter_set(dev,
4996 (struct rte_eth_syn_filter *)arg,
4999 case RTE_ETH_FILTER_DELETE:
5000 ret = ixgbe_syn_filter_set(dev,
5001 (struct rte_eth_syn_filter *)arg,
5004 case RTE_ETH_FILTER_GET:
5005 ret = ixgbe_syn_filter_get(dev,
5006 (struct rte_eth_syn_filter *)arg);
5009 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5018 static inline enum ixgbe_5tuple_protocol
5019 convert_protocol_type(uint8_t protocol_value)
5021 if (protocol_value == IPPROTO_TCP)
5022 return IXGBE_FILTER_PROTOCOL_TCP;
5023 else if (protocol_value == IPPROTO_UDP)
5024 return IXGBE_FILTER_PROTOCOL_UDP;
5025 else if (protocol_value == IPPROTO_SCTP)
5026 return IXGBE_FILTER_PROTOCOL_SCTP;
5028 return IXGBE_FILTER_PROTOCOL_NONE;
5032 * add a 5tuple filter
5035 * dev: Pointer to struct rte_eth_dev.
5036 * index: the index the filter allocates.
5037 * filter: ponter to the filter that will be added.
5038 * rx_queue: the queue id the filter assigned to.
5041 * - On success, zero.
5042 * - On failure, a negative value.
5045 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5046 struct ixgbe_5tuple_filter *filter)
5048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049 struct ixgbe_filter_info *filter_info =
5050 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5052 uint32_t ftqf, sdpqf;
5053 uint32_t l34timir = 0;
5054 uint8_t mask = 0xff;
5057 * look for an unused 5tuple filter index,
5058 * and insert the filter to list.
5060 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5061 idx = i / (sizeof(uint32_t) * NBBY);
5062 shift = i % (sizeof(uint32_t) * NBBY);
5063 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5064 filter_info->fivetuple_mask[idx] |= 1 << shift;
5066 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5072 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5073 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5077 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5078 IXGBE_SDPQF_DSTPORT_SHIFT);
5079 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5081 ftqf = (uint32_t)(filter->filter_info.proto &
5082 IXGBE_FTQF_PROTOCOL_MASK);
5083 ftqf |= (uint32_t)((filter->filter_info.priority &
5084 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5085 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5086 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5087 if (filter->filter_info.dst_ip_mask == 0)
5088 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5089 if (filter->filter_info.src_port_mask == 0)
5090 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5091 if (filter->filter_info.dst_port_mask == 0)
5092 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5093 if (filter->filter_info.proto_mask == 0)
5094 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5095 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5096 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5097 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5099 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5100 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5101 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5102 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5104 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5105 l34timir |= (uint32_t)(filter->queue <<
5106 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5107 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5112 * remove a 5tuple filter
5115 * dev: Pointer to struct rte_eth_dev.
5116 * filter: the pointer of the filter will be removed.
5119 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5120 struct ixgbe_5tuple_filter *filter)
5122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 struct ixgbe_filter_info *filter_info =
5124 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5125 uint16_t index = filter->index;
5127 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5128 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5129 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5132 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5133 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5134 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5135 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5136 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5140 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5142 struct ixgbe_hw *hw;
5143 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5145 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5150 /* refuse mtu that requires the support of scattered packets when this
5151 * feature has not been enabled before. */
5152 if (!dev->data->scattered_rx &&
5153 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5154 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5158 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5159 * request of the version 2.0 of the mailbox API.
5160 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5161 * of the mailbox API.
5162 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5163 * prior to 3.11.33 which contains the following change:
5164 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5166 ixgbevf_rlpml_set_vf(hw, max_frame);
5168 /* update max frame size */
5169 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5173 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5174 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5178 static inline struct ixgbe_5tuple_filter *
5179 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5180 struct ixgbe_5tuple_filter_info *key)
5182 struct ixgbe_5tuple_filter *it;
5184 TAILQ_FOREACH(it, filter_list, entries) {
5185 if (memcmp(key, &it->filter_info,
5186 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5193 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5195 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5196 struct ixgbe_5tuple_filter_info *filter_info)
5198 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5199 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5200 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5203 switch (filter->dst_ip_mask) {
5205 filter_info->dst_ip_mask = 0;
5206 filter_info->dst_ip = filter->dst_ip;
5209 filter_info->dst_ip_mask = 1;
5212 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5216 switch (filter->src_ip_mask) {
5218 filter_info->src_ip_mask = 0;
5219 filter_info->src_ip = filter->src_ip;
5222 filter_info->src_ip_mask = 1;
5225 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5229 switch (filter->dst_port_mask) {
5231 filter_info->dst_port_mask = 0;
5232 filter_info->dst_port = filter->dst_port;
5235 filter_info->dst_port_mask = 1;
5238 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5242 switch (filter->src_port_mask) {
5244 filter_info->src_port_mask = 0;
5245 filter_info->src_port = filter->src_port;
5248 filter_info->src_port_mask = 1;
5251 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5255 switch (filter->proto_mask) {
5257 filter_info->proto_mask = 0;
5258 filter_info->proto =
5259 convert_protocol_type(filter->proto);
5262 filter_info->proto_mask = 1;
5265 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5269 filter_info->priority = (uint8_t)filter->priority;
5274 * add or delete a ntuple filter
5277 * dev: Pointer to struct rte_eth_dev.
5278 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5279 * add: if true, add filter, if false, remove filter
5282 * - On success, zero.
5283 * - On failure, a negative value.
5286 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5287 struct rte_eth_ntuple_filter *ntuple_filter,
5290 struct ixgbe_filter_info *filter_info =
5291 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5292 struct ixgbe_5tuple_filter_info filter_5tuple;
5293 struct ixgbe_5tuple_filter *filter;
5296 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5297 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5301 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5302 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5306 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5308 if (filter != NULL && add) {
5309 PMD_DRV_LOG(ERR, "filter exists.");
5312 if (filter == NULL && !add) {
5313 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5318 filter = rte_zmalloc("ixgbe_5tuple_filter",
5319 sizeof(struct ixgbe_5tuple_filter), 0);
5322 (void)rte_memcpy(&filter->filter_info,
5324 sizeof(struct ixgbe_5tuple_filter_info));
5325 filter->queue = ntuple_filter->queue;
5326 ret = ixgbe_add_5tuple_filter(dev, filter);
5332 ixgbe_remove_5tuple_filter(dev, filter);
5338 * get a ntuple filter
5341 * dev: Pointer to struct rte_eth_dev.
5342 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5345 * - On success, zero.
5346 * - On failure, a negative value.
5349 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5350 struct rte_eth_ntuple_filter *ntuple_filter)
5352 struct ixgbe_filter_info *filter_info =
5353 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5354 struct ixgbe_5tuple_filter_info filter_5tuple;
5355 struct ixgbe_5tuple_filter *filter;
5358 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5359 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5363 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5364 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5368 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5370 if (filter == NULL) {
5371 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5374 ntuple_filter->queue = filter->queue;
5379 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5380 * @dev: pointer to rte_eth_dev structure
5381 * @filter_op:operation will be taken.
5382 * @arg: a pointer to specific structure corresponding to the filter_op
5385 * - On success, zero.
5386 * - On failure, a negative value.
5389 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5390 enum rte_filter_op filter_op,
5393 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5396 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5398 if (filter_op == RTE_ETH_FILTER_NOP)
5402 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5407 switch (filter_op) {
5408 case RTE_ETH_FILTER_ADD:
5409 ret = ixgbe_add_del_ntuple_filter(dev,
5410 (struct rte_eth_ntuple_filter *)arg,
5413 case RTE_ETH_FILTER_DELETE:
5414 ret = ixgbe_add_del_ntuple_filter(dev,
5415 (struct rte_eth_ntuple_filter *)arg,
5418 case RTE_ETH_FILTER_GET:
5419 ret = ixgbe_get_ntuple_filter(dev,
5420 (struct rte_eth_ntuple_filter *)arg);
5423 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5431 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5436 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5437 if (filter_info->ethertype_filters[i] == ethertype &&
5438 (filter_info->ethertype_mask & (1 << i)))
5445 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5450 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5451 if (!(filter_info->ethertype_mask & (1 << i))) {
5452 filter_info->ethertype_mask |= 1 << i;
5453 filter_info->ethertype_filters[i] = ethertype;
5461 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5464 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5466 filter_info->ethertype_mask &= ~(1 << idx);
5467 filter_info->ethertype_filters[idx] = 0;
5472 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5473 struct rte_eth_ethertype_filter *filter,
5476 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5477 struct ixgbe_filter_info *filter_info =
5478 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5483 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5486 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5487 filter->ether_type == ETHER_TYPE_IPv6) {
5488 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5489 " ethertype filter.", filter->ether_type);
5493 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5494 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5497 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5498 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5502 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5503 if (ret >= 0 && add) {
5504 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5505 filter->ether_type);
5508 if (ret < 0 && !add) {
5509 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5510 filter->ether_type);
5515 ret = ixgbe_ethertype_filter_insert(filter_info,
5516 filter->ether_type);
5518 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5521 etqf = IXGBE_ETQF_FILTER_EN;
5522 etqf |= (uint32_t)filter->ether_type;
5523 etqs |= (uint32_t)((filter->queue <<
5524 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5525 IXGBE_ETQS_RX_QUEUE);
5526 etqs |= IXGBE_ETQS_QUEUE_EN;
5528 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5532 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5533 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5534 IXGBE_WRITE_FLUSH(hw);
5540 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5541 struct rte_eth_ethertype_filter *filter)
5543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544 struct ixgbe_filter_info *filter_info =
5545 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5546 uint32_t etqf, etqs;
5549 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5551 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5552 filter->ether_type);
5556 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5557 if (etqf & IXGBE_ETQF_FILTER_EN) {
5558 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5559 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5561 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5562 IXGBE_ETQS_RX_QUEUE_SHIFT;
5569 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5570 * @dev: pointer to rte_eth_dev structure
5571 * @filter_op:operation will be taken.
5572 * @arg: a pointer to specific structure corresponding to the filter_op
5575 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5576 enum rte_filter_op filter_op,
5579 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582 MAC_TYPE_FILTER_SUP(hw->mac.type);
5584 if (filter_op == RTE_ETH_FILTER_NOP)
5588 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5593 switch (filter_op) {
5594 case RTE_ETH_FILTER_ADD:
5595 ret = ixgbe_add_del_ethertype_filter(dev,
5596 (struct rte_eth_ethertype_filter *)arg,
5599 case RTE_ETH_FILTER_DELETE:
5600 ret = ixgbe_add_del_ethertype_filter(dev,
5601 (struct rte_eth_ethertype_filter *)arg,
5604 case RTE_ETH_FILTER_GET:
5605 ret = ixgbe_get_ethertype_filter(dev,
5606 (struct rte_eth_ethertype_filter *)arg);
5609 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5617 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5618 enum rte_filter_type filter_type,
5619 enum rte_filter_op filter_op,
5624 switch (filter_type) {
5625 case RTE_ETH_FILTER_NTUPLE:
5626 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5628 case RTE_ETH_FILTER_ETHERTYPE:
5629 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5631 case RTE_ETH_FILTER_SYN:
5632 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5634 case RTE_ETH_FILTER_FDIR:
5635 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5638 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5647 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5648 u8 **mc_addr_ptr, u32 *vmdq)
5653 mc_addr = *mc_addr_ptr;
5654 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5659 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5660 struct ether_addr *mc_addr_set,
5661 uint32_t nb_mc_addr)
5663 struct ixgbe_hw *hw;
5666 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5667 mc_addr_list = (u8 *)mc_addr_set;
5668 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5669 ixgbe_dev_addr_list_itr, TRUE);
5673 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5679 /* Enable system time for platforms where it isn't on by default. */
5680 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5681 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5682 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5684 /* Start incrementing the register used to timestamp PTP packets. */
5685 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5687 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5688 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5690 IXGBE_ETQF_FILTER_EN |
5693 /* Enable timestamping of received PTP packets. */
5694 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5695 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5696 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5698 /* Enable timestamping of transmitted PTP packets. */
5699 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5700 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5701 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5707 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712 /* Disable timestamping of transmitted PTP packets. */
5713 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5714 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5715 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5717 /* Disable timestamping of received PTP packets. */
5718 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5719 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5720 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5722 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5723 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5725 /* Stop incrementating the System Time registers. */
5726 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5732 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5733 struct timespec *timestamp,
5734 uint32_t flags __rte_unused)
5736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737 uint32_t tsync_rxctl;
5741 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5742 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5745 rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5746 rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5748 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5749 timestamp->tv_nsec = 0;
5755 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5756 struct timespec *timestamp)
5758 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5759 uint32_t tsync_txctl;
5763 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5764 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5767 tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5768 tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5770 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5771 timestamp->tv_nsec = 0;
5777 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782 const struct reg_info *reg_group;
5783 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5784 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5786 while ((reg_group = reg_set[g_ind++]))
5787 count += ixgbe_regs_group_count(reg_group);
5793 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5797 const struct reg_info *reg_group;
5799 while ((reg_group = ixgbevf_regs[g_ind++]))
5800 count += ixgbe_regs_group_count(reg_group);
5806 ixgbe_get_regs(struct rte_eth_dev *dev,
5807 struct rte_dev_reg_info *regs)
5809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5810 uint32_t *data = regs->data;
5813 const struct reg_info *reg_group;
5814 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5815 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5817 /* Support only full register dump */
5818 if ((regs->length == 0) ||
5819 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5820 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5822 while ((reg_group = reg_set[g_ind++]))
5823 count += ixgbe_read_regs_group(dev, &data[count],
5832 ixgbevf_get_regs(struct rte_eth_dev *dev,
5833 struct rte_dev_reg_info *regs)
5835 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836 uint32_t *data = regs->data;
5839 const struct reg_info *reg_group;
5841 /* Support only full register dump */
5842 if ((regs->length == 0) ||
5843 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5844 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5846 while ((reg_group = ixgbevf_regs[g_ind++]))
5847 count += ixgbe_read_regs_group(dev, &data[count],
5856 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860 /* Return unit is byte count */
5861 return hw->eeprom.word_size * 2;
5865 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5866 struct rte_dev_eeprom_info *in_eeprom)
5868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5870 uint16_t *data = in_eeprom->data;
5873 first = in_eeprom->offset >> 1;
5874 length = in_eeprom->length >> 1;
5875 if ((first > hw->eeprom.word_size) ||
5876 ((first + length) > hw->eeprom.word_size))
5879 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5881 return eeprom->ops.read_buffer(hw, first, length, data);
5885 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5886 struct rte_dev_eeprom_info *in_eeprom)
5888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5889 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5890 uint16_t *data = in_eeprom->data;
5893 first = in_eeprom->offset >> 1;
5894 length = in_eeprom->length >> 1;
5895 if ((first > hw->eeprom.word_size) ||
5896 ((first + length) > hw->eeprom.word_size))
5899 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5901 return eeprom->ops.write_buffer(hw, first, length, data);
5905 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5907 case ixgbe_mac_X550:
5908 case ixgbe_mac_X550EM_x:
5909 return ETH_RSS_RETA_SIZE_512;
5910 case ixgbe_mac_X550_vf:
5911 case ixgbe_mac_X550EM_x_vf:
5912 return ETH_RSS_RETA_SIZE_64;
5914 return ETH_RSS_RETA_SIZE_128;
5919 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5921 case ixgbe_mac_X550:
5922 case ixgbe_mac_X550EM_x:
5923 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5924 return IXGBE_RETA(reta_idx >> 2);
5926 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5927 case ixgbe_mac_X550_vf:
5928 case ixgbe_mac_X550EM_x_vf:
5929 return IXGBE_VFRETA(reta_idx >> 2);
5931 return IXGBE_RETA(reta_idx >> 2);
5936 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5938 case ixgbe_mac_X550_vf:
5939 case ixgbe_mac_X550EM_x_vf:
5940 return IXGBE_VFMRQC;
5947 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5949 case ixgbe_mac_X550_vf:
5950 case ixgbe_mac_X550EM_x_vf:
5951 return IXGBE_VFRSSRK(i);
5953 return IXGBE_RSSRK(i);
5958 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5960 case ixgbe_mac_82599_vf:
5961 case ixgbe_mac_X540_vf:
5969 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5970 struct rte_eth_dcb_info *dcb_info)
5972 struct ixgbe_dcb_config *dcb_config =
5973 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5974 struct ixgbe_dcb_tc_config *tc;
5977 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5978 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5980 dcb_info->nb_tcs = 1;
5982 if (dcb_config->vt_mode) { /* vt is enabled*/
5983 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5984 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5985 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5986 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5987 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5988 for (j = 0; j < dcb_info->nb_tcs; j++) {
5989 dcb_info->tc_queue.tc_rxq[i][j].base =
5990 i * dcb_info->nb_tcs + j;
5991 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5992 dcb_info->tc_queue.tc_txq[i][j].base =
5993 i * dcb_info->nb_tcs + j;
5994 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5997 } else { /* vt is disabled*/
5998 struct rte_eth_dcb_rx_conf *rx_conf =
5999 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6000 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6001 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6002 if (dcb_info->nb_tcs == ETH_4_TCS) {
6003 for (i = 0; i < dcb_info->nb_tcs; i++) {
6004 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6005 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6007 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6008 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6009 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6010 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6011 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6012 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6013 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6014 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6015 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6016 for (i = 0; i < dcb_info->nb_tcs; i++) {
6017 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6018 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6020 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6021 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6022 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6023 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6024 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6025 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6026 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6027 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6028 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6029 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6030 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6031 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6032 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6033 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6034 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6035 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6038 for (i = 0; i < dcb_info->nb_tcs; i++) {
6039 tc = &dcb_config->tc_config[i];
6040 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6045 static struct rte_driver rte_ixgbe_driver = {
6047 .init = rte_ixgbe_pmd_init,
6050 static struct rte_driver rte_ixgbevf_driver = {
6052 .init = rte_ixgbevf_pmd_init,
6055 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6056 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);