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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
42 /* need update link, bit flag */
43 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
44 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
45 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
46 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
49 * Defines that were not part of ixgbe_type.h as they are not used by the
52 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
53 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
54 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
55 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
56 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
57 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
58 #define IXGBE_NB_STAT_MAPPING_REGS 32
59 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
60 #define IXGBE_VFTA_SIZE 128
61 #define IXGBE_VLAN_TAG_SIZE 4
62 #define IXGBE_MAX_RX_QUEUE_NUM 128
63 #define IXGBE_MAX_INTR_QUEUE_NUM 15
64 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
65 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
69 #define NBBY 8 /* number of bits in a byte */
71 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
73 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
74 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
75 #define IXGBE_EITR_ITR_INT_SHIFT 3
76 #define IXGBE_EITR_INTERVAL_US(us) \
77 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
78 IXGBE_EITR_ITR_INT_MASK)
81 /* Loopback operation modes */
82 /* 82599 specific loopback operation types */
83 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
84 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
86 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
88 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
90 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
92 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
94 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
95 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
96 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
97 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
99 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
100 #define IXGBE_ETQF_SHIFT 16
101 #define IXGBE_ETQF_UP_EN 0x00080000
102 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
103 #define IXGBE_ETQF_MAX_PRI 7
105 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
106 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
107 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
109 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
110 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
111 #define IXGBE_L34T_IMIR_LLI 0x00100000
112 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
113 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
114 #define IXGBE_5TUPLE_MAX_PRI 7
115 #define IXGBE_5TUPLE_MIN_PRI 1
117 #define IXGBE_RSS_OFFLOAD_ALL ( \
119 ETH_RSS_NONFRAG_IPV4_TCP | \
120 ETH_RSS_NONFRAG_IPV4_UDP | \
122 ETH_RSS_NONFRAG_IPV6_TCP | \
123 ETH_RSS_NONFRAG_IPV6_UDP | \
125 ETH_RSS_IPV6_TCP_EX | \
128 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
129 #define IXGBE_VF_MAXMSIVECTOR 1
131 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
132 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
134 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
136 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 * Information about the fdir mode.
142 struct ixgbe_hw_fdir_mask {
143 uint16_t vlan_tci_mask;
144 uint32_t src_ipv4_mask;
145 uint32_t dst_ipv4_mask;
146 uint16_t src_ipv6_mask;
147 uint16_t dst_ipv6_mask;
148 uint16_t src_port_mask;
149 uint16_t dst_port_mask;
150 uint16_t flex_bytes_mask;
151 uint8_t mac_addr_byte_mask;
152 uint32_t tunnel_id_mask;
153 uint8_t tunnel_type_mask;
156 struct ixgbe_hw_fdir_info {
157 struct ixgbe_hw_fdir_mask mask;
158 uint8_t flex_bytes_offset;
169 /* structure for interrupt relative data */
170 struct ixgbe_interrupt {
175 struct ixgbe_stat_mapping_registers {
176 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
177 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
181 uint32_t vfta[IXGBE_VFTA_SIZE];
184 struct ixgbe_hwstrip {
185 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
189 * VF data which used by PF host only
191 #define IXGBE_MAX_VF_MC_ENTRIES 30
192 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
193 #define IXGBE_MAX_UTA 128
195 struct ixgbe_uta_info {
196 uint8_t uc_filter_type;
198 uint32_t uta_shadow[IXGBE_MAX_UTA];
201 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
203 struct ixgbe_mirror_info {
204 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
205 /**< store PF mirror rules configuration*/
208 struct ixgbe_vf_info {
209 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
210 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
211 uint16_t num_vf_mc_hashes;
212 uint16_t default_vf_vlan_id;
213 uint16_t vlans_enabled;
215 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
217 uint8_t spoofchk_enabled;
222 * Possible l4type of 5tuple filters.
224 enum ixgbe_5tuple_protocol {
225 IXGBE_FILTER_PROTOCOL_TCP = 0,
226 IXGBE_FILTER_PROTOCOL_UDP,
227 IXGBE_FILTER_PROTOCOL_SCTP,
228 IXGBE_FILTER_PROTOCOL_NONE,
231 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
233 struct ixgbe_5tuple_filter_info {
238 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
239 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
240 used when more than one filter matches. */
241 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
242 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
243 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
244 src_port_mask:1, /* if mask is 1b, do not compare src port. */
245 proto_mask:1; /* if mask is 1b, do not compare protocol. */
248 /* 5tuple filter structure */
249 struct ixgbe_5tuple_filter {
250 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
251 uint16_t index; /* the index of 5tuple filter */
252 struct ixgbe_5tuple_filter_info filter_info;
253 uint16_t queue; /* rx queue assigned to */
256 #define IXGBE_5TUPLE_ARRAY_SIZE \
257 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
258 (sizeof(uint32_t) * NBBY))
261 * Structure to store filters' info.
263 struct ixgbe_filter_info {
264 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
265 /* store used ethertype filters*/
266 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
267 /* Bit mask for every used 5tuple filter */
268 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
269 struct ixgbe_5tuple_filter_list fivetuple_list;
273 * Statistics counters collected by the MACsec
275 struct ixgbe_macsec_stats {
276 /* TX port statistics */
277 uint64_t out_pkts_untagged;
278 uint64_t out_pkts_encrypted;
279 uint64_t out_pkts_protected;
280 uint64_t out_octets_encrypted;
281 uint64_t out_octets_protected;
283 /* RX port statistics */
284 uint64_t in_pkts_untagged;
285 uint64_t in_pkts_badtag;
286 uint64_t in_pkts_nosci;
287 uint64_t in_pkts_unknownsci;
288 uint64_t in_octets_decrypted;
289 uint64_t in_octets_validated;
291 /* RX SC statistics */
292 uint64_t in_pkts_unchecked;
293 uint64_t in_pkts_delayed;
294 uint64_t in_pkts_late;
296 /* RX SA statistics */
298 uint64_t in_pkts_invalid;
299 uint64_t in_pkts_notvalid;
300 uint64_t in_pkts_unusedsa;
301 uint64_t in_pkts_notusingsa;
305 * Structure to store private data for each driver instance (for each port).
307 struct ixgbe_adapter {
309 struct ixgbe_hw_stats stats;
310 struct ixgbe_macsec_stats macsec_stats;
311 struct ixgbe_hw_fdir_info fdir;
312 struct ixgbe_interrupt intr;
313 struct ixgbe_stat_mapping_registers stat_mappings;
314 struct ixgbe_vfta shadow_vfta;
315 struct ixgbe_hwstrip hwstrip;
316 struct ixgbe_dcb_config dcb_config;
317 struct ixgbe_mirror_info mr_data;
318 struct ixgbe_vf_info *vfdata;
319 struct ixgbe_uta_info uta_info;
320 #ifdef RTE_NIC_BYPASS
321 struct ixgbe_bypass_info bps;
322 #endif /* RTE_NIC_BYPASS */
323 struct ixgbe_filter_info filter;
325 bool rx_bulk_alloc_allowed;
327 struct rte_timecounter systime_tc;
328 struct rte_timecounter rx_tstamp_tc;
329 struct rte_timecounter tx_tstamp_tc;
332 #define IXGBE_DEV_TO_PCI(eth_dev) \
333 RTE_DEV_TO_PCI((eth_dev)->device)
335 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
336 (&((struct ixgbe_adapter *)adapter)->hw)
338 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
339 (&((struct ixgbe_adapter *)adapter)->stats)
341 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
342 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
344 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
345 (&((struct ixgbe_adapter *)adapter)->intr)
347 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
348 (&((struct ixgbe_adapter *)adapter)->fdir)
350 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
351 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
353 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
354 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
356 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
357 (&((struct ixgbe_adapter *)adapter)->hwstrip)
359 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
360 (&((struct ixgbe_adapter *)adapter)->dcb_config)
362 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
363 (&((struct ixgbe_adapter *)adapter)->vfdata)
365 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
366 (&((struct ixgbe_adapter *)adapter)->mr_data)
368 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
369 (&((struct ixgbe_adapter *)adapter)->uta_info)
371 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
372 (&((struct ixgbe_adapter *)adapter)->filter)
375 * RX/TX function prototypes
377 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
379 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
381 void ixgbe_dev_rx_queue_release(void *rxq);
383 void ixgbe_dev_tx_queue_release(void *txq);
385 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
386 uint16_t nb_rx_desc, unsigned int socket_id,
387 const struct rte_eth_rxconf *rx_conf,
388 struct rte_mempool *mb_pool);
390 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
391 uint16_t nb_tx_desc, unsigned int socket_id,
392 const struct rte_eth_txconf *tx_conf);
394 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
395 uint16_t rx_queue_id);
397 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
398 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
400 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
402 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
404 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
406 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
408 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
410 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
412 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
414 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
415 struct rte_eth_rxq_info *qinfo);
417 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
418 struct rte_eth_txq_info *qinfo);
420 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
422 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
424 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
426 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
429 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
432 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
433 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
434 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
435 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
437 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
440 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
443 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
446 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
447 struct rte_eth_rss_conf *rss_conf);
449 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
450 struct rte_eth_rss_conf *rss_conf);
452 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
454 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
456 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
458 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
460 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
463 * Flow director function prototypes
465 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
467 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
470 * misc function prototypes
472 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
474 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
476 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
478 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
480 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
482 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
484 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
486 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
488 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
490 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
491 enum rte_filter_op filter_op, void *arg);
493 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
495 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
496 #endif /* _IXGBE_ETHDEV_H_ */