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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 * Defines that were not part of ixgbe_type.h as they are not used by the
53 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
54 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
55 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
56 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
57 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
58 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
59 #define IXGBE_NB_STAT_MAPPING_REGS 32
60 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
61 #define IXGBE_VFTA_SIZE 128
62 #define IXGBE_VLAN_TAG_SIZE 4
63 #define IXGBE_MAX_RX_QUEUE_NUM 128
64 #define IXGBE_MAX_INTR_QUEUE_NUM 15
65 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
70 #define NBBY 8 /* number of bits in a byte */
72 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
74 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
75 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
76 #define IXGBE_EITR_ITR_INT_SHIFT 3
77 #define IXGBE_EITR_INTERVAL_US(us) \
78 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
79 IXGBE_EITR_ITR_INT_MASK)
82 /* Loopback operation modes */
83 /* 82599 specific loopback operation types */
84 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
85 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
87 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
91 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
93 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
95 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
96 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
97 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
98 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
100 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
101 #define IXGBE_ETQF_SHIFT 16
102 #define IXGBE_ETQF_UP_EN 0x00080000
103 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
104 #define IXGBE_ETQF_MAX_PRI 7
106 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
107 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
108 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
110 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
111 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
112 #define IXGBE_L34T_IMIR_LLI 0x00100000
113 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
114 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
115 #define IXGBE_5TUPLE_MAX_PRI 7
116 #define IXGBE_5TUPLE_MIN_PRI 1
118 #define IXGBE_RSS_OFFLOAD_ALL ( \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
126 ETH_RSS_IPV6_TCP_EX | \
129 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
130 #define IXGBE_VF_MAXMSIVECTOR 1
132 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
137 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
140 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
143 * Information about the fdir mode.
145 struct ixgbe_hw_fdir_mask {
146 uint16_t vlan_tci_mask;
147 uint32_t src_ipv4_mask;
148 uint32_t dst_ipv4_mask;
149 uint16_t src_ipv6_mask;
150 uint16_t dst_ipv6_mask;
151 uint16_t src_port_mask;
152 uint16_t dst_port_mask;
153 uint16_t flex_bytes_mask;
154 uint8_t mac_addr_byte_mask;
155 uint32_t tunnel_id_mask;
156 uint8_t tunnel_type_mask;
159 struct ixgbe_fdir_filter {
160 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
161 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
162 uint32_t fdirflags; /* drop or forward */
163 uint32_t fdirhash; /* hash value for fdir */
164 uint8_t queue; /* assigned rx queue */
167 /* list of fdir filters */
168 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
170 struct ixgbe_hw_fdir_info {
171 struct ixgbe_hw_fdir_mask mask;
172 uint8_t flex_bytes_offset;
181 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
182 /* store the pointers of the filters, index is the hash value. */
183 struct ixgbe_fdir_filter **hash_map;
184 struct rte_hash *hash_handle; /* cuckoo hash handler */
187 /* structure for interrupt relative data */
188 struct ixgbe_interrupt {
193 struct ixgbe_stat_mapping_registers {
194 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
195 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
199 uint32_t vfta[IXGBE_VFTA_SIZE];
202 struct ixgbe_hwstrip {
203 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
207 * VF data which used by PF host only
209 #define IXGBE_MAX_VF_MC_ENTRIES 30
210 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
211 #define IXGBE_MAX_UTA 128
213 struct ixgbe_uta_info {
214 uint8_t uc_filter_type;
216 uint32_t uta_shadow[IXGBE_MAX_UTA];
219 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
221 struct ixgbe_mirror_info {
222 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
223 /**< store PF mirror rules configuration*/
226 struct ixgbe_vf_info {
227 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
228 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
229 uint16_t num_vf_mc_hashes;
230 uint16_t default_vf_vlan_id;
231 uint16_t vlans_enabled;
233 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
235 uint8_t spoofchk_enabled;
240 * Possible l4type of 5tuple filters.
242 enum ixgbe_5tuple_protocol {
243 IXGBE_FILTER_PROTOCOL_TCP = 0,
244 IXGBE_FILTER_PROTOCOL_UDP,
245 IXGBE_FILTER_PROTOCOL_SCTP,
246 IXGBE_FILTER_PROTOCOL_NONE,
249 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
251 struct ixgbe_5tuple_filter_info {
256 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
257 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
258 used when more than one filter matches. */
259 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
260 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
261 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
262 src_port_mask:1, /* if mask is 1b, do not compare src port. */
263 proto_mask:1; /* if mask is 1b, do not compare protocol. */
266 /* 5tuple filter structure */
267 struct ixgbe_5tuple_filter {
268 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
269 uint16_t index; /* the index of 5tuple filter */
270 struct ixgbe_5tuple_filter_info filter_info;
271 uint16_t queue; /* rx queue assigned to */
274 #define IXGBE_5TUPLE_ARRAY_SIZE \
275 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
276 (sizeof(uint32_t) * NBBY))
278 struct ixgbe_ethertype_filter {
285 * Structure to store filters' info.
287 struct ixgbe_filter_info {
288 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
289 /* store used ethertype filters*/
290 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
291 /* Bit mask for every used 5tuple filter */
292 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
293 struct ixgbe_5tuple_filter_list fivetuple_list;
294 /* store the SYN filter info */
298 struct ixgbe_l2_tn_key {
299 enum rte_eth_tunnel_type l2_tn_type;
303 struct ixgbe_l2_tn_filter {
304 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
305 struct ixgbe_l2_tn_key key;
309 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
311 struct ixgbe_l2_tn_info {
312 struct ixgbe_l2_tn_filter_list l2_tn_list;
313 struct ixgbe_l2_tn_filter **hash_map;
314 struct rte_hash *hash_handle;
318 * Statistics counters collected by the MACsec
320 struct ixgbe_macsec_stats {
321 /* TX port statistics */
322 uint64_t out_pkts_untagged;
323 uint64_t out_pkts_encrypted;
324 uint64_t out_pkts_protected;
325 uint64_t out_octets_encrypted;
326 uint64_t out_octets_protected;
328 /* RX port statistics */
329 uint64_t in_pkts_untagged;
330 uint64_t in_pkts_badtag;
331 uint64_t in_pkts_nosci;
332 uint64_t in_pkts_unknownsci;
333 uint64_t in_octets_decrypted;
334 uint64_t in_octets_validated;
336 /* RX SC statistics */
337 uint64_t in_pkts_unchecked;
338 uint64_t in_pkts_delayed;
339 uint64_t in_pkts_late;
341 /* RX SA statistics */
343 uint64_t in_pkts_invalid;
344 uint64_t in_pkts_notvalid;
345 uint64_t in_pkts_unusedsa;
346 uint64_t in_pkts_notusingsa;
350 * Structure to store private data for each driver instance (for each port).
352 struct ixgbe_adapter {
354 struct ixgbe_hw_stats stats;
355 struct ixgbe_macsec_stats macsec_stats;
356 struct ixgbe_hw_fdir_info fdir;
357 struct ixgbe_interrupt intr;
358 struct ixgbe_stat_mapping_registers stat_mappings;
359 struct ixgbe_vfta shadow_vfta;
360 struct ixgbe_hwstrip hwstrip;
361 struct ixgbe_dcb_config dcb_config;
362 struct ixgbe_mirror_info mr_data;
363 struct ixgbe_vf_info *vfdata;
364 struct ixgbe_uta_info uta_info;
365 #ifdef RTE_NIC_BYPASS
366 struct ixgbe_bypass_info bps;
367 #endif /* RTE_NIC_BYPASS */
368 struct ixgbe_filter_info filter;
369 struct ixgbe_l2_tn_info l2_tn;
371 bool rx_bulk_alloc_allowed;
373 struct rte_timecounter systime_tc;
374 struct rte_timecounter rx_tstamp_tc;
375 struct rte_timecounter tx_tstamp_tc;
378 #define IXGBE_DEV_TO_PCI(eth_dev) \
379 RTE_DEV_TO_PCI((eth_dev)->device)
381 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
382 (&((struct ixgbe_adapter *)adapter)->hw)
384 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
385 (&((struct ixgbe_adapter *)adapter)->stats)
387 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
388 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
390 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
391 (&((struct ixgbe_adapter *)adapter)->intr)
393 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
394 (&((struct ixgbe_adapter *)adapter)->fdir)
396 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
397 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
399 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
400 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
402 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
403 (&((struct ixgbe_adapter *)adapter)->hwstrip)
405 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
406 (&((struct ixgbe_adapter *)adapter)->dcb_config)
408 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
409 (&((struct ixgbe_adapter *)adapter)->vfdata)
411 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
412 (&((struct ixgbe_adapter *)adapter)->mr_data)
414 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
415 (&((struct ixgbe_adapter *)adapter)->uta_info)
417 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
418 (&((struct ixgbe_adapter *)adapter)->filter)
420 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
421 (&((struct ixgbe_adapter *)adapter)->l2_tn)
424 * RX/TX function prototypes
426 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
428 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
430 void ixgbe_dev_rx_queue_release(void *rxq);
432 void ixgbe_dev_tx_queue_release(void *txq);
434 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
435 uint16_t nb_rx_desc, unsigned int socket_id,
436 const struct rte_eth_rxconf *rx_conf,
437 struct rte_mempool *mb_pool);
439 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
440 uint16_t nb_tx_desc, unsigned int socket_id,
441 const struct rte_eth_txconf *tx_conf);
443 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
444 uint16_t rx_queue_id);
446 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
447 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
449 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
451 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
453 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
455 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
457 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
459 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
461 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
463 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
464 struct rte_eth_rxq_info *qinfo);
466 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
467 struct rte_eth_txq_info *qinfo);
469 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
471 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
473 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
475 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
478 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
481 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
482 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
483 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
484 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
486 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
489 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
492 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
495 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
496 struct rte_eth_rss_conf *rss_conf);
498 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
499 struct rte_eth_rss_conf *rss_conf);
501 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
503 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
505 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
507 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
509 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
512 * Flow director function prototypes
514 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
516 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
519 * misc function prototypes
521 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
523 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
525 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
527 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
529 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
531 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
533 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
535 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
537 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
539 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
540 enum rte_filter_op filter_op, void *arg);
542 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
544 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
547 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
552 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
553 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
554 (filter_info->ethertype_mask & (1 << i)))
561 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
562 struct ixgbe_ethertype_filter *ethertype_filter)
566 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
567 if (!(filter_info->ethertype_mask & (1 << i))) {
568 filter_info->ethertype_mask |= 1 << i;
569 filter_info->ethertype_filters[i].ethertype =
570 ethertype_filter->ethertype;
571 filter_info->ethertype_filters[i].etqf =
572 ethertype_filter->etqf;
573 filter_info->ethertype_filters[i].etqs =
574 ethertype_filter->etqs;
582 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
585 if (idx >= IXGBE_MAX_ETQF_FILTERS)
587 filter_info->ethertype_mask &= ~(1 << idx);
588 filter_info->ethertype_filters[idx].ethertype = 0;
589 filter_info->ethertype_filters[idx].etqf = 0;
590 filter_info->ethertype_filters[idx].etqs = 0;
594 #endif /* _IXGBE_ETHDEV_H_ */