4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 #include <rte_tm_driver.h>
45 /* need update link, bit flag */
46 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
47 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
48 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
49 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
53 * Defines that were not part of ixgbe_type.h as they are not used by the
56 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
57 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
58 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
59 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
60 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
61 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
62 #define IXGBE_NB_STAT_MAPPING_REGS 32
63 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
64 #define IXGBE_VFTA_SIZE 128
65 #define IXGBE_VLAN_TAG_SIZE 4
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
67 #define IXGBE_MAX_INTR_QUEUE_NUM 15
68 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
69 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
70 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
73 #define NBBY 8 /* number of bits in a byte */
75 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
77 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
78 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
79 #define IXGBE_EITR_ITR_INT_SHIFT 3
80 #define IXGBE_EITR_INTERVAL_US(us) \
81 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
82 IXGBE_EITR_ITR_INT_MASK)
85 /* Loopback operation modes */
86 /* 82599 specific loopback operation types */
87 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
88 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
90 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
92 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
93 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
94 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
96 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
98 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
99 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
100 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
101 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
103 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
104 #define IXGBE_ETQF_SHIFT 16
105 #define IXGBE_ETQF_UP_EN 0x00080000
106 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
107 #define IXGBE_ETQF_MAX_PRI 7
109 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
110 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
111 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
113 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
114 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
115 #define IXGBE_L34T_IMIR_LLI 0x00100000
116 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
117 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
118 #define IXGBE_5TUPLE_MAX_PRI 7
119 #define IXGBE_5TUPLE_MIN_PRI 1
121 #define IXGBE_RSS_OFFLOAD_ALL ( \
123 ETH_RSS_NONFRAG_IPV4_TCP | \
124 ETH_RSS_NONFRAG_IPV4_UDP | \
126 ETH_RSS_NONFRAG_IPV6_TCP | \
127 ETH_RSS_NONFRAG_IPV6_UDP | \
129 ETH_RSS_IPV6_TCP_EX | \
132 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
133 #define IXGBE_VF_MAXMSIVECTOR 1
135 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
136 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
138 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
140 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
142 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
143 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
145 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
146 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
150 #define MAC_TYPE_FILTER_SUP(type) do {\
151 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
152 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
153 (type) != ixgbe_mac_X550EM_a)\
158 * Information about the fdir mode.
160 struct ixgbe_hw_fdir_mask {
161 uint16_t vlan_tci_mask;
162 uint32_t src_ipv4_mask;
163 uint32_t dst_ipv4_mask;
164 uint16_t src_ipv6_mask;
165 uint16_t dst_ipv6_mask;
166 uint16_t src_port_mask;
167 uint16_t dst_port_mask;
168 uint16_t flex_bytes_mask;
169 uint8_t mac_addr_byte_mask;
170 uint32_t tunnel_id_mask;
171 uint8_t tunnel_type_mask;
174 struct ixgbe_fdir_filter {
175 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
176 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
177 uint32_t fdirflags; /* drop or forward */
178 uint32_t fdirhash; /* hash value for fdir */
179 uint8_t queue; /* assigned rx queue */
182 /* list of fdir filters */
183 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
185 struct ixgbe_fdir_rule {
186 struct ixgbe_hw_fdir_mask mask;
187 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
188 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
189 bool b_mask; /* If TRUE, mask has meaning. */
190 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
191 uint32_t fdirflags; /* drop or forward */
192 uint32_t soft_id; /* an unique value for this rule */
193 uint8_t queue; /* assigned rx queue */
194 uint8_t flex_bytes_offset;
197 struct ixgbe_hw_fdir_info {
198 struct ixgbe_hw_fdir_mask mask;
199 uint8_t flex_bytes_offset;
208 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
209 /* store the pointers of the filters, index is the hash value. */
210 struct ixgbe_fdir_filter **hash_map;
211 struct rte_hash *hash_handle; /* cuckoo hash handler */
212 bool mask_added; /* If already got mask from consistent filter */
215 /* structure for interrupt relative data */
216 struct ixgbe_interrupt {
219 /*to save original mask during delayed handler */
220 uint32_t mask_original;
223 struct ixgbe_stat_mapping_registers {
224 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
225 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
229 uint32_t vfta[IXGBE_VFTA_SIZE];
232 struct ixgbe_hwstrip {
233 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
237 * VF data which used by PF host only
239 #define IXGBE_MAX_VF_MC_ENTRIES 30
240 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
241 #define IXGBE_MAX_UTA 128
243 struct ixgbe_uta_info {
244 uint8_t uc_filter_type;
246 uint32_t uta_shadow[IXGBE_MAX_UTA];
249 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
251 struct ixgbe_mirror_info {
252 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
253 /**< store PF mirror rules configuration*/
256 struct ixgbe_vf_info {
257 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
258 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
259 uint16_t num_vf_mc_hashes;
260 uint16_t default_vf_vlan_id;
261 uint16_t vlans_enabled;
263 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
265 uint8_t spoofchk_enabled;
270 * Possible l4type of 5tuple filters.
272 enum ixgbe_5tuple_protocol {
273 IXGBE_FILTER_PROTOCOL_TCP = 0,
274 IXGBE_FILTER_PROTOCOL_UDP,
275 IXGBE_FILTER_PROTOCOL_SCTP,
276 IXGBE_FILTER_PROTOCOL_NONE,
279 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
281 struct ixgbe_5tuple_filter_info {
286 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
287 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
288 used when more than one filter matches. */
289 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
290 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
291 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
292 src_port_mask:1, /* if mask is 1b, do not compare src port. */
293 proto_mask:1; /* if mask is 1b, do not compare protocol. */
296 /* 5tuple filter structure */
297 struct ixgbe_5tuple_filter {
298 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
299 uint16_t index; /* the index of 5tuple filter */
300 struct ixgbe_5tuple_filter_info filter_info;
301 uint16_t queue; /* rx queue assigned to */
304 #define IXGBE_5TUPLE_ARRAY_SIZE \
305 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
306 (sizeof(uint32_t) * NBBY))
308 struct ixgbe_ethertype_filter {
313 * If this filter is added by configuration,
314 * it should not be removed.
320 * Structure to store filters' info.
322 struct ixgbe_filter_info {
323 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
324 /* store used ethertype filters*/
325 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
326 /* Bit mask for every used 5tuple filter */
327 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
328 struct ixgbe_5tuple_filter_list fivetuple_list;
329 /* store the SYN filter info */
333 struct ixgbe_l2_tn_key {
334 enum rte_eth_tunnel_type l2_tn_type;
338 struct ixgbe_l2_tn_filter {
339 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
340 struct ixgbe_l2_tn_key key;
344 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
346 struct ixgbe_l2_tn_info {
347 struct ixgbe_l2_tn_filter_list l2_tn_list;
348 struct ixgbe_l2_tn_filter **hash_map;
349 struct rte_hash *hash_handle;
350 bool e_tag_en; /* e-tag enabled */
351 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
352 bool e_tag_ether_type; /* ether type for e-tag */
356 enum rte_filter_type filter_type;
359 /* ntuple filter list structure */
360 struct ixgbe_ntuple_filter_ele {
361 TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
362 struct rte_eth_ntuple_filter filter_info;
364 /* ethertype filter list structure */
365 struct ixgbe_ethertype_filter_ele {
366 TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
367 struct rte_eth_ethertype_filter filter_info;
369 /* syn filter list structure */
370 struct ixgbe_eth_syn_filter_ele {
371 TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
372 struct rte_eth_syn_filter filter_info;
374 /* fdir filter list structure */
375 struct ixgbe_fdir_rule_ele {
376 TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
377 struct ixgbe_fdir_rule filter_info;
379 /* l2_tunnel filter list structure */
380 struct ixgbe_eth_l2_tunnel_conf_ele {
381 TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
382 struct rte_eth_l2_tunnel_conf filter_info;
384 /* ixgbe_flow memory list structure */
385 struct ixgbe_flow_mem {
386 TAILQ_ENTRY(ixgbe_flow_mem) entries;
387 struct rte_flow *flow;
390 TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
391 struct ixgbe_ntuple_filter_list filter_ntuple_list;
392 TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
393 struct ixgbe_ethertype_filter_list filter_ethertype_list;
394 TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
395 struct ixgbe_syn_filter_list filter_syn_list;
396 TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
397 struct ixgbe_fdir_rule_filter_list filter_fdir_list;
398 TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
399 struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
400 TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
401 struct ixgbe_flow_mem_list ixgbe_flow_list;
404 * Statistics counters collected by the MACsec
406 struct ixgbe_macsec_stats {
407 /* TX port statistics */
408 uint64_t out_pkts_untagged;
409 uint64_t out_pkts_encrypted;
410 uint64_t out_pkts_protected;
411 uint64_t out_octets_encrypted;
412 uint64_t out_octets_protected;
414 /* RX port statistics */
415 uint64_t in_pkts_untagged;
416 uint64_t in_pkts_badtag;
417 uint64_t in_pkts_nosci;
418 uint64_t in_pkts_unknownsci;
419 uint64_t in_octets_decrypted;
420 uint64_t in_octets_validated;
422 /* RX SC statistics */
423 uint64_t in_pkts_unchecked;
424 uint64_t in_pkts_delayed;
425 uint64_t in_pkts_late;
427 /* RX SA statistics */
429 uint64_t in_pkts_invalid;
430 uint64_t in_pkts_notvalid;
431 uint64_t in_pkts_unusedsa;
432 uint64_t in_pkts_notusingsa;
435 /* The configuration of bandwidth */
436 struct ixgbe_bw_conf {
437 uint8_t tc_num; /* Number of TCs. */
441 * Structure to store private data for each driver instance (for each port).
443 struct ixgbe_adapter {
445 struct ixgbe_hw_stats stats;
446 struct ixgbe_macsec_stats macsec_stats;
447 struct ixgbe_hw_fdir_info fdir;
448 struct ixgbe_interrupt intr;
449 struct ixgbe_stat_mapping_registers stat_mappings;
450 struct ixgbe_vfta shadow_vfta;
451 struct ixgbe_hwstrip hwstrip;
452 struct ixgbe_dcb_config dcb_config;
453 struct ixgbe_mirror_info mr_data;
454 struct ixgbe_vf_info *vfdata;
455 struct ixgbe_uta_info uta_info;
456 #ifdef RTE_LIBRTE_IXGBE_BYPASS
457 struct ixgbe_bypass_info bps;
458 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
459 struct ixgbe_filter_info filter;
460 struct ixgbe_l2_tn_info l2_tn;
461 struct ixgbe_bw_conf bw_conf;
463 bool rx_bulk_alloc_allowed;
465 struct rte_timecounter systime_tc;
466 struct rte_timecounter rx_tstamp_tc;
467 struct rte_timecounter tx_tstamp_tc;
470 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
471 (&((struct ixgbe_adapter *)adapter)->hw)
473 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
474 (&((struct ixgbe_adapter *)adapter)->stats)
476 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
477 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
479 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
480 (&((struct ixgbe_adapter *)adapter)->intr)
482 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
483 (&((struct ixgbe_adapter *)adapter)->fdir)
485 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
486 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
488 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
489 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
491 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
492 (&((struct ixgbe_adapter *)adapter)->hwstrip)
494 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
495 (&((struct ixgbe_adapter *)adapter)->dcb_config)
497 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
498 (&((struct ixgbe_adapter *)adapter)->vfdata)
500 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
501 (&((struct ixgbe_adapter *)adapter)->mr_data)
503 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
504 (&((struct ixgbe_adapter *)adapter)->uta_info)
506 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
507 (&((struct ixgbe_adapter *)adapter)->filter)
509 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
510 (&((struct ixgbe_adapter *)adapter)->l2_tn)
512 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
513 (&((struct ixgbe_adapter *)adapter)->bw_conf)
516 * RX/TX function prototypes
518 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
520 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
522 void ixgbe_dev_rx_queue_release(void *rxq);
524 void ixgbe_dev_tx_queue_release(void *txq);
526 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
527 uint16_t nb_rx_desc, unsigned int socket_id,
528 const struct rte_eth_rxconf *rx_conf,
529 struct rte_mempool *mb_pool);
531 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
532 uint16_t nb_tx_desc, unsigned int socket_id,
533 const struct rte_eth_txconf *tx_conf);
535 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
536 uint16_t rx_queue_id);
538 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
540 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
541 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
543 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
545 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
547 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
549 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
551 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
553 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
555 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
557 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
558 struct rte_eth_rxq_info *qinfo);
560 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
561 struct rte_eth_txq_info *qinfo);
563 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
565 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
567 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
569 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
572 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
575 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
576 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
577 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
578 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
580 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
583 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
586 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
589 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
590 struct rte_eth_rss_conf *rss_conf);
592 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
593 struct rte_eth_rss_conf *rss_conf);
595 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
597 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
599 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
601 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
603 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
605 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
606 struct rte_eth_ntuple_filter *filter,
608 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
609 struct rte_eth_ethertype_filter *filter,
611 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
612 struct rte_eth_syn_filter *filter,
615 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
616 struct rte_eth_l2_tunnel_conf *l2_tunnel,
619 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
620 struct rte_eth_l2_tunnel_conf *l2_tunnel);
621 void ixgbe_filterlist_flush(void);
623 * Flow director function prototypes
625 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
626 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
627 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
629 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
630 struct ixgbe_fdir_rule *rule,
631 bool del, bool update);
633 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
636 * misc function prototypes
638 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
640 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
642 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
644 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
646 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
648 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
650 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
652 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
654 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
656 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
657 enum rte_filter_op filter_op, void *arg);
658 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
659 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
661 extern const struct rte_flow_ops ixgbe_flow_ops;
663 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
664 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
665 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
666 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
668 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
670 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
672 int ixgbe_vt_check(struct ixgbe_hw *hw);
673 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
674 uint16_t tx_rate, uint64_t q_msk);
675 bool is_ixgbe_supported(struct rte_eth_dev *dev);
676 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
679 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
684 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
685 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
686 (filter_info->ethertype_mask & (1 << i)))
693 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
694 struct ixgbe_ethertype_filter *ethertype_filter)
698 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
699 if (!(filter_info->ethertype_mask & (1 << i))) {
700 filter_info->ethertype_mask |= 1 << i;
701 filter_info->ethertype_filters[i].ethertype =
702 ethertype_filter->ethertype;
703 filter_info->ethertype_filters[i].etqf =
704 ethertype_filter->etqf;
705 filter_info->ethertype_filters[i].etqs =
706 ethertype_filter->etqs;
707 filter_info->ethertype_filters[i].conf =
708 ethertype_filter->conf;
716 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
719 if (idx >= IXGBE_MAX_ETQF_FILTERS)
721 filter_info->ethertype_mask &= ~(1 << idx);
722 filter_info->ethertype_filters[idx].ethertype = 0;
723 filter_info->ethertype_filters[idx].etqf = 0;
724 filter_info->ethertype_filters[idx].etqs = 0;
725 filter_info->ethertype_filters[idx].etqs = FALSE;
729 #endif /* _IXGBE_ETHDEV_H_ */