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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
55 #define IXGBE_MAX_VFTA (128)
56 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
57 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
58 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
60 static inline uint16_t
61 dev_num_vf(struct rte_eth_dev *eth_dev)
63 return eth_dev->pci_dev->max_vfs;
67 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
69 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
70 struct ixgbe_vf_info *vfinfo =
71 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
74 for (vfn = 0; vfn < vf_num; vfn++) {
75 eth_random_addr(vf_mac_addr);
76 /* keep the random address as default */
77 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
85 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
87 struct ixgbe_interrupt *intr =
88 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
90 intr->mask |= IXGBE_EICR_MAILBOX;
95 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
97 struct ixgbe_vf_info **vfinfo =
98 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
99 struct ixgbe_mirror_info *mirror_info =
100 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
101 struct ixgbe_uta_info *uta_info =
102 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
103 struct ixgbe_hw *hw =
104 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
108 PMD_INIT_FUNC_TRACE();
110 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
111 if (0 == (vf_num = dev_num_vf(eth_dev)))
114 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
116 rte_panic("Cannot allocate memory for private VF data\n");
118 memset(mirror_info,0,sizeof(struct ixgbe_mirror_info));
119 memset(uta_info,0,sizeof(struct ixgbe_uta_info));
120 hw->mac.mc_filter_type = 0;
122 if (vf_num >= ETH_32_POOLS) {
124 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
125 } else if (vf_num >= ETH_16_POOLS) {
127 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
130 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
133 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
134 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
135 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
137 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
139 /* init_mailbox_params */
140 hw->mbx.ops.init_params(hw);
142 /* set mb interrupt mask */
143 ixgbe_mb_intr_setup(eth_dev);
148 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
150 struct ixgbe_vf_info **vfinfo;
153 PMD_INIT_FUNC_TRACE();
155 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
157 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
158 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
159 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
160 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
162 vf_num = dev_num_vf(eth_dev);
171 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
173 struct ixgbe_hw *hw =
174 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
175 struct ixgbe_filter_info *filter_info =
176 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
180 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
181 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
186 /* occupy an entity of ether type filter */
187 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
188 if (!(filter_info->ethertype_mask & (1 << i))) {
189 filter_info->ethertype_mask |= 1 << i;
190 filter_info->ethertype_filters[i] =
191 IXGBE_ETHERTYPE_FLOW_CTRL;
195 if (i == IXGBE_MAX_ETQF_FILTERS) {
196 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
197 " entity for flow control.\n");
201 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
202 (IXGBE_ETQF_FILTER_EN |
203 IXGBE_ETQF_TX_ANTISPOOF |
204 IXGBE_ETHERTYPE_FLOW_CTRL));
206 vf_num = dev_num_vf(eth_dev);
207 for (i = 0; i < vf_num; i++)
208 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
211 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
213 uint32_t vtctl, fcrth;
214 uint32_t vfre_slot, vfre_offset;
216 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
217 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
219 uint32_t gpie, gcr_ext;
223 if (0 == (vf_num = dev_num_vf(eth_dev)))
226 /* enable VMDq and set the default pool for PF */
227 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
228 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
229 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
230 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
231 << IXGBE_VT_CTL_POOL_SHIFT;
232 vtctl |= IXGBE_VT_CTL_REPLEN;
233 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
235 vfre_offset = vf_num & VFRE_MASK;
236 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
238 /* Enable pools reserved to PF only */
239 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
240 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
241 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
242 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
244 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
245 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
247 /* clear VMDq map to perment rar 0 */
248 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
250 /* clear VMDq map to scan rar 127 */
251 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
252 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
254 /* set VMDq map to default PF pool */
255 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
258 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
260 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
261 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
263 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
264 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
265 gpie |= IXGBE_GPIE_MSIX_MODE;
267 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
269 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
270 gpie |= IXGBE_GPIE_VTMODE_64;
273 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
274 gpie |= IXGBE_GPIE_VTMODE_32;
277 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
278 gpie |= IXGBE_GPIE_VTMODE_16;
282 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
283 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
286 * enable vlan filtering and allow all vlan tags through
288 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
289 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
290 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
292 /* VFTA - enable all vlan filters */
293 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
294 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
297 /* Enable MAC Anti-Spoofing */
298 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
300 /* set flow control threshold to max to avoid tx switch hang */
301 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
303 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
304 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
307 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
313 set_rx_mode(struct rte_eth_dev *dev)
315 struct rte_eth_dev_data *dev_data =
316 (struct rte_eth_dev_data*)dev->data->dev_private;
317 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
318 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
319 uint16_t vfn = dev_num_vf(dev);
321 /* Check for Promiscuous and All Multicast modes */
322 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
324 /* set all bits that we expect to always be set */
325 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
326 fctrl |= IXGBE_FCTRL_BAM;
328 /* clear the bits we are changing the status of */
329 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
331 if (dev_data->promiscuous) {
332 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
333 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
335 if (dev_data->all_multicast) {
336 fctrl |= IXGBE_FCTRL_MPE;
337 vmolr |= IXGBE_VMOLR_MPE;
339 vmolr |= IXGBE_VMOLR_ROMPE;
343 if (hw->mac.type != ixgbe_mac_82598EB) {
344 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
345 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
347 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
350 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
352 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
353 ixgbe_vlan_hw_strip_enable_all(dev);
355 ixgbe_vlan_hw_strip_disable_all(dev);
359 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
361 struct ixgbe_hw *hw =
362 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
363 struct ixgbe_vf_info *vfinfo =
364 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
365 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
366 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
368 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
369 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
370 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
372 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
374 /* reset multicast table array for vf */
375 vfinfo[vf].num_vf_mc_hashes = 0;
380 hw->mac.ops.clear_rar(hw, rar_entry);
384 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 uint32_t reg_offset, vf_shift;
389 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
390 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
392 vf_shift = vf & VFRE_MASK;
393 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
395 /* enable transmit and receive for vf */
396 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
397 reg |= (reg | (1 << vf_shift));
398 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
400 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
401 reg |= (reg | (1 << vf_shift));
402 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
404 /* Enable counting of spoofed packets in the SSVPC register */
405 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
406 reg |= (1 << vf_shift);
407 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
409 ixgbe_vf_reset_event(dev, vf);
413 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
415 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
416 struct ixgbe_vf_info *vfinfo =
417 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
418 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
419 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
420 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
422 ixgbe_vf_reset_msg(dev, vf);
424 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
426 /* reply to reset with ack and vf mac address */
427 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
428 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
430 * Piggyback the multicast filter type so VF can compute the
433 msgbuf[3] = hw->mac.mc_filter_type;
434 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
440 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
442 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
443 struct ixgbe_vf_info *vfinfo =
444 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
445 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
446 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
448 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
449 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
450 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
456 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 struct ixgbe_vf_info *vfinfo =
460 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
461 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
462 IXGBE_VT_MSGINFO_SHIFT;
463 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
466 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
467 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
468 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
472 /* only so many hash values supported */
473 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
475 /* store the mc entries */
476 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
477 for (i = 0; i < nb_entries; i++) {
478 vfinfo->vf_mc_hashes[i] = hash_list[i];
481 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
482 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
483 & IXGBE_MTA_INDEX_MASK;
484 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
485 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
486 reg_val |= (1 << mta_shift);
487 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
494 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
498 struct ixgbe_vf_info *vfinfo =
499 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
501 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
502 >> IXGBE_VT_MSGINFO_SHIFT;
503 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
506 vfinfo[vf].vlan_count++;
507 else if (vfinfo[vf].vlan_count)
508 vfinfo[vf].vlan_count--;
509 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
513 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
516 uint32_t new_mtu = msgbuf[1];
518 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
520 /* X540 and X550 support jumbo frames in IOV mode */
521 if (hw->mac.type != ixgbe_mac_X540 &&
522 hw->mac.type != ixgbe_mac_X550 &&
523 hw->mac.type != ixgbe_mac_X550EM_x)
526 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
529 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
530 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
531 if (max_frs < new_mtu) {
532 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
533 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
540 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
542 uint32_t api_version = msgbuf[1];
543 struct ixgbe_vf_info *vfinfo =
544 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
546 switch (api_version) {
547 case ixgbe_mbox_api_10:
548 case ixgbe_mbox_api_11:
549 vfinfo[vf].api_version = (uint8_t)api_version;
555 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
562 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
564 struct ixgbe_vf_info *vfinfo =
565 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
566 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
568 /* Verify if the PF supports the mbox APIs version or not */
569 switch (vfinfo[vf].api_version) {
570 case ixgbe_mbox_api_20:
571 case ixgbe_mbox_api_11:
577 /* Notify VF of Rx and Tx queue number */
578 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
579 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
581 /* Notify VF of default queue */
582 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
585 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
586 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
593 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
595 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
596 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
597 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
599 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
600 struct ixgbe_vf_info *vfinfo =
601 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
603 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
605 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
609 /* do nothing with the message already been processed */
610 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
613 /* flush the ack before we write any messages back */
614 IXGBE_WRITE_FLUSH(hw);
616 /* perform VF reset */
617 if (msgbuf[0] == IXGBE_VF_RESET) {
618 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
619 vfinfo[vf].clear_to_send = true;
623 /* check & process VF to PF mailbox message */
624 switch ((msgbuf[0] & 0xFFFF)) {
625 case IXGBE_VF_SET_MAC_ADDR:
626 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
628 case IXGBE_VF_SET_MULTICAST:
629 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
631 case IXGBE_VF_SET_LPE:
632 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
634 case IXGBE_VF_SET_VLAN:
635 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
637 case IXGBE_VF_API_NEGOTIATE:
638 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
640 case IXGBE_VF_GET_QUEUES:
641 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
642 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
645 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
646 retval = IXGBE_ERR_MBX;
650 /* response the VF according to the message process result */
652 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
654 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
656 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
658 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
664 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
666 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
667 struct ixgbe_hw *hw =
668 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
669 struct ixgbe_vf_info *vfinfo =
670 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
672 if (!vfinfo[vf].clear_to_send)
673 ixgbe_write_mbx(hw, &msg, 1, vf);
676 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
679 struct ixgbe_hw *hw =
680 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
682 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
683 /* check & process vf function level reset */
684 if (!ixgbe_check_for_rst(hw, vf))
685 ixgbe_vf_reset_event(eth_dev, vf);
687 /* check & process vf mailbox messages */
688 if (!ixgbe_check_for_msg(hw, vf))
689 ixgbe_rcv_msg_from_vf(eth_dev, vf);
691 /* check & process acks from vf */
692 if (!ixgbe_check_for_ack(hw, vf))
693 ixgbe_rcv_ack_from_vf(eth_dev, vf);