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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
54 #include "rte_pmd_ixgbe.h"
56 #define IXGBE_MAX_VFTA (128)
57 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
58 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
59 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
61 static inline uint16_t
62 dev_num_vf(struct rte_eth_dev *eth_dev)
64 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
66 return pci_dev->max_vfs;
70 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
72 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
73 struct ixgbe_vf_info *vfinfo =
74 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
77 for (vfn = 0; vfn < vf_num; vfn++) {
78 eth_random_addr(vf_mac_addr);
79 /* keep the random address as default */
80 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
88 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
90 struct ixgbe_interrupt *intr =
91 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
93 intr->mask |= IXGBE_EICR_MAILBOX;
98 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
100 struct ixgbe_vf_info **vfinfo =
101 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
102 struct ixgbe_mirror_info *mirror_info =
103 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
104 struct ixgbe_uta_info *uta_info =
105 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
106 struct ixgbe_hw *hw =
107 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
111 PMD_INIT_FUNC_TRACE();
113 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
114 vf_num = dev_num_vf(eth_dev);
118 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
120 rte_panic("Cannot allocate memory for private VF data\n");
122 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
123 memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
124 hw->mac.mc_filter_type = 0;
126 if (vf_num >= ETH_32_POOLS) {
128 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
129 } else if (vf_num >= ETH_16_POOLS) {
131 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
134 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
137 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
138 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
139 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
141 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
143 /* init_mailbox_params */
144 hw->mbx.ops.init_params(hw);
146 /* set mb interrupt mask */
147 ixgbe_mb_intr_setup(eth_dev);
150 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
152 struct ixgbe_vf_info **vfinfo;
155 PMD_INIT_FUNC_TRACE();
157 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
159 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
160 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
161 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
162 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
164 vf_num = dev_num_vf(eth_dev);
173 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
175 struct ixgbe_hw *hw =
176 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
177 struct ixgbe_filter_info *filter_info =
178 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
182 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
183 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
188 /* occupy an entity of ether type filter */
189 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
190 if (!(filter_info->ethertype_mask & (1 << i))) {
191 filter_info->ethertype_mask |= 1 << i;
192 filter_info->ethertype_filters[i] =
193 IXGBE_ETHERTYPE_FLOW_CTRL;
197 if (i == IXGBE_MAX_ETQF_FILTERS) {
198 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
199 " entity for flow control.\n");
203 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
204 (IXGBE_ETQF_FILTER_EN |
205 IXGBE_ETQF_TX_ANTISPOOF |
206 IXGBE_ETHERTYPE_FLOW_CTRL));
208 vf_num = dev_num_vf(eth_dev);
209 for (i = 0; i < vf_num; i++)
210 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
213 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
215 uint32_t vtctl, fcrth;
216 uint32_t vfre_slot, vfre_offset;
218 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
219 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
221 uint32_t gpie, gcr_ext;
225 vf_num = dev_num_vf(eth_dev);
229 /* enable VMDq and set the default pool for PF */
230 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
231 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
232 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
233 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
234 << IXGBE_VT_CTL_POOL_SHIFT;
235 vtctl |= IXGBE_VT_CTL_REPLEN;
236 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
238 vfre_offset = vf_num & VFRE_MASK;
239 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
241 /* Enable pools reserved to PF only */
242 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
243 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
244 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
245 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
247 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
248 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
250 /* clear VMDq map to perment rar 0 */
251 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
253 /* clear VMDq map to scan rar 127 */
254 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
255 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
257 /* set VMDq map to default PF pool */
258 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
261 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
263 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
264 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
266 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
267 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
268 gpie |= IXGBE_GPIE_MSIX_MODE;
270 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
272 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
273 gpie |= IXGBE_GPIE_VTMODE_64;
276 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
277 gpie |= IXGBE_GPIE_VTMODE_32;
280 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
281 gpie |= IXGBE_GPIE_VTMODE_16;
285 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
286 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
289 * enable vlan filtering and allow all vlan tags through
291 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
292 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
293 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
295 /* VFTA - enable all vlan filters */
296 for (i = 0; i < IXGBE_MAX_VFTA; i++)
297 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
299 /* Enable MAC Anti-Spoofing */
300 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
302 /* set flow control threshold to max to avoid tx switch hang */
303 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
304 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
305 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
306 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
309 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
315 set_rx_mode(struct rte_eth_dev *dev)
317 struct rte_eth_dev_data *dev_data = dev->data;
318 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
320 uint16_t vfn = dev_num_vf(dev);
322 /* Check for Promiscuous and All Multicast modes */
323 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
325 /* set all bits that we expect to always be set */
326 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
327 fctrl |= IXGBE_FCTRL_BAM;
329 /* clear the bits we are changing the status of */
330 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
332 if (dev_data->promiscuous) {
333 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
334 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
336 if (dev_data->all_multicast) {
337 fctrl |= IXGBE_FCTRL_MPE;
338 vmolr |= IXGBE_VMOLR_MPE;
340 vmolr |= IXGBE_VMOLR_ROMPE;
344 if (hw->mac.type != ixgbe_mac_82598EB) {
345 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
346 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
348 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
351 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
353 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
354 ixgbe_vlan_hw_strip_enable_all(dev);
356 ixgbe_vlan_hw_strip_disable_all(dev);
360 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
362 struct ixgbe_hw *hw =
363 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
364 struct ixgbe_vf_info *vfinfo =
365 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
366 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
367 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
369 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
370 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
371 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
373 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
375 /* reset multicast table array for vf */
376 vfinfo[vf].num_vf_mc_hashes = 0;
381 hw->mac.ops.clear_rar(hw, rar_entry);
385 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
387 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
389 uint32_t reg_offset, vf_shift;
390 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
391 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
393 vf_shift = vf & VFRE_MASK;
394 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
396 /* enable transmit and receive for vf */
397 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
398 reg |= (reg | (1 << vf_shift));
399 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
401 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
402 reg |= (reg | (1 << vf_shift));
403 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
405 /* Enable counting of spoofed packets in the SSVPC register */
406 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
407 reg |= (1 << vf_shift);
408 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
410 ixgbe_vf_reset_event(dev, vf);
414 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
416 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
419 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
421 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf);
423 vmolr |= IXGBE_VMOLR_MPE;
425 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
431 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
436 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
438 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
440 vmolr &= ~IXGBE_VMOLR_MPE;
442 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
448 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
450 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
451 struct ixgbe_vf_info *vfinfo =
452 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
453 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
454 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
455 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
457 ixgbe_vf_reset_msg(dev, vf);
459 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
461 /* Disable multicast promiscuous at reset */
462 ixgbe_disable_vf_mc_promisc(dev, vf);
464 /* reply to reset with ack and vf mac address */
465 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
466 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
468 * Piggyback the multicast filter type so VF can compute the
471 msgbuf[3] = hw->mac.mc_filter_type;
472 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
478 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
481 struct ixgbe_vf_info *vfinfo =
482 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
483 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
484 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
486 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
487 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
488 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
494 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
497 struct ixgbe_vf_info *vfinfo =
498 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
499 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
500 IXGBE_VT_MSGINFO_SHIFT;
501 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
504 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
505 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
506 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
510 /* Disable multicast promiscuous first */
511 ixgbe_disable_vf_mc_promisc(dev, vf);
513 /* only so many hash values supported */
514 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
516 /* store the mc entries */
517 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
518 for (i = 0; i < nb_entries; i++) {
519 vfinfo->vf_mc_hashes[i] = hash_list[i];
522 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
523 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
524 & IXGBE_MTA_INDEX_MASK;
525 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
526 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
527 reg_val |= (1 << mta_shift);
528 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
535 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
538 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
539 struct ixgbe_vf_info *vfinfo =
540 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
542 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
543 >> IXGBE_VT_MSGINFO_SHIFT;
544 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
547 vfinfo[vf].vlan_count++;
548 else if (vfinfo[vf].vlan_count)
549 vfinfo[vf].vlan_count--;
550 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
554 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
556 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
557 uint32_t new_mtu = msgbuf[1];
559 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
561 /* X540 and X550 support jumbo frames in IOV mode */
562 if (hw->mac.type != ixgbe_mac_X540 &&
563 hw->mac.type != ixgbe_mac_X550 &&
564 hw->mac.type != ixgbe_mac_X550EM_x &&
565 hw->mac.type != ixgbe_mac_X550EM_a)
568 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
571 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
572 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
573 if (max_frs < new_mtu) {
574 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
575 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
582 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
584 uint32_t api_version = msgbuf[1];
585 struct ixgbe_vf_info *vfinfo =
586 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
588 switch (api_version) {
589 case ixgbe_mbox_api_10:
590 case ixgbe_mbox_api_11:
591 case ixgbe_mbox_api_12:
592 vfinfo[vf].api_version = (uint8_t)api_version;
598 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
605 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
607 struct ixgbe_vf_info *vfinfo =
608 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
609 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
611 /* Verify if the PF supports the mbox APIs version or not */
612 switch (vfinfo[vf].api_version) {
613 case ixgbe_mbox_api_20:
614 case ixgbe_mbox_api_11:
615 case ixgbe_mbox_api_12:
621 /* Notify VF of Rx and Tx queue number */
622 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
623 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
625 /* Notify VF of default queue */
626 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
629 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
630 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
637 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
639 struct ixgbe_vf_info *vfinfo =
640 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
641 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */
643 switch (vfinfo[vf].api_version) {
644 case ixgbe_mbox_api_12:
651 return ixgbe_enable_vf_mc_promisc(dev, vf);
653 return ixgbe_disable_vf_mc_promisc(dev, vf);
657 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
659 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
660 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
661 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
663 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
664 struct ixgbe_vf_info *vfinfo =
665 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
666 struct rte_pmd_ixgbe_mb_event_param cb_param;
668 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
670 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
674 /* do nothing with the message already been processed */
675 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
678 /* flush the ack before we write any messages back */
679 IXGBE_WRITE_FLUSH(hw);
682 * initialise structure to send to user application
683 * will return response from user in retval field
685 cb_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
687 cb_param.msg_type = msgbuf[0] & 0xFFFF;
688 cb_param.msg = (void *)msgbuf;
690 /* perform VF reset */
691 if (msgbuf[0] == IXGBE_VF_RESET) {
692 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
694 vfinfo[vf].clear_to_send = true;
696 /* notify application about VF reset */
697 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
702 * ask user application if we allowed to perform those functions
703 * if we get cb_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
704 * then business as usual,
705 * if 0, do nothing and send ACK to VF
706 * if cb_param.retval > 1, do nothing and send NAK to VF
708 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
710 retval = cb_param.retval;
712 /* check & process VF to PF mailbox message */
713 switch ((msgbuf[0] & 0xFFFF)) {
714 case IXGBE_VF_SET_MAC_ADDR:
715 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
716 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
718 case IXGBE_VF_SET_MULTICAST:
719 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
720 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
722 case IXGBE_VF_SET_LPE:
723 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
724 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
726 case IXGBE_VF_SET_VLAN:
727 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
728 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
730 case IXGBE_VF_API_NEGOTIATE:
731 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
733 case IXGBE_VF_GET_QUEUES:
734 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
735 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
737 case IXGBE_VF_UPDATE_XCAST_MODE:
738 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
739 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
742 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
743 retval = IXGBE_ERR_MBX;
747 /* response the VF according to the message process result */
749 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
751 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
753 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
755 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
761 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
763 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
764 struct ixgbe_hw *hw =
765 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
766 struct ixgbe_vf_info *vfinfo =
767 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
769 if (!vfinfo[vf].clear_to_send)
770 ixgbe_write_mbx(hw, &msg, 1, vf);
773 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
776 struct ixgbe_hw *hw =
777 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
779 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
780 /* check & process vf function level reset */
781 if (!ixgbe_check_for_rst(hw, vf))
782 ixgbe_vf_reset_event(eth_dev, vf);
784 /* check & process vf mailbox messages */
785 if (!ixgbe_check_for_msg(hw, vf))
786 ixgbe_rcv_msg_from_vf(eth_dev, vf);
788 /* check & process acks from vf */
789 if (!ixgbe_check_for_ack(hw, vf))
790 ixgbe_rcv_ack_from_vf(eth_dev, vf);