4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum and TCP cksum */
379 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
380 IXGBE_ADVTXD_TUCMD_L4T_TCP |
381 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
383 tx_offload_mask.l2_len |= ~0;
384 tx_offload_mask.l3_len |= ~0;
385 tx_offload_mask.l4_len |= ~0;
386 tx_offload_mask.tso_segsz |= ~0;
387 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
388 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
389 } else { /* no TSO, check if hardware checksum is needed */
390 if (ol_flags & PKT_TX_IP_CKSUM) {
391 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
392 tx_offload_mask.l2_len |= ~0;
393 tx_offload_mask.l3_len |= ~0;
396 switch (ol_flags & PKT_TX_L4_MASK) {
397 case PKT_TX_UDP_CKSUM:
398 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
399 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
401 tx_offload_mask.l2_len |= ~0;
402 tx_offload_mask.l3_len |= ~0;
404 case PKT_TX_TCP_CKSUM:
405 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
406 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
407 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
408 tx_offload_mask.l2_len |= ~0;
409 tx_offload_mask.l3_len |= ~0;
410 tx_offload_mask.l4_len |= ~0;
412 case PKT_TX_SCTP_CKSUM:
413 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
414 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
415 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
416 tx_offload_mask.l2_len |= ~0;
417 tx_offload_mask.l3_len |= ~0;
420 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
421 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
426 txq->ctx_cache[ctx_idx].flags = ol_flags;
427 txq->ctx_cache[ctx_idx].tx_offload.data =
428 tx_offload_mask.data & tx_offload.data;
429 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
431 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
432 vlan_macip_lens = tx_offload.l3_len;
433 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
434 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
435 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
436 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
437 ctx_txd->seqnum_seed = 0;
441 * Check which hardware context can be used. Use the existing match
442 * or create a new context descriptor.
444 static inline uint32_t
445 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
446 union ixgbe_tx_offload tx_offload)
448 /* If match with the current used context */
449 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
450 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
451 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
452 return txq->ctx_curr;
455 /* What if match with the next context */
457 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
458 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
459 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
460 return txq->ctx_curr;
463 /* Mismatch, use the previous context */
464 return (IXGBE_CTX_NUM);
467 static inline uint32_t
468 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
471 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
472 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
473 if (ol_flags & PKT_TX_IP_CKSUM)
474 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
475 if (ol_flags & PKT_TX_TCP_SEG)
476 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
480 static inline uint32_t
481 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
483 uint32_t cmdtype = 0;
484 if (ol_flags & PKT_TX_VLAN_PKT)
485 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
486 if (ol_flags & PKT_TX_TCP_SEG)
487 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
491 /* Default RS bit threshold values */
492 #ifndef DEFAULT_TX_RS_THRESH
493 #define DEFAULT_TX_RS_THRESH 32
495 #ifndef DEFAULT_TX_FREE_THRESH
496 #define DEFAULT_TX_FREE_THRESH 32
499 /* Reset transmit descriptors after they have been used */
501 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
503 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
504 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
505 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
506 uint16_t nb_tx_desc = txq->nb_tx_desc;
507 uint16_t desc_to_clean_to;
508 uint16_t nb_tx_to_clean;
510 /* Determine the last descriptor needing to be cleaned */
511 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
512 if (desc_to_clean_to >= nb_tx_desc)
513 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
515 /* Check to make sure the last descriptor to clean is done */
516 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
517 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
519 PMD_TX_FREE_LOG(DEBUG,
520 "TX descriptor %4u is not done"
521 "(port=%d queue=%d)",
523 txq->port_id, txq->queue_id);
524 /* Failed to clean any descriptors, better luck next time */
528 /* Figure out how many descriptors will be cleaned */
529 if (last_desc_cleaned > desc_to_clean_to)
530 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
533 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
536 PMD_TX_FREE_LOG(DEBUG,
537 "Cleaning %4u TX descriptors: %4u to %4u "
538 "(port=%d queue=%d)",
539 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
540 txq->port_id, txq->queue_id);
543 * The last descriptor to clean is done, so that means all the
544 * descriptors from the last descriptor that was cleaned
545 * up to the last descriptor with the RS bit set
546 * are done. Only reset the threshold descriptor.
548 txr[desc_to_clean_to].wb.status = 0;
550 /* Update the txq to reflect the last descriptor that was cleaned */
551 txq->last_desc_cleaned = desc_to_clean_to;
552 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
559 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
562 struct ixgbe_tx_queue *txq;
563 struct ixgbe_tx_entry *sw_ring;
564 struct ixgbe_tx_entry *txe, *txn;
565 volatile union ixgbe_adv_tx_desc *txr;
566 volatile union ixgbe_adv_tx_desc *txd;
567 struct rte_mbuf *tx_pkt;
568 struct rte_mbuf *m_seg;
569 uint64_t buf_dma_addr;
570 uint32_t olinfo_status;
571 uint32_t cmd_type_len;
582 union ixgbe_tx_offload tx_offload = {0};
585 sw_ring = txq->sw_ring;
587 tx_id = txq->tx_tail;
588 txe = &sw_ring[tx_id];
590 /* Determine if the descriptor ring needs to be cleaned. */
591 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
592 ixgbe_xmit_cleanup(txq);
595 rte_prefetch0(&txe->mbuf->pool);
598 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
601 pkt_len = tx_pkt->pkt_len;
604 * Determine how many (if any) context descriptors
605 * are needed for offload functionality.
607 ol_flags = tx_pkt->ol_flags;
609 /* If hardware offload required */
610 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
612 tx_offload.l2_len = tx_pkt->l2_len;
613 tx_offload.l3_len = tx_pkt->l3_len;
614 tx_offload.l4_len = tx_pkt->l4_len;
615 tx_offload.vlan_tci = tx_pkt->vlan_tci;
616 tx_offload.tso_segsz = tx_pkt->tso_segsz;
618 /* If new context need be built or reuse the exist ctx. */
619 ctx = what_advctx_update(txq, tx_ol_req,
621 /* Only allocate context descriptor if required*/
622 new_ctx = (ctx == IXGBE_CTX_NUM);
627 * Keep track of how many descriptors are used this loop
628 * This will always be the number of segments + the number of
629 * Context descriptors required to transmit the packet
631 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
634 * The number of descriptors that must be allocated for a
635 * packet is the number of segments of that packet, plus 1
636 * Context Descriptor for the hardware offload, if any.
637 * Determine the last TX descriptor to allocate in the TX ring
638 * for the packet, starting from the current position (tx_id)
641 tx_last = (uint16_t) (tx_id + nb_used - 1);
644 if (tx_last >= txq->nb_tx_desc)
645 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
647 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
648 " tx_first=%u tx_last=%u",
649 (unsigned) txq->port_id,
650 (unsigned) txq->queue_id,
656 * Make sure there are enough TX descriptors available to
657 * transmit the entire packet.
658 * nb_used better be less than or equal to txq->tx_rs_thresh
660 if (nb_used > txq->nb_tx_free) {
661 PMD_TX_FREE_LOG(DEBUG,
662 "Not enough free TX descriptors "
663 "nb_used=%4u nb_free=%4u "
664 "(port=%d queue=%d)",
665 nb_used, txq->nb_tx_free,
666 txq->port_id, txq->queue_id);
668 if (ixgbe_xmit_cleanup(txq) != 0) {
669 /* Could not clean any descriptors */
675 /* nb_used better be <= txq->tx_rs_thresh */
676 if (unlikely(nb_used > txq->tx_rs_thresh)) {
677 PMD_TX_FREE_LOG(DEBUG,
678 "The number of descriptors needed to "
679 "transmit the packet exceeds the "
680 "RS bit threshold. This will impact "
682 "nb_used=%4u nb_free=%4u "
684 "(port=%d queue=%d)",
685 nb_used, txq->nb_tx_free,
687 txq->port_id, txq->queue_id);
689 * Loop here until there are enough TX
690 * descriptors or until the ring cannot be
693 while (nb_used > txq->nb_tx_free) {
694 if (ixgbe_xmit_cleanup(txq) != 0) {
696 * Could not clean any
708 * By now there are enough free TX descriptors to transmit
713 * Set common flags of all TX Data Descriptors.
715 * The following bits must be set in all Data Descriptors:
716 * - IXGBE_ADVTXD_DTYP_DATA
717 * - IXGBE_ADVTXD_DCMD_DEXT
719 * The following bits must be set in the first Data Descriptor
720 * and are ignored in the other ones:
721 * - IXGBE_ADVTXD_DCMD_IFCS
722 * - IXGBE_ADVTXD_MAC_1588
723 * - IXGBE_ADVTXD_DCMD_VLE
725 * The following bits must only be set in the last Data
727 * - IXGBE_TXD_CMD_EOP
729 * The following bits can be set in any Data Descriptor, but
730 * are only set in the last Data Descriptor:
733 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
734 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
736 #ifdef RTE_LIBRTE_IEEE1588
737 if (ol_flags & PKT_TX_IEEE1588_TMST)
738 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
744 if (ol_flags & PKT_TX_TCP_SEG) {
745 /* when TSO is on, paylen in descriptor is the
746 * not the packet len but the tcp payload len */
747 pkt_len -= (tx_offload.l2_len +
748 tx_offload.l3_len + tx_offload.l4_len);
752 * Setup the TX Advanced Context Descriptor if required
755 volatile struct ixgbe_adv_tx_context_desc *
758 ctx_txd = (volatile struct
759 ixgbe_adv_tx_context_desc *)
762 txn = &sw_ring[txe->next_id];
763 rte_prefetch0(&txn->mbuf->pool);
765 if (txe->mbuf != NULL) {
766 rte_pktmbuf_free_seg(txe->mbuf);
770 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
773 txe->last_id = tx_last;
774 tx_id = txe->next_id;
779 * Setup the TX Advanced Data Descriptor,
780 * This path will go through
781 * whatever new/reuse the context descriptor
783 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
784 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
785 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
788 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
793 txn = &sw_ring[txe->next_id];
794 rte_prefetch0(&txn->mbuf->pool);
796 if (txe->mbuf != NULL)
797 rte_pktmbuf_free_seg(txe->mbuf);
801 * Set up Transmit Data Descriptor.
803 slen = m_seg->data_len;
804 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
805 txd->read.buffer_addr =
806 rte_cpu_to_le_64(buf_dma_addr);
807 txd->read.cmd_type_len =
808 rte_cpu_to_le_32(cmd_type_len | slen);
809 txd->read.olinfo_status =
810 rte_cpu_to_le_32(olinfo_status);
811 txe->last_id = tx_last;
812 tx_id = txe->next_id;
815 } while (m_seg != NULL);
818 * The last packet data descriptor needs End Of Packet (EOP)
820 cmd_type_len |= IXGBE_TXD_CMD_EOP;
821 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
822 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
824 /* Set RS bit only on threshold packets' last descriptor */
825 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
826 PMD_TX_FREE_LOG(DEBUG,
827 "Setting RS bit on TXD id="
828 "%4u (port=%d queue=%d)",
829 tx_last, txq->port_id, txq->queue_id);
831 cmd_type_len |= IXGBE_TXD_CMD_RS;
833 /* Update txq RS bit counters */
836 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
842 * Set the Transmit Descriptor Tail (TDT)
844 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
845 (unsigned) txq->port_id, (unsigned) txq->queue_id,
846 (unsigned) tx_id, (unsigned) nb_tx);
847 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
848 txq->tx_tail = tx_id;
853 /*********************************************************************
857 **********************************************************************/
858 static inline uint64_t
859 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
863 static const uint64_t ip_pkt_types_map[16] = {
864 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
865 PKT_RX_IPV6_HDR, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
867 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
870 static const uint64_t ip_rss_types_map[16] = {
871 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
872 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
873 PKT_RX_RSS_HASH, 0, 0, 0,
874 0, 0, 0, PKT_RX_FDIR,
877 #ifdef RTE_LIBRTE_IEEE1588
878 static uint64_t ip_pkt_etqf_map[8] = {
879 0, 0, 0, PKT_RX_IEEE1588_PTP,
883 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
884 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
885 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
887 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
888 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
891 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
894 static inline uint64_t
895 rx_desc_status_to_pkt_flags(uint32_t rx_status)
900 * Check if VLAN present only.
901 * Do not check whether L3/L4 rx checksum done by NIC or not,
902 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
904 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
906 #ifdef RTE_LIBRTE_IEEE1588
907 if (rx_status & IXGBE_RXD_STAT_TMST)
908 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
913 static inline uint64_t
914 rx_desc_error_to_pkt_flags(uint32_t rx_status)
917 * Bit 31: IPE, IPv4 checksum error
918 * Bit 30: L4I, L4I integrity error
920 static uint64_t error_to_pkt_flags_map[4] = {
921 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
922 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
924 return error_to_pkt_flags_map[(rx_status >>
925 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
928 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
930 * LOOK_AHEAD defines how many desc statuses to check beyond the
931 * current descriptor.
932 * It must be a pound define for optimal performance.
933 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
934 * function only works with LOOK_AHEAD=8.
937 #if (LOOK_AHEAD != 8)
938 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
941 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
943 volatile union ixgbe_adv_rx_desc *rxdp;
944 struct ixgbe_rx_entry *rxep;
948 int s[LOOK_AHEAD], nb_dd;
952 /* get references to current descriptor and S/W ring entry */
953 rxdp = &rxq->rx_ring[rxq->rx_tail];
954 rxep = &rxq->sw_ring[rxq->rx_tail];
956 /* check to make sure there is at least 1 packet to receive */
957 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
961 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
962 * reference packets that are ready to be received.
964 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
965 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
967 /* Read desc statuses backwards to avoid race condition */
968 for (j = LOOK_AHEAD-1; j >= 0; --j)
969 s[j] = rxdp[j].wb.upper.status_error;
971 /* Compute how many status bits were set */
973 for (j = 0; j < LOOK_AHEAD; ++j)
974 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
978 /* Translate descriptor info to mbuf format */
979 for (j = 0; j < nb_dd; ++j) {
981 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
982 mb->data_len = pkt_len;
983 mb->pkt_len = pkt_len;
984 mb->vlan_tci = rxdp[j].wb.upper.vlan;
985 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
987 /* convert descriptor fields to rte mbuf flags */
988 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
989 rxdp[j].wb.lower.lo_dword.data);
990 /* reuse status field from scan list */
991 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
992 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
993 mb->ol_flags = pkt_flags;
995 if (likely(pkt_flags & PKT_RX_RSS_HASH))
996 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
997 else if (pkt_flags & PKT_RX_FDIR) {
999 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1000 & IXGBE_ATR_HASH_MASK);
1001 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1005 /* Move mbuf pointers from the S/W ring to the stage */
1006 for (j = 0; j < LOOK_AHEAD; ++j) {
1007 rxq->rx_stage[i + j] = rxep[j].mbuf;
1010 /* stop if all requested packets could not be received */
1011 if (nb_dd != LOOK_AHEAD)
1015 /* clear software ring entries so we can cleanup correctly */
1016 for (i = 0; i < nb_rx; ++i) {
1017 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1025 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1027 volatile union ixgbe_adv_rx_desc *rxdp;
1028 struct ixgbe_rx_entry *rxep;
1029 struct rte_mbuf *mb;
1034 /* allocate buffers in bulk directly into the S/W ring */
1035 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1036 rxep = &rxq->sw_ring[alloc_idx];
1037 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1038 rxq->rx_free_thresh);
1039 if (unlikely(diag != 0))
1042 rxdp = &rxq->rx_ring[alloc_idx];
1043 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1044 /* populate the static rte mbuf fields */
1049 mb->port = rxq->port_id;
1052 rte_mbuf_refcnt_set(mb, 1);
1053 mb->data_off = RTE_PKTMBUF_HEADROOM;
1055 /* populate the descriptors */
1056 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1057 rxdp[i].read.hdr_addr = dma_addr;
1058 rxdp[i].read.pkt_addr = dma_addr;
1061 /* update state of internal queue structure */
1062 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1063 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1064 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1070 static inline uint16_t
1071 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1074 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1077 /* how many packets are ready to return? */
1078 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1080 /* copy mbuf pointers to the application's packet list */
1081 for (i = 0; i < nb_pkts; ++i)
1082 rx_pkts[i] = stage[i];
1084 /* update internal queue state */
1085 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1086 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1091 static inline uint16_t
1092 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1095 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1098 /* Any previously recv'd pkts will be returned from the Rx stage */
1099 if (rxq->rx_nb_avail)
1100 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1102 /* Scan the H/W ring for packets to receive */
1103 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1105 /* update internal queue state */
1106 rxq->rx_next_avail = 0;
1107 rxq->rx_nb_avail = nb_rx;
1108 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1110 /* if required, allocate new buffers to replenish descriptors */
1111 if (rxq->rx_tail > rxq->rx_free_trigger) {
1112 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1114 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1116 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1117 "queue_id=%u", (unsigned) rxq->port_id,
1118 (unsigned) rxq->queue_id);
1120 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1121 rxq->rx_free_thresh;
1124 * Need to rewind any previous receives if we cannot
1125 * allocate new buffers to replenish the old ones.
1127 rxq->rx_nb_avail = 0;
1128 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1129 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1130 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1135 /* update tail pointer */
1137 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1140 if (rxq->rx_tail >= rxq->nb_rx_desc)
1143 /* received any packets this loop? */
1144 if (rxq->rx_nb_avail)
1145 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1150 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1152 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1157 if (unlikely(nb_pkts == 0))
1160 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1161 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1163 /* request is relatively large, chunk it up */
1167 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1168 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1169 nb_rx = (uint16_t)(nb_rx + ret);
1170 nb_pkts = (uint16_t)(nb_pkts - ret);
1180 /* Stub to avoid extra ifdefs */
1182 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1183 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1189 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1190 __rte_unused bool reset_mbuf)
1194 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1197 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1200 struct ixgbe_rx_queue *rxq;
1201 volatile union ixgbe_adv_rx_desc *rx_ring;
1202 volatile union ixgbe_adv_rx_desc *rxdp;
1203 struct ixgbe_rx_entry *sw_ring;
1204 struct ixgbe_rx_entry *rxe;
1205 struct rte_mbuf *rxm;
1206 struct rte_mbuf *nmb;
1207 union ixgbe_adv_rx_desc rxd;
1210 uint32_t hlen_type_rss;
1220 rx_id = rxq->rx_tail;
1221 rx_ring = rxq->rx_ring;
1222 sw_ring = rxq->sw_ring;
1223 while (nb_rx < nb_pkts) {
1225 * The order of operations here is important as the DD status
1226 * bit must not be read after any other descriptor fields.
1227 * rx_ring and rxdp are pointing to volatile data so the order
1228 * of accesses cannot be reordered by the compiler. If they were
1229 * not volatile, they could be reordered which could lead to
1230 * using invalid descriptor fields when read from rxd.
1232 rxdp = &rx_ring[rx_id];
1233 staterr = rxdp->wb.upper.status_error;
1234 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1241 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1242 * is likely to be invalid and to be dropped by the various
1243 * validation checks performed by the network stack.
1245 * Allocate a new mbuf to replenish the RX ring descriptor.
1246 * If the allocation fails:
1247 * - arrange for that RX descriptor to be the first one
1248 * being parsed the next time the receive function is
1249 * invoked [on the same queue].
1251 * - Stop parsing the RX ring and return immediately.
1253 * This policy do not drop the packet received in the RX
1254 * descriptor for which the allocation of a new mbuf failed.
1255 * Thus, it allows that packet to be later retrieved if
1256 * mbuf have been freed in the mean time.
1257 * As a side effect, holding RX descriptors instead of
1258 * systematically giving them back to the NIC may lead to
1259 * RX ring exhaustion situations.
1260 * However, the NIC can gracefully prevent such situations
1261 * to happen by sending specific "back-pressure" flow control
1262 * frames to its peer(s).
1264 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1265 "ext_err_stat=0x%08x pkt_len=%u",
1266 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1267 (unsigned) rx_id, (unsigned) staterr,
1268 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1270 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1272 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1273 "queue_id=%u", (unsigned) rxq->port_id,
1274 (unsigned) rxq->queue_id);
1275 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1280 rxe = &sw_ring[rx_id];
1282 if (rx_id == rxq->nb_rx_desc)
1285 /* Prefetch next mbuf while processing current one. */
1286 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1289 * When next RX descriptor is on a cache-line boundary,
1290 * prefetch the next 4 RX descriptors and the next 8 pointers
1293 if ((rx_id & 0x3) == 0) {
1294 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1295 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1301 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1302 rxdp->read.hdr_addr = dma_addr;
1303 rxdp->read.pkt_addr = dma_addr;
1306 * Initialize the returned mbuf.
1307 * 1) setup generic mbuf fields:
1308 * - number of segments,
1311 * - RX port identifier.
1312 * 2) integrate hardware offload data, if any:
1313 * - RSS flag & hash,
1314 * - IP checksum flag,
1315 * - VLAN TCI, if any,
1318 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1320 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1321 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1324 rxm->pkt_len = pkt_len;
1325 rxm->data_len = pkt_len;
1326 rxm->port = rxq->port_id;
1328 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1329 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1330 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1332 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1333 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1334 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1335 rxm->ol_flags = pkt_flags;
1337 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1338 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1339 else if (pkt_flags & PKT_RX_FDIR) {
1340 rxm->hash.fdir.hash =
1341 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1342 & IXGBE_ATR_HASH_MASK);
1343 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1346 * Store the mbuf address into the next entry of the array
1347 * of returned packets.
1349 rx_pkts[nb_rx++] = rxm;
1351 rxq->rx_tail = rx_id;
1354 * If the number of free RX descriptors is greater than the RX free
1355 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1357 * Update the RDT with the value of the last processed RX descriptor
1358 * minus 1, to guarantee that the RDT register is never equal to the
1359 * RDH register, which creates a "full" ring situtation from the
1360 * hardware point of view...
1362 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1363 if (nb_hold > rxq->rx_free_thresh) {
1364 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1365 "nb_hold=%u nb_rx=%u",
1366 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1367 (unsigned) rx_id, (unsigned) nb_hold,
1369 rx_id = (uint16_t) ((rx_id == 0) ?
1370 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1371 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1374 rxq->nb_rx_hold = nb_hold;
1379 * Detect an RSC descriptor.
1381 static inline uint32_t
1382 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1384 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1385 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1389 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1391 * Fill the following info in the HEAD buffer of the Rx cluster:
1392 * - RX port identifier
1393 * - hardware offload data, if any:
1395 * - IP checksum flag
1396 * - VLAN TCI, if any
1398 * @head HEAD of the packet cluster
1399 * @desc HW descriptor to get data from
1400 * @port_id Port ID of the Rx queue
1403 ixgbe_fill_cluster_head_buf(
1404 struct rte_mbuf *head,
1405 union ixgbe_adv_rx_desc *desc,
1409 uint32_t hlen_type_rss;
1412 head->port = port_id;
1415 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1416 * set in the pkt_flags field.
1418 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1419 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1420 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1421 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1422 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1423 head->ol_flags = pkt_flags;
1425 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1426 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1427 else if (pkt_flags & PKT_RX_FDIR) {
1428 head->hash.fdir.hash =
1429 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1430 & IXGBE_ATR_HASH_MASK;
1431 head->hash.fdir.id =
1432 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1437 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1439 * @rx_queue Rx queue handle
1440 * @rx_pkts table of received packets
1441 * @nb_pkts size of rx_pkts table
1442 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1444 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1445 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1447 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1448 * 1) When non-EOP RSC completion arrives:
1449 * a) Update the HEAD of the current RSC aggregation cluster with the new
1450 * segment's data length.
1451 * b) Set the "next" pointer of the current segment to point to the segment
1452 * at the NEXTP index.
1453 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1454 * in the sw_rsc_ring.
1455 * 2) When EOP arrives we just update the cluster's total length and offload
1456 * flags and deliver the cluster up to the upper layers. In our case - put it
1457 * in the rx_pkts table.
1459 * Returns the number of received packets/clusters (according to the "bulk
1460 * receive" interface).
1462 static inline uint16_t
1463 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1466 struct ixgbe_rx_queue *rxq = rx_queue;
1467 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1468 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1469 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1470 uint16_t rx_id = rxq->rx_tail;
1472 uint16_t nb_hold = rxq->nb_rx_hold;
1473 uint16_t prev_id = rxq->rx_tail;
1475 while (nb_rx < nb_pkts) {
1477 struct ixgbe_rx_entry *rxe;
1478 struct ixgbe_scattered_rx_entry *sc_entry;
1479 struct ixgbe_scattered_rx_entry *next_sc_entry;
1480 struct ixgbe_rx_entry *next_rxe;
1481 struct rte_mbuf *first_seg;
1482 struct rte_mbuf *rxm;
1483 struct rte_mbuf *nmb;
1484 union ixgbe_adv_rx_desc rxd;
1487 volatile union ixgbe_adv_rx_desc *rxdp;
1492 * The code in this whole file uses the volatile pointer to
1493 * ensure the read ordering of the status and the rest of the
1494 * descriptor fields (on the compiler level only!!!). This is so
1495 * UGLY - why not to just use the compiler barrier instead? DPDK
1496 * even has the rte_compiler_barrier() for that.
1498 * But most importantly this is just wrong because this doesn't
1499 * ensure memory ordering in a general case at all. For
1500 * instance, DPDK is supposed to work on Power CPUs where
1501 * compiler barrier may just not be enough!
1503 * I tried to write only this function properly to have a
1504 * starting point (as a part of an LRO/RSC series) but the
1505 * compiler cursed at me when I tried to cast away the
1506 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1507 * keeping it the way it is for now.
1509 * The code in this file is broken in so many other places and
1510 * will just not work on a big endian CPU anyway therefore the
1511 * lines below will have to be revisited together with the rest
1515 * - Get rid of "volatile" crap and let the compiler do its
1517 * - Use the proper memory barrier (rte_rmb()) to ensure the
1518 * memory ordering below.
1520 rxdp = &rx_ring[rx_id];
1521 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1523 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1528 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1529 "staterr=0x%x data_len=%u",
1530 rxq->port_id, rxq->queue_id, rx_id, staterr,
1531 rte_le_to_cpu_16(rxd.wb.upper.length));
1534 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1536 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1537 "port_id=%u queue_id=%u",
1538 rxq->port_id, rxq->queue_id);
1540 rte_eth_devices[rxq->port_id].data->
1541 rx_mbuf_alloc_failed++;
1544 } else if (nb_hold > rxq->rx_free_thresh) {
1545 uint16_t next_rdt = rxq->rx_free_trigger;
1547 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1549 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1551 nb_hold -= rxq->rx_free_thresh;
1553 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1554 "port_id=%u queue_id=%u",
1555 rxq->port_id, rxq->queue_id);
1557 rte_eth_devices[rxq->port_id].data->
1558 rx_mbuf_alloc_failed++;
1564 rxe = &sw_ring[rx_id];
1565 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1567 next_id = rx_id + 1;
1568 if (next_id == rxq->nb_rx_desc)
1571 /* Prefetch next mbuf while processing current one. */
1572 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1575 * When next RX descriptor is on a cache-line boundary,
1576 * prefetch the next 4 RX descriptors and the next 4 pointers
1579 if ((next_id & 0x3) == 0) {
1580 rte_ixgbe_prefetch(&rx_ring[next_id]);
1581 rte_ixgbe_prefetch(&sw_ring[next_id]);
1588 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1590 * Update RX descriptor with the physical address of the
1591 * new data buffer of the new allocated mbuf.
1595 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1596 rxdp->read.hdr_addr = dma;
1597 rxdp->read.pkt_addr = dma;
1602 * Set data length & data buffer address of mbuf.
1604 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1605 rxm->data_len = data_len;
1610 * Get next descriptor index:
1611 * - For RSC it's in the NEXTP field.
1612 * - For a scattered packet - it's just a following
1615 if (ixgbe_rsc_count(&rxd))
1617 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1618 IXGBE_RXDADV_NEXTP_SHIFT;
1622 next_sc_entry = &sw_sc_ring[nextp_id];
1623 next_rxe = &sw_ring[nextp_id];
1624 rte_ixgbe_prefetch(next_rxe);
1627 sc_entry = &sw_sc_ring[rx_id];
1628 first_seg = sc_entry->fbuf;
1629 sc_entry->fbuf = NULL;
1632 * If this is the first buffer of the received packet,
1633 * set the pointer to the first mbuf of the packet and
1634 * initialize its context.
1635 * Otherwise, update the total length and the number of segments
1636 * of the current scattered packet, and update the pointer to
1637 * the last mbuf of the current packet.
1639 if (first_seg == NULL) {
1641 first_seg->pkt_len = data_len;
1642 first_seg->nb_segs = 1;
1644 first_seg->pkt_len += data_len;
1645 first_seg->nb_segs++;
1652 * If this is not the last buffer of the received packet, update
1653 * the pointer to the first mbuf at the NEXTP entry in the
1654 * sw_sc_ring and continue to parse the RX ring.
1657 rxm->next = next_rxe->mbuf;
1658 next_sc_entry->fbuf = first_seg;
1663 * This is the last buffer of the received packet - return
1664 * the current cluster to the user.
1668 /* Initialize the first mbuf of the returned packet */
1669 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1672 /* Prefetch data of first segment, if configured to do so. */
1673 rte_packet_prefetch((char *)first_seg->buf_addr +
1674 first_seg->data_off);
1677 * Store the mbuf address into the next entry of the array
1678 * of returned packets.
1680 rx_pkts[nb_rx++] = first_seg;
1684 * Record index of the next RX descriptor to probe.
1686 rxq->rx_tail = rx_id;
1689 * If the number of free RX descriptors is greater than the RX free
1690 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1692 * Update the RDT with the value of the last processed RX descriptor
1693 * minus 1, to guarantee that the RDT register is never equal to the
1694 * RDH register, which creates a "full" ring situtation from the
1695 * hardware point of view...
1697 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1698 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1699 "nb_hold=%u nb_rx=%u",
1700 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1703 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1707 rxq->nb_rx_hold = nb_hold;
1712 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1715 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1719 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1722 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1725 /*********************************************************************
1727 * Queue management functions
1729 **********************************************************************/
1732 * Rings setup and release.
1734 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1735 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1736 * also optimize cache line size effect. H/W supports up to cache line size 128.
1738 #define IXGBE_ALIGN 128
1741 * Maximum number of Ring Descriptors.
1743 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1744 * descriptors should meet the following condition:
1745 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1747 #define IXGBE_MIN_RING_DESC 32
1748 #define IXGBE_MAX_RING_DESC 4096
1751 * Create memzone for HW rings. malloc can't be used as the physical address is
1752 * needed. If the memzone is already created, then this function returns a ptr
1755 static const struct rte_memzone *
1756 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1757 uint16_t queue_id, uint32_t ring_size, int socket_id)
1759 char z_name[RTE_MEMZONE_NAMESIZE];
1760 const struct rte_memzone *mz;
1762 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1763 dev->driver->pci_drv.name, ring_name,
1764 dev->data->port_id, queue_id);
1766 mz = rte_memzone_lookup(z_name);
1770 #ifdef RTE_LIBRTE_XEN_DOM0
1771 return rte_memzone_reserve_bounded(z_name, ring_size,
1772 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1774 return rte_memzone_reserve_aligned(z_name, ring_size,
1775 socket_id, 0, IXGBE_ALIGN);
1780 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1784 if (txq->sw_ring != NULL) {
1785 for (i = 0; i < txq->nb_tx_desc; i++) {
1786 if (txq->sw_ring[i].mbuf != NULL) {
1787 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1788 txq->sw_ring[i].mbuf = NULL;
1795 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1798 txq->sw_ring != NULL)
1799 rte_free(txq->sw_ring);
1803 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1805 if (txq != NULL && txq->ops != NULL) {
1806 txq->ops->release_mbufs(txq);
1807 txq->ops->free_swring(txq);
1813 ixgbe_dev_tx_queue_release(void *txq)
1815 ixgbe_tx_queue_release(txq);
1818 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1820 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1822 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1823 struct ixgbe_tx_entry *txe = txq->sw_ring;
1826 /* Zero out HW ring memory */
1827 for (i = 0; i < txq->nb_tx_desc; i++) {
1828 txq->tx_ring[i] = zeroed_desc;
1831 /* Initialize SW ring entries */
1832 prev = (uint16_t) (txq->nb_tx_desc - 1);
1833 for (i = 0; i < txq->nb_tx_desc; i++) {
1834 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1835 txd->wb.status = IXGBE_TXD_STAT_DD;
1838 txe[prev].next_id = i;
1842 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1843 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1846 txq->nb_tx_used = 0;
1848 * Always allow 1 descriptor to be un-allocated to avoid
1849 * a H/W race condition
1851 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1852 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1854 memset((void*)&txq->ctx_cache, 0,
1855 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1858 static const struct ixgbe_txq_ops def_txq_ops = {
1859 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1860 .free_swring = ixgbe_tx_free_swring,
1861 .reset = ixgbe_reset_tx_queue,
1864 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1865 * the queue parameters. Used in tx_queue_setup by primary process and then
1866 * in dev_init by secondary process when attaching to an existing ethdev.
1869 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1871 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1872 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1873 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1874 PMD_INIT_LOG(INFO, "Using simple tx code path");
1875 #ifdef RTE_IXGBE_INC_VECTOR
1876 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1877 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1878 ixgbe_txq_vec_setup(txq) == 0)) {
1879 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1880 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1883 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1885 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1887 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1888 (unsigned long)txq->txq_flags,
1889 (unsigned long)IXGBE_SIMPLE_FLAGS);
1891 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1892 (unsigned long)txq->tx_rs_thresh,
1893 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1894 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1899 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1902 unsigned int socket_id,
1903 const struct rte_eth_txconf *tx_conf)
1905 const struct rte_memzone *tz;
1906 struct ixgbe_tx_queue *txq;
1907 struct ixgbe_hw *hw;
1908 uint16_t tx_rs_thresh, tx_free_thresh;
1910 PMD_INIT_FUNC_TRACE();
1911 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914 * Validate number of transmit descriptors.
1915 * It must not exceed hardware maximum, and must be multiple
1918 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1919 (nb_desc > IXGBE_MAX_RING_DESC) ||
1920 (nb_desc < IXGBE_MIN_RING_DESC)) {
1925 * The following two parameters control the setting of the RS bit on
1926 * transmit descriptors.
1927 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1928 * descriptors have been used.
1929 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1930 * descriptors are used or if the number of descriptors required
1931 * to transmit a packet is greater than the number of free TX
1933 * The following constraints must be satisfied:
1934 * tx_rs_thresh must be greater than 0.
1935 * tx_rs_thresh must be less than the size of the ring minus 2.
1936 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1937 * tx_rs_thresh must be a divisor of the ring size.
1938 * tx_free_thresh must be greater than 0.
1939 * tx_free_thresh must be less than the size of the ring minus 3.
1940 * One descriptor in the TX ring is used as a sentinel to avoid a
1941 * H/W race condition, hence the maximum threshold constraints.
1942 * When set to zero use default values.
1944 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1945 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1946 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1947 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1948 if (tx_rs_thresh >= (nb_desc - 2)) {
1949 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1950 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1951 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1952 (int)dev->data->port_id, (int)queue_idx);
1955 if (tx_free_thresh >= (nb_desc - 3)) {
1956 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1957 "tx_free_thresh must be less than the number of "
1958 "TX descriptors minus 3. (tx_free_thresh=%u "
1959 "port=%d queue=%d)",
1960 (unsigned int)tx_free_thresh,
1961 (int)dev->data->port_id, (int)queue_idx);
1964 if (tx_rs_thresh > tx_free_thresh) {
1965 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1966 "tx_free_thresh. (tx_free_thresh=%u "
1967 "tx_rs_thresh=%u port=%d queue=%d)",
1968 (unsigned int)tx_free_thresh,
1969 (unsigned int)tx_rs_thresh,
1970 (int)dev->data->port_id,
1974 if ((nb_desc % tx_rs_thresh) != 0) {
1975 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1976 "number of TX descriptors. (tx_rs_thresh=%u "
1977 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1978 (int)dev->data->port_id, (int)queue_idx);
1983 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1984 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1985 * by the NIC and all descriptors are written back after the NIC
1986 * accumulates WTHRESH descriptors.
1988 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1989 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1990 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1991 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1992 (int)dev->data->port_id, (int)queue_idx);
1996 /* Free memory prior to re-allocation if needed... */
1997 if (dev->data->tx_queues[queue_idx] != NULL) {
1998 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1999 dev->data->tx_queues[queue_idx] = NULL;
2002 /* First allocate the tx queue data structure */
2003 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2004 RTE_CACHE_LINE_SIZE, socket_id);
2009 * Allocate TX ring hardware descriptors. A memzone large enough to
2010 * handle the maximum ring size is allocated in order to allow for
2011 * resizing in later calls to the queue setup function.
2013 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2014 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2017 ixgbe_tx_queue_release(txq);
2021 txq->nb_tx_desc = nb_desc;
2022 txq->tx_rs_thresh = tx_rs_thresh;
2023 txq->tx_free_thresh = tx_free_thresh;
2024 txq->pthresh = tx_conf->tx_thresh.pthresh;
2025 txq->hthresh = tx_conf->tx_thresh.hthresh;
2026 txq->wthresh = tx_conf->tx_thresh.wthresh;
2027 txq->queue_id = queue_idx;
2028 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2029 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2030 txq->port_id = dev->data->port_id;
2031 txq->txq_flags = tx_conf->txq_flags;
2032 txq->ops = &def_txq_ops;
2033 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2036 * Modification to set VFTDT for virtual function if vf is detected
2038 if (hw->mac.type == ixgbe_mac_82599_vf ||
2039 hw->mac.type == ixgbe_mac_X540_vf ||
2040 hw->mac.type == ixgbe_mac_X550_vf ||
2041 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2042 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2044 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2045 #ifndef RTE_LIBRTE_XEN_DOM0
2046 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2048 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2050 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2052 /* Allocate software ring */
2053 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2054 sizeof(struct ixgbe_tx_entry) * nb_desc,
2055 RTE_CACHE_LINE_SIZE, socket_id);
2056 if (txq->sw_ring == NULL) {
2057 ixgbe_tx_queue_release(txq);
2060 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2061 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2063 /* set up vector or scalar TX function as appropriate */
2064 ixgbe_set_tx_function(dev, txq);
2066 txq->ops->reset(txq);
2068 dev->data->tx_queues[queue_idx] = txq;
2075 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2077 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2078 * in the sw_rsc_ring is not set to NULL but rather points to the next
2079 * mbuf of this RSC aggregation (that has not been completed yet and still
2080 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2081 * will just free first "nb_segs" segments of the cluster explicitly by calling
2082 * an rte_pktmbuf_free_seg().
2084 * @m scattered cluster head
2087 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2089 uint8_t i, nb_segs = m->nb_segs;
2090 struct rte_mbuf *next_seg;
2092 for (i = 0; i < nb_segs; i++) {
2094 rte_pktmbuf_free_seg(m);
2100 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2104 if (rxq->sw_ring != NULL) {
2105 for (i = 0; i < rxq->nb_rx_desc; i++) {
2106 if (rxq->sw_ring[i].mbuf != NULL) {
2107 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2108 rxq->sw_ring[i].mbuf = NULL;
2111 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2112 if (rxq->rx_nb_avail) {
2113 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2114 struct rte_mbuf *mb;
2115 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2116 rte_pktmbuf_free_seg(mb);
2118 rxq->rx_nb_avail = 0;
2123 if (rxq->sw_sc_ring)
2124 for (i = 0; i < rxq->nb_rx_desc; i++)
2125 if (rxq->sw_sc_ring[i].fbuf) {
2126 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2127 rxq->sw_sc_ring[i].fbuf = NULL;
2132 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2135 ixgbe_rx_queue_release_mbufs(rxq);
2136 rte_free(rxq->sw_ring);
2137 rte_free(rxq->sw_sc_ring);
2143 ixgbe_dev_rx_queue_release(void *rxq)
2145 ixgbe_rx_queue_release(rxq);
2149 * Check if Rx Burst Bulk Alloc function can be used.
2151 * 0: the preconditions are satisfied and the bulk allocation function
2153 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2154 * function must be used.
2157 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2158 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2160 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2166 * Make sure the following pre-conditions are satisfied:
2167 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2168 * rxq->rx_free_thresh < rxq->nb_rx_desc
2169 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2170 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2171 * Scattered packets are not supported. This should be checked
2172 * outside of this function.
2174 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2175 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2176 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2177 "rxq->rx_free_thresh=%d, "
2178 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2179 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2181 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2182 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2183 "rxq->rx_free_thresh=%d, "
2184 "rxq->nb_rx_desc=%d",
2185 rxq->rx_free_thresh, rxq->nb_rx_desc);
2187 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2188 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2189 "rxq->nb_rx_desc=%d, "
2190 "rxq->rx_free_thresh=%d",
2191 rxq->nb_rx_desc, rxq->rx_free_thresh);
2193 } else if (!(rxq->nb_rx_desc <
2194 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2195 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2196 "rxq->nb_rx_desc=%d, "
2197 "IXGBE_MAX_RING_DESC=%d, "
2198 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2199 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2200 RTE_PMD_IXGBE_RX_MAX_BURST);
2210 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2212 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2214 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2216 uint16_t len = rxq->nb_rx_desc;
2219 * By default, the Rx queue setup function allocates enough memory for
2220 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2221 * extra memory at the end of the descriptor ring to be zero'd out. A
2222 * pre-condition for using the Rx burst bulk alloc function is that the
2223 * number of descriptors is less than or equal to
2224 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2225 * constraints here to see if we need to zero out memory after the end
2226 * of the H/W descriptor ring.
2228 if (adapter->rx_bulk_alloc_allowed)
2229 /* zero out extra memory */
2230 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2233 * Zero out HW ring memory. Zero out extra memory at the end of
2234 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2235 * reads extra memory as zeros.
2237 for (i = 0; i < len; i++) {
2238 rxq->rx_ring[i] = zeroed_desc;
2241 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2243 * initialize extra software ring entries. Space for these extra
2244 * entries is always allocated
2246 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2247 for (i = rxq->nb_rx_desc; i < len; ++i) {
2248 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2251 rxq->rx_nb_avail = 0;
2252 rxq->rx_next_avail = 0;
2253 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2254 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2256 rxq->nb_rx_hold = 0;
2257 rxq->pkt_first_seg = NULL;
2258 rxq->pkt_last_seg = NULL;
2262 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2265 unsigned int socket_id,
2266 const struct rte_eth_rxconf *rx_conf,
2267 struct rte_mempool *mp)
2269 const struct rte_memzone *rz;
2270 struct ixgbe_rx_queue *rxq;
2271 struct ixgbe_hw *hw;
2273 struct ixgbe_adapter *adapter =
2274 (struct ixgbe_adapter *)dev->data->dev_private;
2276 PMD_INIT_FUNC_TRACE();
2277 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2280 * Validate number of receive descriptors.
2281 * It must not exceed hardware maximum, and must be multiple
2284 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2285 (nb_desc > IXGBE_MAX_RING_DESC) ||
2286 (nb_desc < IXGBE_MIN_RING_DESC)) {
2290 /* Free memory prior to re-allocation if needed... */
2291 if (dev->data->rx_queues[queue_idx] != NULL) {
2292 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2293 dev->data->rx_queues[queue_idx] = NULL;
2296 /* First allocate the rx queue data structure */
2297 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2298 RTE_CACHE_LINE_SIZE, socket_id);
2302 rxq->nb_rx_desc = nb_desc;
2303 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2304 rxq->queue_id = queue_idx;
2305 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2306 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2307 rxq->port_id = dev->data->port_id;
2308 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2310 rxq->drop_en = rx_conf->rx_drop_en;
2311 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2314 * Allocate RX ring hardware descriptors. A memzone large enough to
2315 * handle the maximum ring size is allocated in order to allow for
2316 * resizing in later calls to the queue setup function.
2318 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2319 RX_RING_SZ, socket_id);
2321 ixgbe_rx_queue_release(rxq);
2326 * Zero init all the descriptors in the ring.
2328 memset (rz->addr, 0, RX_RING_SZ);
2331 * Modified to setup VFRDT for Virtual Function
2333 if (hw->mac.type == ixgbe_mac_82599_vf ||
2334 hw->mac.type == ixgbe_mac_X540_vf ||
2335 hw->mac.type == ixgbe_mac_X550_vf ||
2336 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2338 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2340 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2344 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2346 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2348 #ifndef RTE_LIBRTE_XEN_DOM0
2349 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2351 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2353 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2356 * Certain constraints must be met in order to use the bulk buffer
2357 * allocation Rx burst function. If any of Rx queues doesn't meet them
2358 * the feature should be disabled for the whole port.
2360 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2361 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2362 "preconditions - canceling the feature for "
2363 "the whole port[%d]",
2364 rxq->queue_id, rxq->port_id);
2365 adapter->rx_bulk_alloc_allowed = false;
2369 * Allocate software ring. Allow for space at the end of the
2370 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2371 * function does not access an invalid memory region.
2374 if (adapter->rx_bulk_alloc_allowed)
2375 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2377 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2378 sizeof(struct ixgbe_rx_entry) * len,
2379 RTE_CACHE_LINE_SIZE, socket_id);
2380 if (!rxq->sw_ring) {
2381 ixgbe_rx_queue_release(rxq);
2386 * Always allocate even if it's not going to be needed in order to
2387 * simplify the code.
2389 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2390 * be requested in ixgbe_dev_rx_init(), which is called later from
2394 rte_zmalloc_socket("rxq->sw_sc_ring",
2395 sizeof(struct ixgbe_scattered_rx_entry) * len,
2396 RTE_CACHE_LINE_SIZE, socket_id);
2397 if (!rxq->sw_sc_ring) {
2398 ixgbe_rx_queue_release(rxq);
2402 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2403 "dma_addr=0x%"PRIx64,
2404 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2405 rxq->rx_ring_phys_addr);
2407 if (!rte_is_power_of_2(nb_desc)) {
2408 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2409 "preconditions - canceling the feature for "
2410 "the whole port[%d]",
2411 rxq->queue_id, rxq->port_id);
2412 adapter->rx_vec_allowed = false;
2414 ixgbe_rxq_vec_setup(rxq);
2416 dev->data->rx_queues[queue_idx] = rxq;
2418 ixgbe_reset_rx_queue(adapter, rxq);
2424 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2426 #define IXGBE_RXQ_SCAN_INTERVAL 4
2427 volatile union ixgbe_adv_rx_desc *rxdp;
2428 struct ixgbe_rx_queue *rxq;
2431 if (rx_queue_id >= dev->data->nb_rx_queues) {
2432 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2436 rxq = dev->data->rx_queues[rx_queue_id];
2437 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2439 while ((desc < rxq->nb_rx_desc) &&
2440 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2441 desc += IXGBE_RXQ_SCAN_INTERVAL;
2442 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2443 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2444 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2445 desc - rxq->nb_rx_desc]);
2452 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2454 volatile union ixgbe_adv_rx_desc *rxdp;
2455 struct ixgbe_rx_queue *rxq = rx_queue;
2458 if (unlikely(offset >= rxq->nb_rx_desc))
2460 desc = rxq->rx_tail + offset;
2461 if (desc >= rxq->nb_rx_desc)
2462 desc -= rxq->nb_rx_desc;
2464 rxdp = &rxq->rx_ring[desc];
2465 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2469 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2472 struct ixgbe_adapter *adapter =
2473 (struct ixgbe_adapter *)dev->data->dev_private;
2475 PMD_INIT_FUNC_TRACE();
2477 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2478 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2480 txq->ops->release_mbufs(txq);
2481 txq->ops->reset(txq);
2485 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2486 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2488 ixgbe_rx_queue_release_mbufs(rxq);
2489 ixgbe_reset_rx_queue(adapter, rxq);
2494 /*********************************************************************
2496 * Device RX/TX init functions
2498 **********************************************************************/
2501 * Receive Side Scaling (RSS)
2502 * See section 7.1.2.8 in the following document:
2503 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2506 * The source and destination IP addresses of the IP header and the source
2507 * and destination ports of TCP/UDP headers, if any, of received packets are
2508 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2509 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2510 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2511 * RSS output index which is used as the RX queue index where to store the
2513 * The following output is supplied in the RX write-back descriptor:
2514 * - 32-bit result of the Microsoft RSS hash function,
2515 * - 4-bit RSS type field.
2519 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2520 * Used as the default key.
2522 static uint8_t rss_intel_key[40] = {
2523 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2524 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2525 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2526 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2527 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2531 ixgbe_rss_disable(struct rte_eth_dev *dev)
2533 struct ixgbe_hw *hw;
2536 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2538 mrqc &= ~IXGBE_MRQC_RSSEN;
2539 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2543 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2551 hash_key = rss_conf->rss_key;
2552 if (hash_key != NULL) {
2553 /* Fill in RSS hash key */
2554 for (i = 0; i < 10; i++) {
2555 rss_key = hash_key[(i * 4)];
2556 rss_key |= hash_key[(i * 4) + 1] << 8;
2557 rss_key |= hash_key[(i * 4) + 2] << 16;
2558 rss_key |= hash_key[(i * 4) + 3] << 24;
2559 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2563 /* Set configured hashing protocols in MRQC register */
2564 rss_hf = rss_conf->rss_hf;
2565 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2566 if (rss_hf & ETH_RSS_IPV4)
2567 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2568 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2569 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2570 if (rss_hf & ETH_RSS_IPV6)
2571 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2572 if (rss_hf & ETH_RSS_IPV6_EX)
2573 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2574 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2575 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2576 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2577 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2578 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2579 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2580 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2581 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2582 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2583 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2584 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2588 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2589 struct rte_eth_rss_conf *rss_conf)
2591 struct ixgbe_hw *hw;
2595 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2599 * "RSS enabling cannot be done dynamically while it must be
2600 * preceded by a software reset"
2601 * Before changing anything, first check that the update RSS operation
2602 * does not attempt to disable RSS, if RSS was enabled at
2603 * initialization time, or does not attempt to enable RSS, if RSS was
2604 * disabled at initialization time.
2606 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2607 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2608 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2609 if (rss_hf != 0) /* Enable RSS */
2611 return 0; /* Nothing to do */
2614 if (rss_hf == 0) /* Disable RSS */
2616 ixgbe_hw_rss_hash_set(hw, rss_conf);
2621 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2622 struct rte_eth_rss_conf *rss_conf)
2624 struct ixgbe_hw *hw;
2631 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 hash_key = rss_conf->rss_key;
2633 if (hash_key != NULL) {
2634 /* Return RSS hash key */
2635 for (i = 0; i < 10; i++) {
2636 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2637 hash_key[(i * 4)] = rss_key & 0x000000FF;
2638 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2639 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2640 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2644 /* Get RSS functions configured in MRQC register */
2645 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2646 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2647 rss_conf->rss_hf = 0;
2651 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2652 rss_hf |= ETH_RSS_IPV4;
2653 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2654 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2655 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2656 rss_hf |= ETH_RSS_IPV6;
2657 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2658 rss_hf |= ETH_RSS_IPV6_EX;
2659 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2660 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2661 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2662 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2663 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2664 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2665 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2666 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2667 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2668 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2669 rss_conf->rss_hf = rss_hf;
2674 ixgbe_rss_configure(struct rte_eth_dev *dev)
2676 struct rte_eth_rss_conf rss_conf;
2677 struct ixgbe_hw *hw;
2682 PMD_INIT_FUNC_TRACE();
2683 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686 * Fill in redirection table
2687 * The byte-swap is needed because NIC registers are in
2688 * little-endian order.
2691 for (i = 0, j = 0; i < 128; i++, j++) {
2692 if (j == dev->data->nb_rx_queues)
2694 reta = (reta << 8) | j;
2696 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2701 * Configure the RSS key and the RSS protocols used to compute
2702 * the RSS hash of input packets.
2704 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2705 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2706 ixgbe_rss_disable(dev);
2709 if (rss_conf.rss_key == NULL)
2710 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2711 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2714 #define NUM_VFTA_REGISTERS 128
2715 #define NIC_RX_BUFFER_SIZE 0x200
2718 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2720 struct rte_eth_vmdq_dcb_conf *cfg;
2721 struct ixgbe_hw *hw;
2722 enum rte_eth_nb_pools num_pools;
2723 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2725 uint8_t nb_tcs; /* number of traffic classes */
2728 PMD_INIT_FUNC_TRACE();
2729 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2731 num_pools = cfg->nb_queue_pools;
2732 /* Check we have a valid number of pools */
2733 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2734 ixgbe_rss_disable(dev);
2737 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2738 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2742 * split rx buffer up into sections, each for 1 traffic class
2744 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2745 for (i = 0 ; i < nb_tcs; i++) {
2746 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2747 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2748 /* clear 10 bits. */
2749 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2750 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2752 /* zero alloc all unused TCs */
2753 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2754 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2755 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2756 /* clear 10 bits. */
2757 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2760 /* MRQC: enable vmdq and dcb */
2761 mrqc = ((num_pools == ETH_16_POOLS) ? \
2762 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2763 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2765 /* PFVTCTL: turn on virtualisation and set the default pool */
2766 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2767 if (cfg->enable_default_pool) {
2768 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2770 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2773 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2775 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2777 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2779 * mapping is done with 3 bits per priority,
2780 * so shift by i*3 each time
2782 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2784 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2786 /* RTRPCS: DCB related */
2787 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2789 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2790 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2791 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2792 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2794 /* VFTA - enable all vlan filters */
2795 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2796 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2799 /* VFRE: pool enabling for receive - 16 or 32 */
2800 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2801 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2804 * MPSAR - allow pools to read specific mac addresses
2805 * In this case, all pools should be able to read from mac addr 0
2807 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2808 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2810 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2811 for (i = 0; i < cfg->nb_pool_maps; i++) {
2812 /* set vlan id in VF register and set the valid bit */
2813 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2814 (cfg->pool_map[i].vlan_id & 0xFFF)));
2816 * Put the allowed pools in VFB reg. As we only have 16 or 32
2817 * pools, we only need to use the first half of the register
2820 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2825 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2826 * @hw: pointer to hardware structure
2827 * @dcb_config: pointer to ixgbe_dcb_config structure
2830 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2831 struct ixgbe_dcb_config *dcb_config)
2836 PMD_INIT_FUNC_TRACE();
2837 if (hw->mac.type != ixgbe_mac_82598EB) {
2838 /* Disable the Tx desc arbiter so that MTQC can be changed */
2839 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2840 reg |= IXGBE_RTTDCS_ARBDIS;
2841 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2843 /* Enable DCB for Tx with 8 TCs */
2844 if (dcb_config->num_tcs.pg_tcs == 8) {
2845 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2848 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2850 if (dcb_config->vt_mode)
2851 reg |= IXGBE_MTQC_VT_ENA;
2852 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2854 /* Disable drop for all queues */
2855 for (q = 0; q < 128; q++)
2856 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2857 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2859 /* Enable the Tx desc arbiter */
2860 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2861 reg &= ~IXGBE_RTTDCS_ARBDIS;
2862 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2864 /* Enable Security TX Buffer IFG for DCB */
2865 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2866 reg |= IXGBE_SECTX_DCB;
2867 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2873 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2874 * @dev: pointer to rte_eth_dev structure
2875 * @dcb_config: pointer to ixgbe_dcb_config structure
2878 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2879 struct ixgbe_dcb_config *dcb_config)
2881 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2882 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2883 struct ixgbe_hw *hw =
2884 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886 PMD_INIT_FUNC_TRACE();
2887 if (hw->mac.type != ixgbe_mac_82598EB)
2888 /*PF VF Transmit Enable*/
2889 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2890 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2892 /*Configure general DCB TX parameters*/
2893 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2898 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2899 struct ixgbe_dcb_config *dcb_config)
2901 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2902 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2903 struct ixgbe_dcb_tc_config *tc;
2906 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2907 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2908 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2909 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2912 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2913 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2915 /* User Priority to Traffic Class mapping */
2916 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2917 j = vmdq_rx_conf->dcb_queue[i];
2918 tc = &dcb_config->tc_config[j];
2919 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2925 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2926 struct ixgbe_dcb_config *dcb_config)
2928 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2929 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2930 struct ixgbe_dcb_tc_config *tc;
2933 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2934 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2935 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2936 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2939 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2940 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2943 /* User Priority to Traffic Class mapping */
2944 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2945 j = vmdq_tx_conf->dcb_queue[i];
2946 tc = &dcb_config->tc_config[j];
2947 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2954 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2955 struct ixgbe_dcb_config *dcb_config)
2957 struct rte_eth_dcb_rx_conf *rx_conf =
2958 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2959 struct ixgbe_dcb_tc_config *tc;
2962 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2963 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2965 /* User Priority to Traffic Class mapping */
2966 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2967 j = rx_conf->dcb_queue[i];
2968 tc = &dcb_config->tc_config[j];
2969 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2975 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2976 struct ixgbe_dcb_config *dcb_config)
2978 struct rte_eth_dcb_tx_conf *tx_conf =
2979 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2980 struct ixgbe_dcb_tc_config *tc;
2983 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2984 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2986 /* User Priority to Traffic Class mapping */
2987 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2988 j = tx_conf->dcb_queue[i];
2989 tc = &dcb_config->tc_config[j];
2990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2996 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2997 * @hw: pointer to hardware structure
2998 * @dcb_config: pointer to ixgbe_dcb_config structure
3001 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3002 struct ixgbe_dcb_config *dcb_config)
3008 PMD_INIT_FUNC_TRACE();
3010 * Disable the arbiter before changing parameters
3011 * (always enable recycle mode; WSP)
3013 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3014 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3016 if (hw->mac.type != ixgbe_mac_82598EB) {
3017 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3018 if (dcb_config->num_tcs.pg_tcs == 4) {
3019 if (dcb_config->vt_mode)
3020 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3021 IXGBE_MRQC_VMDQRT4TCEN;
3023 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3024 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3028 if (dcb_config->num_tcs.pg_tcs == 8) {
3029 if (dcb_config->vt_mode)
3030 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3031 IXGBE_MRQC_VMDQRT8TCEN;
3033 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3034 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3039 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3042 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3043 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3044 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3045 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3047 /* VFTA - enable all vlan filters */
3048 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3049 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3053 * Configure Rx packet plane (recycle mode; WSP) and
3056 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3057 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3063 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3064 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3066 switch (hw->mac.type) {
3067 case ixgbe_mac_82598EB:
3068 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3070 case ixgbe_mac_82599EB:
3071 case ixgbe_mac_X540:
3072 case ixgbe_mac_X550:
3073 case ixgbe_mac_X550EM_x:
3074 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3083 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3084 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3086 switch (hw->mac.type) {
3087 case ixgbe_mac_82598EB:
3088 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3089 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3091 case ixgbe_mac_82599EB:
3092 case ixgbe_mac_X540:
3093 case ixgbe_mac_X550:
3094 case ixgbe_mac_X550EM_x:
3095 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3096 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3103 #define DCB_RX_CONFIG 1
3104 #define DCB_TX_CONFIG 1
3105 #define DCB_TX_PB 1024
3107 * ixgbe_dcb_hw_configure - Enable DCB and configure
3108 * general DCB in VT mode and non-VT mode parameters
3109 * @dev: pointer to rte_eth_dev structure
3110 * @dcb_config: pointer to ixgbe_dcb_config structure
3113 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3114 struct ixgbe_dcb_config *dcb_config)
3117 uint8_t i,pfc_en,nb_tcs;
3119 uint8_t config_dcb_rx = 0;
3120 uint8_t config_dcb_tx = 0;
3121 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3122 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3123 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3124 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3125 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3126 struct ixgbe_dcb_tc_config *tc;
3127 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3128 struct ixgbe_hw *hw =
3129 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 switch(dev->data->dev_conf.rxmode.mq_mode){
3132 case ETH_MQ_RX_VMDQ_DCB:
3133 dcb_config->vt_mode = true;
3134 if (hw->mac.type != ixgbe_mac_82598EB) {
3135 config_dcb_rx = DCB_RX_CONFIG;
3137 *get dcb and VT rx configuration parameters
3140 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3141 /*Configure general VMDQ and DCB RX parameters*/
3142 ixgbe_vmdq_dcb_configure(dev);
3146 dcb_config->vt_mode = false;
3147 config_dcb_rx = DCB_RX_CONFIG;
3148 /* Get dcb TX configuration parameters from rte_eth_conf */
3149 ixgbe_dcb_rx_config(dev,dcb_config);
3150 /*Configure general DCB RX parameters*/
3151 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3154 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3157 switch (dev->data->dev_conf.txmode.mq_mode) {
3158 case ETH_MQ_TX_VMDQ_DCB:
3159 dcb_config->vt_mode = true;
3160 config_dcb_tx = DCB_TX_CONFIG;
3161 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3162 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3163 /*Configure general VMDQ and DCB TX parameters*/
3164 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3168 dcb_config->vt_mode = false;
3169 config_dcb_tx = DCB_TX_CONFIG;
3170 /*get DCB TX configuration parameters from rte_eth_conf*/
3171 ixgbe_dcb_tx_config(dev,dcb_config);
3172 /*Configure general DCB TX parameters*/
3173 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3176 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3180 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3182 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3183 if(nb_tcs == ETH_4_TCS) {
3184 /* Avoid un-configured priority mapping to TC0 */
3186 uint8_t mask = 0xFF;
3187 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3188 mask = (uint8_t)(mask & (~ (1 << map[i])));
3189 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3190 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3194 /* Re-configure 4 TCs BW */
3195 for (i = 0; i < nb_tcs; i++) {
3196 tc = &dcb_config->tc_config[i];
3197 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3198 (uint8_t)(100 / nb_tcs);
3199 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3200 (uint8_t)(100 / nb_tcs);
3202 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3203 tc = &dcb_config->tc_config[i];
3204 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3205 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3210 /* Set RX buffer size */
3211 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3212 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3213 for (i = 0 ; i < nb_tcs; i++) {
3214 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3216 /* zero alloc all unused TCs */
3217 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3218 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3222 /* Only support an equally distributed Tx packet buffer strategy. */
3223 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3224 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3225 for (i = 0; i < nb_tcs; i++) {
3226 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3227 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3229 /* Clear unused TCs, if any, to zero buffer size*/
3230 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3231 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3232 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3236 /*Calculates traffic class credits*/
3237 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3238 IXGBE_DCB_TX_CONFIG);
3239 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3240 IXGBE_DCB_RX_CONFIG);
3243 /* Unpack CEE standard containers */
3244 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3245 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3246 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3247 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3248 /* Configure PG(ETS) RX */
3249 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3253 /* Unpack CEE standard containers */
3254 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3255 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3256 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3257 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3258 /* Configure PG(ETS) TX */
3259 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3262 /*Configure queue statistics registers*/
3263 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3265 /* Check if the PFC is supported */
3266 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3267 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3268 for (i = 0; i < nb_tcs; i++) {
3270 * If the TC count is 8,and the default high_water is 48,
3271 * the low_water is 16 as default.
3273 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3274 hw->fc.low_water[i] = pbsize / 4;
3275 /* Enable pfc for this TC */
3276 tc = &dcb_config->tc_config[i];
3277 tc->pfc = ixgbe_dcb_pfc_enabled;
3279 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3280 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3282 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3289 * ixgbe_configure_dcb - Configure DCB Hardware
3290 * @dev: pointer to rte_eth_dev
3292 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3294 struct ixgbe_dcb_config *dcb_cfg =
3295 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3296 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3298 PMD_INIT_FUNC_TRACE();
3300 /* check support mq_mode for DCB */
3301 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3302 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3305 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3308 /** Configure DCB hardware **/
3309 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3315 * VMDq only support for 10 GbE NIC.
3318 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3320 struct rte_eth_vmdq_rx_conf *cfg;
3321 struct ixgbe_hw *hw;
3322 enum rte_eth_nb_pools num_pools;
3323 uint32_t mrqc, vt_ctl, vlanctrl;
3327 PMD_INIT_FUNC_TRACE();
3328 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3330 num_pools = cfg->nb_queue_pools;
3332 ixgbe_rss_disable(dev);
3334 /* MRQC: enable vmdq */
3335 mrqc = IXGBE_MRQC_VMDQEN;
3336 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3338 /* PFVTCTL: turn on virtualisation and set the default pool */
3339 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3340 if (cfg->enable_default_pool)
3341 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3343 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3345 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3347 for (i = 0; i < (int)num_pools; i++) {
3348 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3349 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3352 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3353 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3354 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3355 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3357 /* VFTA - enable all vlan filters */
3358 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3359 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3361 /* VFRE: pool enabling for receive - 64 */
3362 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3363 if (num_pools == ETH_64_POOLS)
3364 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3367 * MPSAR - allow pools to read specific mac addresses
3368 * In this case, all pools should be able to read from mac addr 0
3370 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3371 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3373 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3374 for (i = 0; i < cfg->nb_pool_maps; i++) {
3375 /* set vlan id in VF register and set the valid bit */
3376 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3377 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3379 * Put the allowed pools in VFB reg. As we only have 16 or 64
3380 * pools, we only need to use the first half of the register
3383 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3384 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3385 (cfg->pool_map[i].pools & UINT32_MAX));
3387 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3388 ((cfg->pool_map[i].pools >> 32) \
3393 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3394 if (cfg->enable_loop_back) {
3395 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3396 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3397 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3400 IXGBE_WRITE_FLUSH(hw);
3404 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3405 * @hw: pointer to hardware structure
3408 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3413 PMD_INIT_FUNC_TRACE();
3414 /*PF VF Transmit Enable*/
3415 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3416 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3418 /* Disable the Tx desc arbiter so that MTQC can be changed */
3419 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3420 reg |= IXGBE_RTTDCS_ARBDIS;
3421 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3423 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3424 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3426 /* Disable drop for all queues */
3427 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3428 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3429 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3431 /* Enable the Tx desc arbiter */
3432 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3433 reg &= ~IXGBE_RTTDCS_ARBDIS;
3434 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3436 IXGBE_WRITE_FLUSH(hw);
3442 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3444 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3448 /* Initialize software ring entries */
3449 for (i = 0; i < rxq->nb_rx_desc; i++) {
3450 volatile union ixgbe_adv_rx_desc *rxd;
3451 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3453 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3454 (unsigned) rxq->queue_id);
3458 rte_mbuf_refcnt_set(mbuf, 1);
3460 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3462 mbuf->port = rxq->port_id;
3465 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3466 rxd = &rxq->rx_ring[i];
3467 rxd->read.hdr_addr = dma_addr;
3468 rxd->read.pkt_addr = dma_addr;
3476 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3478 struct ixgbe_hw *hw;
3481 ixgbe_rss_configure(dev);
3483 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485 /* MRQC: enable VF RSS */
3486 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3487 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3488 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3490 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3494 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3498 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3502 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3508 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3510 struct ixgbe_hw *hw =
3511 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3515 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3520 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3521 IXGBE_MRQC_VMDQRT4TCEN);
3525 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3526 IXGBE_MRQC_VMDQRT8TCEN);
3530 "invalid pool number in IOV mode");
3537 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3539 struct ixgbe_hw *hw =
3540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542 if (hw->mac.type == ixgbe_mac_82598EB)
3545 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3547 * SRIOV inactive scheme
3548 * any DCB/RSS w/o VMDq multi-queue setting
3550 switch (dev->data->dev_conf.rxmode.mq_mode) {
3552 ixgbe_rss_configure(dev);
3555 case ETH_MQ_RX_VMDQ_DCB:
3556 ixgbe_vmdq_dcb_configure(dev);
3559 case ETH_MQ_RX_VMDQ_ONLY:
3560 ixgbe_vmdq_rx_hw_configure(dev);
3563 case ETH_MQ_RX_NONE:
3564 /* if mq_mode is none, disable rss mode.*/
3565 default: ixgbe_rss_disable(dev);
3569 * SRIOV active scheme
3570 * Support RSS together with VMDq & SRIOV
3572 switch (dev->data->dev_conf.rxmode.mq_mode) {
3574 case ETH_MQ_RX_VMDQ_RSS:
3575 ixgbe_config_vf_rss(dev);
3578 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3579 case ETH_MQ_RX_VMDQ_DCB:
3580 case ETH_MQ_RX_VMDQ_DCB_RSS:
3582 "Could not support DCB with VMDq & SRIOV");
3585 ixgbe_config_vf_default(dev);
3594 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3596 struct ixgbe_hw *hw =
3597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601 if (hw->mac.type == ixgbe_mac_82598EB)
3604 /* disable arbiter before setting MTQC */
3605 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3606 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3607 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3609 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3611 * SRIOV inactive scheme
3612 * any DCB w/o VMDq multi-queue setting
3614 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3615 ixgbe_vmdq_tx_hw_configure(hw);
3617 mtqc = IXGBE_MTQC_64Q_1PB;
3618 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3621 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3624 * SRIOV active scheme
3625 * FIXME if support DCB together with VMDq & SRIOV
3628 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3631 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3634 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3638 mtqc = IXGBE_MTQC_64Q_1PB;
3639 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3641 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3644 /* re-enable arbiter */
3645 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3646 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3652 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3654 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3655 * spec rev. 3.0 chapter 8.2.3.8.13.
3657 * @pool Memory pool of the Rx queue
3659 static inline uint32_t
3660 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3662 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3664 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3667 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3670 return IXGBE_RSCCTL_MAXDESC_16;
3671 else if (maxdesc >= 8)
3672 return IXGBE_RSCCTL_MAXDESC_8;
3673 else if (maxdesc >= 4)
3674 return IXGBE_RSCCTL_MAXDESC_4;
3676 return IXGBE_RSCCTL_MAXDESC_1;
3680 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3683 * (Taken from FreeBSD tree)
3684 * (yes this is all very magic and confusing :)
3687 * @entry the register array entry
3688 * @vector the MSIX vector for this queue
3692 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697 vector |= IXGBE_IVAR_ALLOC_VAL;
3699 switch (hw->mac.type) {
3701 case ixgbe_mac_82598EB:
3703 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3705 entry += (type * 64);
3706 index = (entry >> 2) & 0x1F;
3707 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3708 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3709 ivar |= (vector << (8 * (entry & 0x3)));
3710 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3713 case ixgbe_mac_82599EB:
3714 case ixgbe_mac_X540:
3715 if (type == -1) { /* MISC IVAR */
3716 index = (entry & 1) * 8;
3717 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3718 ivar &= ~(0xFF << index);
3719 ivar |= (vector << index);
3720 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3721 } else { /* RX/TX IVARS */
3722 index = (16 * (entry & 1)) + (8 * type);
3723 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3724 ivar &= ~(0xFF << index);
3725 ivar |= (vector << index);
3726 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3736 void ixgbe_set_rx_function(struct rte_eth_dev *dev)
3738 struct ixgbe_adapter *adapter =
3739 (struct ixgbe_adapter *)dev->data->dev_private;
3742 * In order to allow Vector Rx there are a few configuration
3743 * conditions to be met and Rx Bulk Allocation should be allowed.
3745 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3746 !adapter->rx_bulk_alloc_allowed) {
3747 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3748 "preconditions or RTE_IXGBE_INC_VECTOR is "
3750 dev->data->port_id);
3752 adapter->rx_vec_allowed = false;
3756 * Initialize the appropriate LRO callback.
3758 * If all queues satisfy the bulk allocation preconditions
3759 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3760 * Otherwise use a single allocation version.
3762 if (dev->data->lro) {
3763 if (adapter->rx_bulk_alloc_allowed) {
3764 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
3765 "allocation version");
3766 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3768 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
3769 "allocation version");
3770 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3772 } else if (dev->data->scattered_rx) {
3774 * Set the non-LRO scattered callback: there are Vector and
3775 * single allocation versions.
3777 if (adapter->rx_vec_allowed) {
3778 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3779 "callback (port=%d).",
3780 dev->data->port_id);
3782 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3783 } else if (adapter->rx_bulk_alloc_allowed) {
3784 PMD_INIT_LOG(INFO, "Using a Scattered with bulk "
3785 "allocation callback (port=%d).",
3786 dev->data->port_id);
3787 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3789 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3790 "single allocation) "
3791 "Scattered Rx callback "
3793 dev->data->port_id);
3795 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3798 * Below we set "simple" callbacks according to port/queues parameters.
3799 * If parameters allow we are going to choose between the following
3803 * - Single buffer allocation (the simplest one)
3805 } else if (adapter->rx_vec_allowed) {
3806 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3807 "burst size no less than 32.");
3809 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3810 } else if (adapter->rx_bulk_alloc_allowed) {
3811 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3812 "satisfied. Rx Burst Bulk Alloc function "
3813 "will be used on port=%d.",
3814 dev->data->port_id);
3816 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
3818 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3819 "satisfied, or Scattered Rx is requested, "
3820 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
3821 "is not enabled (port=%d).",
3822 dev->data->port_id);
3824 dev->rx_pkt_burst = ixgbe_recv_pkts;
3829 * ixgbe_set_rsc - configure RSC related port HW registers
3831 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
3832 * of 82599 Spec (x540 configuration is virtually the same).
3836 * Returns 0 in case of success or a non-zero error code
3839 ixgbe_set_rsc(struct rte_eth_dev *dev)
3841 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
3842 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3843 struct rte_eth_dev_info dev_info = { 0 };
3844 bool rsc_capable = false;
3849 dev->dev_ops->dev_infos_get(dev, &dev_info);
3850 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
3853 if (!rsc_capable && rx_conf->enable_lro) {
3854 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
3859 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
3861 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
3863 * According to chapter of 4.6.7.2.1 of the Spec Rev.
3864 * 3.0 RSC configuration requires HW CRC stripping being
3865 * enabled. If user requested both HW CRC stripping off
3866 * and RSC on - return an error.
3868 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
3873 /* RFCTL configuration */
3875 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3876 if (rx_conf->enable_lro)
3878 * Since NFS packets coalescing is not supported - clear
3879 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
3882 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
3883 IXGBE_RFCTL_NFSR_DIS);
3885 rfctl |= IXGBE_RFCTL_RSC_DIS;
3887 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3890 /* If LRO hasn't been requested - we are done here. */
3891 if (!rx_conf->enable_lro)
3894 /* Set RDRXCTL.RSCACKC bit */
3895 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3896 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
3897 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3899 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
3900 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3901 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3903 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
3905 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
3907 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
3909 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
3912 * ixgbe PMD doesn't support header-split at the moment.
3914 * Following the 4.6.7.2.1 chapter of the 82599/x540
3915 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
3916 * should be configured even if header split is not
3917 * enabled. We will configure it 128 bytes following the
3918 * recommendation in the spec.
3920 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
3921 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3922 IXGBE_SRRCTL_BSIZEHDR_MASK;
3925 * TODO: Consider setting the Receive Descriptor Minimum
3926 * Threshold Size for an RSC case. This is not an obviously
3927 * beneficiary option but the one worth considering...
3930 rscctl |= IXGBE_RSCCTL_RSCEN;
3931 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
3932 psrtype |= IXGBE_PSRTYPE_TCPHDR;
3935 * RSC: Set ITR interval corresponding to 2K ints/s.
3937 * Full-sized RSC aggregations for a 10Gb/s link will
3938 * arrive at about 20K aggregation/s rate.
3940 * 2K inst/s rate will make only 10% of the
3941 * aggregations to be closed due to the interrupt timer
3942 * expiration for a streaming at wire-speed case.
3944 * For a sparse streaming case this setting will yield
3945 * at most 500us latency for a single RSC aggregation.
3947 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
3948 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
3950 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3951 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
3952 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3953 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
3956 * RSC requires the mapping of the queue to the
3959 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
3964 PMD_INIT_LOG(INFO, "enabling LRO mode");
3970 * Initializes Receive Unit.
3973 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3975 struct ixgbe_hw *hw;
3976 struct ixgbe_rx_queue *rxq;
3987 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
3990 PMD_INIT_FUNC_TRACE();
3991 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 * Make sure receives are disabled while setting
3995 * up the RX context (registers, descriptor rings, etc.).
3997 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3998 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4000 /* Enable receipt of broadcasted frames */
4001 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4002 fctrl |= IXGBE_FCTRL_BAM;
4003 fctrl |= IXGBE_FCTRL_DPF;
4004 fctrl |= IXGBE_FCTRL_PMCF;
4005 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4008 * Configure CRC stripping, if any.
4010 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4011 if (rx_conf->hw_strip_crc)
4012 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4014 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4017 * Configure jumbo frame support, if any.
4019 if (rx_conf->jumbo_frame == 1) {
4020 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4021 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4022 maxfrs &= 0x0000FFFF;
4023 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4024 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4026 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4029 * If loopback mode is configured for 82599, set LPBK bit.
4031 if (hw->mac.type == ixgbe_mac_82599EB &&
4032 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4033 hlreg0 |= IXGBE_HLREG0_LPBK;
4035 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4037 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4039 /* Setup RX queues */
4040 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4041 rxq = dev->data->rx_queues[i];
4044 * Reset crc_len in case it was changed after queue setup by a
4045 * call to configure.
4047 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4049 /* Setup the Base and Length of the Rx Descriptor Rings */
4050 bus_addr = rxq->rx_ring_phys_addr;
4051 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4052 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4053 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4054 (uint32_t)(bus_addr >> 32));
4055 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4056 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4057 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4058 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4060 /* Configure the SRRCTL register */
4061 #ifdef RTE_HEADER_SPLIT_ENABLE
4063 * Configure Header Split
4065 if (rx_conf->header_split) {
4066 if (hw->mac.type == ixgbe_mac_82599EB) {
4067 /* Must setup the PSRTYPE register */
4069 psrtype = IXGBE_PSRTYPE_TCPHDR |
4070 IXGBE_PSRTYPE_UDPHDR |
4071 IXGBE_PSRTYPE_IPV4HDR |
4072 IXGBE_PSRTYPE_IPV6HDR;
4073 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4075 srrctl = ((rx_conf->split_hdr_size <<
4076 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4077 IXGBE_SRRCTL_BSIZEHDR_MASK);
4078 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4081 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4083 /* Set if packets are dropped when no descriptors available */
4085 srrctl |= IXGBE_SRRCTL_DROP_EN;
4088 * Configure the RX buffer size in the BSIZEPACKET field of
4089 * the SRRCTL register of the queue.
4090 * The value is in 1 KB resolution. Valid values can be from
4093 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4094 RTE_PKTMBUF_HEADROOM);
4095 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4096 IXGBE_SRRCTL_BSIZEPKT_MASK);
4098 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4100 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4101 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4103 /* It adds dual VLAN length for supporting dual VLAN */
4104 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4105 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4106 dev->data->scattered_rx = 1;
4109 if (rx_conf->enable_scatter)
4110 dev->data->scattered_rx = 1;
4113 * Device configured with multiple RX queues.
4115 ixgbe_dev_mq_rx_configure(dev);
4118 * Setup the Checksum Register.
4119 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4120 * Enable IP/L4 checkum computation by hardware if requested to do so.
4122 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4123 rxcsum |= IXGBE_RXCSUM_PCSD;
4124 if (rx_conf->hw_ip_checksum)
4125 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4127 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4129 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4131 if (hw->mac.type == ixgbe_mac_82599EB ||
4132 hw->mac.type == ixgbe_mac_X540) {
4133 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4134 if (rx_conf->hw_strip_crc)
4135 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4137 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4138 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4139 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4142 rc = ixgbe_set_rsc(dev);
4146 ixgbe_set_rx_function(dev);
4152 * Initializes Transmit Unit.
4155 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4157 struct ixgbe_hw *hw;
4158 struct ixgbe_tx_queue *txq;
4164 PMD_INIT_FUNC_TRACE();
4165 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4167 /* Enable TX CRC (checksum offload requirement) and hw padding
4168 * (TSO requirement) */
4169 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4170 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4171 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4173 /* Setup the Base and Length of the Tx Descriptor Rings */
4174 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4175 txq = dev->data->tx_queues[i];
4177 bus_addr = txq->tx_ring_phys_addr;
4178 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4179 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4180 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4181 (uint32_t)(bus_addr >> 32));
4182 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4183 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4184 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4185 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4186 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4189 * Disable Tx Head Writeback RO bit, since this hoses
4190 * bookkeeping if things aren't delivered in order.
4192 switch (hw->mac.type) {
4193 case ixgbe_mac_82598EB:
4194 txctrl = IXGBE_READ_REG(hw,
4195 IXGBE_DCA_TXCTRL(txq->reg_idx));
4196 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4197 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4201 case ixgbe_mac_82599EB:
4202 case ixgbe_mac_X540:
4203 case ixgbe_mac_X550:
4204 case ixgbe_mac_X550EM_x:
4206 txctrl = IXGBE_READ_REG(hw,
4207 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4208 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4209 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4215 /* Device configured with multiple TX queues. */
4216 ixgbe_dev_mq_tx_configure(dev);
4220 * Set up link for 82599 loopback mode Tx->Rx.
4223 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4225 PMD_INIT_FUNC_TRACE();
4227 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4228 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4230 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4239 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4240 ixgbe_reset_pipeline_82599(hw);
4242 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4248 * Start Transmit and Receive Units.
4251 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4253 struct ixgbe_hw *hw;
4254 struct ixgbe_tx_queue *txq;
4255 struct ixgbe_rx_queue *rxq;
4262 PMD_INIT_FUNC_TRACE();
4263 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4265 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4266 txq = dev->data->tx_queues[i];
4267 /* Setup Transmit Threshold Registers */
4268 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4269 txdctl |= txq->pthresh & 0x7F;
4270 txdctl |= ((txq->hthresh & 0x7F) << 8);
4271 txdctl |= ((txq->wthresh & 0x7F) << 16);
4272 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4275 if (hw->mac.type != ixgbe_mac_82598EB) {
4276 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4277 dmatxctl |= IXGBE_DMATXCTL_TE;
4278 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4281 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4282 txq = dev->data->tx_queues[i];
4283 if (!txq->tx_deferred_start) {
4284 ret = ixgbe_dev_tx_queue_start(dev, i);
4290 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4291 rxq = dev->data->rx_queues[i];
4292 if (!rxq->rx_deferred_start) {
4293 ret = ixgbe_dev_rx_queue_start(dev, i);
4299 /* Enable Receive engine */
4300 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4301 if (hw->mac.type == ixgbe_mac_82598EB)
4302 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4303 rxctrl |= IXGBE_RXCTRL_RXEN;
4304 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4306 /* If loopback mode is enabled for 82599, set up the link accordingly */
4307 if (hw->mac.type == ixgbe_mac_82599EB &&
4308 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4309 ixgbe_setup_loopback_link_82599(hw);
4315 * Start Receive Units for specified queue.
4318 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4320 struct ixgbe_hw *hw;
4321 struct ixgbe_rx_queue *rxq;
4325 PMD_INIT_FUNC_TRACE();
4326 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328 if (rx_queue_id < dev->data->nb_rx_queues) {
4329 rxq = dev->data->rx_queues[rx_queue_id];
4331 /* Allocate buffers for descriptor rings */
4332 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4333 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4337 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4338 rxdctl |= IXGBE_RXDCTL_ENABLE;
4339 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4341 /* Wait until RX Enable ready */
4342 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4345 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4346 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4348 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4351 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4352 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4360 * Stop Receive Units for specified queue.
4363 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4365 struct ixgbe_hw *hw;
4366 struct ixgbe_adapter *adapter =
4367 (struct ixgbe_adapter *)dev->data->dev_private;
4368 struct ixgbe_rx_queue *rxq;
4372 PMD_INIT_FUNC_TRACE();
4373 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375 if (rx_queue_id < dev->data->nb_rx_queues) {
4376 rxq = dev->data->rx_queues[rx_queue_id];
4378 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4379 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4380 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4382 /* Wait until RX Enable ready */
4383 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4386 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4387 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4389 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4392 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4394 ixgbe_rx_queue_release_mbufs(rxq);
4395 ixgbe_reset_rx_queue(adapter, rxq);
4404 * Start Transmit Units for specified queue.
4407 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4409 struct ixgbe_hw *hw;
4410 struct ixgbe_tx_queue *txq;
4414 PMD_INIT_FUNC_TRACE();
4415 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417 if (tx_queue_id < dev->data->nb_tx_queues) {
4418 txq = dev->data->tx_queues[tx_queue_id];
4419 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4420 txdctl |= IXGBE_TXDCTL_ENABLE;
4421 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4423 /* Wait until TX Enable ready */
4424 if (hw->mac.type == ixgbe_mac_82599EB) {
4425 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4428 txdctl = IXGBE_READ_REG(hw,
4429 IXGBE_TXDCTL(txq->reg_idx));
4430 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4432 PMD_INIT_LOG(ERR, "Could not enable "
4433 "Tx Queue %d", tx_queue_id);
4436 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4437 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4445 * Stop Transmit Units for specified queue.
4448 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4450 struct ixgbe_hw *hw;
4451 struct ixgbe_tx_queue *txq;
4453 uint32_t txtdh, txtdt;
4456 PMD_INIT_FUNC_TRACE();
4457 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459 if (tx_queue_id < dev->data->nb_tx_queues) {
4460 txq = dev->data->tx_queues[tx_queue_id];
4462 /* Wait until TX queue is empty */
4463 if (hw->mac.type == ixgbe_mac_82599EB) {
4464 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4466 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4467 txtdh = IXGBE_READ_REG(hw,
4468 IXGBE_TDH(txq->reg_idx));
4469 txtdt = IXGBE_READ_REG(hw,
4470 IXGBE_TDT(txq->reg_idx));
4471 } while (--poll_ms && (txtdh != txtdt));
4473 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4474 "when stopping.", tx_queue_id);
4477 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4478 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4481 /* Wait until TX Enable ready */
4482 if (hw->mac.type == ixgbe_mac_82599EB) {
4483 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4486 txdctl = IXGBE_READ_REG(hw,
4487 IXGBE_TXDCTL(txq->reg_idx));
4488 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4490 PMD_INIT_LOG(ERR, "Could not disable "
4491 "Tx Queue %d", tx_queue_id);
4494 if (txq->ops != NULL) {
4495 txq->ops->release_mbufs(txq);
4496 txq->ops->reset(txq);
4505 * [VF] Initializes Receive Unit.
4508 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4510 struct ixgbe_hw *hw;
4511 struct ixgbe_rx_queue *rxq;
4513 uint32_t srrctl, psrtype = 0;
4518 PMD_INIT_FUNC_TRACE();
4519 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4522 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4523 "it should be power of 2");
4527 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4528 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4529 "it should be equal to or less than %d",
4530 hw->mac.max_rx_queues);
4535 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4536 * disables the VF receipt of packets if the PF MTU is > 1500.
4537 * This is done to deal with 82599 limitations that imposes
4538 * the PF and all VFs to share the same MTU.
4539 * Then, the PF driver enables again the VF receipt of packet when
4540 * the VF driver issues a IXGBE_VF_SET_LPE request.
4541 * In the meantime, the VF device cannot be used, even if the VF driver
4542 * and the Guest VM network stack are ready to accept packets with a
4543 * size up to the PF MTU.
4544 * As a work-around to this PF behaviour, force the call to
4545 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4546 * VF packets received can work in all cases.
4548 ixgbevf_rlpml_set_vf(hw,
4549 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4551 /* Setup RX queues */
4552 dev->rx_pkt_burst = ixgbe_recv_pkts;
4553 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4554 rxq = dev->data->rx_queues[i];
4556 /* Allocate buffers for descriptor rings */
4557 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4561 /* Setup the Base and Length of the Rx Descriptor Rings */
4562 bus_addr = rxq->rx_ring_phys_addr;
4564 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4565 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4566 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4567 (uint32_t)(bus_addr >> 32));
4568 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4569 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4570 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4571 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4574 /* Configure the SRRCTL register */
4575 #ifdef RTE_HEADER_SPLIT_ENABLE
4577 * Configure Header Split
4579 if (dev->data->dev_conf.rxmode.header_split) {
4580 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4581 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4582 IXGBE_SRRCTL_BSIZEHDR_MASK);
4583 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4586 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4588 /* Set if packets are dropped when no descriptors available */
4590 srrctl |= IXGBE_SRRCTL_DROP_EN;
4593 * Configure the RX buffer size in the BSIZEPACKET field of
4594 * the SRRCTL register of the queue.
4595 * The value is in 1 KB resolution. Valid values can be from
4598 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4599 RTE_PKTMBUF_HEADROOM);
4600 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4601 IXGBE_SRRCTL_BSIZEPKT_MASK);
4604 * VF modification to write virtual function SRRCTL register
4606 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4608 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4609 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4611 if (dev->data->dev_conf.rxmode.enable_scatter ||
4612 /* It adds dual VLAN length for supporting dual VLAN */
4613 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4614 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4615 if (!dev->data->scattered_rx)
4616 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4617 dev->data->scattered_rx = 1;
4618 #ifdef RTE_IXGBE_INC_VECTOR
4619 if (rte_is_power_of_2(rxq->nb_rx_desc))
4621 ixgbe_recv_scattered_pkts_vec;
4625 ixgbe_recv_pkts_lro_single_alloc;
4629 #ifdef RTE_HEADER_SPLIT_ENABLE
4630 if (dev->data->dev_conf.rxmode.header_split)
4631 /* Must setup the PSRTYPE register */
4632 psrtype = IXGBE_PSRTYPE_TCPHDR |
4633 IXGBE_PSRTYPE_UDPHDR |
4634 IXGBE_PSRTYPE_IPV4HDR |
4635 IXGBE_PSRTYPE_IPV6HDR;
4638 /* Set RQPL for VF RSS according to max Rx queue */
4639 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4640 IXGBE_PSRTYPE_RQPL_SHIFT;
4641 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4647 * [VF] Initializes Transmit Unit.
4650 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4652 struct ixgbe_hw *hw;
4653 struct ixgbe_tx_queue *txq;
4658 PMD_INIT_FUNC_TRACE();
4659 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661 /* Setup the Base and Length of the Tx Descriptor Rings */
4662 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4663 txq = dev->data->tx_queues[i];
4664 bus_addr = txq->tx_ring_phys_addr;
4665 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4666 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4667 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4668 (uint32_t)(bus_addr >> 32));
4669 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4670 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4671 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4672 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4673 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4676 * Disable Tx Head Writeback RO bit, since this hoses
4677 * bookkeeping if things aren't delivered in order.
4679 txctrl = IXGBE_READ_REG(hw,
4680 IXGBE_VFDCA_TXCTRL(i));
4681 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4682 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4688 * [VF] Start Transmit and Receive Units.
4691 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4693 struct ixgbe_hw *hw;
4694 struct ixgbe_tx_queue *txq;
4695 struct ixgbe_rx_queue *rxq;
4701 PMD_INIT_FUNC_TRACE();
4702 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4705 txq = dev->data->tx_queues[i];
4706 /* Setup Transmit Threshold Registers */
4707 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4708 txdctl |= txq->pthresh & 0x7F;
4709 txdctl |= ((txq->hthresh & 0x7F) << 8);
4710 txdctl |= ((txq->wthresh & 0x7F) << 16);
4711 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4714 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4716 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4717 txdctl |= IXGBE_TXDCTL_ENABLE;
4718 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4721 /* Wait until TX Enable ready */
4724 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4725 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4727 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4729 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4731 rxq = dev->data->rx_queues[i];
4733 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4734 rxdctl |= IXGBE_RXDCTL_ENABLE;
4735 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4737 /* Wait until RX Enable ready */
4741 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4742 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4744 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4746 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4751 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4752 int __attribute__((weak))
4753 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4758 uint16_t __attribute__((weak))
4759 ixgbe_recv_pkts_vec(
4760 void __rte_unused *rx_queue,
4761 struct rte_mbuf __rte_unused **rx_pkts,
4762 uint16_t __rte_unused nb_pkts)
4767 uint16_t __attribute__((weak))
4768 ixgbe_recv_scattered_pkts_vec(
4769 void __rte_unused *rx_queue,
4770 struct rte_mbuf __rte_unused **rx_pkts,
4771 uint16_t __rte_unused nb_pkts)
4776 int __attribute__((weak))
4777 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)