4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum in IPv4 */
379 if (ol_flags & PKT_TX_IP_CKSUM)
380 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
381 IXGBE_ADVTXD_TUCMD_L4T_TCP |
382 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
384 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
385 IXGBE_ADVTXD_TUCMD_L4T_TCP |
386 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
388 tx_offload_mask.l2_len |= ~0;
389 tx_offload_mask.l3_len |= ~0;
390 tx_offload_mask.l4_len |= ~0;
391 tx_offload_mask.tso_segsz |= ~0;
392 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
393 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
394 } else { /* no TSO, check if hardware checksum is needed */
395 if (ol_flags & PKT_TX_IP_CKSUM) {
396 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
397 tx_offload_mask.l2_len |= ~0;
398 tx_offload_mask.l3_len |= ~0;
401 switch (ol_flags & PKT_TX_L4_MASK) {
402 case PKT_TX_UDP_CKSUM:
403 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
404 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
405 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
406 tx_offload_mask.l2_len |= ~0;
407 tx_offload_mask.l3_len |= ~0;
409 case PKT_TX_TCP_CKSUM:
410 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
411 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
412 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
413 tx_offload_mask.l2_len |= ~0;
414 tx_offload_mask.l3_len |= ~0;
415 tx_offload_mask.l4_len |= ~0;
417 case PKT_TX_SCTP_CKSUM:
418 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
419 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
420 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
421 tx_offload_mask.l2_len |= ~0;
422 tx_offload_mask.l3_len |= ~0;
425 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
426 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
431 txq->ctx_cache[ctx_idx].flags = ol_flags;
432 txq->ctx_cache[ctx_idx].tx_offload.data =
433 tx_offload_mask.data & tx_offload.data;
434 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
436 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
437 vlan_macip_lens = tx_offload.l3_len;
438 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
439 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
440 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
441 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
442 ctx_txd->seqnum_seed = 0;
446 * Check which hardware context can be used. Use the existing match
447 * or create a new context descriptor.
449 static inline uint32_t
450 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
451 union ixgbe_tx_offload tx_offload)
453 /* If match with the current used context */
454 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
455 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
456 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
457 return txq->ctx_curr;
460 /* What if match with the next context */
462 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
463 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
464 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
465 return txq->ctx_curr;
468 /* Mismatch, use the previous context */
469 return (IXGBE_CTX_NUM);
472 static inline uint32_t
473 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
476 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
477 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
478 if (ol_flags & PKT_TX_IP_CKSUM)
479 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
480 if (ol_flags & PKT_TX_TCP_SEG)
481 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
485 static inline uint32_t
486 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
488 uint32_t cmdtype = 0;
489 if (ol_flags & PKT_TX_VLAN_PKT)
490 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
491 if (ol_flags & PKT_TX_TCP_SEG)
492 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
496 /* Default RS bit threshold values */
497 #ifndef DEFAULT_TX_RS_THRESH
498 #define DEFAULT_TX_RS_THRESH 32
500 #ifndef DEFAULT_TX_FREE_THRESH
501 #define DEFAULT_TX_FREE_THRESH 32
504 /* Reset transmit descriptors after they have been used */
506 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
508 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
509 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
510 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
511 uint16_t nb_tx_desc = txq->nb_tx_desc;
512 uint16_t desc_to_clean_to;
513 uint16_t nb_tx_to_clean;
515 /* Determine the last descriptor needing to be cleaned */
516 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
517 if (desc_to_clean_to >= nb_tx_desc)
518 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
520 /* Check to make sure the last descriptor to clean is done */
521 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
522 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
524 PMD_TX_FREE_LOG(DEBUG,
525 "TX descriptor %4u is not done"
526 "(port=%d queue=%d)",
528 txq->port_id, txq->queue_id);
529 /* Failed to clean any descriptors, better luck next time */
533 /* Figure out how many descriptors will be cleaned */
534 if (last_desc_cleaned > desc_to_clean_to)
535 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
538 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
541 PMD_TX_FREE_LOG(DEBUG,
542 "Cleaning %4u TX descriptors: %4u to %4u "
543 "(port=%d queue=%d)",
544 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
545 txq->port_id, txq->queue_id);
548 * The last descriptor to clean is done, so that means all the
549 * descriptors from the last descriptor that was cleaned
550 * up to the last descriptor with the RS bit set
551 * are done. Only reset the threshold descriptor.
553 txr[desc_to_clean_to].wb.status = 0;
555 /* Update the txq to reflect the last descriptor that was cleaned */
556 txq->last_desc_cleaned = desc_to_clean_to;
557 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
564 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
567 struct ixgbe_tx_queue *txq;
568 struct ixgbe_tx_entry *sw_ring;
569 struct ixgbe_tx_entry *txe, *txn;
570 volatile union ixgbe_adv_tx_desc *txr;
571 volatile union ixgbe_adv_tx_desc *txd;
572 struct rte_mbuf *tx_pkt;
573 struct rte_mbuf *m_seg;
574 uint64_t buf_dma_addr;
575 uint32_t olinfo_status;
576 uint32_t cmd_type_len;
587 union ixgbe_tx_offload tx_offload = {0};
590 sw_ring = txq->sw_ring;
592 tx_id = txq->tx_tail;
593 txe = &sw_ring[tx_id];
595 /* Determine if the descriptor ring needs to be cleaned. */
596 if (txq->nb_tx_free < txq->tx_free_thresh)
597 ixgbe_xmit_cleanup(txq);
599 rte_prefetch0(&txe->mbuf->pool);
602 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
605 pkt_len = tx_pkt->pkt_len;
608 * Determine how many (if any) context descriptors
609 * are needed for offload functionality.
611 ol_flags = tx_pkt->ol_flags;
613 /* If hardware offload required */
614 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
616 tx_offload.l2_len = tx_pkt->l2_len;
617 tx_offload.l3_len = tx_pkt->l3_len;
618 tx_offload.l4_len = tx_pkt->l4_len;
619 tx_offload.vlan_tci = tx_pkt->vlan_tci;
620 tx_offload.tso_segsz = tx_pkt->tso_segsz;
622 /* If new context need be built or reuse the exist ctx. */
623 ctx = what_advctx_update(txq, tx_ol_req,
625 /* Only allocate context descriptor if required*/
626 new_ctx = (ctx == IXGBE_CTX_NUM);
631 * Keep track of how many descriptors are used this loop
632 * This will always be the number of segments + the number of
633 * Context descriptors required to transmit the packet
635 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
638 * The number of descriptors that must be allocated for a
639 * packet is the number of segments of that packet, plus 1
640 * Context Descriptor for the hardware offload, if any.
641 * Determine the last TX descriptor to allocate in the TX ring
642 * for the packet, starting from the current position (tx_id)
645 tx_last = (uint16_t) (tx_id + nb_used - 1);
648 if (tx_last >= txq->nb_tx_desc)
649 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
651 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
652 " tx_first=%u tx_last=%u",
653 (unsigned) txq->port_id,
654 (unsigned) txq->queue_id,
660 * Make sure there are enough TX descriptors available to
661 * transmit the entire packet.
662 * nb_used better be less than or equal to txq->tx_rs_thresh
664 if (nb_used > txq->nb_tx_free) {
665 PMD_TX_FREE_LOG(DEBUG,
666 "Not enough free TX descriptors "
667 "nb_used=%4u nb_free=%4u "
668 "(port=%d queue=%d)",
669 nb_used, txq->nb_tx_free,
670 txq->port_id, txq->queue_id);
672 if (ixgbe_xmit_cleanup(txq) != 0) {
673 /* Could not clean any descriptors */
679 /* nb_used better be <= txq->tx_rs_thresh */
680 if (unlikely(nb_used > txq->tx_rs_thresh)) {
681 PMD_TX_FREE_LOG(DEBUG,
682 "The number of descriptors needed to "
683 "transmit the packet exceeds the "
684 "RS bit threshold. This will impact "
686 "nb_used=%4u nb_free=%4u "
688 "(port=%d queue=%d)",
689 nb_used, txq->nb_tx_free,
691 txq->port_id, txq->queue_id);
693 * Loop here until there are enough TX
694 * descriptors or until the ring cannot be
697 while (nb_used > txq->nb_tx_free) {
698 if (ixgbe_xmit_cleanup(txq) != 0) {
700 * Could not clean any
712 * By now there are enough free TX descriptors to transmit
717 * Set common flags of all TX Data Descriptors.
719 * The following bits must be set in all Data Descriptors:
720 * - IXGBE_ADVTXD_DTYP_DATA
721 * - IXGBE_ADVTXD_DCMD_DEXT
723 * The following bits must be set in the first Data Descriptor
724 * and are ignored in the other ones:
725 * - IXGBE_ADVTXD_DCMD_IFCS
726 * - IXGBE_ADVTXD_MAC_1588
727 * - IXGBE_ADVTXD_DCMD_VLE
729 * The following bits must only be set in the last Data
731 * - IXGBE_TXD_CMD_EOP
733 * The following bits can be set in any Data Descriptor, but
734 * are only set in the last Data Descriptor:
737 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
738 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
740 #ifdef RTE_LIBRTE_IEEE1588
741 if (ol_flags & PKT_TX_IEEE1588_TMST)
742 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
748 if (ol_flags & PKT_TX_TCP_SEG) {
749 /* when TSO is on, paylen in descriptor is the
750 * not the packet len but the tcp payload len */
751 pkt_len -= (tx_offload.l2_len +
752 tx_offload.l3_len + tx_offload.l4_len);
756 * Setup the TX Advanced Context Descriptor if required
759 volatile struct ixgbe_adv_tx_context_desc *
762 ctx_txd = (volatile struct
763 ixgbe_adv_tx_context_desc *)
766 txn = &sw_ring[txe->next_id];
767 rte_prefetch0(&txn->mbuf->pool);
769 if (txe->mbuf != NULL) {
770 rte_pktmbuf_free_seg(txe->mbuf);
774 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
777 txe->last_id = tx_last;
778 tx_id = txe->next_id;
783 * Setup the TX Advanced Data Descriptor,
784 * This path will go through
785 * whatever new/reuse the context descriptor
787 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
788 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
789 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
792 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
797 txn = &sw_ring[txe->next_id];
798 rte_prefetch0(&txn->mbuf->pool);
800 if (txe->mbuf != NULL)
801 rte_pktmbuf_free_seg(txe->mbuf);
805 * Set up Transmit Data Descriptor.
807 slen = m_seg->data_len;
808 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
809 txd->read.buffer_addr =
810 rte_cpu_to_le_64(buf_dma_addr);
811 txd->read.cmd_type_len =
812 rte_cpu_to_le_32(cmd_type_len | slen);
813 txd->read.olinfo_status =
814 rte_cpu_to_le_32(olinfo_status);
815 txe->last_id = tx_last;
816 tx_id = txe->next_id;
819 } while (m_seg != NULL);
822 * The last packet data descriptor needs End Of Packet (EOP)
824 cmd_type_len |= IXGBE_TXD_CMD_EOP;
825 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
826 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
828 /* Set RS bit only on threshold packets' last descriptor */
829 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
830 PMD_TX_FREE_LOG(DEBUG,
831 "Setting RS bit on TXD id="
832 "%4u (port=%d queue=%d)",
833 tx_last, txq->port_id, txq->queue_id);
835 cmd_type_len |= IXGBE_TXD_CMD_RS;
837 /* Update txq RS bit counters */
840 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
846 * Set the Transmit Descriptor Tail (TDT)
848 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
849 (unsigned) txq->port_id, (unsigned) txq->queue_id,
850 (unsigned) tx_id, (unsigned) nb_tx);
851 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
852 txq->tx_tail = tx_id;
857 /*********************************************************************
861 **********************************************************************/
863 #define IXGBE_PACKET_TYPE_IPV4 0X01
864 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
865 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
866 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
867 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
868 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
869 #define IXGBE_PACKET_TYPE_IPV6 0X04
870 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
871 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
872 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
873 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
874 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
875 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
876 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
877 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
878 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
879 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
880 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
881 #define IXGBE_PACKET_TYPE_MAX 0X80
882 #define IXGBE_PACKET_TYPE_MASK 0X7F
883 #define IXGBE_PACKET_TYPE_SHIFT 0X04
884 static inline uint32_t
885 ixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
887 static const uint32_t
888 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
889 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
891 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
892 RTE_PTYPE_L3_IPV4_EXT,
893 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
895 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
896 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
897 RTE_PTYPE_INNER_L3_IPV6,
898 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
899 RTE_PTYPE_L3_IPV6_EXT,
900 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
901 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
902 RTE_PTYPE_INNER_L3_IPV6_EXT,
903 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
904 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
905 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
906 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
907 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
908 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
909 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
910 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
911 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
912 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
913 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
914 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
915 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
916 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
917 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
918 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
919 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
920 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
921 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
922 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
923 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
924 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
925 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
926 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
927 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
928 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
929 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
930 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
932 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
933 return RTE_PTYPE_UNKNOWN;
935 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &
936 IXGBE_PACKET_TYPE_MASK;
938 return ptype_table[pkt_info];
941 static inline uint64_t
942 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
944 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
945 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
946 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
947 PKT_RX_RSS_HASH, 0, 0, 0,
948 0, 0, 0, PKT_RX_FDIR,
950 #ifdef RTE_LIBRTE_IEEE1588
951 static uint64_t ip_pkt_etqf_map[8] = {
952 0, 0, 0, PKT_RX_IEEE1588_PTP,
956 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
957 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
958 ip_rss_types_map[pkt_info & 0XF];
960 return ip_rss_types_map[pkt_info & 0XF];
962 return ip_rss_types_map[pkt_info & 0XF];
965 #else /* RTE_NEXT_ABI */
966 static inline uint64_t
967 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
971 static const uint64_t ip_pkt_types_map[16] = {
972 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
973 PKT_RX_IPV6_HDR, 0, 0, 0,
974 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
975 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
978 static const uint64_t ip_rss_types_map[16] = {
979 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
980 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
981 PKT_RX_RSS_HASH, 0, 0, 0,
982 0, 0, 0, PKT_RX_FDIR,
985 #ifdef RTE_LIBRTE_IEEE1588
986 static uint64_t ip_pkt_etqf_map[8] = {
987 0, 0, 0, PKT_RX_IEEE1588_PTP,
991 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
992 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
993 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
995 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
996 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
999 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
1001 #endif /* RTE_NEXT_ABI */
1003 static inline uint64_t
1004 rx_desc_status_to_pkt_flags(uint32_t rx_status)
1009 * Check if VLAN present only.
1010 * Do not check whether L3/L4 rx checksum done by NIC or not,
1011 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1013 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
1015 #ifdef RTE_LIBRTE_IEEE1588
1016 if (rx_status & IXGBE_RXD_STAT_TMST)
1017 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1022 static inline uint64_t
1023 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1026 * Bit 31: IPE, IPv4 checksum error
1027 * Bit 30: L4I, L4I integrity error
1029 static uint64_t error_to_pkt_flags_map[4] = {
1030 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1031 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1033 return error_to_pkt_flags_map[(rx_status >>
1034 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1037 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1039 * LOOK_AHEAD defines how many desc statuses to check beyond the
1040 * current descriptor.
1041 * It must be a pound define for optimal performance.
1042 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1043 * function only works with LOOK_AHEAD=8.
1045 #define LOOK_AHEAD 8
1046 #if (LOOK_AHEAD != 8)
1047 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1050 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1052 volatile union ixgbe_adv_rx_desc *rxdp;
1053 struct ixgbe_rx_entry *rxep;
1054 struct rte_mbuf *mb;
1059 uint32_t s[LOOK_AHEAD];
1060 uint16_t pkt_info[LOOK_AHEAD];
1062 int s[LOOK_AHEAD], nb_dd;
1063 #endif /* RTE_NEXT_ABI */
1064 int i, j, nb_rx = 0;
1067 /* get references to current descriptor and S/W ring entry */
1068 rxdp = &rxq->rx_ring[rxq->rx_tail];
1069 rxep = &rxq->sw_ring[rxq->rx_tail];
1071 /* check to make sure there is at least 1 packet to receive */
1072 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1076 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1077 * reference packets that are ready to be received.
1079 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1080 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1082 /* Read desc statuses backwards to avoid race condition */
1083 for (j = LOOK_AHEAD-1; j >= 0; --j)
1084 s[j] = rxdp[j].wb.upper.status_error;
1087 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1088 pkt_info[j] = rxdp[j].wb.lower.lo_dword.
1090 #endif /* RTE_NEXT_ABI */
1092 /* Compute how many status bits were set */
1094 for (j = 0; j < LOOK_AHEAD; ++j)
1095 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1099 /* Translate descriptor info to mbuf format */
1100 for (j = 0; j < nb_dd; ++j) {
1102 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
1103 mb->data_len = pkt_len;
1104 mb->pkt_len = pkt_len;
1105 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1107 /* convert descriptor fields to rte mbuf flags */
1109 pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1110 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1112 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1113 mb->ol_flags = pkt_flags;
1115 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
1116 #else /* RTE_NEXT_ABI */
1117 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1118 rxdp[j].wb.lower.lo_dword.data);
1119 /* reuse status field from scan list */
1120 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
1121 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1122 mb->ol_flags = pkt_flags;
1123 #endif /* RTE_NEXT_ABI */
1125 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1126 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1127 else if (pkt_flags & PKT_RX_FDIR) {
1128 mb->hash.fdir.hash =
1129 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1130 & IXGBE_ATR_HASH_MASK);
1131 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1135 /* Move mbuf pointers from the S/W ring to the stage */
1136 for (j = 0; j < LOOK_AHEAD; ++j) {
1137 rxq->rx_stage[i + j] = rxep[j].mbuf;
1140 /* stop if all requested packets could not be received */
1141 if (nb_dd != LOOK_AHEAD)
1145 /* clear software ring entries so we can cleanup correctly */
1146 for (i = 0; i < nb_rx; ++i) {
1147 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1155 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1157 volatile union ixgbe_adv_rx_desc *rxdp;
1158 struct ixgbe_rx_entry *rxep;
1159 struct rte_mbuf *mb;
1164 /* allocate buffers in bulk directly into the S/W ring */
1165 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1166 rxep = &rxq->sw_ring[alloc_idx];
1167 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1168 rxq->rx_free_thresh);
1169 if (unlikely(diag != 0))
1172 rxdp = &rxq->rx_ring[alloc_idx];
1173 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1174 /* populate the static rte mbuf fields */
1179 mb->port = rxq->port_id;
1182 rte_mbuf_refcnt_set(mb, 1);
1183 mb->data_off = RTE_PKTMBUF_HEADROOM;
1185 /* populate the descriptors */
1186 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1187 rxdp[i].read.hdr_addr = dma_addr;
1188 rxdp[i].read.pkt_addr = dma_addr;
1191 /* update state of internal queue structure */
1192 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1193 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1194 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1200 static inline uint16_t
1201 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1204 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1207 /* how many packets are ready to return? */
1208 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1210 /* copy mbuf pointers to the application's packet list */
1211 for (i = 0; i < nb_pkts; ++i)
1212 rx_pkts[i] = stage[i];
1214 /* update internal queue state */
1215 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1216 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1221 static inline uint16_t
1222 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1225 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1228 /* Any previously recv'd pkts will be returned from the Rx stage */
1229 if (rxq->rx_nb_avail)
1230 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1232 /* Scan the H/W ring for packets to receive */
1233 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1235 /* update internal queue state */
1236 rxq->rx_next_avail = 0;
1237 rxq->rx_nb_avail = nb_rx;
1238 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1240 /* if required, allocate new buffers to replenish descriptors */
1241 if (rxq->rx_tail > rxq->rx_free_trigger) {
1242 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1244 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1246 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1247 "queue_id=%u", (unsigned) rxq->port_id,
1248 (unsigned) rxq->queue_id);
1250 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1251 rxq->rx_free_thresh;
1254 * Need to rewind any previous receives if we cannot
1255 * allocate new buffers to replenish the old ones.
1257 rxq->rx_nb_avail = 0;
1258 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1259 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1260 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1265 /* update tail pointer */
1267 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1270 if (rxq->rx_tail >= rxq->nb_rx_desc)
1273 /* received any packets this loop? */
1274 if (rxq->rx_nb_avail)
1275 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1280 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1282 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1287 if (unlikely(nb_pkts == 0))
1290 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1291 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1293 /* request is relatively large, chunk it up */
1297 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1298 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1299 nb_rx = (uint16_t)(nb_rx + ret);
1300 nb_pkts = (uint16_t)(nb_pkts - ret);
1310 /* Stub to avoid extra ifdefs */
1312 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1313 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1319 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1320 __rte_unused bool reset_mbuf)
1324 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1327 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1330 struct ixgbe_rx_queue *rxq;
1331 volatile union ixgbe_adv_rx_desc *rx_ring;
1332 volatile union ixgbe_adv_rx_desc *rxdp;
1333 struct ixgbe_rx_entry *sw_ring;
1334 struct ixgbe_rx_entry *rxe;
1335 struct rte_mbuf *rxm;
1336 struct rte_mbuf *nmb;
1337 union ixgbe_adv_rx_desc rxd;
1343 uint32_t hlen_type_rss;
1354 rx_id = rxq->rx_tail;
1355 rx_ring = rxq->rx_ring;
1356 sw_ring = rxq->sw_ring;
1357 while (nb_rx < nb_pkts) {
1359 * The order of operations here is important as the DD status
1360 * bit must not be read after any other descriptor fields.
1361 * rx_ring and rxdp are pointing to volatile data so the order
1362 * of accesses cannot be reordered by the compiler. If they were
1363 * not volatile, they could be reordered which could lead to
1364 * using invalid descriptor fields when read from rxd.
1366 rxdp = &rx_ring[rx_id];
1367 staterr = rxdp->wb.upper.status_error;
1368 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1375 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1376 * is likely to be invalid and to be dropped by the various
1377 * validation checks performed by the network stack.
1379 * Allocate a new mbuf to replenish the RX ring descriptor.
1380 * If the allocation fails:
1381 * - arrange for that RX descriptor to be the first one
1382 * being parsed the next time the receive function is
1383 * invoked [on the same queue].
1385 * - Stop parsing the RX ring and return immediately.
1387 * This policy do not drop the packet received in the RX
1388 * descriptor for which the allocation of a new mbuf failed.
1389 * Thus, it allows that packet to be later retrieved if
1390 * mbuf have been freed in the mean time.
1391 * As a side effect, holding RX descriptors instead of
1392 * systematically giving them back to the NIC may lead to
1393 * RX ring exhaustion situations.
1394 * However, the NIC can gracefully prevent such situations
1395 * to happen by sending specific "back-pressure" flow control
1396 * frames to its peer(s).
1398 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1399 "ext_err_stat=0x%08x pkt_len=%u",
1400 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1401 (unsigned) rx_id, (unsigned) staterr,
1402 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1404 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1406 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1407 "queue_id=%u", (unsigned) rxq->port_id,
1408 (unsigned) rxq->queue_id);
1409 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1414 rxe = &sw_ring[rx_id];
1416 if (rx_id == rxq->nb_rx_desc)
1419 /* Prefetch next mbuf while processing current one. */
1420 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1423 * When next RX descriptor is on a cache-line boundary,
1424 * prefetch the next 4 RX descriptors and the next 8 pointers
1427 if ((rx_id & 0x3) == 0) {
1428 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1429 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1435 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1436 rxdp->read.hdr_addr = dma_addr;
1437 rxdp->read.pkt_addr = dma_addr;
1440 * Initialize the returned mbuf.
1441 * 1) setup generic mbuf fields:
1442 * - number of segments,
1445 * - RX port identifier.
1446 * 2) integrate hardware offload data, if any:
1447 * - RSS flag & hash,
1448 * - IP checksum flag,
1449 * - VLAN TCI, if any,
1452 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1454 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1455 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1458 rxm->pkt_len = pkt_len;
1459 rxm->data_len = pkt_len;
1460 rxm->port = rxq->port_id;
1463 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.
1465 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1466 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1468 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1469 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1470 pkt_flags = pkt_flags |
1471 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1472 rxm->ol_flags = pkt_flags;
1473 rxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1474 #else /* RTE_NEXT_ABI */
1475 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1476 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1477 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1479 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1480 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1481 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1482 rxm->ol_flags = pkt_flags;
1483 #endif /* RTE_NEXT_ABI */
1485 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1486 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1487 else if (pkt_flags & PKT_RX_FDIR) {
1488 rxm->hash.fdir.hash =
1489 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1490 & IXGBE_ATR_HASH_MASK);
1491 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1494 * Store the mbuf address into the next entry of the array
1495 * of returned packets.
1497 rx_pkts[nb_rx++] = rxm;
1499 rxq->rx_tail = rx_id;
1502 * If the number of free RX descriptors is greater than the RX free
1503 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1505 * Update the RDT with the value of the last processed RX descriptor
1506 * minus 1, to guarantee that the RDT register is never equal to the
1507 * RDH register, which creates a "full" ring situtation from the
1508 * hardware point of view...
1510 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1511 if (nb_hold > rxq->rx_free_thresh) {
1512 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1513 "nb_hold=%u nb_rx=%u",
1514 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1515 (unsigned) rx_id, (unsigned) nb_hold,
1517 rx_id = (uint16_t) ((rx_id == 0) ?
1518 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1519 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1522 rxq->nb_rx_hold = nb_hold;
1527 * Detect an RSC descriptor.
1529 static inline uint32_t
1530 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1532 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1533 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1537 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1539 * Fill the following info in the HEAD buffer of the Rx cluster:
1540 * - RX port identifier
1541 * - hardware offload data, if any:
1543 * - IP checksum flag
1544 * - VLAN TCI, if any
1546 * @head HEAD of the packet cluster
1547 * @desc HW descriptor to get data from
1548 * @port_id Port ID of the Rx queue
1551 ixgbe_fill_cluster_head_buf(
1552 struct rte_mbuf *head,
1553 union ixgbe_adv_rx_desc *desc,
1561 head->port = port_id;
1563 /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1564 * set in the pkt_flags field.
1566 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1567 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);
1568 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1569 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1570 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1571 head->ol_flags = pkt_flags;
1572 head->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1573 #else /* RTE_NEXT_ABI */
1574 uint32_t hlen_type_rss;
1577 head->port = port_id;
1580 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1581 * set in the pkt_flags field.
1583 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1584 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1585 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1586 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1587 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1588 head->ol_flags = pkt_flags;
1589 #endif /* RTE_NEXT_ABI */
1591 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1592 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1593 else if (pkt_flags & PKT_RX_FDIR) {
1594 head->hash.fdir.hash =
1595 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1596 & IXGBE_ATR_HASH_MASK;
1597 head->hash.fdir.id =
1598 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1603 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1605 * @rx_queue Rx queue handle
1606 * @rx_pkts table of received packets
1607 * @nb_pkts size of rx_pkts table
1608 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1610 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1611 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1613 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1614 * 1) When non-EOP RSC completion arrives:
1615 * a) Update the HEAD of the current RSC aggregation cluster with the new
1616 * segment's data length.
1617 * b) Set the "next" pointer of the current segment to point to the segment
1618 * at the NEXTP index.
1619 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1620 * in the sw_rsc_ring.
1621 * 2) When EOP arrives we just update the cluster's total length and offload
1622 * flags and deliver the cluster up to the upper layers. In our case - put it
1623 * in the rx_pkts table.
1625 * Returns the number of received packets/clusters (according to the "bulk
1626 * receive" interface).
1628 static inline uint16_t
1629 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1632 struct ixgbe_rx_queue *rxq = rx_queue;
1633 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1634 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1635 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1636 uint16_t rx_id = rxq->rx_tail;
1638 uint16_t nb_hold = rxq->nb_rx_hold;
1639 uint16_t prev_id = rxq->rx_tail;
1641 while (nb_rx < nb_pkts) {
1643 struct ixgbe_rx_entry *rxe;
1644 struct ixgbe_scattered_rx_entry *sc_entry;
1645 struct ixgbe_scattered_rx_entry *next_sc_entry;
1646 struct ixgbe_rx_entry *next_rxe;
1647 struct rte_mbuf *first_seg;
1648 struct rte_mbuf *rxm;
1649 struct rte_mbuf *nmb;
1650 union ixgbe_adv_rx_desc rxd;
1653 volatile union ixgbe_adv_rx_desc *rxdp;
1658 * The code in this whole file uses the volatile pointer to
1659 * ensure the read ordering of the status and the rest of the
1660 * descriptor fields (on the compiler level only!!!). This is so
1661 * UGLY - why not to just use the compiler barrier instead? DPDK
1662 * even has the rte_compiler_barrier() for that.
1664 * But most importantly this is just wrong because this doesn't
1665 * ensure memory ordering in a general case at all. For
1666 * instance, DPDK is supposed to work on Power CPUs where
1667 * compiler barrier may just not be enough!
1669 * I tried to write only this function properly to have a
1670 * starting point (as a part of an LRO/RSC series) but the
1671 * compiler cursed at me when I tried to cast away the
1672 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1673 * keeping it the way it is for now.
1675 * The code in this file is broken in so many other places and
1676 * will just not work on a big endian CPU anyway therefore the
1677 * lines below will have to be revisited together with the rest
1681 * - Get rid of "volatile" crap and let the compiler do its
1683 * - Use the proper memory barrier (rte_rmb()) to ensure the
1684 * memory ordering below.
1686 rxdp = &rx_ring[rx_id];
1687 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1689 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1694 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1695 "staterr=0x%x data_len=%u",
1696 rxq->port_id, rxq->queue_id, rx_id, staterr,
1697 rte_le_to_cpu_16(rxd.wb.upper.length));
1700 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1702 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1703 "port_id=%u queue_id=%u",
1704 rxq->port_id, rxq->queue_id);
1706 rte_eth_devices[rxq->port_id].data->
1707 rx_mbuf_alloc_failed++;
1710 } else if (nb_hold > rxq->rx_free_thresh) {
1711 uint16_t next_rdt = rxq->rx_free_trigger;
1713 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1715 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1717 nb_hold -= rxq->rx_free_thresh;
1719 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1720 "port_id=%u queue_id=%u",
1721 rxq->port_id, rxq->queue_id);
1723 rte_eth_devices[rxq->port_id].data->
1724 rx_mbuf_alloc_failed++;
1730 rxe = &sw_ring[rx_id];
1731 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1733 next_id = rx_id + 1;
1734 if (next_id == rxq->nb_rx_desc)
1737 /* Prefetch next mbuf while processing current one. */
1738 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1741 * When next RX descriptor is on a cache-line boundary,
1742 * prefetch the next 4 RX descriptors and the next 4 pointers
1745 if ((next_id & 0x3) == 0) {
1746 rte_ixgbe_prefetch(&rx_ring[next_id]);
1747 rte_ixgbe_prefetch(&sw_ring[next_id]);
1754 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1756 * Update RX descriptor with the physical address of the
1757 * new data buffer of the new allocated mbuf.
1761 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1762 rxdp->read.hdr_addr = dma;
1763 rxdp->read.pkt_addr = dma;
1768 * Set data length & data buffer address of mbuf.
1770 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1771 rxm->data_len = data_len;
1776 * Get next descriptor index:
1777 * - For RSC it's in the NEXTP field.
1778 * - For a scattered packet - it's just a following
1781 if (ixgbe_rsc_count(&rxd))
1783 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1784 IXGBE_RXDADV_NEXTP_SHIFT;
1788 next_sc_entry = &sw_sc_ring[nextp_id];
1789 next_rxe = &sw_ring[nextp_id];
1790 rte_ixgbe_prefetch(next_rxe);
1793 sc_entry = &sw_sc_ring[rx_id];
1794 first_seg = sc_entry->fbuf;
1795 sc_entry->fbuf = NULL;
1798 * If this is the first buffer of the received packet,
1799 * set the pointer to the first mbuf of the packet and
1800 * initialize its context.
1801 * Otherwise, update the total length and the number of segments
1802 * of the current scattered packet, and update the pointer to
1803 * the last mbuf of the current packet.
1805 if (first_seg == NULL) {
1807 first_seg->pkt_len = data_len;
1808 first_seg->nb_segs = 1;
1810 first_seg->pkt_len += data_len;
1811 first_seg->nb_segs++;
1818 * If this is not the last buffer of the received packet, update
1819 * the pointer to the first mbuf at the NEXTP entry in the
1820 * sw_sc_ring and continue to parse the RX ring.
1823 rxm->next = next_rxe->mbuf;
1824 next_sc_entry->fbuf = first_seg;
1829 * This is the last buffer of the received packet - return
1830 * the current cluster to the user.
1834 /* Initialize the first mbuf of the returned packet */
1835 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1838 /* Prefetch data of first segment, if configured to do so. */
1839 rte_packet_prefetch((char *)first_seg->buf_addr +
1840 first_seg->data_off);
1843 * Store the mbuf address into the next entry of the array
1844 * of returned packets.
1846 rx_pkts[nb_rx++] = first_seg;
1850 * Record index of the next RX descriptor to probe.
1852 rxq->rx_tail = rx_id;
1855 * If the number of free RX descriptors is greater than the RX free
1856 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1858 * Update the RDT with the value of the last processed RX descriptor
1859 * minus 1, to guarantee that the RDT register is never equal to the
1860 * RDH register, which creates a "full" ring situtation from the
1861 * hardware point of view...
1863 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1864 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1865 "nb_hold=%u nb_rx=%u",
1866 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1869 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1873 rxq->nb_rx_hold = nb_hold;
1878 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1881 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1885 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1888 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1891 /*********************************************************************
1893 * Queue management functions
1895 **********************************************************************/
1898 * Rings setup and release.
1900 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1901 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1902 * also optimize cache line size effect. H/W supports up to cache line size 128.
1904 #define IXGBE_ALIGN 128
1907 * Maximum number of Ring Descriptors.
1909 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1910 * descriptors should meet the following condition:
1911 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1913 #define IXGBE_MIN_RING_DESC 32
1914 #define IXGBE_MAX_RING_DESC 4096
1917 * Create memzone for HW rings. malloc can't be used as the physical address is
1918 * needed. If the memzone is already created, then this function returns a ptr
1921 static const struct rte_memzone * __attribute__((cold))
1922 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1923 uint16_t queue_id, uint32_t ring_size, int socket_id)
1925 char z_name[RTE_MEMZONE_NAMESIZE];
1926 const struct rte_memzone *mz;
1928 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1929 dev->driver->pci_drv.name, ring_name,
1930 dev->data->port_id, queue_id);
1932 mz = rte_memzone_lookup(z_name);
1936 #ifdef RTE_LIBRTE_XEN_DOM0
1937 return rte_memzone_reserve_bounded(z_name, ring_size,
1938 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1940 return rte_memzone_reserve_aligned(z_name, ring_size,
1941 socket_id, 0, IXGBE_ALIGN);
1945 static void __attribute__((cold))
1946 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1950 if (txq->sw_ring != NULL) {
1951 for (i = 0; i < txq->nb_tx_desc; i++) {
1952 if (txq->sw_ring[i].mbuf != NULL) {
1953 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1954 txq->sw_ring[i].mbuf = NULL;
1960 static void __attribute__((cold))
1961 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1964 txq->sw_ring != NULL)
1965 rte_free(txq->sw_ring);
1968 static void __attribute__((cold))
1969 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1971 if (txq != NULL && txq->ops != NULL) {
1972 txq->ops->release_mbufs(txq);
1973 txq->ops->free_swring(txq);
1978 void __attribute__((cold))
1979 ixgbe_dev_tx_queue_release(void *txq)
1981 ixgbe_tx_queue_release(txq);
1984 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1985 static void __attribute__((cold))
1986 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1988 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1989 struct ixgbe_tx_entry *txe = txq->sw_ring;
1992 /* Zero out HW ring memory */
1993 for (i = 0; i < txq->nb_tx_desc; i++) {
1994 txq->tx_ring[i] = zeroed_desc;
1997 /* Initialize SW ring entries */
1998 prev = (uint16_t) (txq->nb_tx_desc - 1);
1999 for (i = 0; i < txq->nb_tx_desc; i++) {
2000 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2001 txd->wb.status = IXGBE_TXD_STAT_DD;
2004 txe[prev].next_id = i;
2008 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2009 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2012 txq->nb_tx_used = 0;
2014 * Always allow 1 descriptor to be un-allocated to avoid
2015 * a H/W race condition
2017 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2018 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2020 memset((void*)&txq->ctx_cache, 0,
2021 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2024 static const struct ixgbe_txq_ops def_txq_ops = {
2025 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2026 .free_swring = ixgbe_tx_free_swring,
2027 .reset = ixgbe_reset_tx_queue,
2030 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2031 * the queue parameters. Used in tx_queue_setup by primary process and then
2032 * in dev_init by secondary process when attaching to an existing ethdev.
2034 void __attribute__((cold))
2035 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2037 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2038 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2039 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2040 PMD_INIT_LOG(INFO, "Using simple tx code path");
2041 #ifdef RTE_IXGBE_INC_VECTOR
2042 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2043 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2044 ixgbe_txq_vec_setup(txq) == 0)) {
2045 PMD_INIT_LOG(INFO, "Vector tx enabled.");
2046 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2049 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2051 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
2053 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2054 (unsigned long)txq->txq_flags,
2055 (unsigned long)IXGBE_SIMPLE_FLAGS);
2057 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2058 (unsigned long)txq->tx_rs_thresh,
2059 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2060 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2064 int __attribute__((cold))
2065 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2068 unsigned int socket_id,
2069 const struct rte_eth_txconf *tx_conf)
2071 const struct rte_memzone *tz;
2072 struct ixgbe_tx_queue *txq;
2073 struct ixgbe_hw *hw;
2074 uint16_t tx_rs_thresh, tx_free_thresh;
2076 PMD_INIT_FUNC_TRACE();
2077 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080 * Validate number of transmit descriptors.
2081 * It must not exceed hardware maximum, and must be multiple
2084 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2085 (nb_desc > IXGBE_MAX_RING_DESC) ||
2086 (nb_desc < IXGBE_MIN_RING_DESC)) {
2091 * The following two parameters control the setting of the RS bit on
2092 * transmit descriptors.
2093 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2094 * descriptors have been used.
2095 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2096 * descriptors are used or if the number of descriptors required
2097 * to transmit a packet is greater than the number of free TX
2099 * The following constraints must be satisfied:
2100 * tx_rs_thresh must be greater than 0.
2101 * tx_rs_thresh must be less than the size of the ring minus 2.
2102 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2103 * tx_rs_thresh must be a divisor of the ring size.
2104 * tx_free_thresh must be greater than 0.
2105 * tx_free_thresh must be less than the size of the ring minus 3.
2106 * One descriptor in the TX ring is used as a sentinel to avoid a
2107 * H/W race condition, hence the maximum threshold constraints.
2108 * When set to zero use default values.
2110 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2111 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2112 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2113 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2114 if (tx_rs_thresh >= (nb_desc - 2)) {
2115 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2116 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2117 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2118 (int)dev->data->port_id, (int)queue_idx);
2121 if (tx_free_thresh >= (nb_desc - 3)) {
2122 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2123 "tx_free_thresh must be less than the number of "
2124 "TX descriptors minus 3. (tx_free_thresh=%u "
2125 "port=%d queue=%d)",
2126 (unsigned int)tx_free_thresh,
2127 (int)dev->data->port_id, (int)queue_idx);
2130 if (tx_rs_thresh > tx_free_thresh) {
2131 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2132 "tx_free_thresh. (tx_free_thresh=%u "
2133 "tx_rs_thresh=%u port=%d queue=%d)",
2134 (unsigned int)tx_free_thresh,
2135 (unsigned int)tx_rs_thresh,
2136 (int)dev->data->port_id,
2140 if ((nb_desc % tx_rs_thresh) != 0) {
2141 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2142 "number of TX descriptors. (tx_rs_thresh=%u "
2143 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2144 (int)dev->data->port_id, (int)queue_idx);
2149 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2150 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2151 * by the NIC and all descriptors are written back after the NIC
2152 * accumulates WTHRESH descriptors.
2154 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2155 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2156 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2157 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2158 (int)dev->data->port_id, (int)queue_idx);
2162 /* Free memory prior to re-allocation if needed... */
2163 if (dev->data->tx_queues[queue_idx] != NULL) {
2164 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2165 dev->data->tx_queues[queue_idx] = NULL;
2168 /* First allocate the tx queue data structure */
2169 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2170 RTE_CACHE_LINE_SIZE, socket_id);
2175 * Allocate TX ring hardware descriptors. A memzone large enough to
2176 * handle the maximum ring size is allocated in order to allow for
2177 * resizing in later calls to the queue setup function.
2179 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2180 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2183 ixgbe_tx_queue_release(txq);
2187 txq->nb_tx_desc = nb_desc;
2188 txq->tx_rs_thresh = tx_rs_thresh;
2189 txq->tx_free_thresh = tx_free_thresh;
2190 txq->pthresh = tx_conf->tx_thresh.pthresh;
2191 txq->hthresh = tx_conf->tx_thresh.hthresh;
2192 txq->wthresh = tx_conf->tx_thresh.wthresh;
2193 txq->queue_id = queue_idx;
2194 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2195 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2196 txq->port_id = dev->data->port_id;
2197 txq->txq_flags = tx_conf->txq_flags;
2198 txq->ops = &def_txq_ops;
2199 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2202 * Modification to set VFTDT for virtual function if vf is detected
2204 if (hw->mac.type == ixgbe_mac_82599_vf ||
2205 hw->mac.type == ixgbe_mac_X540_vf ||
2206 hw->mac.type == ixgbe_mac_X550_vf ||
2207 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2208 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2210 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2211 #ifndef RTE_LIBRTE_XEN_DOM0
2212 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2214 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2216 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2218 /* Allocate software ring */
2219 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2220 sizeof(struct ixgbe_tx_entry) * nb_desc,
2221 RTE_CACHE_LINE_SIZE, socket_id);
2222 if (txq->sw_ring == NULL) {
2223 ixgbe_tx_queue_release(txq);
2226 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2227 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2229 /* set up vector or scalar TX function as appropriate */
2230 ixgbe_set_tx_function(dev, txq);
2232 txq->ops->reset(txq);
2234 dev->data->tx_queues[queue_idx] = txq;
2241 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2243 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2244 * in the sw_rsc_ring is not set to NULL but rather points to the next
2245 * mbuf of this RSC aggregation (that has not been completed yet and still
2246 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2247 * will just free first "nb_segs" segments of the cluster explicitly by calling
2248 * an rte_pktmbuf_free_seg().
2250 * @m scattered cluster head
2252 static void __attribute__((cold))
2253 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2255 uint8_t i, nb_segs = m->nb_segs;
2256 struct rte_mbuf *next_seg;
2258 for (i = 0; i < nb_segs; i++) {
2260 rte_pktmbuf_free_seg(m);
2265 static void __attribute__((cold))
2266 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2270 if (rxq->sw_ring != NULL) {
2271 for (i = 0; i < rxq->nb_rx_desc; i++) {
2272 if (rxq->sw_ring[i].mbuf != NULL &&
2273 rte_mbuf_refcnt_read(rxq->sw_ring[i].mbuf)) {
2274 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2275 rxq->sw_ring[i].mbuf = NULL;
2278 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2279 if (rxq->rx_nb_avail) {
2280 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2281 struct rte_mbuf *mb;
2282 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2283 rte_pktmbuf_free_seg(mb);
2285 rxq->rx_nb_avail = 0;
2290 if (rxq->sw_sc_ring)
2291 for (i = 0; i < rxq->nb_rx_desc; i++)
2292 if (rxq->sw_sc_ring[i].fbuf) {
2293 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2294 rxq->sw_sc_ring[i].fbuf = NULL;
2298 static void __attribute__((cold))
2299 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2302 ixgbe_rx_queue_release_mbufs(rxq);
2303 rte_free(rxq->sw_ring);
2304 rte_free(rxq->sw_sc_ring);
2309 void __attribute__((cold))
2310 ixgbe_dev_rx_queue_release(void *rxq)
2312 ixgbe_rx_queue_release(rxq);
2316 * Check if Rx Burst Bulk Alloc function can be used.
2318 * 0: the preconditions are satisfied and the bulk allocation function
2320 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2321 * function must be used.
2323 static inline int __attribute__((cold))
2324 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2325 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2327 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2333 * Make sure the following pre-conditions are satisfied:
2334 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2335 * rxq->rx_free_thresh < rxq->nb_rx_desc
2336 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2337 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2338 * Scattered packets are not supported. This should be checked
2339 * outside of this function.
2341 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2342 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2343 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2344 "rxq->rx_free_thresh=%d, "
2345 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2346 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2348 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2349 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2350 "rxq->rx_free_thresh=%d, "
2351 "rxq->nb_rx_desc=%d",
2352 rxq->rx_free_thresh, rxq->nb_rx_desc);
2354 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2355 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2356 "rxq->nb_rx_desc=%d, "
2357 "rxq->rx_free_thresh=%d",
2358 rxq->nb_rx_desc, rxq->rx_free_thresh);
2360 } else if (!(rxq->nb_rx_desc <
2361 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2362 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2363 "rxq->nb_rx_desc=%d, "
2364 "IXGBE_MAX_RING_DESC=%d, "
2365 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2366 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2367 RTE_PMD_IXGBE_RX_MAX_BURST);
2377 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2378 static void __attribute__((cold))
2379 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2381 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2383 uint16_t len = rxq->nb_rx_desc;
2386 * By default, the Rx queue setup function allocates enough memory for
2387 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2388 * extra memory at the end of the descriptor ring to be zero'd out. A
2389 * pre-condition for using the Rx burst bulk alloc function is that the
2390 * number of descriptors is less than or equal to
2391 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2392 * constraints here to see if we need to zero out memory after the end
2393 * of the H/W descriptor ring.
2395 if (adapter->rx_bulk_alloc_allowed)
2396 /* zero out extra memory */
2397 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2400 * Zero out HW ring memory. Zero out extra memory at the end of
2401 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2402 * reads extra memory as zeros.
2404 for (i = 0; i < len; i++) {
2405 rxq->rx_ring[i] = zeroed_desc;
2408 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2410 * initialize extra software ring entries. Space for these extra
2411 * entries is always allocated
2413 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2414 for (i = rxq->nb_rx_desc; i < len; ++i) {
2415 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2418 rxq->rx_nb_avail = 0;
2419 rxq->rx_next_avail = 0;
2420 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2421 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2423 rxq->nb_rx_hold = 0;
2424 rxq->pkt_first_seg = NULL;
2425 rxq->pkt_last_seg = NULL;
2428 int __attribute__((cold))
2429 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2432 unsigned int socket_id,
2433 const struct rte_eth_rxconf *rx_conf,
2434 struct rte_mempool *mp)
2436 const struct rte_memzone *rz;
2437 struct ixgbe_rx_queue *rxq;
2438 struct ixgbe_hw *hw;
2440 struct ixgbe_adapter *adapter =
2441 (struct ixgbe_adapter *)dev->data->dev_private;
2443 PMD_INIT_FUNC_TRACE();
2444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2447 * Validate number of receive descriptors.
2448 * It must not exceed hardware maximum, and must be multiple
2451 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2452 (nb_desc > IXGBE_MAX_RING_DESC) ||
2453 (nb_desc < IXGBE_MIN_RING_DESC)) {
2457 /* Free memory prior to re-allocation if needed... */
2458 if (dev->data->rx_queues[queue_idx] != NULL) {
2459 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2460 dev->data->rx_queues[queue_idx] = NULL;
2463 /* First allocate the rx queue data structure */
2464 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2465 RTE_CACHE_LINE_SIZE, socket_id);
2469 rxq->nb_rx_desc = nb_desc;
2470 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2471 rxq->queue_id = queue_idx;
2472 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2473 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2474 rxq->port_id = dev->data->port_id;
2475 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2477 rxq->drop_en = rx_conf->rx_drop_en;
2478 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2481 * Allocate RX ring hardware descriptors. A memzone large enough to
2482 * handle the maximum ring size is allocated in order to allow for
2483 * resizing in later calls to the queue setup function.
2485 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2486 RX_RING_SZ, socket_id);
2488 ixgbe_rx_queue_release(rxq);
2493 * Zero init all the descriptors in the ring.
2495 memset (rz->addr, 0, RX_RING_SZ);
2498 * Modified to setup VFRDT for Virtual Function
2500 if (hw->mac.type == ixgbe_mac_82599_vf ||
2501 hw->mac.type == ixgbe_mac_X540_vf ||
2502 hw->mac.type == ixgbe_mac_X550_vf ||
2503 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2505 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2507 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2511 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2513 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2515 #ifndef RTE_LIBRTE_XEN_DOM0
2516 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2518 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2520 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2523 * Certain constraints must be met in order to use the bulk buffer
2524 * allocation Rx burst function. If any of Rx queues doesn't meet them
2525 * the feature should be disabled for the whole port.
2527 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2528 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2529 "preconditions - canceling the feature for "
2530 "the whole port[%d]",
2531 rxq->queue_id, rxq->port_id);
2532 adapter->rx_bulk_alloc_allowed = false;
2536 * Allocate software ring. Allow for space at the end of the
2537 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2538 * function does not access an invalid memory region.
2541 if (adapter->rx_bulk_alloc_allowed)
2542 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2544 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2545 sizeof(struct ixgbe_rx_entry) * len,
2546 RTE_CACHE_LINE_SIZE, socket_id);
2547 if (!rxq->sw_ring) {
2548 ixgbe_rx_queue_release(rxq);
2553 * Always allocate even if it's not going to be needed in order to
2554 * simplify the code.
2556 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2557 * be requested in ixgbe_dev_rx_init(), which is called later from
2561 rte_zmalloc_socket("rxq->sw_sc_ring",
2562 sizeof(struct ixgbe_scattered_rx_entry) * len,
2563 RTE_CACHE_LINE_SIZE, socket_id);
2564 if (!rxq->sw_sc_ring) {
2565 ixgbe_rx_queue_release(rxq);
2569 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2570 "dma_addr=0x%"PRIx64,
2571 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2572 rxq->rx_ring_phys_addr);
2574 if (!rte_is_power_of_2(nb_desc)) {
2575 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2576 "preconditions - canceling the feature for "
2577 "the whole port[%d]",
2578 rxq->queue_id, rxq->port_id);
2579 adapter->rx_vec_allowed = false;
2581 ixgbe_rxq_vec_setup(rxq);
2583 dev->data->rx_queues[queue_idx] = rxq;
2585 ixgbe_reset_rx_queue(adapter, rxq);
2591 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2593 #define IXGBE_RXQ_SCAN_INTERVAL 4
2594 volatile union ixgbe_adv_rx_desc *rxdp;
2595 struct ixgbe_rx_queue *rxq;
2598 if (rx_queue_id >= dev->data->nb_rx_queues) {
2599 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2603 rxq = dev->data->rx_queues[rx_queue_id];
2604 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2606 while ((desc < rxq->nb_rx_desc) &&
2607 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2608 desc += IXGBE_RXQ_SCAN_INTERVAL;
2609 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2610 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2611 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2612 desc - rxq->nb_rx_desc]);
2619 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2621 volatile union ixgbe_adv_rx_desc *rxdp;
2622 struct ixgbe_rx_queue *rxq = rx_queue;
2625 if (unlikely(offset >= rxq->nb_rx_desc))
2627 desc = rxq->rx_tail + offset;
2628 if (desc >= rxq->nb_rx_desc)
2629 desc -= rxq->nb_rx_desc;
2631 rxdp = &rxq->rx_ring[desc];
2632 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2635 void __attribute__((cold))
2636 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2639 struct ixgbe_adapter *adapter =
2640 (struct ixgbe_adapter *)dev->data->dev_private;
2642 PMD_INIT_FUNC_TRACE();
2644 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2645 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2647 txq->ops->release_mbufs(txq);
2648 txq->ops->reset(txq);
2652 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2653 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2655 ixgbe_rx_queue_release_mbufs(rxq);
2656 ixgbe_reset_rx_queue(adapter, rxq);
2662 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2666 PMD_INIT_FUNC_TRACE();
2668 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2669 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2670 dev->data->rx_queues[i] = NULL;
2672 dev->data->nb_rx_queues = 0;
2674 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2675 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2676 dev->data->tx_queues[i] = NULL;
2678 dev->data->nb_tx_queues = 0;
2681 /*********************************************************************
2683 * Device RX/TX init functions
2685 **********************************************************************/
2688 * Receive Side Scaling (RSS)
2689 * See section 7.1.2.8 in the following document:
2690 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2693 * The source and destination IP addresses of the IP header and the source
2694 * and destination ports of TCP/UDP headers, if any, of received packets are
2695 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2696 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2697 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2698 * RSS output index which is used as the RX queue index where to store the
2700 * The following output is supplied in the RX write-back descriptor:
2701 * - 32-bit result of the Microsoft RSS hash function,
2702 * - 4-bit RSS type field.
2706 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2707 * Used as the default key.
2709 static uint8_t rss_intel_key[40] = {
2710 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2711 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2712 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2713 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2714 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2718 ixgbe_rss_disable(struct rte_eth_dev *dev)
2720 struct ixgbe_hw *hw;
2723 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2725 mrqc &= ~IXGBE_MRQC_RSSEN;
2726 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2730 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2738 hash_key = rss_conf->rss_key;
2739 if (hash_key != NULL) {
2740 /* Fill in RSS hash key */
2741 for (i = 0; i < 10; i++) {
2742 rss_key = hash_key[(i * 4)];
2743 rss_key |= hash_key[(i * 4) + 1] << 8;
2744 rss_key |= hash_key[(i * 4) + 2] << 16;
2745 rss_key |= hash_key[(i * 4) + 3] << 24;
2746 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2750 /* Set configured hashing protocols in MRQC register */
2751 rss_hf = rss_conf->rss_hf;
2752 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2753 if (rss_hf & ETH_RSS_IPV4)
2754 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2755 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2756 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2757 if (rss_hf & ETH_RSS_IPV6)
2758 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2759 if (rss_hf & ETH_RSS_IPV6_EX)
2760 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2761 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2762 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2763 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2764 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2765 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2766 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2767 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2768 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2769 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2770 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2771 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2775 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2776 struct rte_eth_rss_conf *rss_conf)
2778 struct ixgbe_hw *hw;
2782 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2786 * "RSS enabling cannot be done dynamically while it must be
2787 * preceded by a software reset"
2788 * Before changing anything, first check that the update RSS operation
2789 * does not attempt to disable RSS, if RSS was enabled at
2790 * initialization time, or does not attempt to enable RSS, if RSS was
2791 * disabled at initialization time.
2793 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2794 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2795 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2796 if (rss_hf != 0) /* Enable RSS */
2798 return 0; /* Nothing to do */
2801 if (rss_hf == 0) /* Disable RSS */
2803 ixgbe_hw_rss_hash_set(hw, rss_conf);
2808 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2809 struct rte_eth_rss_conf *rss_conf)
2811 struct ixgbe_hw *hw;
2818 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 hash_key = rss_conf->rss_key;
2820 if (hash_key != NULL) {
2821 /* Return RSS hash key */
2822 for (i = 0; i < 10; i++) {
2823 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2824 hash_key[(i * 4)] = rss_key & 0x000000FF;
2825 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2826 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2827 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2831 /* Get RSS functions configured in MRQC register */
2832 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2833 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2834 rss_conf->rss_hf = 0;
2838 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2839 rss_hf |= ETH_RSS_IPV4;
2840 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2841 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2842 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2843 rss_hf |= ETH_RSS_IPV6;
2844 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2845 rss_hf |= ETH_RSS_IPV6_EX;
2846 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2847 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2848 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2849 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2850 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2851 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2852 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2853 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2854 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2855 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2856 rss_conf->rss_hf = rss_hf;
2861 ixgbe_rss_configure(struct rte_eth_dev *dev)
2863 struct rte_eth_rss_conf rss_conf;
2864 struct ixgbe_hw *hw;
2869 PMD_INIT_FUNC_TRACE();
2870 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 * Fill in redirection table
2874 * The byte-swap is needed because NIC registers are in
2875 * little-endian order.
2878 for (i = 0, j = 0; i < 128; i++, j++) {
2879 if (j == dev->data->nb_rx_queues)
2881 reta = (reta << 8) | j;
2883 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2888 * Configure the RSS key and the RSS protocols used to compute
2889 * the RSS hash of input packets.
2891 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2892 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2893 ixgbe_rss_disable(dev);
2896 if (rss_conf.rss_key == NULL)
2897 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2898 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2901 #define NUM_VFTA_REGISTERS 128
2902 #define NIC_RX_BUFFER_SIZE 0x200
2905 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2907 struct rte_eth_vmdq_dcb_conf *cfg;
2908 struct ixgbe_hw *hw;
2909 enum rte_eth_nb_pools num_pools;
2910 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2912 uint8_t nb_tcs; /* number of traffic classes */
2915 PMD_INIT_FUNC_TRACE();
2916 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2918 num_pools = cfg->nb_queue_pools;
2919 /* Check we have a valid number of pools */
2920 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2921 ixgbe_rss_disable(dev);
2924 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2925 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2929 * split rx buffer up into sections, each for 1 traffic class
2931 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2932 for (i = 0 ; i < nb_tcs; i++) {
2933 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2934 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2935 /* clear 10 bits. */
2936 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2937 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2939 /* zero alloc all unused TCs */
2940 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2941 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2942 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2943 /* clear 10 bits. */
2944 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2947 /* MRQC: enable vmdq and dcb */
2948 mrqc = ((num_pools == ETH_16_POOLS) ? \
2949 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2950 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2952 /* PFVTCTL: turn on virtualisation and set the default pool */
2953 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2954 if (cfg->enable_default_pool) {
2955 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2957 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2960 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2962 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2964 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2966 * mapping is done with 3 bits per priority,
2967 * so shift by i*3 each time
2969 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2971 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2973 /* RTRPCS: DCB related */
2974 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2976 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2977 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2978 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2979 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2981 /* VFTA - enable all vlan filters */
2982 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2983 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2986 /* VFRE: pool enabling for receive - 16 or 32 */
2987 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2988 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2991 * MPSAR - allow pools to read specific mac addresses
2992 * In this case, all pools should be able to read from mac addr 0
2994 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2995 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2997 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2998 for (i = 0; i < cfg->nb_pool_maps; i++) {
2999 /* set vlan id in VF register and set the valid bit */
3000 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3001 (cfg->pool_map[i].vlan_id & 0xFFF)));
3003 * Put the allowed pools in VFB reg. As we only have 16 or 32
3004 * pools, we only need to use the first half of the register
3007 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3012 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3013 * @hw: pointer to hardware structure
3014 * @dcb_config: pointer to ixgbe_dcb_config structure
3017 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3018 struct ixgbe_dcb_config *dcb_config)
3023 PMD_INIT_FUNC_TRACE();
3024 if (hw->mac.type != ixgbe_mac_82598EB) {
3025 /* Disable the Tx desc arbiter so that MTQC can be changed */
3026 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3027 reg |= IXGBE_RTTDCS_ARBDIS;
3028 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3030 /* Enable DCB for Tx with 8 TCs */
3031 if (dcb_config->num_tcs.pg_tcs == 8) {
3032 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3035 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3037 if (dcb_config->vt_mode)
3038 reg |= IXGBE_MTQC_VT_ENA;
3039 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3041 /* Disable drop for all queues */
3042 for (q = 0; q < 128; q++)
3043 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3044 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3046 /* Enable the Tx desc arbiter */
3047 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3048 reg &= ~IXGBE_RTTDCS_ARBDIS;
3049 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3051 /* Enable Security TX Buffer IFG for DCB */
3052 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3053 reg |= IXGBE_SECTX_DCB;
3054 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3060 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3061 * @dev: pointer to rte_eth_dev structure
3062 * @dcb_config: pointer to ixgbe_dcb_config structure
3065 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3066 struct ixgbe_dcb_config *dcb_config)
3068 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3069 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3070 struct ixgbe_hw *hw =
3071 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3073 PMD_INIT_FUNC_TRACE();
3074 if (hw->mac.type != ixgbe_mac_82598EB)
3075 /*PF VF Transmit Enable*/
3076 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3077 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3079 /*Configure general DCB TX parameters*/
3080 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3085 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3086 struct ixgbe_dcb_config *dcb_config)
3088 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3089 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3090 struct ixgbe_dcb_tc_config *tc;
3093 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3094 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3095 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3096 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3099 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3100 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3102 /* User Priority to Traffic Class mapping */
3103 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3104 j = vmdq_rx_conf->dcb_queue[i];
3105 tc = &dcb_config->tc_config[j];
3106 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3112 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3113 struct ixgbe_dcb_config *dcb_config)
3115 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3116 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3117 struct ixgbe_dcb_tc_config *tc;
3120 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3121 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3122 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3123 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3126 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3127 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3130 /* User Priority to Traffic Class mapping */
3131 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3132 j = vmdq_tx_conf->dcb_queue[i];
3133 tc = &dcb_config->tc_config[j];
3134 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3141 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3142 struct ixgbe_dcb_config *dcb_config)
3144 struct rte_eth_dcb_rx_conf *rx_conf =
3145 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3146 struct ixgbe_dcb_tc_config *tc;
3149 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3150 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3152 /* User Priority to Traffic Class mapping */
3153 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3154 j = rx_conf->dcb_queue[i];
3155 tc = &dcb_config->tc_config[j];
3156 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3162 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3163 struct ixgbe_dcb_config *dcb_config)
3165 struct rte_eth_dcb_tx_conf *tx_conf =
3166 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3167 struct ixgbe_dcb_tc_config *tc;
3170 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3171 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3173 /* User Priority to Traffic Class mapping */
3174 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3175 j = tx_conf->dcb_queue[i];
3176 tc = &dcb_config->tc_config[j];
3177 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3183 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3184 * @hw: pointer to hardware structure
3185 * @dcb_config: pointer to ixgbe_dcb_config structure
3188 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3189 struct ixgbe_dcb_config *dcb_config)
3195 PMD_INIT_FUNC_TRACE();
3197 * Disable the arbiter before changing parameters
3198 * (always enable recycle mode; WSP)
3200 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3201 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3203 if (hw->mac.type != ixgbe_mac_82598EB) {
3204 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3205 if (dcb_config->num_tcs.pg_tcs == 4) {
3206 if (dcb_config->vt_mode)
3207 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3208 IXGBE_MRQC_VMDQRT4TCEN;
3210 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3211 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3215 if (dcb_config->num_tcs.pg_tcs == 8) {
3216 if (dcb_config->vt_mode)
3217 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3218 IXGBE_MRQC_VMDQRT8TCEN;
3220 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3221 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3226 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3229 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3230 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3231 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3232 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3234 /* VFTA - enable all vlan filters */
3235 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3236 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3240 * Configure Rx packet plane (recycle mode; WSP) and
3243 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3244 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3250 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3251 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3253 switch (hw->mac.type) {
3254 case ixgbe_mac_82598EB:
3255 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3257 case ixgbe_mac_82599EB:
3258 case ixgbe_mac_X540:
3259 case ixgbe_mac_X550:
3260 case ixgbe_mac_X550EM_x:
3261 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3270 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3271 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3273 switch (hw->mac.type) {
3274 case ixgbe_mac_82598EB:
3275 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3276 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3278 case ixgbe_mac_82599EB:
3279 case ixgbe_mac_X540:
3280 case ixgbe_mac_X550:
3281 case ixgbe_mac_X550EM_x:
3282 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3283 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3290 #define DCB_RX_CONFIG 1
3291 #define DCB_TX_CONFIG 1
3292 #define DCB_TX_PB 1024
3294 * ixgbe_dcb_hw_configure - Enable DCB and configure
3295 * general DCB in VT mode and non-VT mode parameters
3296 * @dev: pointer to rte_eth_dev structure
3297 * @dcb_config: pointer to ixgbe_dcb_config structure
3300 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3301 struct ixgbe_dcb_config *dcb_config)
3304 uint8_t i,pfc_en,nb_tcs;
3306 uint8_t config_dcb_rx = 0;
3307 uint8_t config_dcb_tx = 0;
3308 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3309 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3310 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3311 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3312 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3313 struct ixgbe_dcb_tc_config *tc;
3314 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3315 struct ixgbe_hw *hw =
3316 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318 switch(dev->data->dev_conf.rxmode.mq_mode){
3319 case ETH_MQ_RX_VMDQ_DCB:
3320 dcb_config->vt_mode = true;
3321 if (hw->mac.type != ixgbe_mac_82598EB) {
3322 config_dcb_rx = DCB_RX_CONFIG;
3324 *get dcb and VT rx configuration parameters
3327 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3328 /*Configure general VMDQ and DCB RX parameters*/
3329 ixgbe_vmdq_dcb_configure(dev);
3333 dcb_config->vt_mode = false;
3334 config_dcb_rx = DCB_RX_CONFIG;
3335 /* Get dcb TX configuration parameters from rte_eth_conf */
3336 ixgbe_dcb_rx_config(dev,dcb_config);
3337 /*Configure general DCB RX parameters*/
3338 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3341 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3344 switch (dev->data->dev_conf.txmode.mq_mode) {
3345 case ETH_MQ_TX_VMDQ_DCB:
3346 dcb_config->vt_mode = true;
3347 config_dcb_tx = DCB_TX_CONFIG;
3348 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3349 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3350 /*Configure general VMDQ and DCB TX parameters*/
3351 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3355 dcb_config->vt_mode = false;
3356 config_dcb_tx = DCB_TX_CONFIG;
3357 /*get DCB TX configuration parameters from rte_eth_conf*/
3358 ixgbe_dcb_tx_config(dev,dcb_config);
3359 /*Configure general DCB TX parameters*/
3360 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3363 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3367 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3369 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3370 if(nb_tcs == ETH_4_TCS) {
3371 /* Avoid un-configured priority mapping to TC0 */
3373 uint8_t mask = 0xFF;
3374 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3375 mask = (uint8_t)(mask & (~ (1 << map[i])));
3376 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3377 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3381 /* Re-configure 4 TCs BW */
3382 for (i = 0; i < nb_tcs; i++) {
3383 tc = &dcb_config->tc_config[i];
3384 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3385 (uint8_t)(100 / nb_tcs);
3386 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3387 (uint8_t)(100 / nb_tcs);
3389 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3390 tc = &dcb_config->tc_config[i];
3391 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3392 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3397 /* Set RX buffer size */
3398 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3399 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3400 for (i = 0 ; i < nb_tcs; i++) {
3401 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3403 /* zero alloc all unused TCs */
3404 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3405 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3409 /* Only support an equally distributed Tx packet buffer strategy. */
3410 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3411 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3412 for (i = 0; i < nb_tcs; i++) {
3413 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3414 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3416 /* Clear unused TCs, if any, to zero buffer size*/
3417 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3418 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3419 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3423 /*Calculates traffic class credits*/
3424 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3425 IXGBE_DCB_TX_CONFIG);
3426 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3427 IXGBE_DCB_RX_CONFIG);
3430 /* Unpack CEE standard containers */
3431 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3432 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3433 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3434 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3435 /* Configure PG(ETS) RX */
3436 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3440 /* Unpack CEE standard containers */
3441 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3442 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3443 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3444 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3445 /* Configure PG(ETS) TX */
3446 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3449 /*Configure queue statistics registers*/
3450 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3452 /* Check if the PFC is supported */
3453 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3454 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3455 for (i = 0; i < nb_tcs; i++) {
3457 * If the TC count is 8,and the default high_water is 48,
3458 * the low_water is 16 as default.
3460 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3461 hw->fc.low_water[i] = pbsize / 4;
3462 /* Enable pfc for this TC */
3463 tc = &dcb_config->tc_config[i];
3464 tc->pfc = ixgbe_dcb_pfc_enabled;
3466 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3467 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3469 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3476 * ixgbe_configure_dcb - Configure DCB Hardware
3477 * @dev: pointer to rte_eth_dev
3479 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3481 struct ixgbe_dcb_config *dcb_cfg =
3482 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3483 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3485 PMD_INIT_FUNC_TRACE();
3487 /* check support mq_mode for DCB */
3488 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3489 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3492 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3495 /** Configure DCB hardware **/
3496 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3502 * VMDq only support for 10 GbE NIC.
3505 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3507 struct rte_eth_vmdq_rx_conf *cfg;
3508 struct ixgbe_hw *hw;
3509 enum rte_eth_nb_pools num_pools;
3510 uint32_t mrqc, vt_ctl, vlanctrl;
3514 PMD_INIT_FUNC_TRACE();
3515 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3517 num_pools = cfg->nb_queue_pools;
3519 ixgbe_rss_disable(dev);
3521 /* MRQC: enable vmdq */
3522 mrqc = IXGBE_MRQC_VMDQEN;
3523 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3525 /* PFVTCTL: turn on virtualisation and set the default pool */
3526 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3527 if (cfg->enable_default_pool)
3528 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3530 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3532 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3534 for (i = 0; i < (int)num_pools; i++) {
3535 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3536 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3539 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3540 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3541 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3542 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3544 /* VFTA - enable all vlan filters */
3545 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3546 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3548 /* VFRE: pool enabling for receive - 64 */
3549 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3550 if (num_pools == ETH_64_POOLS)
3551 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3554 * MPSAR - allow pools to read specific mac addresses
3555 * In this case, all pools should be able to read from mac addr 0
3557 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3558 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3560 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3561 for (i = 0; i < cfg->nb_pool_maps; i++) {
3562 /* set vlan id in VF register and set the valid bit */
3563 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3564 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3566 * Put the allowed pools in VFB reg. As we only have 16 or 64
3567 * pools, we only need to use the first half of the register
3570 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3571 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3572 (cfg->pool_map[i].pools & UINT32_MAX));
3574 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3575 ((cfg->pool_map[i].pools >> 32) \
3580 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3581 if (cfg->enable_loop_back) {
3582 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3583 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3584 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3587 IXGBE_WRITE_FLUSH(hw);
3591 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3592 * @hw: pointer to hardware structure
3595 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3600 PMD_INIT_FUNC_TRACE();
3601 /*PF VF Transmit Enable*/
3602 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3603 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3605 /* Disable the Tx desc arbiter so that MTQC can be changed */
3606 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3607 reg |= IXGBE_RTTDCS_ARBDIS;
3608 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3610 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3611 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3613 /* Disable drop for all queues */
3614 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3615 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3616 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3618 /* Enable the Tx desc arbiter */
3619 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3620 reg &= ~IXGBE_RTTDCS_ARBDIS;
3621 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3623 IXGBE_WRITE_FLUSH(hw);
3628 static int __attribute__((cold))
3629 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3631 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3635 /* Initialize software ring entries */
3636 for (i = 0; i < rxq->nb_rx_desc; i++) {
3637 volatile union ixgbe_adv_rx_desc *rxd;
3638 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3640 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3641 (unsigned) rxq->queue_id);
3645 rte_mbuf_refcnt_set(mbuf, 1);
3647 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3649 mbuf->port = rxq->port_id;
3652 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3653 rxd = &rxq->rx_ring[i];
3654 rxd->read.hdr_addr = dma_addr;
3655 rxd->read.pkt_addr = dma_addr;
3663 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3665 struct ixgbe_hw *hw;
3668 ixgbe_rss_configure(dev);
3670 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3672 /* MRQC: enable VF RSS */
3673 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3674 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3675 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3677 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3681 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3685 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3689 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3695 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3697 struct ixgbe_hw *hw =
3698 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3700 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3702 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3707 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3708 IXGBE_MRQC_VMDQRT4TCEN);
3712 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3713 IXGBE_MRQC_VMDQRT8TCEN);
3717 "invalid pool number in IOV mode");
3724 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3726 struct ixgbe_hw *hw =
3727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729 if (hw->mac.type == ixgbe_mac_82598EB)
3732 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3734 * SRIOV inactive scheme
3735 * any DCB/RSS w/o VMDq multi-queue setting
3737 switch (dev->data->dev_conf.rxmode.mq_mode) {
3739 ixgbe_rss_configure(dev);
3742 case ETH_MQ_RX_VMDQ_DCB:
3743 ixgbe_vmdq_dcb_configure(dev);
3746 case ETH_MQ_RX_VMDQ_ONLY:
3747 ixgbe_vmdq_rx_hw_configure(dev);
3750 case ETH_MQ_RX_NONE:
3751 /* if mq_mode is none, disable rss mode.*/
3752 default: ixgbe_rss_disable(dev);
3756 * SRIOV active scheme
3757 * Support RSS together with VMDq & SRIOV
3759 switch (dev->data->dev_conf.rxmode.mq_mode) {
3761 case ETH_MQ_RX_VMDQ_RSS:
3762 ixgbe_config_vf_rss(dev);
3765 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3766 case ETH_MQ_RX_VMDQ_DCB:
3767 case ETH_MQ_RX_VMDQ_DCB_RSS:
3769 "Could not support DCB with VMDq & SRIOV");
3772 ixgbe_config_vf_default(dev);
3781 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3783 struct ixgbe_hw *hw =
3784 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788 if (hw->mac.type == ixgbe_mac_82598EB)
3791 /* disable arbiter before setting MTQC */
3792 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3793 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3794 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3796 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3798 * SRIOV inactive scheme
3799 * any DCB w/o VMDq multi-queue setting
3801 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3802 ixgbe_vmdq_tx_hw_configure(hw);
3804 mtqc = IXGBE_MTQC_64Q_1PB;
3805 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3808 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3811 * SRIOV active scheme
3812 * FIXME if support DCB together with VMDq & SRIOV
3815 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3818 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3821 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3825 mtqc = IXGBE_MTQC_64Q_1PB;
3826 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3828 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3831 /* re-enable arbiter */
3832 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3833 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3839 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3841 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3842 * spec rev. 3.0 chapter 8.2.3.8.13.
3844 * @pool Memory pool of the Rx queue
3846 static inline uint32_t
3847 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3849 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3851 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3854 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3857 return IXGBE_RSCCTL_MAXDESC_16;
3858 else if (maxdesc >= 8)
3859 return IXGBE_RSCCTL_MAXDESC_8;
3860 else if (maxdesc >= 4)
3861 return IXGBE_RSCCTL_MAXDESC_4;
3863 return IXGBE_RSCCTL_MAXDESC_1;
3867 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3870 * (Taken from FreeBSD tree)
3871 * (yes this is all very magic and confusing :)
3874 * @entry the register array entry
3875 * @vector the MSIX vector for this queue
3879 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3881 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3884 vector |= IXGBE_IVAR_ALLOC_VAL;
3886 switch (hw->mac.type) {
3888 case ixgbe_mac_82598EB:
3890 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3892 entry += (type * 64);
3893 index = (entry >> 2) & 0x1F;
3894 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3895 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3896 ivar |= (vector << (8 * (entry & 0x3)));
3897 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3900 case ixgbe_mac_82599EB:
3901 case ixgbe_mac_X540:
3902 if (type == -1) { /* MISC IVAR */
3903 index = (entry & 1) * 8;
3904 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3905 ivar &= ~(0xFF << index);
3906 ivar |= (vector << index);
3907 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3908 } else { /* RX/TX IVARS */
3909 index = (16 * (entry & 1)) + (8 * type);
3910 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3911 ivar &= ~(0xFF << index);
3912 ivar |= (vector << index);
3913 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3923 void __attribute__((cold))
3924 ixgbe_set_rx_function(struct rte_eth_dev *dev)
3926 struct ixgbe_adapter *adapter =
3927 (struct ixgbe_adapter *)dev->data->dev_private;
3930 * In order to allow Vector Rx there are a few configuration
3931 * conditions to be met and Rx Bulk Allocation should be allowed.
3933 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3934 !adapter->rx_bulk_alloc_allowed) {
3935 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3936 "preconditions or RTE_IXGBE_INC_VECTOR is "
3938 dev->data->port_id);
3940 adapter->rx_vec_allowed = false;
3944 * Initialize the appropriate LRO callback.
3946 * If all queues satisfy the bulk allocation preconditions
3947 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3948 * Otherwise use a single allocation version.
3950 if (dev->data->lro) {
3951 if (adapter->rx_bulk_alloc_allowed) {
3952 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
3953 "allocation version");
3954 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3956 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
3957 "allocation version");
3958 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3960 } else if (dev->data->scattered_rx) {
3962 * Set the non-LRO scattered callback: there are Vector and
3963 * single allocation versions.
3965 if (adapter->rx_vec_allowed) {
3966 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3967 "callback (port=%d).",
3968 dev->data->port_id);
3970 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3971 } else if (adapter->rx_bulk_alloc_allowed) {
3972 PMD_INIT_LOG(INFO, "Using a Scattered with bulk "
3973 "allocation callback (port=%d).",
3974 dev->data->port_id);
3975 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3977 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3978 "single allocation) "
3979 "Scattered Rx callback "
3981 dev->data->port_id);
3983 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3986 * Below we set "simple" callbacks according to port/queues parameters.
3987 * If parameters allow we are going to choose between the following
3991 * - Single buffer allocation (the simplest one)
3993 } else if (adapter->rx_vec_allowed) {
3994 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3995 "burst size no less than 32.");
3997 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3998 } else if (adapter->rx_bulk_alloc_allowed) {
3999 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4000 "satisfied. Rx Burst Bulk Alloc function "
4001 "will be used on port=%d.",
4002 dev->data->port_id);
4004 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4006 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4007 "satisfied, or Scattered Rx is requested, "
4008 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
4009 "is not enabled (port=%d).",
4010 dev->data->port_id);
4012 dev->rx_pkt_burst = ixgbe_recv_pkts;
4017 * ixgbe_set_rsc - configure RSC related port HW registers
4019 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4020 * of 82599 Spec (x540 configuration is virtually the same).
4024 * Returns 0 in case of success or a non-zero error code
4027 ixgbe_set_rsc(struct rte_eth_dev *dev)
4029 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031 struct rte_eth_dev_info dev_info = { 0 };
4032 bool rsc_capable = false;
4037 dev->dev_ops->dev_infos_get(dev, &dev_info);
4038 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4041 if (!rsc_capable && rx_conf->enable_lro) {
4042 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4047 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4049 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4051 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4052 * 3.0 RSC configuration requires HW CRC stripping being
4053 * enabled. If user requested both HW CRC stripping off
4054 * and RSC on - return an error.
4056 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4061 /* RFCTL configuration */
4063 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4064 if (rx_conf->enable_lro)
4066 * Since NFS packets coalescing is not supported - clear
4067 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4070 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4071 IXGBE_RFCTL_NFSR_DIS);
4073 rfctl |= IXGBE_RFCTL_RSC_DIS;
4075 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4078 /* If LRO hasn't been requested - we are done here. */
4079 if (!rx_conf->enable_lro)
4082 /* Set RDRXCTL.RSCACKC bit */
4083 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4084 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4085 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4087 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4088 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4089 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4091 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4093 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4095 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4097 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4100 * ixgbe PMD doesn't support header-split at the moment.
4102 * Following the 4.6.7.2.1 chapter of the 82599/x540
4103 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4104 * should be configured even if header split is not
4105 * enabled. We will configure it 128 bytes following the
4106 * recommendation in the spec.
4108 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4109 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4110 IXGBE_SRRCTL_BSIZEHDR_MASK;
4113 * TODO: Consider setting the Receive Descriptor Minimum
4114 * Threshold Size for an RSC case. This is not an obviously
4115 * beneficiary option but the one worth considering...
4118 rscctl |= IXGBE_RSCCTL_RSCEN;
4119 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4120 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4123 * RSC: Set ITR interval corresponding to 2K ints/s.
4125 * Full-sized RSC aggregations for a 10Gb/s link will
4126 * arrive at about 20K aggregation/s rate.
4128 * 2K inst/s rate will make only 10% of the
4129 * aggregations to be closed due to the interrupt timer
4130 * expiration for a streaming at wire-speed case.
4132 * For a sparse streaming case this setting will yield
4133 * at most 500us latency for a single RSC aggregation.
4135 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4136 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4138 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4139 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4140 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4141 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4144 * RSC requires the mapping of the queue to the
4147 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4152 PMD_INIT_LOG(INFO, "enabling LRO mode");
4158 * Initializes Receive Unit.
4160 int __attribute__((cold))
4161 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4163 struct ixgbe_hw *hw;
4164 struct ixgbe_rx_queue *rxq;
4175 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4178 PMD_INIT_FUNC_TRACE();
4179 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 * Make sure receives are disabled while setting
4183 * up the RX context (registers, descriptor rings, etc.).
4185 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4186 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4188 /* Enable receipt of broadcasted frames */
4189 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4190 fctrl |= IXGBE_FCTRL_BAM;
4191 fctrl |= IXGBE_FCTRL_DPF;
4192 fctrl |= IXGBE_FCTRL_PMCF;
4193 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4196 * Configure CRC stripping, if any.
4198 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4199 if (rx_conf->hw_strip_crc)
4200 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4202 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4205 * Configure jumbo frame support, if any.
4207 if (rx_conf->jumbo_frame == 1) {
4208 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4209 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4210 maxfrs &= 0x0000FFFF;
4211 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4212 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4214 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4217 * If loopback mode is configured for 82599, set LPBK bit.
4219 if (hw->mac.type == ixgbe_mac_82599EB &&
4220 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4221 hlreg0 |= IXGBE_HLREG0_LPBK;
4223 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4225 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4227 /* Setup RX queues */
4228 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4229 rxq = dev->data->rx_queues[i];
4232 * Reset crc_len in case it was changed after queue setup by a
4233 * call to configure.
4235 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4237 /* Setup the Base and Length of the Rx Descriptor Rings */
4238 bus_addr = rxq->rx_ring_phys_addr;
4239 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4240 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4241 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4242 (uint32_t)(bus_addr >> 32));
4243 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4244 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4245 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4246 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4248 /* Configure the SRRCTL register */
4249 #ifdef RTE_HEADER_SPLIT_ENABLE
4251 * Configure Header Split
4253 if (rx_conf->header_split) {
4254 if (hw->mac.type == ixgbe_mac_82599EB) {
4255 /* Must setup the PSRTYPE register */
4257 psrtype = IXGBE_PSRTYPE_TCPHDR |
4258 IXGBE_PSRTYPE_UDPHDR |
4259 IXGBE_PSRTYPE_IPV4HDR |
4260 IXGBE_PSRTYPE_IPV6HDR;
4261 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4263 srrctl = ((rx_conf->split_hdr_size <<
4264 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4265 IXGBE_SRRCTL_BSIZEHDR_MASK);
4266 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4269 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4271 /* Set if packets are dropped when no descriptors available */
4273 srrctl |= IXGBE_SRRCTL_DROP_EN;
4276 * Configure the RX buffer size in the BSIZEPACKET field of
4277 * the SRRCTL register of the queue.
4278 * The value is in 1 KB resolution. Valid values can be from
4281 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4282 RTE_PKTMBUF_HEADROOM);
4283 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4284 IXGBE_SRRCTL_BSIZEPKT_MASK);
4286 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4288 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4289 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4291 /* It adds dual VLAN length for supporting dual VLAN */
4292 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4293 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4294 dev->data->scattered_rx = 1;
4297 if (rx_conf->enable_scatter)
4298 dev->data->scattered_rx = 1;
4301 * Device configured with multiple RX queues.
4303 ixgbe_dev_mq_rx_configure(dev);
4306 * Setup the Checksum Register.
4307 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4308 * Enable IP/L4 checkum computation by hardware if requested to do so.
4310 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4311 rxcsum |= IXGBE_RXCSUM_PCSD;
4312 if (rx_conf->hw_ip_checksum)
4313 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4315 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4317 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4319 if (hw->mac.type == ixgbe_mac_82599EB ||
4320 hw->mac.type == ixgbe_mac_X540) {
4321 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4322 if (rx_conf->hw_strip_crc)
4323 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4325 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4326 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4327 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4330 rc = ixgbe_set_rsc(dev);
4334 ixgbe_set_rx_function(dev);
4340 * Initializes Transmit Unit.
4342 void __attribute__((cold))
4343 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4345 struct ixgbe_hw *hw;
4346 struct ixgbe_tx_queue *txq;
4352 PMD_INIT_FUNC_TRACE();
4353 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355 /* Enable TX CRC (checksum offload requirement) and hw padding
4356 * (TSO requirement) */
4357 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4358 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4359 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4361 /* Setup the Base and Length of the Tx Descriptor Rings */
4362 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4363 txq = dev->data->tx_queues[i];
4365 bus_addr = txq->tx_ring_phys_addr;
4366 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4367 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4368 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4369 (uint32_t)(bus_addr >> 32));
4370 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4371 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4372 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4373 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4374 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4377 * Disable Tx Head Writeback RO bit, since this hoses
4378 * bookkeeping if things aren't delivered in order.
4380 switch (hw->mac.type) {
4381 case ixgbe_mac_82598EB:
4382 txctrl = IXGBE_READ_REG(hw,
4383 IXGBE_DCA_TXCTRL(txq->reg_idx));
4384 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4385 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4389 case ixgbe_mac_82599EB:
4390 case ixgbe_mac_X540:
4391 case ixgbe_mac_X550:
4392 case ixgbe_mac_X550EM_x:
4394 txctrl = IXGBE_READ_REG(hw,
4395 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4396 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4397 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4403 /* Device configured with multiple TX queues. */
4404 ixgbe_dev_mq_tx_configure(dev);
4408 * Set up link for 82599 loopback mode Tx->Rx.
4410 static inline void __attribute__((cold))
4411 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4413 PMD_INIT_FUNC_TRACE();
4415 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4416 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4418 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4427 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4428 ixgbe_reset_pipeline_82599(hw);
4430 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4436 * Start Transmit and Receive Units.
4438 int __attribute__((cold))
4439 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4441 struct ixgbe_hw *hw;
4442 struct ixgbe_tx_queue *txq;
4443 struct ixgbe_rx_queue *rxq;
4450 PMD_INIT_FUNC_TRACE();
4451 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4453 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4454 txq = dev->data->tx_queues[i];
4455 /* Setup Transmit Threshold Registers */
4456 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4457 txdctl |= txq->pthresh & 0x7F;
4458 txdctl |= ((txq->hthresh & 0x7F) << 8);
4459 txdctl |= ((txq->wthresh & 0x7F) << 16);
4460 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4463 if (hw->mac.type != ixgbe_mac_82598EB) {
4464 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4465 dmatxctl |= IXGBE_DMATXCTL_TE;
4466 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4469 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4470 txq = dev->data->tx_queues[i];
4471 if (!txq->tx_deferred_start) {
4472 ret = ixgbe_dev_tx_queue_start(dev, i);
4478 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4479 rxq = dev->data->rx_queues[i];
4480 if (!rxq->rx_deferred_start) {
4481 ret = ixgbe_dev_rx_queue_start(dev, i);
4487 /* Enable Receive engine */
4488 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4489 if (hw->mac.type == ixgbe_mac_82598EB)
4490 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4491 rxctrl |= IXGBE_RXCTRL_RXEN;
4492 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4494 /* If loopback mode is enabled for 82599, set up the link accordingly */
4495 if (hw->mac.type == ixgbe_mac_82599EB &&
4496 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4497 ixgbe_setup_loopback_link_82599(hw);
4503 * Start Receive Units for specified queue.
4505 int __attribute__((cold))
4506 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4508 struct ixgbe_hw *hw;
4509 struct ixgbe_rx_queue *rxq;
4513 PMD_INIT_FUNC_TRACE();
4514 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516 if (rx_queue_id < dev->data->nb_rx_queues) {
4517 rxq = dev->data->rx_queues[rx_queue_id];
4519 /* Allocate buffers for descriptor rings */
4520 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4521 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4525 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4526 rxdctl |= IXGBE_RXDCTL_ENABLE;
4527 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4529 /* Wait until RX Enable ready */
4530 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4533 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4534 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4536 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4539 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4540 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4548 * Stop Receive Units for specified queue.
4550 int __attribute__((cold))
4551 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4553 struct ixgbe_hw *hw;
4554 struct ixgbe_adapter *adapter =
4555 (struct ixgbe_adapter *)dev->data->dev_private;
4556 struct ixgbe_rx_queue *rxq;
4560 PMD_INIT_FUNC_TRACE();
4561 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4563 if (rx_queue_id < dev->data->nb_rx_queues) {
4564 rxq = dev->data->rx_queues[rx_queue_id];
4566 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4567 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4568 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4570 /* Wait until RX Enable ready */
4571 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4574 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4575 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4577 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4580 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4582 ixgbe_rx_queue_release_mbufs(rxq);
4583 ixgbe_reset_rx_queue(adapter, rxq);
4592 * Start Transmit Units for specified queue.
4594 int __attribute__((cold))
4595 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4597 struct ixgbe_hw *hw;
4598 struct ixgbe_tx_queue *txq;
4602 PMD_INIT_FUNC_TRACE();
4603 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605 if (tx_queue_id < dev->data->nb_tx_queues) {
4606 txq = dev->data->tx_queues[tx_queue_id];
4607 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4608 txdctl |= IXGBE_TXDCTL_ENABLE;
4609 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4611 /* Wait until TX Enable ready */
4612 if (hw->mac.type == ixgbe_mac_82599EB) {
4613 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4616 txdctl = IXGBE_READ_REG(hw,
4617 IXGBE_TXDCTL(txq->reg_idx));
4618 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4620 PMD_INIT_LOG(ERR, "Could not enable "
4621 "Tx Queue %d", tx_queue_id);
4624 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4625 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4633 * Stop Transmit Units for specified queue.
4635 int __attribute__((cold))
4636 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4638 struct ixgbe_hw *hw;
4639 struct ixgbe_tx_queue *txq;
4641 uint32_t txtdh, txtdt;
4644 PMD_INIT_FUNC_TRACE();
4645 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647 if (tx_queue_id < dev->data->nb_tx_queues) {
4648 txq = dev->data->tx_queues[tx_queue_id];
4650 /* Wait until TX queue is empty */
4651 if (hw->mac.type == ixgbe_mac_82599EB) {
4652 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4654 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4655 txtdh = IXGBE_READ_REG(hw,
4656 IXGBE_TDH(txq->reg_idx));
4657 txtdt = IXGBE_READ_REG(hw,
4658 IXGBE_TDT(txq->reg_idx));
4659 } while (--poll_ms && (txtdh != txtdt));
4661 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4662 "when stopping.", tx_queue_id);
4665 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4666 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4667 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4669 /* Wait until TX Enable ready */
4670 if (hw->mac.type == ixgbe_mac_82599EB) {
4671 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4674 txdctl = IXGBE_READ_REG(hw,
4675 IXGBE_TXDCTL(txq->reg_idx));
4676 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4678 PMD_INIT_LOG(ERR, "Could not disable "
4679 "Tx Queue %d", tx_queue_id);
4682 if (txq->ops != NULL) {
4683 txq->ops->release_mbufs(txq);
4684 txq->ops->reset(txq);
4693 * [VF] Initializes Receive Unit.
4695 int __attribute__((cold))
4696 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4698 struct ixgbe_hw *hw;
4699 struct ixgbe_rx_queue *rxq;
4701 uint32_t srrctl, psrtype = 0;
4706 PMD_INIT_FUNC_TRACE();
4707 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4710 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4711 "it should be power of 2");
4715 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4716 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4717 "it should be equal to or less than %d",
4718 hw->mac.max_rx_queues);
4723 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4724 * disables the VF receipt of packets if the PF MTU is > 1500.
4725 * This is done to deal with 82599 limitations that imposes
4726 * the PF and all VFs to share the same MTU.
4727 * Then, the PF driver enables again the VF receipt of packet when
4728 * the VF driver issues a IXGBE_VF_SET_LPE request.
4729 * In the meantime, the VF device cannot be used, even if the VF driver
4730 * and the Guest VM network stack are ready to accept packets with a
4731 * size up to the PF MTU.
4732 * As a work-around to this PF behaviour, force the call to
4733 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4734 * VF packets received can work in all cases.
4736 ixgbevf_rlpml_set_vf(hw,
4737 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4739 /* Setup RX queues */
4740 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4741 rxq = dev->data->rx_queues[i];
4743 /* Allocate buffers for descriptor rings */
4744 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4748 /* Setup the Base and Length of the Rx Descriptor Rings */
4749 bus_addr = rxq->rx_ring_phys_addr;
4751 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4752 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4753 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4754 (uint32_t)(bus_addr >> 32));
4755 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4756 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4757 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4758 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4761 /* Configure the SRRCTL register */
4762 #ifdef RTE_HEADER_SPLIT_ENABLE
4764 * Configure Header Split
4766 if (dev->data->dev_conf.rxmode.header_split) {
4767 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4768 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4769 IXGBE_SRRCTL_BSIZEHDR_MASK);
4770 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4773 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4775 /* Set if packets are dropped when no descriptors available */
4777 srrctl |= IXGBE_SRRCTL_DROP_EN;
4780 * Configure the RX buffer size in the BSIZEPACKET field of
4781 * the SRRCTL register of the queue.
4782 * The value is in 1 KB resolution. Valid values can be from
4785 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4786 RTE_PKTMBUF_HEADROOM);
4787 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4788 IXGBE_SRRCTL_BSIZEPKT_MASK);
4791 * VF modification to write virtual function SRRCTL register
4793 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4795 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4796 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4798 if (dev->data->dev_conf.rxmode.enable_scatter ||
4799 /* It adds dual VLAN length for supporting dual VLAN */
4800 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4801 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4802 if (!dev->data->scattered_rx)
4803 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4804 dev->data->scattered_rx = 1;
4808 #ifdef RTE_HEADER_SPLIT_ENABLE
4809 if (dev->data->dev_conf.rxmode.header_split)
4810 /* Must setup the PSRTYPE register */
4811 psrtype = IXGBE_PSRTYPE_TCPHDR |
4812 IXGBE_PSRTYPE_UDPHDR |
4813 IXGBE_PSRTYPE_IPV4HDR |
4814 IXGBE_PSRTYPE_IPV6HDR;
4817 /* Set RQPL for VF RSS according to max Rx queue */
4818 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4819 IXGBE_PSRTYPE_RQPL_SHIFT;
4820 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4822 ixgbe_set_rx_function(dev);
4828 * [VF] Initializes Transmit Unit.
4830 void __attribute__((cold))
4831 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4833 struct ixgbe_hw *hw;
4834 struct ixgbe_tx_queue *txq;
4839 PMD_INIT_FUNC_TRACE();
4840 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4842 /* Setup the Base and Length of the Tx Descriptor Rings */
4843 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4844 txq = dev->data->tx_queues[i];
4845 bus_addr = txq->tx_ring_phys_addr;
4846 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4847 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4848 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4849 (uint32_t)(bus_addr >> 32));
4850 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4851 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4852 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4853 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4854 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4857 * Disable Tx Head Writeback RO bit, since this hoses
4858 * bookkeeping if things aren't delivered in order.
4860 txctrl = IXGBE_READ_REG(hw,
4861 IXGBE_VFDCA_TXCTRL(i));
4862 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4863 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4869 * [VF] Start Transmit and Receive Units.
4871 void __attribute__((cold))
4872 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4874 struct ixgbe_hw *hw;
4875 struct ixgbe_tx_queue *txq;
4876 struct ixgbe_rx_queue *rxq;
4882 PMD_INIT_FUNC_TRACE();
4883 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4886 txq = dev->data->tx_queues[i];
4887 /* Setup Transmit Threshold Registers */
4888 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4889 txdctl |= txq->pthresh & 0x7F;
4890 txdctl |= ((txq->hthresh & 0x7F) << 8);
4891 txdctl |= ((txq->wthresh & 0x7F) << 16);
4892 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4895 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4897 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4898 txdctl |= IXGBE_TXDCTL_ENABLE;
4899 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4902 /* Wait until TX Enable ready */
4905 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4906 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4908 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4910 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4912 rxq = dev->data->rx_queues[i];
4914 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4915 rxdctl |= IXGBE_RXDCTL_ENABLE;
4916 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4918 /* Wait until RX Enable ready */
4922 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4923 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4925 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4927 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4932 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4933 int __attribute__((weak))
4934 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4939 uint16_t __attribute__((weak))
4940 ixgbe_recv_pkts_vec(
4941 void __rte_unused *rx_queue,
4942 struct rte_mbuf __rte_unused **rx_pkts,
4943 uint16_t __rte_unused nb_pkts)
4948 uint16_t __attribute__((weak))
4949 ixgbe_recv_scattered_pkts_vec(
4950 void __rte_unused *rx_queue,
4951 struct rte_mbuf __rte_unused **rx_pkts,
4952 uint16_t __rte_unused nb_pkts)
4957 int __attribute__((weak))
4958 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)