4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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15 * the documentation and/or other materials provided with the
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34 #include <rte_ethdev.h>
35 #include <rte_cycles.h>
36 #include <rte_malloc.h>
39 #include "lio_23xx_vf.h"
40 #include "lio_23xx_reg.h"
43 cn23xx_vf_setup_device(struct lio_device *lio_dev)
47 PMD_INIT_FUNC_TRACE();
49 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
50 reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
52 lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
53 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
54 lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
55 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
57 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
59 lio_dev->sriov_info.rings_per_vf =
60 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
62 lio_dev->default_config = lio_get_conf(lio_dev);
63 if (lio_dev->default_config == NULL)
70 cn23xx_vf_set_io_queues_off(struct lio_device *lio_dev)
72 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
75 /* Disable the i/p and o/p queues for this Octeon.
76 * IOQs will already be in reset.
77 * If RST bit is set, wait for Quiet bit to be set
78 * Once Quiet bit is set, clear the RST bit
80 PMD_INIT_FUNC_TRACE();
82 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
83 volatile uint64_t reg_val;
85 reg_val = lio_read_csr64(lio_dev,
86 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
87 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && !(reg_val &
88 CN23XX_PKT_INPUT_CTL_QUIET) && loop) {
89 reg_val = lio_read_csr64(
91 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
97 "clearing the reset reg failed or setting the quiet reg failed for qno %lu\n",
102 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
103 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
106 reg_val = lio_read_csr64(lio_dev,
107 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
108 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
109 lio_dev_err(lio_dev, "unable to reset qno %lu\n",
110 (unsigned long)q_no);