4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox
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39 /* Verbs headers do not support -pedantic. */
41 #pragma GCC diagnostic ignored "-Wpedantic"
43 #include <infiniband/verbs.h>
45 #pragma GCC diagnostic error "-Wpedantic"
49 #include <rte_mempool.h>
53 /** Rx queue counters. */
54 struct mlx4_rxq_stats {
55 unsigned int idx; /**< Mapping index. */
56 uint64_t ipackets; /**< Total of successfully received packets. */
57 uint64_t ibytes; /**< Total of successfully received bytes. */
58 uint64_t idropped; /**< Total of packets dropped when Rx ring full. */
59 uint64_t rx_nombuf; /**< Total of Rx mbuf allocation failures. */
64 struct ibv_recv_wr wr; /**< Work request. */
65 struct ibv_sge sge; /**< Scatter/gather element. */
66 struct rte_mbuf *buf; /**< Buffer. */
69 /** Rx queue descriptor. */
71 struct priv *priv; /**< Back pointer to private data. */
72 struct rte_mempool *mp; /**< Memory pool for allocations. */
73 struct ibv_mr *mr; /**< Memory region (for mp). */
74 struct ibv_cq *cq; /**< Completion queue. */
75 struct ibv_qp *qp; /**< Queue pair. */
76 struct ibv_comp_channel *channel; /**< Rx completion channel. */
77 unsigned int port_id; /**< Port ID for incoming packets. */
78 unsigned int elts_n; /**< (*elts)[] length. */
79 unsigned int elts_head; /**< Current index in (*elts)[]. */
80 struct rxq_elt (*elts)[]; /**< Rx elements. */
81 struct mlx4_rxq_stats stats; /**< Rx queue counters. */
82 unsigned int socket; /**< CPU socket ID for allocations. */
87 struct ibv_send_wr wr; /* Work request. */
88 struct ibv_sge sge; /* Scatter/gather element. */
89 struct rte_mbuf *buf; /**< Buffer. */
92 /** Rx queue counters. */
93 struct mlx4_txq_stats {
94 unsigned int idx; /**< Mapping index. */
95 uint64_t opackets; /**< Total of successfully sent packets. */
96 uint64_t obytes; /**< Total of successfully sent bytes. */
97 uint64_t odropped; /**< Total of packets not sent when Tx ring full. */
100 /** Tx queue descriptor. */
102 struct priv *priv; /**< Back pointer to private data. */
104 const struct rte_mempool *mp; /**< Cached memory pool. */
105 struct ibv_mr *mr; /**< Memory region (for mp). */
106 uint32_t lkey; /**< mr->lkey copy. */
107 } mp2mr[MLX4_PMD_TX_MP_CACHE]; /**< MP to MR translation table. */
108 struct ibv_cq *cq; /**< Completion queue. */
109 struct ibv_qp *qp; /**< Queue pair. */
110 uint32_t max_inline; /**< Max inline send size. */
111 unsigned int elts_n; /**< (*elts)[] length. */
112 struct txq_elt (*elts)[]; /**< Tx elements. */
113 unsigned int elts_head; /**< Current index in (*elts)[]. */
114 unsigned int elts_tail; /**< First element awaiting completion. */
115 unsigned int elts_comp; /**< Number of completion requests. */
116 unsigned int elts_comp_cd; /**< Countdown for next completion. */
117 unsigned int elts_comp_cd_init; /**< Initial value for countdown. */
118 struct mlx4_txq_stats stats; /**< Tx queue counters. */
119 unsigned int socket; /**< CPU socket ID for allocations. */
122 #endif /* MLX4_RXTX_H_ */