1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
39 #include "mlx5_utils.h"
40 #include "mlx5_rxtx.h"
41 #include "mlx5_autoconf.h"
42 #include "mlx5_defs.h"
43 #include "mlx5_glue.h"
45 /* Device parameter to enable RX completion queue compression. */
46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
48 /* Device parameter to configure inline send. */
49 #define MLX5_TXQ_INLINE "txq_inline"
52 * Device parameter to configure the number of TX queues threshold for
53 * enabling inline send.
55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
57 /* Device parameter to enable multi-packet send WQEs. */
58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
60 /* Device parameter to include 2 dsegs in the title WQEBB. */
61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
63 /* Device parameter to limit the size of inlining packet. */
64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
66 /* Device parameter to enable hardware Tx vector. */
67 #define MLX5_TX_VEC_EN "tx_vec_en"
69 /* Device parameter to enable hardware Rx vector. */
70 #define MLX5_RX_VEC_EN "rx_vec_en"
72 /* Activate Netlink support in VF mode. */
73 #define MLX5_VF_NL_EN "vf_nl_en"
75 #ifndef HAVE_IBV_MLX5_MOD_MPW
76 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
77 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
80 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
81 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
84 /** Driver-specific log messages type. */
88 * Retrieve integer value from environment variable.
91 * Environment variable name.
94 * Integer value, 0 if the variable is not set.
97 mlx5_getenv_int(const char *name)
99 const char *val = getenv(name);
107 * Verbs callback to allocate a memory. This function should allocate the space
108 * according to the size provided residing inside a huge page.
109 * Please note that all allocation must respect the alignment from libmlx5
110 * (i.e. currently sysconf(_SC_PAGESIZE)).
113 * The size in bytes of the memory to allocate.
115 * A pointer to the callback data.
118 * Allocated buffer, NULL otherwise and rte_errno is set.
121 mlx5_alloc_verbs_buf(size_t size, void *data)
123 struct priv *priv = data;
125 size_t alignment = sysconf(_SC_PAGESIZE);
126 unsigned int socket = SOCKET_ID_ANY;
128 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
129 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
131 socket = ctrl->socket;
132 } else if (priv->verbs_alloc_ctx.type ==
133 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
134 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
136 socket = ctrl->socket;
138 assert(data != NULL);
139 ret = rte_malloc_socket(__func__, size, alignment, socket);
146 * Verbs callback to free a memory.
149 * A pointer to the memory to free.
151 * A pointer to the callback data.
154 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
156 assert(data != NULL);
161 * DPDK callback to close the device.
163 * Destroy all queues and objects, free memory.
166 * Pointer to Ethernet device structure.
169 mlx5_dev_close(struct rte_eth_dev *dev)
171 struct priv *priv = dev->data->dev_private;
175 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
177 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
178 /* In case mlx5_dev_stop() has not been called. */
179 mlx5_dev_interrupt_handler_uninstall(dev);
180 mlx5_traffic_disable(dev);
181 /* Prevent crashes when queues are still in use. */
182 dev->rx_pkt_burst = removed_rx_burst;
183 dev->tx_pkt_burst = removed_tx_burst;
184 if (priv->rxqs != NULL) {
185 /* XXX race condition if mlx5_rx_burst() is still running. */
187 for (i = 0; (i != priv->rxqs_n); ++i)
188 mlx5_rxq_release(dev, i);
192 if (priv->txqs != NULL) {
193 /* XXX race condition if mlx5_tx_burst() is still running. */
195 for (i = 0; (i != priv->txqs_n); ++i)
196 mlx5_txq_release(dev, i);
200 mlx5_flow_delete_drop_queue(dev);
201 if (priv->pd != NULL) {
202 assert(priv->ctx != NULL);
203 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
204 claim_zero(mlx5_glue->close_device(priv->ctx));
206 assert(priv->ctx == NULL);
207 if (priv->rss_conf.rss_key != NULL)
208 rte_free(priv->rss_conf.rss_key);
209 if (priv->reta_idx != NULL)
210 rte_free(priv->reta_idx);
211 if (priv->primary_socket)
212 mlx5_socket_uninit(dev);
214 mlx5_nl_mac_addr_flush(dev);
215 if (priv->nl_socket >= 0)
216 close(priv->nl_socket);
217 ret = mlx5_hrxq_ibv_verify(dev);
219 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
221 ret = mlx5_ind_table_ibv_verify(dev);
223 DRV_LOG(WARNING, "port %u some indirection table still remain",
225 ret = mlx5_rxq_ibv_verify(dev);
227 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
229 ret = mlx5_rxq_verify(dev);
231 DRV_LOG(WARNING, "port %u some Rx queues still remain",
233 ret = mlx5_txq_ibv_verify(dev);
235 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
237 ret = mlx5_txq_verify(dev);
239 DRV_LOG(WARNING, "port %u some Tx queues still remain",
241 ret = mlx5_flow_verify(dev);
243 DRV_LOG(WARNING, "port %u some flows still remain",
245 ret = mlx5_mr_verify(dev);
247 DRV_LOG(WARNING, "port %u some memory region still remain",
249 memset(priv, 0, sizeof(*priv));
252 const struct eth_dev_ops mlx5_dev_ops = {
253 .dev_configure = mlx5_dev_configure,
254 .dev_start = mlx5_dev_start,
255 .dev_stop = mlx5_dev_stop,
256 .dev_set_link_down = mlx5_set_link_down,
257 .dev_set_link_up = mlx5_set_link_up,
258 .dev_close = mlx5_dev_close,
259 .promiscuous_enable = mlx5_promiscuous_enable,
260 .promiscuous_disable = mlx5_promiscuous_disable,
261 .allmulticast_enable = mlx5_allmulticast_enable,
262 .allmulticast_disable = mlx5_allmulticast_disable,
263 .link_update = mlx5_link_update,
264 .stats_get = mlx5_stats_get,
265 .stats_reset = mlx5_stats_reset,
266 .xstats_get = mlx5_xstats_get,
267 .xstats_reset = mlx5_xstats_reset,
268 .xstats_get_names = mlx5_xstats_get_names,
269 .dev_infos_get = mlx5_dev_infos_get,
270 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
271 .vlan_filter_set = mlx5_vlan_filter_set,
272 .rx_queue_setup = mlx5_rx_queue_setup,
273 .tx_queue_setup = mlx5_tx_queue_setup,
274 .rx_queue_release = mlx5_rx_queue_release,
275 .tx_queue_release = mlx5_tx_queue_release,
276 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
277 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
278 .mac_addr_remove = mlx5_mac_addr_remove,
279 .mac_addr_add = mlx5_mac_addr_add,
280 .mac_addr_set = mlx5_mac_addr_set,
281 .set_mc_addr_list = mlx5_set_mc_addr_list,
282 .mtu_set = mlx5_dev_set_mtu,
283 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
284 .vlan_offload_set = mlx5_vlan_offload_set,
285 .reta_update = mlx5_dev_rss_reta_update,
286 .reta_query = mlx5_dev_rss_reta_query,
287 .rss_hash_update = mlx5_rss_hash_update,
288 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
289 .filter_ctrl = mlx5_dev_filter_ctrl,
290 .rx_descriptor_status = mlx5_rx_descriptor_status,
291 .tx_descriptor_status = mlx5_tx_descriptor_status,
292 .rx_queue_intr_enable = mlx5_rx_intr_enable,
293 .rx_queue_intr_disable = mlx5_rx_intr_disable,
294 .is_removed = mlx5_is_removed,
297 static const struct eth_dev_ops mlx5_dev_sec_ops = {
298 .stats_get = mlx5_stats_get,
299 .stats_reset = mlx5_stats_reset,
300 .xstats_get = mlx5_xstats_get,
301 .xstats_reset = mlx5_xstats_reset,
302 .xstats_get_names = mlx5_xstats_get_names,
303 .dev_infos_get = mlx5_dev_infos_get,
304 .rx_descriptor_status = mlx5_rx_descriptor_status,
305 .tx_descriptor_status = mlx5_tx_descriptor_status,
308 /* Available operators in flow isolated mode. */
309 const struct eth_dev_ops mlx5_dev_ops_isolate = {
310 .dev_configure = mlx5_dev_configure,
311 .dev_start = mlx5_dev_start,
312 .dev_stop = mlx5_dev_stop,
313 .dev_set_link_down = mlx5_set_link_down,
314 .dev_set_link_up = mlx5_set_link_up,
315 .dev_close = mlx5_dev_close,
316 .link_update = mlx5_link_update,
317 .stats_get = mlx5_stats_get,
318 .stats_reset = mlx5_stats_reset,
319 .xstats_get = mlx5_xstats_get,
320 .xstats_reset = mlx5_xstats_reset,
321 .xstats_get_names = mlx5_xstats_get_names,
322 .dev_infos_get = mlx5_dev_infos_get,
323 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
324 .vlan_filter_set = mlx5_vlan_filter_set,
325 .rx_queue_setup = mlx5_rx_queue_setup,
326 .tx_queue_setup = mlx5_tx_queue_setup,
327 .rx_queue_release = mlx5_rx_queue_release,
328 .tx_queue_release = mlx5_tx_queue_release,
329 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
330 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
331 .mac_addr_remove = mlx5_mac_addr_remove,
332 .mac_addr_add = mlx5_mac_addr_add,
333 .mac_addr_set = mlx5_mac_addr_set,
334 .set_mc_addr_list = mlx5_set_mc_addr_list,
335 .mtu_set = mlx5_dev_set_mtu,
336 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
337 .vlan_offload_set = mlx5_vlan_offload_set,
338 .filter_ctrl = mlx5_dev_filter_ctrl,
339 .rx_descriptor_status = mlx5_rx_descriptor_status,
340 .tx_descriptor_status = mlx5_tx_descriptor_status,
341 .rx_queue_intr_enable = mlx5_rx_intr_enable,
342 .rx_queue_intr_disable = mlx5_rx_intr_disable,
343 .is_removed = mlx5_is_removed,
347 struct rte_pci_addr pci_addr; /* associated PCI address */
348 uint32_t ports; /* physical ports bitfield. */
352 * Get device index in mlx5_dev[] from PCI bus address.
354 * @param[in] pci_addr
355 * PCI bus address to look for.
358 * mlx5_dev[] index on success, -1 on failure.
361 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
366 assert(pci_addr != NULL);
367 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
368 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
369 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
370 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
371 (mlx5_dev[i].pci_addr.function == pci_addr->function))
373 if ((mlx5_dev[i].ports == 0) && (ret == -1))
380 * Verify and store value for device argument.
383 * Key argument to verify.
385 * Value associated with key.
390 * 0 on success, a negative errno value otherwise and rte_errno is set.
393 mlx5_args_check(const char *key, const char *val, void *opaque)
395 struct mlx5_dev_config *config = opaque;
399 tmp = strtoul(val, NULL, 0);
402 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
405 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
406 config->cqe_comp = !!tmp;
407 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
408 config->txq_inline = tmp;
409 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
410 config->txqs_inline = tmp;
411 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
412 config->mps = !!tmp ? config->mps : 0;
413 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
414 config->mpw_hdr_dseg = !!tmp;
415 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
416 config->inline_max_packet_sz = tmp;
417 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
418 config->tx_vec_en = !!tmp;
419 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
420 config->rx_vec_en = !!tmp;
421 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
422 config->vf_nl_en = !!tmp;
424 DRV_LOG(WARNING, "%s: unknown parameter", key);
432 * Parse device parameters.
435 * Pointer to device configuration structure.
437 * Device arguments structure.
440 * 0 on success, a negative errno value otherwise and rte_errno is set.
443 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
445 const char **params = (const char *[]){
446 MLX5_RXQ_CQE_COMP_EN,
448 MLX5_TXQS_MIN_INLINE,
450 MLX5_TXQ_MPW_HDR_DSEG_EN,
451 MLX5_TXQ_MAX_INLINE_LEN,
457 struct rte_kvargs *kvlist;
463 /* Following UGLY cast is done to pass checkpatch. */
464 kvlist = rte_kvargs_parse(devargs->args, params);
467 /* Process parameters. */
468 for (i = 0; (params[i] != NULL); ++i) {
469 if (rte_kvargs_count(kvlist, params[i])) {
470 ret = rte_kvargs_process(kvlist, params[i],
471 mlx5_args_check, config);
474 rte_kvargs_free(kvlist);
479 rte_kvargs_free(kvlist);
483 static struct rte_pci_driver mlx5_driver;
486 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
487 * local resource used by both primary and secondary to avoid duplicate
489 * The space has to be available on both primary and secondary process,
490 * TXQ UAR maps to this area using fixed mmap w/o double check.
492 static void *uar_base;
495 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
496 const struct rte_memseg *ms, void *arg)
503 *addr = RTE_MIN(*addr, ms->addr);
509 * Reserve UAR address space for primary process.
512 * Pointer to Ethernet device.
515 * 0 on success, a negative errno value otherwise and rte_errno is set.
518 mlx5_uar_init_primary(struct rte_eth_dev *dev)
520 struct priv *priv = dev->data->dev_private;
521 void *addr = (void *)0;
523 if (uar_base) { /* UAR address space mapped. */
524 priv->uar_base = uar_base;
527 /* find out lower bound of hugepage segments */
528 rte_memseg_walk(find_lower_va_bound, &addr);
530 /* keep distance to hugepages to minimize potential conflicts. */
531 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
532 /* anonymous mmap, no real memory consumption. */
533 addr = mmap(addr, MLX5_UAR_SIZE,
534 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
535 if (addr == MAP_FAILED) {
537 "port %u failed to reserve UAR address space, please"
538 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
543 /* Accept either same addr or a new addr returned from mmap if target
546 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
547 dev->data->port_id, addr);
548 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
549 uar_base = addr; /* process local, don't reserve again. */
554 * Reserve UAR address space for secondary process, align with
558 * Pointer to Ethernet device.
561 * 0 on success, a negative errno value otherwise and rte_errno is set.
564 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
566 struct priv *priv = dev->data->dev_private;
569 assert(priv->uar_base);
570 if (uar_base) { /* already reserved. */
571 assert(uar_base == priv->uar_base);
574 /* anonymous mmap, no real memory consumption. */
575 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
576 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
577 if (addr == MAP_FAILED) {
578 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
579 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
583 if (priv->uar_base != addr) {
585 "port %u UAR address %p size %llu occupied, please"
586 " adjust MLX5_UAR_OFFSET or try EAL parameter"
588 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
592 uar_base = addr; /* process local, don't reserve again */
593 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
594 dev->data->port_id, addr);
599 * DPDK callback to register a PCI device.
601 * This function creates an Ethernet device for each port of a given
605 * PCI driver structure (mlx5_driver).
607 * PCI device information.
610 * 0 on success, a negative errno value otherwise and rte_errno is set.
613 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
614 struct rte_pci_device *pci_dev)
616 struct ibv_device **list = NULL;
617 struct ibv_device *ibv_dev;
619 struct ibv_context *attr_ctx = NULL;
620 struct ibv_device_attr_ex device_attr;
623 unsigned int cqe_comp;
624 unsigned int tunnel_en = 0;
625 unsigned int swp = 0;
626 unsigned int verb_priorities = 0;
629 struct mlx5dv_context attrs_out = {0};
630 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
631 struct ibv_counter_set_description cs_desc;
634 assert(pci_drv == &mlx5_driver);
635 /* Get mlx5_dev[] index. */
636 idx = mlx5_dev_idx(&pci_dev->addr);
638 DRV_LOG(ERR, "this driver cannot support any more adapters");
642 DRV_LOG(DEBUG, "using driver device index %d", idx);
643 /* Save PCI address. */
644 mlx5_dev[idx].pci_addr = pci_dev->addr;
645 list = mlx5_glue->get_device_list(&i);
651 "cannot list devices, is ib_uverbs loaded?");
656 * For each listed device, check related sysfs entry against
657 * the provided PCI ID.
660 struct rte_pci_addr pci_addr;
663 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
664 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
666 if ((pci_dev->addr.domain != pci_addr.domain) ||
667 (pci_dev->addr.bus != pci_addr.bus) ||
668 (pci_dev->addr.devid != pci_addr.devid) ||
669 (pci_dev->addr.function != pci_addr.function))
671 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
673 vf = ((pci_dev->id.device_id ==
674 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
675 (pci_dev->id.device_id ==
676 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
677 (pci_dev->id.device_id ==
678 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
679 (pci_dev->id.device_id ==
680 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
681 attr_ctx = mlx5_glue->open_device(list[i]);
686 if (attr_ctx == NULL) {
687 mlx5_glue->free_device_list(list);
691 "cannot access device, is mlx5_ib loaded?");
696 "cannot use device, are drivers up to date?");
701 DRV_LOG(DEBUG, "device opened");
702 #ifdef HAVE_IBV_MLX5_MOD_SWP
703 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
706 * Multi-packet send is supported by ConnectX-4 Lx PF as well
707 * as all ConnectX-5 devices.
709 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
710 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
712 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
713 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
714 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
715 DRV_LOG(DEBUG, "enhanced MPW is supported");
716 mps = MLX5_MPW_ENHANCED;
718 DRV_LOG(DEBUG, "MPW is supported");
722 DRV_LOG(DEBUG, "MPW isn't supported");
723 mps = MLX5_MPW_DISABLED;
725 #ifdef HAVE_IBV_MLX5_MOD_SWP
726 if (attrs_out.comp_mask | MLX5DV_CONTEXT_MASK_SWP)
727 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
728 DRV_LOG(DEBUG, "SWP support: %u", swp);
730 if (RTE_CACHE_LINE_SIZE == 128 &&
731 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
735 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
736 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
737 tunnel_en = ((attrs_out.tunnel_offloads_caps &
738 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
739 (attrs_out.tunnel_offloads_caps &
740 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
742 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
743 tunnel_en ? "" : "not ");
746 "tunnel offloading disabled due to old OFED/rdma-core version");
748 if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
752 DRV_LOG(INFO, "%u port(s) detected",
753 device_attr.orig_attr.phys_port_cnt);
754 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
755 char name[RTE_ETH_NAME_MAX_LEN];
757 uint32_t port = i + 1; /* ports are indexed from one */
758 uint32_t test = (1 << i);
759 struct ibv_context *ctx = NULL;
760 struct ibv_port_attr port_attr;
761 struct ibv_pd *pd = NULL;
762 struct priv *priv = NULL;
763 struct rte_eth_dev *eth_dev = NULL;
764 struct ibv_device_attr_ex device_attr_ex;
765 struct ether_addr mac;
766 struct mlx5_dev_config config = {
767 .cqe_comp = cqe_comp,
769 .tunnel_en = tunnel_en,
773 .txq_inline = MLX5_ARG_UNSET,
774 .txqs_inline = MLX5_ARG_UNSET,
775 .inline_max_packet_sz = MLX5_ARG_UNSET,
780 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
781 pci_dev->addr.domain, pci_dev->addr.bus,
782 pci_dev->addr.devid, pci_dev->addr.function);
783 if (device_attr.orig_attr.phys_port_cnt > 1)
784 snprintf(name + len, sizeof(name), " port %u", i);
785 mlx5_dev[idx].ports |= test;
786 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
787 eth_dev = rte_eth_dev_attach_secondary(name);
788 if (eth_dev == NULL) {
789 DRV_LOG(ERR, "can not attach rte ethdev");
794 eth_dev->device = &pci_dev->device;
795 eth_dev->dev_ops = &mlx5_dev_sec_ops;
796 err = mlx5_uar_init_secondary(eth_dev);
799 /* Receive command fd from primary process */
800 err = mlx5_socket_connect(eth_dev);
803 /* Remap UAR for Tx queues. */
804 err = mlx5_tx_uar_remap(eth_dev, err);
808 * Ethdev pointer is still required as input since
809 * the primary device is not accessible from the
812 eth_dev->rx_pkt_burst =
813 mlx5_select_rx_function(eth_dev);
814 eth_dev->tx_pkt_burst =
815 mlx5_select_tx_function(eth_dev);
818 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
819 ctx = mlx5_glue->open_device(ibv_dev);
824 /* Check port status. */
825 err = mlx5_glue->query_port(ctx, port, &port_attr);
827 DRV_LOG(ERR, "port query failed: %s", strerror(err));
830 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
832 "port %d is not configured in Ethernet mode",
837 if (port_attr.state != IBV_PORT_ACTIVE)
838 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
840 mlx5_glue->port_state_str(port_attr.state),
842 /* Allocate protection domain. */
843 pd = mlx5_glue->alloc_pd(ctx);
845 DRV_LOG(ERR, "PD allocation failure");
849 mlx5_dev[idx].ports |= test;
850 /* from rte_ethdev.c */
851 priv = rte_zmalloc("ethdev private structure",
853 RTE_CACHE_LINE_SIZE);
855 DRV_LOG(ERR, "priv allocation failure");
860 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
861 sizeof(priv->ibdev_path));
862 priv->device_attr = device_attr;
865 priv->mtu = ETHER_MTU;
866 err = mlx5_args(&config, pci_dev->device.devargs);
868 DRV_LOG(ERR, "failed to process device arguments: %s",
872 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
873 DRV_LOG(ERR, "ibv_query_device_ex() failed");
877 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
878 IBV_DEVICE_RAW_IP_CSUM);
879 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
880 (config.hw_csum ? "" : "not "));
881 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
882 config.flow_counter_en = !!(device_attr.max_counter_sets);
883 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
885 "counter type = %d, num of cs = %ld, attributes = %d",
886 cs_desc.counter_type, cs_desc.num_of_cs,
889 config.ind_table_max_size =
890 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
891 /* Remove this check once DPDK supports larger/variable
892 * indirection tables. */
893 if (config.ind_table_max_size >
894 (unsigned int)ETH_RSS_RETA_SIZE_512)
895 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
896 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
897 config.ind_table_max_size);
898 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
899 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
900 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
901 (config.hw_vlan_strip ? "" : "not "));
903 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
904 IBV_RAW_PACKET_CAP_SCATTER_FCS);
905 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
906 (config.hw_fcs_strip ? "" : "not "));
908 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
909 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
912 "hardware Rx end alignment padding is %ssupported",
913 (config.hw_padding ? "" : "not "));
915 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
916 (device_attr_ex.tso_caps.supported_qpts &
917 (1 << IBV_QPT_RAW_PACKET)));
919 config.tso_max_payload_sz =
920 device_attr_ex.tso_caps.max_tso;
921 if (config.mps && !mps) {
923 "multi-packet send not supported on this device"
924 " (" MLX5_TXQ_MPW_EN ")");
928 DRV_LOG(INFO, "%s MPS is %s",
929 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
930 config.mps != MLX5_MPW_DISABLED ? "enabled" :
932 if (config.cqe_comp && !cqe_comp) {
933 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
936 eth_dev = rte_eth_dev_allocate(name);
937 if (eth_dev == NULL) {
938 DRV_LOG(ERR, "can not allocate rte ethdev");
942 eth_dev->data->dev_private = priv;
944 eth_dev->data->mac_addrs = priv->mac;
945 eth_dev->device = &pci_dev->device;
946 rte_eth_copy_pci_info(eth_dev, pci_dev);
947 eth_dev->device->driver = &mlx5_driver.driver;
948 err = mlx5_uar_init_primary(eth_dev);
951 /* Configure the first MAC address by default. */
952 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
954 "port %u cannot get MAC address, is mlx5_en"
955 " loaded? (errno: %s)",
956 eth_dev->data->port_id, strerror(errno));
961 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
962 eth_dev->data->port_id,
963 mac.addr_bytes[0], mac.addr_bytes[1],
964 mac.addr_bytes[2], mac.addr_bytes[3],
965 mac.addr_bytes[4], mac.addr_bytes[5]);
968 char ifname[IF_NAMESIZE];
970 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
971 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
972 eth_dev->data->port_id, ifname);
974 DRV_LOG(DEBUG, "port %u ifname is unknown",
975 eth_dev->data->port_id);
978 /* Get actual MTU if possible. */
979 err = mlx5_get_mtu(eth_dev, &priv->mtu);
982 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
985 * Initialize burst functions to prevent crashes before link-up.
987 eth_dev->rx_pkt_burst = removed_rx_burst;
988 eth_dev->tx_pkt_burst = removed_tx_burst;
989 eth_dev->dev_ops = &mlx5_dev_ops;
990 /* Register MAC address. */
991 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
992 priv->nl_socket = -1;
994 if (vf && config.vf_nl_en) {
995 priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
996 if (priv->nl_socket < 0)
997 priv->nl_socket = -1;
998 mlx5_nl_mac_addr_sync(eth_dev);
1000 TAILQ_INIT(&priv->flows);
1001 TAILQ_INIT(&priv->ctrl_flows);
1002 /* Hint libmlx5 to use PMD allocator for data plane resources */
1003 struct mlx5dv_ctx_allocators alctr = {
1004 .alloc = &mlx5_alloc_verbs_buf,
1005 .free = &mlx5_free_verbs_buf,
1008 mlx5_glue->dv_set_context_attr(ctx,
1009 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1010 (void *)((uintptr_t)&alctr));
1011 /* Bring Ethernet device up. */
1012 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1013 eth_dev->data->port_id);
1014 mlx5_set_link_up(eth_dev);
1016 * Even though the interrupt handler is not installed yet,
1017 * interrupts will still trigger on the asyn_fd from
1018 * Verbs context returned by ibv_open_device().
1020 mlx5_link_update(eth_dev, 0);
1021 /* Store device configuration on private structure. */
1022 priv->config = config;
1023 /* Create drop queue. */
1024 err = mlx5_flow_create_drop_queue(eth_dev);
1026 DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1027 eth_dev->data->port_id, strerror(rte_errno));
1030 /* Supported Verbs flow priority number detection. */
1031 if (verb_priorities == 0)
1032 verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1033 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1034 DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1035 eth_dev->data->port_id, verb_priorities);
1038 priv->config.max_verbs_prio = verb_priorities;
1044 claim_zero(mlx5_glue->dealloc_pd(pd));
1046 claim_zero(mlx5_glue->close_device(ctx));
1050 * XXX if something went wrong in the loop above, there is a resource
1051 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1052 * long as the dpdk does not provide a way to deallocate a ethdev and a
1053 * way to enumerate the registered ethdevs to free the previous ones.
1055 /* no port found, complain */
1056 if (!mlx5_dev[idx].ports) {
1062 claim_zero(mlx5_glue->close_device(attr_ctx));
1064 mlx5_glue->free_device_list(list);
1072 static const struct rte_pci_id mlx5_pci_id_map[] = {
1074 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1075 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1078 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1079 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1082 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1083 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1086 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1087 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1090 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1091 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1094 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1095 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1098 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1099 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1102 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1103 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1110 static struct rte_pci_driver mlx5_driver = {
1112 .name = MLX5_DRIVER_NAME
1114 .id_table = mlx5_pci_id_map,
1115 .probe = mlx5_pci_probe,
1116 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1119 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1122 * Suffix RTE_EAL_PMD_PATH with "-glue".
1124 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1125 * suffixing its last component.
1128 * Output buffer, should be large enough otherwise NULL is returned.
1133 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1136 mlx5_glue_path(char *buf, size_t size)
1138 static const char *const bad[] = { "/", ".", "..", NULL };
1139 const char *path = RTE_EAL_PMD_PATH;
1140 size_t len = strlen(path);
1144 while (len && path[len - 1] == '/')
1146 for (off = len; off && path[off - 1] != '/'; --off)
1148 for (i = 0; bad[i]; ++i)
1149 if (!strncmp(path + off, bad[i], (int)(len - off)))
1151 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1152 if (i == -1 || (size_t)i >= size)
1157 "unable to append \"-glue\" to last component of"
1158 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1159 " please re-configure DPDK");
1164 * Initialization routine for run-time dependency on rdma-core.
1167 mlx5_glue_init(void)
1169 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1170 const char *path[] = {
1172 * A basic security check is necessary before trusting
1173 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1175 (geteuid() == getuid() && getegid() == getgid() ?
1176 getenv("MLX5_GLUE_PATH") : NULL),
1178 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1179 * variant, otherwise let dlopen() look up libraries on its
1182 (*RTE_EAL_PMD_PATH ?
1183 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1186 void *handle = NULL;
1190 while (!handle && i != RTE_DIM(path)) {
1199 end = strpbrk(path[i], ":;");
1201 end = path[i] + strlen(path[i]);
1202 len = end - path[i];
1207 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1209 (!len || *(end - 1) == '/') ? "" : "/");
1212 if (sizeof(name) != (size_t)ret + 1)
1214 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1216 handle = dlopen(name, RTLD_LAZY);
1227 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1230 sym = dlsym(handle, "mlx5_glue");
1231 if (!sym || !*sym) {
1235 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1244 "cannot initialize PMD due to missing run-time dependency on"
1245 " rdma-core libraries (libibverbs, libmlx5)");
1252 * Driver initialization routine.
1254 RTE_INIT(rte_mlx5_pmd_init);
1256 rte_mlx5_pmd_init(void)
1258 /* Build the static tables for Verbs conversion. */
1259 mlx5_set_ptype_table();
1260 mlx5_set_cksum_table();
1261 mlx5_set_swp_types_table();
1263 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1264 * huge pages. Calling ibv_fork_init() during init allows
1265 * applications to use fork() safely for purposes other than
1266 * using this PMD, which is not supported in forked processes.
1268 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1269 /* Match the size of Rx completion entry to the size of a cacheline. */
1270 if (RTE_CACHE_LINE_SIZE == 128)
1271 setenv("MLX5_CQE_SIZE", "128", 0);
1272 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1273 if (mlx5_glue_init())
1278 /* Glue structure must not contain any NULL pointers. */
1282 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1283 assert(((const void *const *)mlx5_glue)[i]);
1286 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1288 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1289 mlx5_glue->version, MLX5_GLUE_VERSION);
1292 mlx5_glue->fork_init();
1293 rte_pci_register(&mlx5_driver);
1296 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1297 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1298 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1300 /** Initialize driver log type. */
1301 RTE_INIT(vdev_netvsc_init_log)
1303 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1304 if (mlx5_logtype >= 0)
1305 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);