1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
16 #include <rte_malloc.h>
17 #include <rte_ethdev_driver.h>
18 #include <rte_ethdev_pci.h>
20 #include <rte_bus_pci.h>
21 #include <rte_common.h>
22 #include <rte_kvargs.h>
23 #include <rte_rwlock.h>
24 #include <rte_spinlock.h>
25 #include <rte_string_fns.h>
26 #include <rte_alarm.h>
28 #include <mlx5_glue.h>
29 #include <mlx5_devx_cmds.h>
30 #include <mlx5_common.h>
31 #include <mlx5_common_os.h>
32 #include <mlx5_common_mp.h>
33 #include <mlx5_common_pci.h>
34 #include <mlx5_malloc.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_utils.h"
39 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "rte_pmd_mlx5.h"
45 /* Device parameter to enable RX completion queue compression. */
46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
48 /* Device parameter to enable RX completion entry padding to 128B. */
49 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
51 /* Device parameter to enable padding Rx packet to cacheline size. */
52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
54 /* Device parameter to enable Multi-Packet Rx queue. */
55 #define MLX5_RX_MPRQ_EN "mprq_en"
57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
69 /* Device parameter to configure inline send. Deprecated, ignored.*/
70 #define MLX5_TXQ_INLINE "txq_inline"
72 /* Device parameter to limit packet size to inline with ordinary SEND. */
73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
75 /* Device parameter to configure minimal data size to inline. */
76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
82 * Device parameter to configure the number of TX queues threshold for
83 * enabling inline send.
85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
88 * Device parameter to configure the number of TX queues threshold for
89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
93 /* Device parameter to enable multi-packet send WQEs. */
94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
97 * Device parameter to force doorbell register mapping
98 * to non-cahed region eliminating the extra write memory barrier.
100 #define MLX5_TX_DB_NC "tx_db_nc"
103 * Device parameter to include 2 dsegs in the title WQEBB.
104 * Deprecated, ignored.
106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
109 * Device parameter to limit the size of inlining packet.
110 * Deprecated, ignored.
112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
115 * Device parameter to enable Tx scheduling on timestamps
116 * and specify the packet pacing granularity in nanoseconds.
118 #define MLX5_TX_PP "tx_pp"
121 * Device parameter to specify skew in nanoseconds on Tx datapath,
122 * it represents the time between SQ start WQE processing and
123 * appearing actual packet data on the wire.
125 #define MLX5_TX_SKEW "tx_skew"
128 * Device parameter to enable hardware Tx vector.
129 * Deprecated, ignored (no vectorized Tx routines anymore).
131 #define MLX5_TX_VEC_EN "tx_vec_en"
133 /* Device parameter to enable hardware Rx vector. */
134 #define MLX5_RX_VEC_EN "rx_vec_en"
136 /* Allow L3 VXLAN flow creation. */
137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
139 /* Activate DV E-Switch flow steering. */
140 #define MLX5_DV_ESW_EN "dv_esw_en"
142 /* Activate DV flow steering. */
143 #define MLX5_DV_FLOW_EN "dv_flow_en"
145 /* Enable extensive flow metadata support. */
146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
148 /* Device parameter to let the user manage the lacp traffic of bonded device */
149 #define MLX5_LACP_BY_USER "lacp_by_user"
151 /* Activate Netlink support in VF mode. */
152 #define MLX5_VF_NL_EN "vf_nl_en"
154 /* Enable extending memsegs when creating a MR. */
155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
157 /* Select port representors to instantiate. */
158 #define MLX5_REPRESENTOR "representor"
160 /* Device parameter to configure the maximum number of dump files per queue. */
161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
163 /* Configure timeout of LRO session (in microseconds). */
164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
167 * Device parameter to configure the total data buffer size for a single
168 * hairpin queue (logarithm value).
170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
172 /* Flow memory reclaim mode. */
173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
175 /* The default memory allocator used in PMD. */
176 #define MLX5_SYS_MEM_EN "sys_mem_en"
177 /* Decap will be used or not. */
178 #define MLX5_DECAP_EN "decap_en"
180 /* Shared memory between primary and secondary processes. */
181 struct mlx5_shared_data *mlx5_shared_data;
183 /** Driver-specific log messages type. */
186 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
187 LIST_HEAD_INITIALIZER();
188 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
191 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
193 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
199 .malloc = mlx5_malloc,
201 .type = "mlx5_encap_decap_ipool",
204 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
210 .malloc = mlx5_malloc,
212 .type = "mlx5_push_vlan_ipool",
215 .size = sizeof(struct mlx5_flow_dv_tag_resource),
221 .malloc = mlx5_malloc,
223 .type = "mlx5_tag_ipool",
226 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
232 .malloc = mlx5_malloc,
234 .type = "mlx5_port_id_ipool",
237 .size = sizeof(struct mlx5_flow_tbl_data_entry),
243 .malloc = mlx5_malloc,
245 .type = "mlx5_jump_ipool",
249 .size = sizeof(struct mlx5_flow_meter),
255 .malloc = mlx5_malloc,
257 .type = "mlx5_meter_ipool",
260 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
266 .malloc = mlx5_malloc,
268 .type = "mlx5_mcp_ipool",
271 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
277 .malloc = mlx5_malloc,
279 .type = "mlx5_hrxq_ipool",
283 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
284 * It set in run time according to PCI function configuration.
292 .malloc = mlx5_malloc,
294 .type = "mlx5_flow_handle_ipool",
297 .size = sizeof(struct rte_flow),
301 .malloc = mlx5_malloc,
303 .type = "rte_flow_ipool",
308 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
309 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
311 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
314 * Allocate ID pool structure.
317 * The maximum id can be allocated from the pool.
320 * Pointer to pool object, NULL value otherwise.
322 struct mlx5_flow_id_pool *
323 mlx5_flow_id_pool_alloc(uint32_t max_id)
325 struct mlx5_flow_id_pool *pool;
328 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
329 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
331 DRV_LOG(ERR, "can't allocate id pool");
335 mem = mlx5_malloc(MLX5_MEM_ZERO,
336 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
337 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
339 DRV_LOG(ERR, "can't allocate mem for id pool");
343 pool->free_arr = mem;
344 pool->curr = pool->free_arr;
345 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
346 pool->base_index = 0;
347 pool->max_id = max_id;
355 * Release ID pool structure.
358 * Pointer to flow id pool object to free.
361 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
363 mlx5_free(pool->free_arr);
371 * Pointer to flow id pool.
376 * 0 on success, error value otherwise.
379 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
381 if (pool->curr == pool->free_arr) {
382 if (pool->base_index == pool->max_id) {
384 DRV_LOG(ERR, "no free id");
387 *id = ++pool->base_index;
390 *id = *(--pool->curr);
398 * Pointer to flow id pool.
403 * 0 on success, error value otherwise.
406 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
412 if (pool->curr == pool->last) {
413 size = pool->curr - pool->free_arr;
414 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
415 MLX5_ASSERT(size2 > size);
416 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
419 DRV_LOG(ERR, "can't allocate mem for id pool");
423 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
424 mlx5_free(pool->free_arr);
425 pool->free_arr = mem;
426 pool->curr = pool->free_arr + size;
427 pool->last = pool->free_arr + size2;
435 * Initialize the shared aging list information per port.
438 * Pointer to mlx5_dev_ctx_shared object.
441 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
444 struct mlx5_age_info *age_info;
446 for (i = 0; i < sh->max_port; i++) {
447 age_info = &sh->port[i].age_info;
449 TAILQ_INIT(&age_info->aged_counters);
450 rte_spinlock_init(&age_info->aged_sl);
451 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
456 * Initialize the counters management structure.
459 * Pointer to mlx5_dev_ctx_shared object to free
462 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
466 memset(&sh->cmng, 0, sizeof(sh->cmng));
467 TAILQ_INIT(&sh->cmng.flow_counters);
468 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
469 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
470 sh->cmng.ccont[i].max_id = -1;
471 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
472 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
473 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
474 TAILQ_INIT(&sh->cmng.ccont[i].counters);
475 rte_spinlock_init(&sh->cmng.ccont[i].csl);
480 * Destroy all the resources allocated for a counter memory management.
483 * Pointer to the memory management structure.
486 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
488 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
490 LIST_REMOVE(mng, next);
491 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
492 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
497 * Close and release all the resources of the counters management.
500 * Pointer to mlx5_dev_ctx_shared object to free.
503 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
505 struct mlx5_counter_stats_mem_mng *mng;
512 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
513 if (rte_errno != EINPROGRESS)
517 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
518 struct mlx5_flow_counter_pool *pool;
519 uint32_t batch = !!(i > 1);
521 if (!sh->cmng.ccont[i].pools)
523 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
525 if (batch && pool->min_dcs)
526 claim_zero(mlx5_devx_cmd_destroy
528 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
529 if (MLX5_POOL_GET_CNT(pool, j)->action)
531 (mlx5_glue->destroy_flow_action
534 if (!batch && MLX5_GET_POOL_CNT_EXT
536 claim_zero(mlx5_devx_cmd_destroy
537 (MLX5_GET_POOL_CNT_EXT
540 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
542 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
544 mlx5_free(sh->cmng.ccont[i].pools);
546 mng = LIST_FIRST(&sh->cmng.mem_mngs);
548 mlx5_flow_destroy_counter_stat_mem_mng(mng);
549 mng = LIST_FIRST(&sh->cmng.mem_mngs);
551 memset(&sh->cmng, 0, sizeof(sh->cmng));
555 * Initialize the flow resources' indexed mempool.
558 * Pointer to mlx5_dev_ctx_shared object.
560 * Pointer to user dev config.
563 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
564 const struct mlx5_dev_config *config)
567 struct mlx5_indexed_pool_config cfg;
569 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
570 cfg = mlx5_ipool_cfg[i];
575 * Set MLX5_IPOOL_MLX5_FLOW ipool size
576 * according to PCI function flow configuration.
578 case MLX5_IPOOL_MLX5_FLOW:
579 cfg.size = config->dv_flow_en ?
580 sizeof(struct mlx5_flow_handle) :
581 MLX5_FLOW_HANDLE_VERBS_SIZE;
584 if (config->reclaim_mode)
585 cfg.release_mem_en = 1;
586 sh->ipool[i] = mlx5_ipool_create(&cfg);
591 * Release the flow resources' indexed mempool.
594 * Pointer to mlx5_dev_ctx_shared object.
597 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
601 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
602 mlx5_ipool_destroy(sh->ipool[i]);
606 * Check if dynamic flex parser for eCPRI already exists.
609 * Pointer to Ethernet device structure.
612 * true on exists, false on not.
615 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
617 struct mlx5_priv *priv = dev->data->dev_private;
618 struct mlx5_flex_parser_profiles *prf =
619 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
625 * Allocation of a flex parser for eCPRI. Once created, this parser related
626 * resources will be held until the device is closed.
629 * Pointer to Ethernet device structure.
632 * 0 on success, a negative errno value otherwise and rte_errno is set.
635 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
637 struct mlx5_priv *priv = dev->data->dev_private;
638 struct mlx5_flex_parser_profiles *prf =
639 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
640 struct mlx5_devx_graph_node_attr node = {
641 .modify_field_select = 0,
646 if (!priv->config.hca_attr.parse_graph_flex_node) {
647 DRV_LOG(ERR, "Dynamic flex parser is not supported "
648 "for device %s.", priv->dev_data->name);
651 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
652 /* 8 bytes now: 4B common header + 4B message body header. */
653 node.header_length_base_value = 0x8;
654 /* After MAC layer: Ether / VLAN. */
655 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
656 /* Type of compared condition should be 0xAEFE in the L2 layer. */
657 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
658 /* Sample #0: type in common header. */
659 node.sample[0].flow_match_sample_en = 1;
661 node.sample[0].flow_match_sample_offset_mode = 0x0;
662 /* Only the 2nd byte will be used. */
663 node.sample[0].flow_match_sample_field_base_offset = 0x0;
664 /* Sample #1: message payload. */
665 node.sample[1].flow_match_sample_en = 1;
667 node.sample[1].flow_match_sample_offset_mode = 0x0;
669 * Only the first two bytes will be used right now, and its offset will
670 * start after the common header that with the length of a DW(u32).
672 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
673 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
675 DRV_LOG(ERR, "Failed to create flex parser node object.");
676 return (rte_errno == 0) ? -ENODEV : -rte_errno;
679 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
681 DRV_LOG(ERR, "Failed to query sample IDs.");
682 return (rte_errno == 0) ? -ENODEV : -rte_errno;
684 prf->offset[0] = 0x0;
685 prf->offset[1] = sizeof(uint32_t);
686 prf->ids[0] = ids[0];
687 prf->ids[1] = ids[1];
692 * Destroy the flex parser node, including the parser itself, input / output
693 * arcs and DW samples. Resources could be reused then.
696 * Pointer to Ethernet device structure.
699 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
701 struct mlx5_priv *priv = dev->data->dev_private;
702 struct mlx5_flex_parser_profiles *prf =
703 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
706 mlx5_devx_cmd_destroy(prf->obj);
711 * Allocate shared device context. If there is multiport device the
712 * master and representors will share this context, if there is single
713 * port dedicated device, the context will be used by only given
714 * port due to unification.
716 * Routine first searches the context for the specified device name,
717 * if found the shared context assumed and reference counter is incremented.
718 * If no context found the new one is created and initialized with specified
719 * device context and parameters.
722 * Pointer to the device attributes (name, port, etc).
724 * Pointer to device configuration structure.
727 * Pointer to mlx5_dev_ctx_shared object on success,
728 * otherwise NULL and rte_errno is set.
730 struct mlx5_dev_ctx_shared *
731 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
732 const struct mlx5_dev_config *config)
734 struct mlx5_dev_ctx_shared *sh;
737 struct mlx5_devx_tis_attr tis_attr = { 0 };
740 /* Secondary process should not create the shared context. */
741 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
742 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
743 /* Search for IB context by device name. */
744 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
745 if (!strcmp(sh->ibdev_name,
746 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
751 /* No device found, we have to create new shared context. */
752 MLX5_ASSERT(spawn->max_port);
753 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
754 sizeof(struct mlx5_dev_ctx_shared) +
756 sizeof(struct mlx5_dev_shared_port),
757 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
759 DRV_LOG(ERR, "shared context allocation failure");
763 err = mlx5_os_open_device(spawn, config, sh);
766 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
768 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
772 sh->max_port = spawn->max_port;
773 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
774 sizeof(sh->ibdev_name) - 1);
775 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
776 sizeof(sh->ibdev_path) - 1);
778 * Setting port_id to max unallowed value means
779 * there is no interrupt subhandler installed for
780 * the given port index i.
782 for (i = 0; i < sh->max_port; i++) {
783 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
784 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
786 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
787 if (sh->pd == NULL) {
788 DRV_LOG(ERR, "PD allocation failure");
793 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
795 DRV_LOG(ERR, "Fail to extract pdn from PD");
798 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
800 DRV_LOG(ERR, "TD allocation failure");
804 tis_attr.transport_domain = sh->td->id;
805 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
807 DRV_LOG(ERR, "TIS allocation failure");
811 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
813 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
817 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
818 if (!sh->devx_rx_uar) {
819 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR.");
824 sh->flow_id_pool = mlx5_flow_id_pool_alloc
825 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
826 if (!sh->flow_id_pool) {
827 DRV_LOG(ERR, "can't create flow id pool");
832 /* Initialize UAR access locks for 32bit implementations. */
833 rte_spinlock_init(&sh->uar_lock_cq);
834 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
835 rte_spinlock_init(&sh->uar_lock[i]);
838 * Once the device is added to the list of memory event
839 * callback, its global MR cache table cannot be expanded
840 * on the fly because of deadlock. If it overflows, lookup
841 * should be done by searching MR list linearly, which is slow.
843 * At this point the device is not added to the memory
844 * event list yet, context is just being created.
846 err = mlx5_mr_btree_init(&sh->share_cache.cache,
847 MLX5_MR_BTREE_CACHE_N * 2,
848 spawn->pci_dev->device.numa_node);
853 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
854 &sh->share_cache.dereg_mr_cb);
855 mlx5_os_dev_shared_handler_install(sh);
856 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
857 if (!sh->cnt_id_tbl) {
861 mlx5_flow_aging_init(sh);
862 mlx5_flow_counters_mng_init(sh);
863 mlx5_flow_ipool_create(sh, config);
864 /* Add device to memory callback list. */
865 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
866 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
868 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
869 /* Add context to the global device list. */
870 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
872 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
875 pthread_mutex_destroy(&sh->txpp.mutex);
876 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
878 if (sh->cnt_id_tbl) {
879 mlx5_l3t_destroy(sh->cnt_id_tbl);
880 sh->cnt_id_tbl = NULL;
883 mlx5_glue->devx_free_uar(sh->tx_uar);
887 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
889 claim_zero(mlx5_devx_cmd_destroy(sh->td));
891 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
893 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
895 claim_zero(mlx5_glue->close_device(sh->ctx));
896 if (sh->flow_id_pool)
897 mlx5_flow_id_pool_release(sh->flow_id_pool);
899 MLX5_ASSERT(err > 0);
905 * Free shared IB device context. Decrement counter and if zero free
906 * all allocated resources and close handles.
909 * Pointer to mlx5_dev_ctx_shared object to free
912 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
914 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
915 #ifdef RTE_LIBRTE_MLX5_DEBUG
916 /* Check the object presence in the list. */
917 struct mlx5_dev_ctx_shared *lctx;
919 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
924 DRV_LOG(ERR, "Freeing non-existing shared IB context");
929 MLX5_ASSERT(sh->refcnt);
930 /* Secondary process should not free the shared context. */
931 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
934 /* Remove from memory callback device list. */
935 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
936 LIST_REMOVE(sh, mem_event_cb);
937 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
938 /* Release created Memory Regions. */
939 mlx5_mr_release_cache(&sh->share_cache);
940 /* Remove context from the global device list. */
941 LIST_REMOVE(sh, next);
943 * Ensure there is no async event handler installed.
944 * Only primary process handles async device events.
946 mlx5_flow_counters_mng_close(sh);
947 mlx5_flow_ipool_destroy(sh);
948 mlx5_os_dev_shared_handler_uninstall(sh);
949 if (sh->cnt_id_tbl) {
950 mlx5_l3t_destroy(sh->cnt_id_tbl);
951 sh->cnt_id_tbl = NULL;
954 mlx5_glue->devx_free_uar(sh->tx_uar);
958 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
960 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
962 claim_zero(mlx5_devx_cmd_destroy(sh->td));
964 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
966 claim_zero(mlx5_glue->close_device(sh->ctx));
967 if (sh->flow_id_pool)
968 mlx5_flow_id_pool_release(sh->flow_id_pool);
969 pthread_mutex_destroy(&sh->txpp.mutex);
972 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
976 * Destroy table hash list and all the root entries per domain.
979 * Pointer to the private device data structure.
982 mlx5_free_table_hash_list(struct mlx5_priv *priv)
984 struct mlx5_dev_ctx_shared *sh = priv->sh;
985 struct mlx5_flow_tbl_data_entry *tbl_data;
986 union mlx5_flow_tbl_key table_key = {
994 struct mlx5_hlist_entry *pos;
998 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1000 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1002 MLX5_ASSERT(tbl_data);
1003 mlx5_hlist_remove(sh->flow_tbls, pos);
1004 mlx5_free(tbl_data);
1006 table_key.direction = 1;
1007 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1009 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1011 MLX5_ASSERT(tbl_data);
1012 mlx5_hlist_remove(sh->flow_tbls, pos);
1013 mlx5_free(tbl_data);
1015 table_key.direction = 0;
1016 table_key.domain = 1;
1017 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1019 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1021 MLX5_ASSERT(tbl_data);
1022 mlx5_hlist_remove(sh->flow_tbls, pos);
1023 mlx5_free(tbl_data);
1025 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1029 * Initialize flow table hash list and create the root tables entry
1033 * Pointer to the private device data structure.
1036 * Zero on success, positive error code otherwise.
1039 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1041 struct mlx5_dev_ctx_shared *sh = priv->sh;
1042 char s[MLX5_HLIST_NAMESIZE];
1046 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1047 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1048 if (!sh->flow_tbls) {
1049 DRV_LOG(ERR, "flow tables with hash creation failed.");
1053 #ifndef HAVE_MLX5DV_DR
1055 * In case we have not DR support, the zero tables should be created
1056 * because DV expect to see them even if they cannot be created by
1059 union mlx5_flow_tbl_key table_key = {
1067 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1068 sizeof(*tbl_data), 0,
1075 tbl_data->entry.key = table_key.v64;
1076 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1079 rte_atomic32_init(&tbl_data->tbl.refcnt);
1080 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1081 table_key.direction = 1;
1082 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1088 tbl_data->entry.key = table_key.v64;
1089 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1092 rte_atomic32_init(&tbl_data->tbl.refcnt);
1093 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1094 table_key.direction = 0;
1095 table_key.domain = 1;
1096 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1102 tbl_data->entry.key = table_key.v64;
1103 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1106 rte_atomic32_init(&tbl_data->tbl.refcnt);
1107 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1110 mlx5_free_table_hash_list(priv);
1111 #endif /* HAVE_MLX5DV_DR */
1116 * Retrieve integer value from environment variable.
1119 * Environment variable name.
1122 * Integer value, 0 if the variable is not set.
1125 mlx5_getenv_int(const char *name)
1127 const char *val = getenv(name);
1135 * DPDK callback to add udp tunnel port
1138 * A pointer to eth_dev
1139 * @param[in] udp_tunnel
1140 * A pointer to udp tunnel
1143 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1146 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1147 struct rte_eth_udp_tunnel *udp_tunnel)
1149 MLX5_ASSERT(udp_tunnel != NULL);
1150 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1151 udp_tunnel->udp_port == 4789)
1153 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1154 udp_tunnel->udp_port == 4790)
1160 * Initialize process private data structure.
1163 * Pointer to Ethernet device structure.
1166 * 0 on success, a negative errno value otherwise and rte_errno is set.
1169 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1171 struct mlx5_priv *priv = dev->data->dev_private;
1172 struct mlx5_proc_priv *ppriv;
1176 * UAR register table follows the process private structure. BlueFlame
1177 * registers for Tx queues are stored in the table.
1180 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1181 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1182 dev->device->numa_node);
1187 ppriv->uar_table_sz = ppriv_size;
1188 dev->process_private = ppriv;
1193 * Un-initialize process private data structure.
1196 * Pointer to Ethernet device structure.
1199 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1201 if (!dev->process_private)
1203 mlx5_free(dev->process_private);
1204 dev->process_private = NULL;
1208 * DPDK callback to close the device.
1210 * Destroy all queues and objects, free memory.
1213 * Pointer to Ethernet device structure.
1216 mlx5_dev_close(struct rte_eth_dev *dev)
1218 struct mlx5_priv *priv = dev->data->dev_private;
1222 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1223 /* Check if process_private released. */
1224 if (!dev->process_private)
1226 mlx5_tx_uar_uninit_secondary(dev);
1227 mlx5_proc_priv_uninit(dev);
1228 rte_eth_dev_release_port(dev);
1233 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1235 ((priv->sh->ctx != NULL) ?
1236 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1238 * If default mreg copy action is removed at the stop stage,
1239 * the search will return none and nothing will be done anymore.
1241 mlx5_flow_stop_default(dev);
1242 mlx5_traffic_disable(dev);
1244 * If all the flows are already flushed in the device stop stage,
1245 * then this will return directly without any action.
1247 mlx5_flow_list_flush(dev, &priv->flows, true);
1248 mlx5_flow_meter_flush(dev, NULL);
1249 /* Free the intermediate buffers for flow creation. */
1250 mlx5_flow_free_intermediate(dev);
1251 /* Prevent crashes when queues are still in use. */
1252 dev->rx_pkt_burst = removed_rx_burst;
1253 dev->tx_pkt_burst = removed_tx_burst;
1255 /* Disable datapath on secondary process. */
1256 mlx5_mp_os_req_stop_rxtx(dev);
1257 /* Free the eCPRI flex parser resource. */
1258 mlx5_flex_parser_ecpri_release(dev);
1259 if (priv->rxqs != NULL) {
1260 /* XXX race condition if mlx5_rx_burst() is still running. */
1262 for (i = 0; (i != priv->rxqs_n); ++i)
1263 mlx5_rxq_release(dev, i);
1267 if (priv->txqs != NULL) {
1268 /* XXX race condition if mlx5_tx_burst() is still running. */
1270 for (i = 0; (i != priv->txqs_n); ++i)
1271 mlx5_txq_release(dev, i);
1275 mlx5_proc_priv_uninit(dev);
1276 if (priv->mreg_cp_tbl)
1277 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1278 mlx5_mprq_free_mp(dev);
1279 mlx5_os_free_shared_dr(priv);
1280 if (priv->rss_conf.rss_key != NULL)
1281 mlx5_free(priv->rss_conf.rss_key);
1282 if (priv->reta_idx != NULL)
1283 mlx5_free(priv->reta_idx);
1284 if (priv->config.vf)
1285 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1286 dev->data->mac_addrs,
1287 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1288 if (priv->nl_socket_route >= 0)
1289 close(priv->nl_socket_route);
1290 if (priv->nl_socket_rdma >= 0)
1291 close(priv->nl_socket_rdma);
1292 if (priv->vmwa_context)
1293 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1294 ret = mlx5_hrxq_verify(dev);
1296 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1297 dev->data->port_id);
1298 ret = mlx5_ind_table_obj_verify(dev);
1300 DRV_LOG(WARNING, "port %u some indirection table still remain",
1301 dev->data->port_id);
1302 ret = mlx5_rxq_obj_verify(dev);
1304 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1305 dev->data->port_id);
1306 ret = mlx5_rxq_verify(dev);
1308 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1309 dev->data->port_id);
1310 ret = mlx5_txq_obj_verify(dev);
1312 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1313 dev->data->port_id);
1314 ret = mlx5_txq_verify(dev);
1316 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1317 dev->data->port_id);
1318 ret = mlx5_flow_verify(dev);
1320 DRV_LOG(WARNING, "port %u some flows still remain",
1321 dev->data->port_id);
1323 * Free the shared context in last turn, because the cleanup
1324 * routines above may use some shared fields, like
1325 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1326 * ifindex if Netlink fails.
1328 mlx5_free_shared_dev_ctx(priv->sh);
1329 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1333 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1334 struct mlx5_priv *opriv =
1335 rte_eth_devices[port_id].data->dev_private;
1338 opriv->domain_id != priv->domain_id ||
1339 &rte_eth_devices[port_id] == dev)
1345 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1347 memset(priv, 0, sizeof(*priv));
1348 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1350 * Reset mac_addrs to NULL such that it is not freed as part of
1351 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1352 * it is freed when dev_private is freed.
1354 dev->data->mac_addrs = NULL;
1358 * Verify and store value for device argument.
1361 * Key argument to verify.
1363 * Value associated with key.
1368 * 0 on success, a negative errno value otherwise and rte_errno is set.
1371 mlx5_args_check(const char *key, const char *val, void *opaque)
1373 struct mlx5_dev_config *config = opaque;
1377 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1378 if (!strcmp(MLX5_REPRESENTOR, key))
1381 tmp = strtol(val, NULL, 0);
1384 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1387 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1388 /* Negative values are acceptable for some keys only. */
1390 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1393 mod = tmp >= 0 ? tmp : -tmp;
1394 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1395 config->cqe_comp = !!tmp;
1396 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1397 config->cqe_pad = !!tmp;
1398 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1399 config->hw_padding = !!tmp;
1400 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1401 config->mprq.enabled = !!tmp;
1402 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1403 config->mprq.stride_num_n = tmp;
1404 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1405 config->mprq.stride_size_n = tmp;
1406 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1407 config->mprq.max_memcpy_len = tmp;
1408 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1409 config->mprq.min_rxqs_num = tmp;
1410 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1411 DRV_LOG(WARNING, "%s: deprecated parameter,"
1412 " converted to txq_inline_max", key);
1413 config->txq_inline_max = tmp;
1414 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1415 config->txq_inline_max = tmp;
1416 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1417 config->txq_inline_min = tmp;
1418 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1419 config->txq_inline_mpw = tmp;
1420 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1421 config->txqs_inline = tmp;
1422 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1423 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1424 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1425 config->mps = !!tmp;
1426 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1427 if (tmp != MLX5_TXDB_CACHED &&
1428 tmp != MLX5_TXDB_NCACHED &&
1429 tmp != MLX5_TXDB_HEURISTIC) {
1430 DRV_LOG(ERR, "invalid Tx doorbell "
1431 "mapping parameter");
1436 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1437 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1438 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1439 DRV_LOG(WARNING, "%s: deprecated parameter,"
1440 " converted to txq_inline_mpw", key);
1441 config->txq_inline_mpw = tmp;
1442 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1443 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1444 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1446 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1450 config->tx_pp = tmp;
1451 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1452 config->tx_skew = tmp;
1453 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1454 config->rx_vec_en = !!tmp;
1455 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1456 config->l3_vxlan_en = !!tmp;
1457 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1458 config->vf_nl_en = !!tmp;
1459 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1460 config->dv_esw_en = !!tmp;
1461 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1462 config->dv_flow_en = !!tmp;
1463 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1464 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1465 tmp != MLX5_XMETA_MODE_META16 &&
1466 tmp != MLX5_XMETA_MODE_META32) {
1467 DRV_LOG(ERR, "invalid extensive "
1468 "metadata parameter");
1472 config->dv_xmeta_en = tmp;
1473 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1474 config->lacp_by_user = !!tmp;
1475 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1476 config->mr_ext_memseg_en = !!tmp;
1477 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1478 config->max_dump_files_num = tmp;
1479 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1480 config->lro.timeout = tmp;
1481 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1482 DRV_LOG(DEBUG, "class argument is %s.", val);
1483 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1484 config->log_hp_size = tmp;
1485 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1486 if (tmp != MLX5_RCM_NONE &&
1487 tmp != MLX5_RCM_LIGHT &&
1488 tmp != MLX5_RCM_AGGR) {
1489 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1493 config->reclaim_mode = tmp;
1494 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1495 config->sys_mem_en = !!tmp;
1496 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1497 config->decap_en = !!tmp;
1499 DRV_LOG(WARNING, "%s: unknown parameter", key);
1507 * Parse device parameters.
1510 * Pointer to device configuration structure.
1512 * Device arguments structure.
1515 * 0 on success, a negative errno value otherwise and rte_errno is set.
1518 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1520 const char **params = (const char *[]){
1521 MLX5_RXQ_CQE_COMP_EN,
1522 MLX5_RXQ_CQE_PAD_EN,
1523 MLX5_RXQ_PKT_PAD_EN,
1525 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1526 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1527 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1530 MLX5_TXQ_INLINE_MIN,
1531 MLX5_TXQ_INLINE_MAX,
1532 MLX5_TXQ_INLINE_MPW,
1533 MLX5_TXQS_MIN_INLINE,
1536 MLX5_TXQ_MPW_HDR_DSEG_EN,
1537 MLX5_TXQ_MAX_INLINE_LEN,
1549 MLX5_MR_EXT_MEMSEG_EN,
1551 MLX5_MAX_DUMP_FILES_NUM,
1552 MLX5_LRO_TIMEOUT_USEC,
1553 MLX5_CLASS_ARG_NAME,
1560 struct rte_kvargs *kvlist;
1564 if (devargs == NULL)
1566 /* Following UGLY cast is done to pass checkpatch. */
1567 kvlist = rte_kvargs_parse(devargs->args, params);
1568 if (kvlist == NULL) {
1572 /* Process parameters. */
1573 for (i = 0; (params[i] != NULL); ++i) {
1574 if (rte_kvargs_count(kvlist, params[i])) {
1575 ret = rte_kvargs_process(kvlist, params[i],
1576 mlx5_args_check, config);
1579 rte_kvargs_free(kvlist);
1584 rte_kvargs_free(kvlist);
1589 * Configures the minimal amount of data to inline into WQE
1590 * while sending packets.
1592 * - the txq_inline_min has the maximal priority, if this
1593 * key is specified in devargs
1594 * - if DevX is enabled the inline mode is queried from the
1595 * device (HCA attributes and NIC vport context if needed).
1596 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1597 * and none (0 bytes) for other NICs
1600 * Verbs device parameters (name, port, switch_info) to spawn.
1602 * Device configuration parameters.
1605 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1606 struct mlx5_dev_config *config)
1608 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1609 /* Application defines size of inlined data explicitly. */
1610 switch (spawn->pci_dev->id.device_id) {
1611 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1612 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1613 if (config->txq_inline_min <
1614 (int)MLX5_INLINE_HSIZE_L2) {
1616 "txq_inline_mix aligned to minimal"
1617 " ConnectX-4 required value %d",
1618 (int)MLX5_INLINE_HSIZE_L2);
1619 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1625 if (config->hca_attr.eth_net_offloads) {
1626 /* We have DevX enabled, inline mode queried successfully. */
1627 switch (config->hca_attr.wqe_inline_mode) {
1628 case MLX5_CAP_INLINE_MODE_L2:
1629 /* outer L2 header must be inlined. */
1630 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1632 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1633 /* No inline data are required by NIC. */
1634 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1635 config->hw_vlan_insert =
1636 config->hca_attr.wqe_vlan_insert;
1637 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1639 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1640 /* inline mode is defined by NIC vport context. */
1641 if (!config->hca_attr.eth_virt)
1643 switch (config->hca_attr.vport_inline_mode) {
1644 case MLX5_INLINE_MODE_NONE:
1645 config->txq_inline_min =
1646 MLX5_INLINE_HSIZE_NONE;
1648 case MLX5_INLINE_MODE_L2:
1649 config->txq_inline_min =
1650 MLX5_INLINE_HSIZE_L2;
1652 case MLX5_INLINE_MODE_IP:
1653 config->txq_inline_min =
1654 MLX5_INLINE_HSIZE_L3;
1656 case MLX5_INLINE_MODE_TCP_UDP:
1657 config->txq_inline_min =
1658 MLX5_INLINE_HSIZE_L4;
1660 case MLX5_INLINE_MODE_INNER_L2:
1661 config->txq_inline_min =
1662 MLX5_INLINE_HSIZE_INNER_L2;
1664 case MLX5_INLINE_MODE_INNER_IP:
1665 config->txq_inline_min =
1666 MLX5_INLINE_HSIZE_INNER_L3;
1668 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1669 config->txq_inline_min =
1670 MLX5_INLINE_HSIZE_INNER_L4;
1676 * We get here if we are unable to deduce
1677 * inline data size with DevX. Try PCI ID
1678 * to determine old NICs.
1680 switch (spawn->pci_dev->id.device_id) {
1681 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1682 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1683 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1684 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1685 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1686 config->hw_vlan_insert = 0;
1688 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1689 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1690 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1691 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1693 * These NICs support VLAN insertion from WQE and
1694 * report the wqe_vlan_insert flag. But there is the bug
1695 * and PFC control may be broken, so disable feature.
1697 config->hw_vlan_insert = 0;
1698 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1701 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1705 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1709 * Configures the metadata mask fields in the shared context.
1712 * Pointer to Ethernet device.
1715 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1717 struct mlx5_priv *priv = dev->data->dev_private;
1718 struct mlx5_dev_ctx_shared *sh = priv->sh;
1719 uint32_t meta, mark, reg_c0;
1721 reg_c0 = ~priv->vport_meta_mask;
1722 switch (priv->config.dv_xmeta_en) {
1723 case MLX5_XMETA_MODE_LEGACY:
1725 mark = MLX5_FLOW_MARK_MASK;
1727 case MLX5_XMETA_MODE_META16:
1728 meta = reg_c0 >> rte_bsf32(reg_c0);
1729 mark = MLX5_FLOW_MARK_MASK;
1731 case MLX5_XMETA_MODE_META32:
1733 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1741 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1742 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1743 sh->dv_mark_mask, mark);
1745 sh->dv_mark_mask = mark;
1746 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1747 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1748 sh->dv_meta_mask, meta);
1750 sh->dv_meta_mask = meta;
1751 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1752 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1753 sh->dv_meta_mask, reg_c0);
1755 sh->dv_regc0_mask = reg_c0;
1756 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1757 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1758 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1759 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1763 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1765 static const char *const dynf_names[] = {
1766 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1767 RTE_MBUF_DYNFLAG_METADATA_NAME,
1768 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1772 if (n < RTE_DIM(dynf_names))
1774 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1775 if (names[i] == NULL)
1777 strcpy(names[i], dynf_names[i]);
1779 return RTE_DIM(dynf_names);
1783 * Comparison callback to sort device data.
1785 * This is meant to be used with qsort().
1788 * Pointer to pointer to first data object.
1790 * Pointer to pointer to second data object.
1793 * 0 if both objects are equal, less than 0 if the first argument is less
1794 * than the second, greater than 0 otherwise.
1797 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1798 struct mlx5_dev_config *config)
1800 struct mlx5_dev_ctx_shared *sh = priv->sh;
1801 struct mlx5_dev_config *sh_conf = NULL;
1805 /* Nothing to compare for the single/first device. */
1806 if (sh->refcnt == 1)
1808 /* Find the device with shared context. */
1809 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1810 struct mlx5_priv *opriv =
1811 rte_eth_devices[port_id].data->dev_private;
1813 if (opriv && opriv != priv && opriv->sh == sh) {
1814 sh_conf = &opriv->config;
1820 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1821 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1822 " for shared %s context", sh->ibdev_name);
1826 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1827 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1828 " for shared %s context", sh->ibdev_name);
1836 * Look for the ethernet device belonging to mlx5 driver.
1838 * @param[in] port_id
1839 * port_id to start looking for device.
1840 * @param[in] pci_dev
1841 * Pointer to the hint PCI device. When device is being probed
1842 * the its siblings (master and preceding representors might
1843 * not have assigned driver yet (because the mlx5_os_pci_probe()
1844 * is not completed yet, for this case match on hint PCI
1845 * device may be used to detect sibling device.
1848 * port_id of found device, RTE_MAX_ETHPORT if not found.
1851 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1853 while (port_id < RTE_MAX_ETHPORTS) {
1854 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1856 if (dev->state != RTE_ETH_DEV_UNUSED &&
1858 (dev->device == &pci_dev->device ||
1859 (dev->device->driver &&
1860 dev->device->driver->name &&
1861 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1865 if (port_id >= RTE_MAX_ETHPORTS)
1866 return RTE_MAX_ETHPORTS;
1871 * DPDK callback to remove a PCI device.
1873 * This function removes all Ethernet devices belong to a given PCI device.
1875 * @param[in] pci_dev
1876 * Pointer to the PCI device.
1879 * 0 on success, the function cannot fail.
1882 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1886 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1888 * mlx5_dev_close() is not registered to secondary process,
1889 * call the close function explicitly for secondary process.
1891 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1892 mlx5_dev_close(&rte_eth_devices[port_id]);
1894 rte_eth_dev_close(port_id);
1899 static const struct rte_pci_id mlx5_pci_id_map[] = {
1901 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1902 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1905 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1906 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1909 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1910 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1913 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1914 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1917 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1918 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1921 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1922 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1925 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1926 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1929 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1930 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1933 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1934 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1937 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1938 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1941 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1942 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1945 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1946 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1949 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1950 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1953 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1954 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1957 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1958 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1961 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1962 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1969 static struct mlx5_pci_driver mlx5_driver = {
1970 .driver_class = MLX5_CLASS_NET,
1973 .name = MLX5_DRIVER_NAME,
1975 .id_table = mlx5_pci_id_map,
1976 .probe = mlx5_os_pci_probe,
1977 .remove = mlx5_pci_remove,
1978 .dma_map = mlx5_dma_map,
1979 .dma_unmap = mlx5_dma_unmap,
1980 .drv_flags = PCI_DRV_FLAGS,
1984 /* Initialize driver log type. */
1985 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1988 * Driver initialization routine.
1990 RTE_INIT(rte_mlx5_pmd_init)
1993 /* Build the static tables for Verbs conversion. */
1994 mlx5_set_ptype_table();
1995 mlx5_set_cksum_table();
1996 mlx5_set_swp_types_table();
1998 mlx5_pci_driver_register(&mlx5_driver);
2001 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2002 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2003 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");