1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
37 #include <rte_rwlock.h>
38 #include <rte_spinlock.h>
39 #include <rte_string_fns.h>
42 #include "mlx5_utils.h"
43 #include "mlx5_rxtx.h"
44 #include "mlx5_autoconf.h"
45 #include "mlx5_defs.h"
46 #include "mlx5_glue.h"
48 #include "mlx5_flow.h"
50 /* Device parameter to enable RX completion queue compression. */
51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
53 /* Device parameter to enable RX completion entry padding to 128B. */
54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
56 /* Device parameter to enable padding Rx packet to cacheline size. */
57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
59 /* Device parameter to enable Multi-Packet Rx queue. */
60 #define MLX5_RX_MPRQ_EN "mprq_en"
62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
71 /* Device parameter to configure inline send. */
72 #define MLX5_TXQ_INLINE "txq_inline"
75 * Device parameter to configure the number of TX queues threshold for
76 * enabling inline send.
78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
81 * Device parameter to configure the number of TX queues threshold for
82 * enabling vectorized Tx.
84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
86 /* Device parameter to enable multi-packet send WQEs. */
87 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
89 /* Device parameter to include 2 dsegs in the title WQEBB. */
90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
92 /* Device parameter to limit the size of inlining packet. */
93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
95 /* Device parameter to enable hardware Tx vector. */
96 #define MLX5_TX_VEC_EN "tx_vec_en"
98 /* Device parameter to enable hardware Rx vector. */
99 #define MLX5_RX_VEC_EN "rx_vec_en"
101 /* Allow L3 VXLAN flow creation. */
102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
104 /* Activate DV flow steering. */
105 #define MLX5_DV_FLOW_EN "dv_flow_en"
107 /* Activate Netlink support in VF mode. */
108 #define MLX5_VF_NL_EN "vf_nl_en"
110 /* Select port representors to instantiate. */
111 #define MLX5_REPRESENTOR "representor"
113 #ifndef HAVE_IBV_MLX5_MOD_MPW
114 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
115 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
118 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
119 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
122 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
124 /* Shared memory between primary and secondary processes. */
125 struct mlx5_shared_data *mlx5_shared_data;
127 /* Spinlock for mlx5_shared_data allocation. */
128 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
130 /* Process local data for secondary processes. */
131 static struct mlx5_local_data mlx5_local_data;
133 /** Driver-specific log messages type. */
136 /** Data associated with devices to spawn. */
137 struct mlx5_dev_spawn_data {
138 uint32_t ifindex; /**< Network interface index. */
139 uint32_t max_port; /**< IB device maximal port index. */
140 uint32_t ibv_port; /**< IB device physical port index. */
141 struct mlx5_switch_info info; /**< Switch information. */
142 struct ibv_device *ibv_dev; /**< Associated IB device. */
143 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
146 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
147 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
150 * Allocate shared IB device context. If there is multiport device the
151 * master and representors will share this context, if there is single
152 * port dedicated IB device, the context will be used by only given
153 * port due to unification.
155 * Routine first searches the context for the spesified IB device name,
156 * if found the shared context assumed and reference counter is incremented.
157 * If no context found the new one is created and initialized with specified
158 * IB device context and parameters.
161 * Pointer to the IB device attributes (name, port, etc).
164 * Pointer to mlx5_ibv_shared object on success,
165 * otherwise NULL and rte_errno is set.
167 static struct mlx5_ibv_shared *
168 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn)
170 struct mlx5_ibv_shared *sh;
175 /* Secondary process should not create the shared context. */
176 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
177 pthread_mutex_lock(&mlx5_ibv_list_mutex);
178 /* Search for IB context by device name. */
179 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
180 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
185 /* No device found, we have to create new sharted context. */
186 assert(spawn->max_port);
187 sh = rte_zmalloc("ethdev shared ib context",
188 sizeof(struct mlx5_ibv_shared) +
190 sizeof(struct mlx5_ibv_shared_port),
191 RTE_CACHE_LINE_SIZE);
193 DRV_LOG(ERR, "shared context allocation failure");
197 /* Try to open IB device with DV first, then usual Verbs. */
199 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
202 DRV_LOG(DEBUG, "DevX is supported");
204 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
206 err = errno ? errno : ENODEV;
209 DRV_LOG(DEBUG, "DevX is NOT supported");
211 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
213 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
217 sh->max_port = spawn->max_port;
218 strncpy(sh->ibdev_name, sh->ctx->device->name,
219 sizeof(sh->ibdev_name));
220 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
221 sizeof(sh->ibdev_path));
222 pthread_mutex_init(&sh->intr_mutex, NULL);
224 * Setting port_id to max unallowed value means
225 * there is no interrupt subhandler installed for
226 * the given port index i.
228 for (i = 0; i < sh->max_port; i++)
229 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
230 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
231 if (sh->pd == NULL) {
232 DRV_LOG(ERR, "PD allocation failure");
236 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
238 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
241 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
244 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
246 claim_zero(mlx5_glue->close_device(sh->ctx));
254 * Free shared IB device context. Decrement counter and if zero free
255 * all allocated resources and close handles.
258 * Pointer to mlx5_ibv_shared object to free
261 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
263 pthread_mutex_lock(&mlx5_ibv_list_mutex);
265 /* Check the object presence in the list. */
266 struct mlx5_ibv_shared *lctx;
268 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
273 DRV_LOG(ERR, "Freeing non-existing shared IB context");
279 /* Secondary process should not free the shared context. */
280 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
283 LIST_REMOVE(sh, next);
285 * Ensure there is no async event handler installed.
286 * Only primary process handles async device events.
288 assert(!sh->intr_cnt);
290 rte_intr_callback_unregister
291 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
292 pthread_mutex_destroy(&sh->intr_mutex);
294 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
296 claim_zero(mlx5_glue->close_device(sh->ctx));
299 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
303 * Initialize shared data between primary and secondary process.
305 * A memzone is reserved by primary process and secondary processes attach to
309 * 0 on success, a negative errno value otherwise and rte_errno is set.
312 mlx5_init_shared_data(void)
314 const struct rte_memzone *mz;
317 rte_spinlock_lock(&mlx5_shared_data_lock);
318 if (mlx5_shared_data == NULL) {
319 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
320 /* Allocate shared memory. */
321 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
322 sizeof(*mlx5_shared_data),
326 "Cannot allocate mlx5 shared data\n");
330 mlx5_shared_data = mz->addr;
331 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
332 rte_spinlock_init(&mlx5_shared_data->lock);
334 /* Lookup allocated shared memory. */
335 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
338 "Cannot attach mlx5 shared data\n");
342 mlx5_shared_data = mz->addr;
343 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
347 rte_spinlock_unlock(&mlx5_shared_data_lock);
352 * Uninitialize shared data between primary and secondary process.
354 * The pointer of secondary process is dereferenced and primary process frees
358 mlx5_uninit_shared_data(void)
360 const struct rte_memzone *mz;
362 rte_spinlock_lock(&mlx5_shared_data_lock);
363 if (mlx5_shared_data) {
364 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
365 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
366 rte_memzone_free(mz);
368 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
370 mlx5_shared_data = NULL;
372 rte_spinlock_unlock(&mlx5_shared_data_lock);
376 * Retrieve integer value from environment variable.
379 * Environment variable name.
382 * Integer value, 0 if the variable is not set.
385 mlx5_getenv_int(const char *name)
387 const char *val = getenv(name);
395 * Verbs callback to allocate a memory. This function should allocate the space
396 * according to the size provided residing inside a huge page.
397 * Please note that all allocation must respect the alignment from libmlx5
398 * (i.e. currently sysconf(_SC_PAGESIZE)).
401 * The size in bytes of the memory to allocate.
403 * A pointer to the callback data.
406 * Allocated buffer, NULL otherwise and rte_errno is set.
409 mlx5_alloc_verbs_buf(size_t size, void *data)
411 struct mlx5_priv *priv = data;
413 size_t alignment = sysconf(_SC_PAGESIZE);
414 unsigned int socket = SOCKET_ID_ANY;
416 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
417 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
419 socket = ctrl->socket;
420 } else if (priv->verbs_alloc_ctx.type ==
421 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
422 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
424 socket = ctrl->socket;
426 assert(data != NULL);
427 ret = rte_malloc_socket(__func__, size, alignment, socket);
434 * Verbs callback to free a memory.
437 * A pointer to the memory to free.
439 * A pointer to the callback data.
442 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
444 assert(data != NULL);
449 * DPDK callback to close the device.
451 * Destroy all queues and objects, free memory.
454 * Pointer to Ethernet device structure.
457 mlx5_dev_close(struct rte_eth_dev *dev)
459 struct mlx5_priv *priv = dev->data->dev_private;
463 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
465 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
466 /* In case mlx5_dev_stop() has not been called. */
467 mlx5_dev_interrupt_handler_uninstall(dev);
468 mlx5_traffic_disable(dev);
469 mlx5_flow_flush(dev, NULL);
470 /* Prevent crashes when queues are still in use. */
471 dev->rx_pkt_burst = removed_rx_burst;
472 dev->tx_pkt_burst = removed_tx_burst;
474 /* Disable datapath on secondary process. */
475 mlx5_mp_req_stop_rxtx(dev);
476 if (priv->rxqs != NULL) {
477 /* XXX race condition if mlx5_rx_burst() is still running. */
479 for (i = 0; (i != priv->rxqs_n); ++i)
480 mlx5_rxq_release(dev, i);
484 if (priv->txqs != NULL) {
485 /* XXX race condition if mlx5_tx_burst() is still running. */
487 for (i = 0; (i != priv->txqs_n); ++i)
488 mlx5_txq_release(dev, i);
492 mlx5_mprq_free_mp(dev);
493 mlx5_mr_release(dev);
496 mlx5_free_shared_ibctx(priv->sh);
498 if (priv->rss_conf.rss_key != NULL)
499 rte_free(priv->rss_conf.rss_key);
500 if (priv->reta_idx != NULL)
501 rte_free(priv->reta_idx);
503 mlx5_nl_mac_addr_flush(dev);
504 if (priv->nl_socket_route >= 0)
505 close(priv->nl_socket_route);
506 if (priv->nl_socket_rdma >= 0)
507 close(priv->nl_socket_rdma);
508 if (priv->tcf_context)
509 mlx5_flow_tcf_context_destroy(priv->tcf_context);
510 ret = mlx5_hrxq_ibv_verify(dev);
512 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
514 ret = mlx5_ind_table_ibv_verify(dev);
516 DRV_LOG(WARNING, "port %u some indirection table still remain",
518 ret = mlx5_rxq_ibv_verify(dev);
520 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
522 ret = mlx5_rxq_verify(dev);
524 DRV_LOG(WARNING, "port %u some Rx queues still remain",
526 ret = mlx5_txq_ibv_verify(dev);
528 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
530 ret = mlx5_txq_verify(dev);
532 DRV_LOG(WARNING, "port %u some Tx queues still remain",
534 ret = mlx5_flow_verify(dev);
536 DRV_LOG(WARNING, "port %u some flows still remain",
538 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
540 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
543 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
545 struct mlx5_priv *opriv =
546 rte_eth_devices[port_id[i]].data->dev_private;
549 opriv->domain_id != priv->domain_id ||
550 &rte_eth_devices[port_id[i]] == dev)
555 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
557 memset(priv, 0, sizeof(*priv));
558 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
560 * Reset mac_addrs to NULL such that it is not freed as part of
561 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
562 * it is freed when dev_private is freed.
564 dev->data->mac_addrs = NULL;
567 const struct eth_dev_ops mlx5_dev_ops = {
568 .dev_configure = mlx5_dev_configure,
569 .dev_start = mlx5_dev_start,
570 .dev_stop = mlx5_dev_stop,
571 .dev_set_link_down = mlx5_set_link_down,
572 .dev_set_link_up = mlx5_set_link_up,
573 .dev_close = mlx5_dev_close,
574 .promiscuous_enable = mlx5_promiscuous_enable,
575 .promiscuous_disable = mlx5_promiscuous_disable,
576 .allmulticast_enable = mlx5_allmulticast_enable,
577 .allmulticast_disable = mlx5_allmulticast_disable,
578 .link_update = mlx5_link_update,
579 .stats_get = mlx5_stats_get,
580 .stats_reset = mlx5_stats_reset,
581 .xstats_get = mlx5_xstats_get,
582 .xstats_reset = mlx5_xstats_reset,
583 .xstats_get_names = mlx5_xstats_get_names,
584 .fw_version_get = mlx5_fw_version_get,
585 .dev_infos_get = mlx5_dev_infos_get,
586 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
587 .vlan_filter_set = mlx5_vlan_filter_set,
588 .rx_queue_setup = mlx5_rx_queue_setup,
589 .tx_queue_setup = mlx5_tx_queue_setup,
590 .rx_queue_release = mlx5_rx_queue_release,
591 .tx_queue_release = mlx5_tx_queue_release,
592 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
593 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
594 .mac_addr_remove = mlx5_mac_addr_remove,
595 .mac_addr_add = mlx5_mac_addr_add,
596 .mac_addr_set = mlx5_mac_addr_set,
597 .set_mc_addr_list = mlx5_set_mc_addr_list,
598 .mtu_set = mlx5_dev_set_mtu,
599 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
600 .vlan_offload_set = mlx5_vlan_offload_set,
601 .reta_update = mlx5_dev_rss_reta_update,
602 .reta_query = mlx5_dev_rss_reta_query,
603 .rss_hash_update = mlx5_rss_hash_update,
604 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
605 .filter_ctrl = mlx5_dev_filter_ctrl,
606 .rx_descriptor_status = mlx5_rx_descriptor_status,
607 .tx_descriptor_status = mlx5_tx_descriptor_status,
608 .rx_queue_count = mlx5_rx_queue_count,
609 .rx_queue_intr_enable = mlx5_rx_intr_enable,
610 .rx_queue_intr_disable = mlx5_rx_intr_disable,
611 .is_removed = mlx5_is_removed,
614 /* Available operations from secondary process. */
615 static const struct eth_dev_ops mlx5_dev_sec_ops = {
616 .stats_get = mlx5_stats_get,
617 .stats_reset = mlx5_stats_reset,
618 .xstats_get = mlx5_xstats_get,
619 .xstats_reset = mlx5_xstats_reset,
620 .xstats_get_names = mlx5_xstats_get_names,
621 .fw_version_get = mlx5_fw_version_get,
622 .dev_infos_get = mlx5_dev_infos_get,
623 .rx_descriptor_status = mlx5_rx_descriptor_status,
624 .tx_descriptor_status = mlx5_tx_descriptor_status,
627 /* Available operations in flow isolated mode. */
628 const struct eth_dev_ops mlx5_dev_ops_isolate = {
629 .dev_configure = mlx5_dev_configure,
630 .dev_start = mlx5_dev_start,
631 .dev_stop = mlx5_dev_stop,
632 .dev_set_link_down = mlx5_set_link_down,
633 .dev_set_link_up = mlx5_set_link_up,
634 .dev_close = mlx5_dev_close,
635 .promiscuous_enable = mlx5_promiscuous_enable,
636 .promiscuous_disable = mlx5_promiscuous_disable,
637 .allmulticast_enable = mlx5_allmulticast_enable,
638 .allmulticast_disable = mlx5_allmulticast_disable,
639 .link_update = mlx5_link_update,
640 .stats_get = mlx5_stats_get,
641 .stats_reset = mlx5_stats_reset,
642 .xstats_get = mlx5_xstats_get,
643 .xstats_reset = mlx5_xstats_reset,
644 .xstats_get_names = mlx5_xstats_get_names,
645 .fw_version_get = mlx5_fw_version_get,
646 .dev_infos_get = mlx5_dev_infos_get,
647 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
648 .vlan_filter_set = mlx5_vlan_filter_set,
649 .rx_queue_setup = mlx5_rx_queue_setup,
650 .tx_queue_setup = mlx5_tx_queue_setup,
651 .rx_queue_release = mlx5_rx_queue_release,
652 .tx_queue_release = mlx5_tx_queue_release,
653 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
654 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
655 .mac_addr_remove = mlx5_mac_addr_remove,
656 .mac_addr_add = mlx5_mac_addr_add,
657 .mac_addr_set = mlx5_mac_addr_set,
658 .set_mc_addr_list = mlx5_set_mc_addr_list,
659 .mtu_set = mlx5_dev_set_mtu,
660 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
661 .vlan_offload_set = mlx5_vlan_offload_set,
662 .filter_ctrl = mlx5_dev_filter_ctrl,
663 .rx_descriptor_status = mlx5_rx_descriptor_status,
664 .tx_descriptor_status = mlx5_tx_descriptor_status,
665 .rx_queue_intr_enable = mlx5_rx_intr_enable,
666 .rx_queue_intr_disable = mlx5_rx_intr_disable,
667 .is_removed = mlx5_is_removed,
671 * Verify and store value for device argument.
674 * Key argument to verify.
676 * Value associated with key.
681 * 0 on success, a negative errno value otherwise and rte_errno is set.
684 mlx5_args_check(const char *key, const char *val, void *opaque)
686 struct mlx5_dev_config *config = opaque;
689 /* No-op, port representors are processed in mlx5_dev_spawn(). */
690 if (!strcmp(MLX5_REPRESENTOR, key))
693 tmp = strtoul(val, NULL, 0);
696 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
699 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
700 config->cqe_comp = !!tmp;
701 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
702 config->cqe_pad = !!tmp;
703 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
704 config->hw_padding = !!tmp;
705 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
706 config->mprq.enabled = !!tmp;
707 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
708 config->mprq.stride_num_n = tmp;
709 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
710 config->mprq.max_memcpy_len = tmp;
711 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
712 config->mprq.min_rxqs_num = tmp;
713 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
714 config->txq_inline = tmp;
715 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
716 config->txqs_inline = tmp;
717 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
718 config->txqs_vec = tmp;
719 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
721 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
722 config->mpw_hdr_dseg = !!tmp;
723 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
724 config->inline_max_packet_sz = tmp;
725 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
726 config->tx_vec_en = !!tmp;
727 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
728 config->rx_vec_en = !!tmp;
729 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
730 config->l3_vxlan_en = !!tmp;
731 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
732 config->vf_nl_en = !!tmp;
733 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
734 config->dv_flow_en = !!tmp;
736 DRV_LOG(WARNING, "%s: unknown parameter", key);
744 * Parse device parameters.
747 * Pointer to device configuration structure.
749 * Device arguments structure.
752 * 0 on success, a negative errno value otherwise and rte_errno is set.
755 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
757 const char **params = (const char *[]){
758 MLX5_RXQ_CQE_COMP_EN,
762 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
763 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
766 MLX5_TXQS_MIN_INLINE,
769 MLX5_TXQ_MPW_HDR_DSEG_EN,
770 MLX5_TXQ_MAX_INLINE_LEN,
779 struct rte_kvargs *kvlist;
785 /* Following UGLY cast is done to pass checkpatch. */
786 kvlist = rte_kvargs_parse(devargs->args, params);
789 /* Process parameters. */
790 for (i = 0; (params[i] != NULL); ++i) {
791 if (rte_kvargs_count(kvlist, params[i])) {
792 ret = rte_kvargs_process(kvlist, params[i],
793 mlx5_args_check, config);
796 rte_kvargs_free(kvlist);
801 rte_kvargs_free(kvlist);
805 static struct rte_pci_driver mlx5_driver;
808 find_lower_va_bound(const struct rte_memseg_list *msl,
809 const struct rte_memseg *ms, void *arg)
818 *addr = RTE_MIN(*addr, ms->addr);
824 * Reserve UAR address space for primary process.
826 * Process local resource is used by both primary and secondary to avoid
827 * duplicate reservation. The space has to be available on both primary and
828 * secondary process, TXQ UAR maps to this area using fixed mmap w/o double
832 * 0 on success, a negative errno value otherwise and rte_errno is set.
835 mlx5_uar_init_primary(void)
837 struct mlx5_shared_data *sd = mlx5_shared_data;
838 void *addr = (void *)0;
842 /* find out lower bound of hugepage segments */
843 rte_memseg_walk(find_lower_va_bound, &addr);
844 /* keep distance to hugepages to minimize potential conflicts. */
845 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
846 /* anonymous mmap, no real memory consumption. */
847 addr = mmap(addr, MLX5_UAR_SIZE,
848 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
849 if (addr == MAP_FAILED) {
851 "Failed to reserve UAR address space, please"
852 " adjust MLX5_UAR_SIZE or try --base-virtaddr");
856 /* Accept either same addr or a new addr returned from mmap if target
859 DRV_LOG(INFO, "Reserved UAR address space: %p", addr);
860 sd->uar_base = addr; /* for primary and secondary UAR re-mmap. */
865 * Unmap UAR address space reserved for primary process.
868 mlx5_uar_uninit_primary(void)
870 struct mlx5_shared_data *sd = mlx5_shared_data;
874 munmap(sd->uar_base, MLX5_UAR_SIZE);
879 * Reserve UAR address space for secondary process, align with primary process.
882 * 0 on success, a negative errno value otherwise and rte_errno is set.
885 mlx5_uar_init_secondary(void)
887 struct mlx5_shared_data *sd = mlx5_shared_data;
888 struct mlx5_local_data *ld = &mlx5_local_data;
891 if (ld->uar_base) { /* Already reserved. */
892 assert(sd->uar_base == ld->uar_base);
895 assert(sd->uar_base);
896 /* anonymous mmap, no real memory consumption. */
897 addr = mmap(sd->uar_base, MLX5_UAR_SIZE,
898 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
899 if (addr == MAP_FAILED) {
900 DRV_LOG(ERR, "UAR mmap failed: %p size: %llu",
901 sd->uar_base, MLX5_UAR_SIZE);
905 if (sd->uar_base != addr) {
907 "UAR address %p size %llu occupied, please"
908 " adjust MLX5_UAR_OFFSET or try EAL parameter"
910 sd->uar_base, MLX5_UAR_SIZE);
915 DRV_LOG(INFO, "Reserved UAR address space: %p", addr);
920 * Unmap UAR address space reserved for secondary process.
923 mlx5_uar_uninit_secondary(void)
925 struct mlx5_local_data *ld = &mlx5_local_data;
929 munmap(ld->uar_base, MLX5_UAR_SIZE);
934 * PMD global initialization.
936 * Independent from individual device, this function initializes global
937 * per-PMD data structures distinguishing primary and secondary processes.
938 * Hence, each initialization is called once per a process.
941 * 0 on success, a negative errno value otherwise and rte_errno is set.
946 struct mlx5_shared_data *sd;
947 struct mlx5_local_data *ld = &mlx5_local_data;
950 if (mlx5_init_shared_data())
952 sd = mlx5_shared_data;
954 rte_spinlock_lock(&sd->lock);
955 switch (rte_eal_process_type()) {
956 case RTE_PROC_PRIMARY:
959 LIST_INIT(&sd->mem_event_cb_list);
960 rte_rwlock_init(&sd->mem_event_rwlock);
961 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
962 mlx5_mr_mem_event_cb, NULL);
963 mlx5_mp_init_primary();
964 ret = mlx5_uar_init_primary();
967 sd->init_done = true;
969 case RTE_PROC_SECONDARY:
972 mlx5_mp_init_secondary();
973 ret = mlx5_uar_init_secondary();
977 ld->init_done = true;
982 rte_spinlock_unlock(&sd->lock);
985 switch (rte_eal_process_type()) {
986 case RTE_PROC_PRIMARY:
987 mlx5_uar_uninit_primary();
988 mlx5_mp_uninit_primary();
989 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", NULL);
991 case RTE_PROC_SECONDARY:
992 mlx5_uar_uninit_secondary();
993 mlx5_mp_uninit_secondary();
998 rte_spinlock_unlock(&sd->lock);
999 mlx5_uninit_shared_data();
1004 * Spawn an Ethernet device from Verbs information.
1007 * Backing DPDK device.
1009 * Verbs device parameters (name, port, switch_info) to spawn.
1011 * Device configuration parameters.
1014 * A valid Ethernet device object on success, NULL otherwise and rte_errno
1015 * is set. The following errors are defined:
1017 * EBUSY: device is not supposed to be spawned.
1018 * EEXIST: device is already spawned
1020 static struct rte_eth_dev *
1021 mlx5_dev_spawn(struct rte_device *dpdk_dev,
1022 struct mlx5_dev_spawn_data *spawn,
1023 struct mlx5_dev_config config)
1025 const struct mlx5_switch_info *switch_info = &spawn->info;
1026 struct mlx5_ibv_shared *sh = NULL;
1027 struct ibv_port_attr port_attr;
1028 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
1029 struct rte_eth_dev *eth_dev = NULL;
1030 struct mlx5_priv *priv = NULL;
1032 unsigned int hw_padding = 0;
1034 unsigned int cqe_comp;
1035 unsigned int cqe_pad = 0;
1036 unsigned int tunnel_en = 0;
1037 unsigned int mpls_en = 0;
1038 unsigned int swp = 0;
1039 unsigned int mprq = 0;
1040 unsigned int mprq_min_stride_size_n = 0;
1041 unsigned int mprq_max_stride_size_n = 0;
1042 unsigned int mprq_min_stride_num_n = 0;
1043 unsigned int mprq_max_stride_num_n = 0;
1044 struct ether_addr mac;
1045 char name[RTE_ETH_NAME_MAX_LEN];
1046 int own_domain_id = 0;
1050 /* Determine if this port representor is supposed to be spawned. */
1051 if (switch_info->representor && dpdk_dev->devargs) {
1052 struct rte_eth_devargs eth_da;
1054 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
1057 DRV_LOG(ERR, "failed to process device arguments: %s",
1058 strerror(rte_errno));
1061 for (i = 0; i < eth_da.nb_representor_ports; ++i)
1062 if (eth_da.representor_ports[i] ==
1063 (uint16_t)switch_info->port_name)
1065 if (i == eth_da.nb_representor_ports) {
1070 /* Build device name. */
1071 if (!switch_info->representor)
1072 strlcpy(name, dpdk_dev->name, sizeof(name));
1074 snprintf(name, sizeof(name), "%s_representor_%u",
1075 dpdk_dev->name, switch_info->port_name);
1076 /* check if the device is already spawned */
1077 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
1081 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
1082 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1083 eth_dev = rte_eth_dev_attach_secondary(name);
1084 if (eth_dev == NULL) {
1085 DRV_LOG(ERR, "can not attach rte ethdev");
1089 eth_dev->device = dpdk_dev;
1090 eth_dev->dev_ops = &mlx5_dev_sec_ops;
1091 /* Receive command fd from primary process */
1092 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
1095 /* Remap UAR for Tx queues. */
1096 err = mlx5_tx_uar_remap(eth_dev, err);
1100 * Ethdev pointer is still required as input since
1101 * the primary device is not accessible from the
1102 * secondary process.
1104 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
1105 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
1108 sh = mlx5_alloc_shared_ibctx(spawn);
1111 config.devx = sh->devx;
1112 #ifdef HAVE_IBV_MLX5_MOD_SWP
1113 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
1116 * Multi-packet send is supported by ConnectX-4 Lx PF as well
1117 * as all ConnectX-5 devices.
1119 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1120 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1122 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1123 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
1125 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
1126 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1127 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1128 DRV_LOG(DEBUG, "enhanced MPW is supported");
1129 mps = MLX5_MPW_ENHANCED;
1131 DRV_LOG(DEBUG, "MPW is supported");
1135 DRV_LOG(DEBUG, "MPW isn't supported");
1136 mps = MLX5_MPW_DISABLED;
1138 #ifdef HAVE_IBV_MLX5_MOD_SWP
1139 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1140 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
1141 DRV_LOG(DEBUG, "SWP support: %u", swp);
1144 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1145 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1146 struct mlx5dv_striding_rq_caps mprq_caps =
1147 dv_attr.striding_rq_caps;
1149 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1150 mprq_caps.min_single_stride_log_num_of_bytes);
1151 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1152 mprq_caps.max_single_stride_log_num_of_bytes);
1153 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1154 mprq_caps.min_single_wqe_log_num_of_strides);
1155 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1156 mprq_caps.max_single_wqe_log_num_of_strides);
1157 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1158 mprq_caps.supported_qpts);
1159 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1161 mprq_min_stride_size_n =
1162 mprq_caps.min_single_stride_log_num_of_bytes;
1163 mprq_max_stride_size_n =
1164 mprq_caps.max_single_stride_log_num_of_bytes;
1165 mprq_min_stride_num_n =
1166 mprq_caps.min_single_wqe_log_num_of_strides;
1167 mprq_max_stride_num_n =
1168 mprq_caps.max_single_wqe_log_num_of_strides;
1169 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1170 mprq_min_stride_num_n);
1173 if (RTE_CACHE_LINE_SIZE == 128 &&
1174 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
1178 config.cqe_comp = cqe_comp;
1179 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1180 /* Whether device supports 128B Rx CQE padding. */
1181 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
1182 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
1184 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1185 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
1186 tunnel_en = ((dv_attr.tunnel_offloads_caps &
1187 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
1188 (dv_attr.tunnel_offloads_caps &
1189 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
1191 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
1192 tunnel_en ? "" : "not ");
1195 "tunnel offloading disabled due to old OFED/rdma-core version");
1197 config.tunnel_en = tunnel_en;
1198 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
1199 mpls_en = ((dv_attr.tunnel_offloads_caps &
1200 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
1201 (dv_attr.tunnel_offloads_caps &
1202 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
1203 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
1204 mpls_en ? "" : "not ");
1206 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
1207 " old OFED/rdma-core version or firmware configuration");
1209 config.mpls_en = mpls_en;
1210 /* Check port status. */
1211 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
1213 DRV_LOG(ERR, "port query failed: %s", strerror(err));
1216 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1217 DRV_LOG(ERR, "port is not configured in Ethernet mode");
1221 if (port_attr.state != IBV_PORT_ACTIVE)
1222 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
1223 mlx5_glue->port_state_str(port_attr.state),
1225 /* Allocate private eth device data. */
1226 priv = rte_zmalloc("ethdev private structure",
1228 RTE_CACHE_LINE_SIZE);
1230 DRV_LOG(ERR, "priv allocation failure");
1235 priv->ibv_port = spawn->ibv_port;
1236 priv->mtu = ETHER_MTU;
1238 /* Initialize UAR access locks for 32bit implementations. */
1239 rte_spinlock_init(&priv->uar_lock_cq);
1240 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1241 rte_spinlock_init(&priv->uar_lock[i]);
1243 /* Some internal functions rely on Netlink sockets, open them now. */
1244 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
1245 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
1247 priv->representor = !!switch_info->representor;
1248 priv->master = !!switch_info->master;
1249 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1251 * Currently we support single E-Switch per PF configurations
1252 * only and vport_id field contains the vport index for
1253 * associated VF, which is deduced from representor port name.
1254 * For exapmple, let's have the IB device port 10, it has
1255 * attached network device eth0, which has port name attribute
1256 * pf0vf2, we can deduce the VF number as 2, and set vport index
1257 * as 3 (2+1). This assigning schema should be changed if the
1258 * multiple E-Switch instances per PF configurations or/and PCI
1259 * subfunctions are added.
1261 priv->vport_id = switch_info->representor ?
1262 switch_info->port_name + 1 : -1;
1263 /* representor_id field keeps the unmodified port/VF index. */
1264 priv->representor_id = switch_info->representor ?
1265 switch_info->port_name : -1;
1267 * Look for sibling devices in order to reuse their switch domain
1268 * if any, otherwise allocate one.
1270 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
1272 uint16_t port_id[i];
1274 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1276 const struct mlx5_priv *opriv =
1277 rte_eth_devices[port_id[i]].data->dev_private;
1281 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1283 priv->domain_id = opriv->domain_id;
1287 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1288 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1291 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1292 strerror(rte_errno));
1297 err = mlx5_args(&config, dpdk_dev->devargs);
1300 DRV_LOG(ERR, "failed to process device arguments: %s",
1301 strerror(rte_errno));
1304 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
1305 IBV_DEVICE_RAW_IP_CSUM);
1306 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1307 (config.hw_csum ? "" : "not "));
1308 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1309 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1310 DRV_LOG(DEBUG, "counters are not supported");
1312 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1313 if (config.dv_flow_en) {
1314 DRV_LOG(WARNING, "DV flow is not supported");
1315 config.dv_flow_en = 0;
1318 config.ind_table_max_size =
1319 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
1321 * Remove this check once DPDK supports larger/variable
1322 * indirection tables.
1324 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1325 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1326 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1327 config.ind_table_max_size);
1328 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
1329 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1330 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1331 (config.hw_vlan_strip ? "" : "not "));
1332 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1333 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1334 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1335 (config.hw_fcs_strip ? "" : "not "));
1336 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1337 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
1338 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1339 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
1340 IBV_DEVICE_PCI_WRITE_END_PADDING);
1342 if (config.hw_padding && !hw_padding) {
1343 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1344 config.hw_padding = 0;
1345 } else if (config.hw_padding) {
1346 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1348 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
1349 (sh->device_attr.tso_caps.supported_qpts &
1350 (1 << IBV_QPT_RAW_PACKET)));
1352 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
1354 * MPW is disabled by default, while the Enhanced MPW is enabled
1357 if (config.mps == MLX5_ARG_UNSET)
1358 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1361 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1362 DRV_LOG(INFO, "%sMPS is %s",
1363 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1364 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1365 if (config.cqe_comp && !cqe_comp) {
1366 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1367 config.cqe_comp = 0;
1369 if (config.cqe_pad && !cqe_pad) {
1370 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1372 } else if (config.cqe_pad) {
1373 DRV_LOG(INFO, "Rx CQE padding is enabled");
1375 if (config.mprq.enabled && mprq) {
1376 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1377 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1378 config.mprq.stride_num_n =
1379 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1380 mprq_min_stride_num_n);
1382 "the number of strides"
1383 " for Multi-Packet RQ is out of range,"
1384 " setting default value (%u)",
1385 1 << config.mprq.stride_num_n);
1387 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1388 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1389 } else if (config.mprq.enabled && !mprq) {
1390 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1391 config.mprq.enabled = 0;
1393 eth_dev = rte_eth_dev_allocate(name);
1394 if (eth_dev == NULL) {
1395 DRV_LOG(ERR, "can not allocate rte ethdev");
1399 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1400 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1401 if (priv->representor) {
1402 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1403 eth_dev->data->representor_id = priv->representor_id;
1405 eth_dev->data->dev_private = priv;
1406 priv->dev_data = eth_dev->data;
1407 eth_dev->data->mac_addrs = priv->mac;
1408 eth_dev->device = dpdk_dev;
1409 /* Configure the first MAC address by default. */
1410 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1412 "port %u cannot get MAC address, is mlx5_en"
1413 " loaded? (errno: %s)",
1414 eth_dev->data->port_id, strerror(rte_errno));
1419 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1420 eth_dev->data->port_id,
1421 mac.addr_bytes[0], mac.addr_bytes[1],
1422 mac.addr_bytes[2], mac.addr_bytes[3],
1423 mac.addr_bytes[4], mac.addr_bytes[5]);
1426 char ifname[IF_NAMESIZE];
1428 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1429 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1430 eth_dev->data->port_id, ifname);
1432 DRV_LOG(DEBUG, "port %u ifname is unknown",
1433 eth_dev->data->port_id);
1436 /* Get actual MTU if possible. */
1437 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1442 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1444 /* Initialize burst functions to prevent crashes before link-up. */
1445 eth_dev->rx_pkt_burst = removed_rx_burst;
1446 eth_dev->tx_pkt_burst = removed_tx_burst;
1447 eth_dev->dev_ops = &mlx5_dev_ops;
1448 /* Register MAC address. */
1449 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1450 if (config.vf && config.vf_nl_en)
1451 mlx5_nl_mac_addr_sync(eth_dev);
1452 priv->tcf_context = mlx5_flow_tcf_context_create();
1453 if (!priv->tcf_context) {
1456 "flow rules relying on switch offloads will not be"
1457 " supported: cannot open libmnl socket: %s",
1458 strerror(rte_errno));
1460 struct rte_flow_error error;
1461 unsigned int ifindex = mlx5_ifindex(eth_dev);
1466 "cannot retrieve network interface index";
1468 err = mlx5_flow_tcf_init(priv->tcf_context,
1473 "flow rules relying on switch offloads will"
1474 " not be supported: %s: %s",
1475 error.message, strerror(rte_errno));
1476 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1477 priv->tcf_context = NULL;
1480 TAILQ_INIT(&priv->flows);
1481 TAILQ_INIT(&priv->ctrl_flows);
1482 /* Hint libmlx5 to use PMD allocator for data plane resources */
1483 struct mlx5dv_ctx_allocators alctr = {
1484 .alloc = &mlx5_alloc_verbs_buf,
1485 .free = &mlx5_free_verbs_buf,
1488 mlx5_glue->dv_set_context_attr(sh->ctx,
1489 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1490 (void *)((uintptr_t)&alctr));
1491 /* Bring Ethernet device up. */
1492 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1493 eth_dev->data->port_id);
1494 mlx5_set_link_up(eth_dev);
1496 * Even though the interrupt handler is not installed yet,
1497 * interrupts will still trigger on the asyn_fd from
1498 * Verbs context returned by ibv_open_device().
1500 mlx5_link_update(eth_dev, 0);
1501 /* Store device configuration on private structure. */
1502 priv->config = config;
1503 /* Supported Verbs flow priority number detection. */
1504 err = mlx5_flow_discover_priorities(eth_dev);
1509 priv->config.flow_prio = err;
1511 * Once the device is added to the list of memory event
1512 * callback, its global MR cache table cannot be expanded
1513 * on the fly because of deadlock. If it overflows, lookup
1514 * should be done by searching MR list linearly, which is slow.
1516 err = mlx5_mr_btree_init(&priv->mr.cache,
1517 MLX5_MR_BTREE_CACHE_N * 2,
1518 eth_dev->device->numa_node);
1523 /* Add device to memory callback list. */
1524 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1525 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1526 priv, mem_event_cb);
1527 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1531 if (priv->nl_socket_route >= 0)
1532 close(priv->nl_socket_route);
1533 if (priv->nl_socket_rdma >= 0)
1534 close(priv->nl_socket_rdma);
1535 if (priv->tcf_context)
1536 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1538 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1540 if (eth_dev != NULL)
1541 eth_dev->data->dev_private = NULL;
1543 if (eth_dev != NULL) {
1544 /* mac_addrs must not be freed alone because part of dev_private */
1545 eth_dev->data->mac_addrs = NULL;
1546 rte_eth_dev_release_port(eth_dev);
1549 mlx5_free_shared_ibctx(sh);
1556 * Comparison callback to sort device data.
1558 * This is meant to be used with qsort().
1561 * Pointer to pointer to first data object.
1563 * Pointer to pointer to second data object.
1566 * 0 if both objects are equal, less than 0 if the first argument is less
1567 * than the second, greater than 0 otherwise.
1570 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1572 const struct mlx5_switch_info *si_a =
1573 &((const struct mlx5_dev_spawn_data *)a)->info;
1574 const struct mlx5_switch_info *si_b =
1575 &((const struct mlx5_dev_spawn_data *)b)->info;
1578 /* Master device first. */
1579 ret = si_b->master - si_a->master;
1582 /* Then representor devices. */
1583 ret = si_b->representor - si_a->representor;
1586 /* Unidentified devices come last in no specific order. */
1587 if (!si_a->representor)
1589 /* Order representors by name. */
1590 return si_a->port_name - si_b->port_name;
1594 * DPDK callback to register a PCI device.
1596 * This function spawns Ethernet devices out of a given PCI device.
1598 * @param[in] pci_drv
1599 * PCI driver structure (mlx5_driver).
1600 * @param[in] pci_dev
1601 * PCI device information.
1604 * 0 on success, a negative errno value otherwise and rte_errno is set.
1607 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1608 struct rte_pci_device *pci_dev)
1610 struct ibv_device **ibv_list;
1612 * Number of found IB Devices matching with requested PCI BDF.
1613 * nd != 1 means there are multiple IB devices over the same
1614 * PCI device and we have representors and master.
1616 unsigned int nd = 0;
1618 * Number of found IB device Ports. nd = 1 and np = 1..n means
1619 * we have the single multiport IB device, and there may be
1620 * representors attached to some of found ports.
1622 unsigned int np = 0;
1624 * Number of DPDK ethernet devices to Spawn - either over
1625 * multiple IB devices or multiple ports of single IB device.
1626 * Actually this is the number of iterations to spawn.
1628 unsigned int ns = 0;
1629 struct mlx5_dev_config dev_config;
1632 ret = mlx5_init_once();
1634 DRV_LOG(ERR, "unable to init PMD global data: %s",
1635 strerror(rte_errno));
1638 assert(pci_drv == &mlx5_driver);
1640 ibv_list = mlx5_glue->get_device_list(&ret);
1642 rte_errno = errno ? errno : ENOSYS;
1643 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1647 * First scan the list of all Infiniband devices to find
1648 * matching ones, gathering into the list.
1650 struct ibv_device *ibv_match[ret + 1];
1656 struct rte_pci_addr pci_addr;
1658 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1659 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1661 if (pci_dev->addr.domain != pci_addr.domain ||
1662 pci_dev->addr.bus != pci_addr.bus ||
1663 pci_dev->addr.devid != pci_addr.devid ||
1664 pci_dev->addr.function != pci_addr.function)
1666 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1667 ibv_list[ret]->name);
1668 ibv_match[nd++] = ibv_list[ret];
1670 ibv_match[nd] = NULL;
1672 /* No device macthes, just complain and bail out. */
1673 mlx5_glue->free_device_list(ibv_list);
1675 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1676 " are kernel drivers loaded?",
1677 pci_dev->addr.domain, pci_dev->addr.bus,
1678 pci_dev->addr.devid, pci_dev->addr.function);
1683 nl_route = mlx5_nl_init(NETLINK_ROUTE);
1684 nl_rdma = mlx5_nl_init(NETLINK_RDMA);
1687 * Found single matching device may have multiple ports.
1688 * Each port may be representor, we have to check the port
1689 * number and check the representors existence.
1692 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
1694 DRV_LOG(WARNING, "can not get IB device \"%s\""
1695 " ports number", ibv_match[0]->name);
1698 * Now we can determine the maximal
1699 * amount of devices to be spawned.
1701 struct mlx5_dev_spawn_data list[np ? np : nd];
1705 * Signle IB device with multiple ports found,
1706 * it may be E-Switch master device and representors.
1707 * We have to perform identification trough the ports.
1709 assert(nl_rdma >= 0);
1712 for (i = 1; i <= np; ++i) {
1713 list[ns].max_port = np;
1714 list[ns].ibv_port = i;
1715 list[ns].ibv_dev = ibv_match[0];
1716 list[ns].eth_dev = NULL;
1717 list[ns].ifindex = mlx5_nl_ifindex
1718 (nl_rdma, list[ns].ibv_dev->name, i);
1719 if (!list[ns].ifindex) {
1721 * No network interface index found for the
1722 * specified port, it means there is no
1723 * representor on this port. It's OK,
1724 * there can be disabled ports, for example
1725 * if sriov_numvfs < sriov_totalvfs.
1731 ret = mlx5_nl_switch_info
1735 if (ret || (!list[ns].info.representor &&
1736 !list[ns].info.master)) {
1738 * We failed to recognize representors with
1739 * Netlink, let's try to perform the task
1742 ret = mlx5_sysfs_switch_info
1746 if (!ret && (list[ns].info.representor ^
1747 list[ns].info.master))
1752 "unable to recognize master/representors"
1753 " on the IB device with multiple ports");
1760 * The existence of several matching entries (nd > 1) means
1761 * port representors have been instantiated. No existing Verbs
1762 * call nor sysfs entries can tell them apart, this can only
1763 * be done through Netlink calls assuming kernel drivers are
1764 * recent enough to support them.
1766 * In the event of identification failure through Netlink,
1767 * try again through sysfs, then:
1769 * 1. A single IB device matches (nd == 1) with single
1770 * port (np=0/1) and is not a representor, assume
1771 * no switch support.
1773 * 2. Otherwise no safe assumptions can be made;
1774 * complain louder and bail out.
1777 for (i = 0; i != nd; ++i) {
1778 memset(&list[ns].info, 0, sizeof(list[ns].info));
1779 list[ns].max_port = 1;
1780 list[ns].ibv_port = 1;
1781 list[ns].ibv_dev = ibv_match[i];
1782 list[ns].eth_dev = NULL;
1783 list[ns].ifindex = 0;
1785 list[ns].ifindex = mlx5_nl_ifindex
1786 (nl_rdma, list[ns].ibv_dev->name, 1);
1787 if (!list[ns].ifindex) {
1789 * No network interface index found for the
1790 * specified device, it means there it is not
1791 * a representor/master.
1797 ret = mlx5_nl_switch_info
1801 if (ret || (!list[ns].info.representor &&
1802 !list[ns].info.master)) {
1804 * We failed to recognize representors with
1805 * Netlink, let's try to perform the task
1808 ret = mlx5_sysfs_switch_info
1812 if (!ret && (list[ns].info.representor ^
1813 list[ns].info.master)) {
1815 } else if ((nd == 1) &&
1816 !list[ns].info.representor &&
1817 !list[ns].info.master) {
1819 * Single IB device with
1820 * one physical port and
1821 * attached network device.
1822 * May be SRIOV is not enabled
1823 * or there is no representors.
1825 DRV_LOG(INFO, "no E-Switch support detected");
1832 "unable to recognize master/representors"
1833 " on the multiple IB devices");
1841 * Sort list to probe devices in natural order for users convenience
1842 * (i.e. master first, then representors from lowest to highest ID).
1844 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
1845 /* Default configuration. */
1846 dev_config = (struct mlx5_dev_config){
1848 .mps = MLX5_ARG_UNSET,
1851 .txq_inline = MLX5_ARG_UNSET,
1852 .txqs_inline = MLX5_ARG_UNSET,
1853 .txqs_vec = MLX5_ARG_UNSET,
1854 .inline_max_packet_sz = MLX5_ARG_UNSET,
1857 .enabled = 0, /* Disabled by default. */
1858 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1859 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1860 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1863 /* Device specific configuration. */
1864 switch (pci_dev->id.device_id) {
1865 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1866 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1868 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1869 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1870 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1871 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1877 /* Set architecture-dependent default value if unset. */
1878 if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1879 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1880 for (i = 0; i != ns; ++i) {
1883 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1886 if (!list[i].eth_dev) {
1887 if (rte_errno != EBUSY && rte_errno != EEXIST)
1889 /* Device is disabled or already spawned. Ignore it. */
1892 restore = list[i].eth_dev->data->dev_flags;
1893 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1894 /* Restore non-PCI flags cleared by the above call. */
1895 list[i].eth_dev->data->dev_flags |= restore;
1896 rte_eth_dev_probing_finish(list[i].eth_dev);
1900 "probe of PCI device " PCI_PRI_FMT " aborted after"
1901 " encountering an error: %s",
1902 pci_dev->addr.domain, pci_dev->addr.bus,
1903 pci_dev->addr.devid, pci_dev->addr.function,
1904 strerror(rte_errno));
1908 if (!list[i].eth_dev)
1910 mlx5_dev_close(list[i].eth_dev);
1911 /* mac_addrs must not be freed because in dev_private */
1912 list[i].eth_dev->data->mac_addrs = NULL;
1913 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1915 /* Restore original error. */
1922 * Do the routine cleanup:
1923 * - close opened Netlink sockets
1924 * - free the Infiniband device list
1931 mlx5_glue->free_device_list(ibv_list);
1936 * DPDK callback to remove a PCI device.
1938 * This function removes all Ethernet devices belong to a given PCI device.
1940 * @param[in] pci_dev
1941 * Pointer to the PCI device.
1944 * 0 on success, the function cannot fail.
1947 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1950 struct rte_eth_dev *port;
1952 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1953 port = &rte_eth_devices[port_id];
1954 if (port->state != RTE_ETH_DEV_UNUSED &&
1955 port->device == &pci_dev->device)
1956 rte_eth_dev_close(port_id);
1961 static const struct rte_pci_id mlx5_pci_id_map[] = {
1963 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1964 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1967 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1968 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1971 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1972 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1975 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1976 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1979 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1980 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1983 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1987 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1991 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1995 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2015 static struct rte_pci_driver mlx5_driver = {
2017 .name = MLX5_DRIVER_NAME
2019 .id_table = mlx5_pci_id_map,
2020 .probe = mlx5_pci_probe,
2021 .remove = mlx5_pci_remove,
2022 .dma_map = mlx5_dma_map,
2023 .dma_unmap = mlx5_dma_unmap,
2024 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
2025 RTE_PCI_DRV_PROBE_AGAIN),
2028 #ifdef RTE_IBVERBS_LINK_DLOPEN
2031 * Suffix RTE_EAL_PMD_PATH with "-glue".
2033 * This function performs a sanity check on RTE_EAL_PMD_PATH before
2034 * suffixing its last component.
2037 * Output buffer, should be large enough otherwise NULL is returned.
2042 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
2045 mlx5_glue_path(char *buf, size_t size)
2047 static const char *const bad[] = { "/", ".", "..", NULL };
2048 const char *path = RTE_EAL_PMD_PATH;
2049 size_t len = strlen(path);
2053 while (len && path[len - 1] == '/')
2055 for (off = len; off && path[off - 1] != '/'; --off)
2057 for (i = 0; bad[i]; ++i)
2058 if (!strncmp(path + off, bad[i], (int)(len - off)))
2060 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
2061 if (i == -1 || (size_t)i >= size)
2066 "unable to append \"-glue\" to last component of"
2067 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
2068 " please re-configure DPDK");
2073 * Initialization routine for run-time dependency on rdma-core.
2076 mlx5_glue_init(void)
2078 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
2079 const char *path[] = {
2081 * A basic security check is necessary before trusting
2082 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
2084 (geteuid() == getuid() && getegid() == getgid() ?
2085 getenv("MLX5_GLUE_PATH") : NULL),
2087 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
2088 * variant, otherwise let dlopen() look up libraries on its
2091 (*RTE_EAL_PMD_PATH ?
2092 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
2095 void *handle = NULL;
2099 while (!handle && i != RTE_DIM(path)) {
2108 end = strpbrk(path[i], ":;");
2110 end = path[i] + strlen(path[i]);
2111 len = end - path[i];
2116 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
2118 (!len || *(end - 1) == '/') ? "" : "/");
2121 if (sizeof(name) != (size_t)ret + 1)
2123 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
2125 handle = dlopen(name, RTLD_LAZY);
2136 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
2139 sym = dlsym(handle, "mlx5_glue");
2140 if (!sym || !*sym) {
2144 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
2153 "cannot initialize PMD due to missing run-time dependency on"
2154 " rdma-core libraries (libibverbs, libmlx5)");
2161 * Driver initialization routine.
2163 RTE_INIT(rte_mlx5_pmd_init)
2165 /* Initialize driver log type. */
2166 mlx5_logtype = rte_log_register("pmd.net.mlx5");
2167 if (mlx5_logtype >= 0)
2168 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2170 /* Build the static tables for Verbs conversion. */
2171 mlx5_set_ptype_table();
2172 mlx5_set_cksum_table();
2173 mlx5_set_swp_types_table();
2175 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
2176 * huge pages. Calling ibv_fork_init() during init allows
2177 * applications to use fork() safely for purposes other than
2178 * using this PMD, which is not supported in forked processes.
2180 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
2181 /* Match the size of Rx completion entry to the size of a cacheline. */
2182 if (RTE_CACHE_LINE_SIZE == 128)
2183 setenv("MLX5_CQE_SIZE", "128", 0);
2185 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
2186 * cleanup all the Verbs resources even when the device was removed.
2188 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
2189 #ifdef RTE_IBVERBS_LINK_DLOPEN
2190 if (mlx5_glue_init())
2195 /* Glue structure must not contain any NULL pointers. */
2199 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
2200 assert(((const void *const *)mlx5_glue)[i]);
2203 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
2205 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
2206 mlx5_glue->version, MLX5_GLUE_VERSION);
2209 mlx5_glue->fork_init();
2210 rte_pci_register(&mlx5_driver);
2213 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2214 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2215 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");