4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 /* DPDK headers don't like -pedantic. */
55 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_malloc.h>
58 #include <rte_ethdev.h>
60 #include <rte_common.h>
61 #include <rte_kvargs.h>
63 #pragma GCC diagnostic error "-Wpedantic"
67 #include "mlx5_utils.h"
68 #include "mlx5_rxtx.h"
69 #include "mlx5_autoconf.h"
70 #include "mlx5_defs.h"
72 /* Device parameter to enable RX completion queue compression. */
73 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
75 /* Device parameter to configure inline send. */
76 #define MLX5_TXQ_INLINE "txq_inline"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
84 /* Device parameter to enable multi-packet send WQEs. */
85 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
88 * Retrieve integer value from environment variable.
91 * Environment variable name.
94 * Integer value, 0 if the variable is not set.
97 mlx5_getenv_int(const char *name)
99 const char *val = getenv(name);
107 * DPDK callback to close the device.
109 * Destroy all queues and objects, free memory.
112 * Pointer to Ethernet device structure.
115 mlx5_dev_close(struct rte_eth_dev *dev)
117 struct priv *priv = mlx5_get_priv(dev);
121 DEBUG("%p: closing device \"%s\"",
123 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
124 /* In case mlx5_dev_stop() has not been called. */
125 priv_dev_interrupt_handler_uninstall(priv, dev);
126 priv_special_flow_disable_all(priv);
127 priv_mac_addrs_disable(priv);
128 priv_destroy_hash_rxqs(priv);
130 /* Remove flow director elements. */
131 priv_fdir_disable(priv);
132 priv_fdir_delete_filters_list(priv);
134 /* Prevent crashes when queues are still in use. */
135 dev->rx_pkt_burst = removed_rx_burst;
136 dev->tx_pkt_burst = removed_tx_burst;
137 if (priv->rxqs != NULL) {
138 /* XXX race condition if mlx5_rx_burst() is still running. */
140 for (i = 0; (i != priv->rxqs_n); ++i) {
141 struct rxq *rxq = (*priv->rxqs)[i];
142 struct rxq_ctrl *rxq_ctrl;
146 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
147 (*priv->rxqs)[i] = NULL;
148 rxq_cleanup(rxq_ctrl);
154 if (priv->txqs != NULL) {
155 /* XXX race condition if mlx5_tx_burst() is still running. */
157 for (i = 0; (i != priv->txqs_n); ++i) {
158 struct txq *txq = (*priv->txqs)[i];
159 struct txq_ctrl *txq_ctrl;
163 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
164 (*priv->txqs)[i] = NULL;
165 txq_cleanup(txq_ctrl);
171 if (priv->pd != NULL) {
172 assert(priv->ctx != NULL);
173 claim_zero(ibv_dealloc_pd(priv->pd));
174 claim_zero(ibv_close_device(priv->ctx));
176 assert(priv->ctx == NULL);
177 if (priv->rss_conf != NULL) {
178 for (i = 0; (i != hash_rxq_init_n); ++i)
179 rte_free((*priv->rss_conf)[i]);
180 rte_free(priv->rss_conf);
182 if (priv->reta_idx != NULL)
183 rte_free(priv->reta_idx);
185 memset(priv, 0, sizeof(*priv));
188 static const struct eth_dev_ops mlx5_dev_ops = {
189 .dev_configure = mlx5_dev_configure,
190 .dev_start = mlx5_dev_start,
191 .dev_stop = mlx5_dev_stop,
192 .dev_set_link_down = mlx5_set_link_down,
193 .dev_set_link_up = mlx5_set_link_up,
194 .dev_close = mlx5_dev_close,
195 .promiscuous_enable = mlx5_promiscuous_enable,
196 .promiscuous_disable = mlx5_promiscuous_disable,
197 .allmulticast_enable = mlx5_allmulticast_enable,
198 .allmulticast_disable = mlx5_allmulticast_disable,
199 .link_update = mlx5_link_update,
200 .stats_get = mlx5_stats_get,
201 .stats_reset = mlx5_stats_reset,
202 .xstats_get = mlx5_xstats_get,
203 .xstats_reset = mlx5_xstats_reset,
204 .xstats_get_names = mlx5_xstats_get_names,
205 .dev_infos_get = mlx5_dev_infos_get,
206 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
207 .vlan_filter_set = mlx5_vlan_filter_set,
208 .rx_queue_setup = mlx5_rx_queue_setup,
209 .tx_queue_setup = mlx5_tx_queue_setup,
210 .rx_queue_release = mlx5_rx_queue_release,
211 .tx_queue_release = mlx5_tx_queue_release,
212 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
213 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
214 .mac_addr_remove = mlx5_mac_addr_remove,
215 .mac_addr_add = mlx5_mac_addr_add,
216 .mac_addr_set = mlx5_mac_addr_set,
217 .mtu_set = mlx5_dev_set_mtu,
218 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
219 .vlan_offload_set = mlx5_vlan_offload_set,
220 .reta_update = mlx5_dev_rss_reta_update,
221 .reta_query = mlx5_dev_rss_reta_query,
222 .rss_hash_update = mlx5_rss_hash_update,
223 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
224 .filter_ctrl = mlx5_dev_filter_ctrl,
228 struct rte_pci_addr pci_addr; /* associated PCI address */
229 uint32_t ports; /* physical ports bitfield. */
233 * Get device index in mlx5_dev[] from PCI bus address.
235 * @param[in] pci_addr
236 * PCI bus address to look for.
239 * mlx5_dev[] index on success, -1 on failure.
242 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
247 assert(pci_addr != NULL);
248 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
249 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
250 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
251 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
252 (mlx5_dev[i].pci_addr.function == pci_addr->function))
254 if ((mlx5_dev[i].ports == 0) && (ret == -1))
261 * Verify and store value for device argument.
264 * Key argument to verify.
266 * Value associated with key.
271 * 0 on success, negative errno value on failure.
274 mlx5_args_check(const char *key, const char *val, void *opaque)
276 struct priv *priv = opaque;
280 tmp = strtoul(val, NULL, 0);
282 WARN("%s: \"%s\" is not a valid integer", key, val);
285 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
286 priv->cqe_comp = !!tmp;
287 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
288 priv->txq_inline = tmp;
289 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
290 priv->txqs_inline = tmp;
291 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
292 priv->mps &= !!tmp; /* Enable MPW only if HW supports */
294 WARN("%s: unknown parameter", key);
301 * Parse device parameters.
304 * Pointer to private structure.
306 * Device arguments structure.
309 * 0 on success, errno value on failure.
312 mlx5_args(struct priv *priv, struct rte_devargs *devargs)
314 const char **params = (const char *[]){
315 MLX5_RXQ_CQE_COMP_EN,
317 MLX5_TXQS_MIN_INLINE,
321 struct rte_kvargs *kvlist;
327 /* Following UGLY cast is done to pass checkpatch. */
328 kvlist = rte_kvargs_parse(devargs->args, params);
331 /* Process parameters. */
332 for (i = 0; (params[i] != NULL); ++i) {
333 if (rte_kvargs_count(kvlist, params[i])) {
334 ret = rte_kvargs_process(kvlist, params[i],
335 mlx5_args_check, priv);
340 rte_kvargs_free(kvlist);
344 static struct eth_driver mlx5_driver;
347 * DPDK callback to register a PCI device.
349 * This function creates an Ethernet device for each port of a given
353 * PCI driver structure (mlx5_driver).
355 * PCI device information.
358 * 0 on success, negative errno value on failure.
361 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
363 struct ibv_device **list;
364 struct ibv_device *ibv_dev;
366 struct ibv_context *attr_ctx = NULL;
367 struct ibv_device_attr device_attr;
374 assert(pci_drv == &mlx5_driver.pci_drv);
375 /* Get mlx5_dev[] index. */
376 idx = mlx5_dev_idx(&pci_dev->addr);
378 ERROR("this driver cannot support any more adapters");
381 DEBUG("using driver device index %d", idx);
383 /* Save PCI address. */
384 mlx5_dev[idx].pci_addr = pci_dev->addr;
385 list = ibv_get_device_list(&i);
388 if (errno == ENOSYS) {
389 WARN("cannot list devices, is ib_uverbs loaded?");
396 * For each listed device, check related sysfs entry against
397 * the provided PCI ID.
400 struct rte_pci_addr pci_addr;
403 DEBUG("checking device \"%s\"", list[i]->name);
404 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
406 if ((pci_dev->addr.domain != pci_addr.domain) ||
407 (pci_dev->addr.bus != pci_addr.bus) ||
408 (pci_dev->addr.devid != pci_addr.devid) ||
409 (pci_dev->addr.function != pci_addr.function))
411 sriov = ((pci_dev->id.device_id ==
412 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
413 (pci_dev->id.device_id ==
414 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
415 (pci_dev->id.device_id ==
416 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
417 (pci_dev->id.device_id ==
418 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
420 * Multi-packet send is supported by ConnectX-4 Lx PF as well
421 * as all ConnectX-5 devices.
423 switch (pci_dev->id.device_id) {
424 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
425 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
426 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
427 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
428 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
434 INFO("PCI information matches, using device \"%s\""
435 " (SR-IOV: %s, MPS: %s)",
437 sriov ? "true" : "false",
438 mps ? "true" : "false");
439 attr_ctx = ibv_open_device(list[i]);
443 if (attr_ctx == NULL) {
444 ibv_free_device_list(list);
447 WARN("cannot access device, is mlx5_ib loaded?");
450 WARN("cannot use device, are drivers up to date?");
458 DEBUG("device opened");
459 if (ibv_query_device(attr_ctx, &device_attr))
461 INFO("%u port(s) detected", device_attr.phys_port_cnt);
463 for (i = 0; i < device_attr.phys_port_cnt; i++) {
464 uint32_t port = i + 1; /* ports are indexed from one */
465 uint32_t test = (1 << i);
466 struct ibv_context *ctx = NULL;
467 struct ibv_port_attr port_attr;
468 struct ibv_pd *pd = NULL;
469 struct priv *priv = NULL;
470 struct rte_eth_dev *eth_dev;
471 struct ibv_exp_device_attr exp_device_attr;
472 struct ether_addr mac;
473 uint16_t num_vfs = 0;
475 exp_device_attr.comp_mask =
476 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |
477 IBV_EXP_DEVICE_ATTR_RX_HASH |
478 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |
479 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |
482 DEBUG("using port %u (%08" PRIx32 ")", port, test);
484 ctx = ibv_open_device(ibv_dev);
488 /* Check port status. */
489 err = ibv_query_port(ctx, port, &port_attr);
491 ERROR("port query failed: %s", strerror(err));
495 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
496 ERROR("port %d is not configured in Ethernet mode",
501 if (port_attr.state != IBV_PORT_ACTIVE)
502 DEBUG("port %d is not active: \"%s\" (%d)",
503 port, ibv_port_state_str(port_attr.state),
506 /* Allocate protection domain. */
507 pd = ibv_alloc_pd(ctx);
509 ERROR("PD allocation failure");
514 mlx5_dev[idx].ports |= test;
516 /* from rte_ethdev.c */
517 priv = rte_zmalloc("ethdev private structure",
519 RTE_CACHE_LINE_SIZE);
521 ERROR("priv allocation failure");
527 priv->device_attr = device_attr;
530 priv->mtu = ETHER_MTU;
531 priv->mps = mps; /* Enable MPW by default if supported. */
532 priv->cqe_comp = 1; /* Enable compression by default. */
533 err = mlx5_args(priv, pci_dev->device.devargs);
535 ERROR("failed to process device arguments: %s",
539 if (ibv_exp_query_device(ctx, &exp_device_attr)) {
540 ERROR("ibv_exp_query_device() failed");
545 ((exp_device_attr.exp_device_cap_flags &
546 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
547 (exp_device_attr.exp_device_cap_flags &
548 IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
549 DEBUG("checksum offloading is %ssupported",
550 (priv->hw_csum ? "" : "not "));
552 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
553 IBV_EXP_DEVICE_VXLAN_SUPPORT);
554 DEBUG("L2 tunnel checksum offloads are %ssupported",
555 (priv->hw_csum_l2tun ? "" : "not "));
557 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;
558 /* Remove this check once DPDK supports larger/variable
559 * indirection tables. */
560 if (priv->ind_table_max_size > (unsigned int)RSS_INDIRECTION_TABLE_SIZE)
561 priv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE;
562 DEBUG("maximum RX indirection table size is %u",
563 priv->ind_table_max_size);
564 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap &
565 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP);
566 DEBUG("VLAN stripping is %ssupported",
567 (priv->hw_vlan_strip ? "" : "not "));
569 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags &
570 IBV_EXP_DEVICE_SCATTER_FCS);
571 DEBUG("FCS stripping configuration is %ssupported",
572 (priv->hw_fcs_strip ? "" : "not "));
574 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align;
575 DEBUG("hardware RX end alignment padding is %ssupported",
576 (priv->hw_padding ? "" : "not "));
578 priv_get_num_vfs(priv, &num_vfs);
579 priv->sriov = (num_vfs || sriov);
580 if (priv->mps && !mps) {
581 ERROR("multi-packet send not supported on this device"
582 " (" MLX5_TXQ_MPW_EN ")");
586 /* Allocate and register default RSS hash keys. */
587 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
588 sizeof((*priv->rss_conf)[0]), 0);
589 if (priv->rss_conf == NULL) {
593 err = rss_hash_rss_conf_new_key(priv,
594 rss_hash_default_key,
595 rss_hash_default_key_len,
599 /* Configure the first MAC address by default. */
600 if (priv_get_mac(priv, &mac.addr_bytes)) {
601 ERROR("cannot get MAC address, is mlx5_en loaded?"
602 " (errno: %s)", strerror(errno));
605 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
607 mac.addr_bytes[0], mac.addr_bytes[1],
608 mac.addr_bytes[2], mac.addr_bytes[3],
609 mac.addr_bytes[4], mac.addr_bytes[5]);
610 /* Register MAC address. */
611 claim_zero(priv_mac_addr_add(priv, 0,
612 (const uint8_t (*)[ETHER_ADDR_LEN])
614 /* Initialize FD filters list. */
615 err = fdir_init_filters_list(priv);
620 char ifname[IF_NAMESIZE];
622 if (priv_get_ifname(priv, &ifname) == 0)
623 DEBUG("port %u ifname is \"%s\"",
626 DEBUG("port %u ifname is unknown", priv->port);
629 /* Get actual MTU if possible. */
630 priv_get_mtu(priv, &priv->mtu);
631 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
633 /* from rte_ethdev.c */
635 char name[RTE_ETH_NAME_MAX_LEN];
637 snprintf(name, sizeof(name), "%s port %u",
638 ibv_get_device_name(ibv_dev), port);
639 eth_dev = rte_eth_dev_allocate(name);
641 if (eth_dev == NULL) {
642 ERROR("can not allocate rte ethdev");
647 /* Secondary processes have to use local storage for their
648 * private data as well as a copy of eth_dev->data, but this
649 * pointer must not be modified before burst functions are
650 * actually called. */
651 if (mlx5_is_secondary()) {
652 struct mlx5_secondary_data *sd =
653 &mlx5_secondary_data[eth_dev->data->port_id];
654 sd->primary_priv = eth_dev->data->dev_private;
655 if (sd->primary_priv == NULL) {
656 ERROR("no private data for port %u",
657 eth_dev->data->port_id);
661 sd->shared_dev_data = eth_dev->data;
662 rte_spinlock_init(&sd->lock);
663 memcpy(sd->data.name, sd->shared_dev_data->name,
664 sizeof(sd->data.name));
665 sd->data.dev_private = priv;
666 sd->data.rx_mbuf_alloc_failed = 0;
667 sd->data.mtu = ETHER_MTU;
668 sd->data.port_id = sd->shared_dev_data->port_id;
669 sd->data.mac_addrs = priv->mac;
670 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup;
671 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup;
673 eth_dev->data->dev_private = priv;
674 eth_dev->data->mac_addrs = priv->mac;
677 eth_dev->device = &pci_dev->device;
678 rte_eth_copy_pci_info(eth_dev, pci_dev);
679 eth_dev->driver = &mlx5_driver;
681 eth_dev->dev_ops = &mlx5_dev_ops;
683 /* Bring Ethernet device up. */
684 DEBUG("forcing Ethernet interface up");
685 priv_set_flags(priv, ~IFF_UP, IFF_UP);
686 mlx5_link_update(priv->dev, 1);
691 rte_free(priv->rss_conf);
695 claim_zero(ibv_dealloc_pd(pd));
697 claim_zero(ibv_close_device(ctx));
702 * XXX if something went wrong in the loop above, there is a resource
703 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
704 * long as the dpdk does not provide a way to deallocate a ethdev and a
705 * way to enumerate the registered ethdevs to free the previous ones.
708 /* no port found, complain */
709 if (!mlx5_dev[idx].ports) {
716 claim_zero(ibv_close_device(attr_ctx));
718 ibv_free_device_list(list);
723 static const struct rte_pci_id mlx5_pci_id_map[] = {
725 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
726 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
729 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
730 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
733 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
734 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
737 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
738 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
741 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
742 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
745 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
746 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
749 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
750 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
753 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
754 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
761 static struct eth_driver mlx5_driver = {
764 .name = MLX5_DRIVER_NAME
766 .id_table = mlx5_pci_id_map,
767 .probe = mlx5_pci_probe,
768 .drv_flags = RTE_PCI_DRV_INTR_LSC,
770 .dev_private_size = sizeof(struct priv)
774 * Driver initialization routine.
776 RTE_INIT(rte_mlx5_pmd_init);
778 rte_mlx5_pmd_init(void)
781 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
782 * huge pages. Calling ibv_fork_init() during init allows
783 * applications to use fork() safely for purposes other than
784 * using this PMD, which is not supported in forked processes.
786 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
788 rte_eal_pci_register(&mlx5_driver.pci_drv);
791 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
792 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
793 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");