1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
268 .size = sizeof(struct mlx5_flow_meter),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_meter_ipool",
279 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_mcp_ipool",
290 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_hrxq_ipool",
302 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
303 * It set in run time according to PCI function configuration.
311 .malloc = mlx5_malloc,
313 .type = "mlx5_flow_handle_ipool",
316 .size = sizeof(struct rte_flow),
320 .malloc = mlx5_malloc,
322 .type = "rte_flow_ipool",
327 .type = "mlx5_flow_rss_id_ipool",
332 .type = "mlx5_flow_tnl_flow_ipool",
337 .type = "mlx5_flow_tnl_tbl_ipool",
340 .size = sizeof(struct mlx5_shared_action_rss),
346 .malloc = mlx5_malloc,
348 .type = "mlx5_shared_action_rss",
354 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
355 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
357 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
360 * Initialize the ASO aging management structure.
363 * Pointer to mlx5_dev_ctx_shared object to free
366 * 0 on success, a negative errno value otherwise and rte_errno is set.
369 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
375 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
376 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
377 if (!sh->aso_age_mng) {
378 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
382 err = mlx5_aso_queue_init(sh);
384 mlx5_free(sh->aso_age_mng);
387 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
388 rte_spinlock_init(&sh->aso_age_mng->free_sl);
389 LIST_INIT(&sh->aso_age_mng->free);
394 * Close and release all the resources of the ASO aging management structure.
397 * Pointer to mlx5_dev_ctx_shared object to free.
400 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
404 mlx5_aso_queue_stop(sh);
405 mlx5_aso_queue_uninit(sh);
406 if (sh->aso_age_mng->pools) {
407 struct mlx5_aso_age_pool *pool;
409 for (i = 0; i < sh->aso_age_mng->next; ++i) {
410 pool = sh->aso_age_mng->pools[i];
411 claim_zero(mlx5_devx_cmd_destroy
412 (pool->flow_hit_aso_obj));
413 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
414 if (pool->actions[j].dr_action)
416 (mlx5_glue->destroy_flow_action
417 (pool->actions[j].dr_action));
420 mlx5_free(sh->aso_age_mng->pools);
422 memset(&sh->aso_age_mng, 0, sizeof(sh->aso_age_mng));
426 * Initialize the shared aging list information per port.
429 * Pointer to mlx5_dev_ctx_shared object.
432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
435 struct mlx5_age_info *age_info;
437 for (i = 0; i < sh->max_port; i++) {
438 age_info = &sh->port[i].age_info;
440 TAILQ_INIT(&age_info->aged_counters);
441 rte_spinlock_init(&age_info->aged_sl);
442 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
447 * Initialize the counters management structure.
450 * Pointer to mlx5_dev_ctx_shared object to free
453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
457 memset(&sh->cmng, 0, sizeof(sh->cmng));
458 TAILQ_INIT(&sh->cmng.flow_counters);
459 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
460 sh->cmng.max_id = -1;
461 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
462 rte_spinlock_init(&sh->cmng.pool_update_sl);
463 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
464 TAILQ_INIT(&sh->cmng.counters[i]);
465 rte_spinlock_init(&sh->cmng.csl[i]);
470 * Destroy all the resources allocated for a counter memory management.
473 * Pointer to the memory management structure.
476 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
478 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
480 LIST_REMOVE(mng, next);
481 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
482 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
487 * Close and release all the resources of the counters management.
490 * Pointer to mlx5_dev_ctx_shared object to free.
493 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
495 struct mlx5_counter_stats_mem_mng *mng;
501 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
502 if (rte_errno != EINPROGRESS)
507 if (sh->cmng.pools) {
508 struct mlx5_flow_counter_pool *pool;
509 uint16_t n_valid = sh->cmng.n_valid;
510 bool fallback = sh->cmng.counter_fallback;
512 for (i = 0; i < n_valid; ++i) {
513 pool = sh->cmng.pools[i];
514 if (!fallback && pool->min_dcs)
515 claim_zero(mlx5_devx_cmd_destroy
517 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
518 struct mlx5_flow_counter *cnt =
519 MLX5_POOL_GET_CNT(pool, j);
523 (mlx5_glue->destroy_flow_action
525 if (fallback && MLX5_POOL_GET_CNT
526 (pool, j)->dcs_when_free)
527 claim_zero(mlx5_devx_cmd_destroy
528 (cnt->dcs_when_free));
532 mlx5_free(sh->cmng.pools);
534 mng = LIST_FIRST(&sh->cmng.mem_mngs);
536 mlx5_flow_destroy_counter_stat_mem_mng(mng);
537 mng = LIST_FIRST(&sh->cmng.mem_mngs);
539 memset(&sh->cmng, 0, sizeof(sh->cmng));
542 /* Send FLOW_AGED event if needed. */
544 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
546 struct mlx5_age_info *age_info;
549 for (i = 0; i < sh->max_port; i++) {
550 age_info = &sh->port[i].age_info;
551 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
553 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
554 rte_eth_dev_callback_process
555 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
556 RTE_ETH_EVENT_FLOW_AGED, NULL);
562 * Initialize the flow resources' indexed mempool.
565 * Pointer to mlx5_dev_ctx_shared object.
567 * Pointer to user dev config.
570 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
571 const struct mlx5_dev_config *config)
574 struct mlx5_indexed_pool_config cfg;
576 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
577 cfg = mlx5_ipool_cfg[i];
582 * Set MLX5_IPOOL_MLX5_FLOW ipool size
583 * according to PCI function flow configuration.
585 case MLX5_IPOOL_MLX5_FLOW:
586 cfg.size = config->dv_flow_en ?
587 sizeof(struct mlx5_flow_handle) :
588 MLX5_FLOW_HANDLE_VERBS_SIZE;
591 if (config->reclaim_mode)
592 cfg.release_mem_en = 1;
593 sh->ipool[i] = mlx5_ipool_create(&cfg);
598 * Release the flow resources' indexed mempool.
601 * Pointer to mlx5_dev_ctx_shared object.
604 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
608 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
609 mlx5_ipool_destroy(sh->ipool[i]);
613 * Check if dynamic flex parser for eCPRI already exists.
616 * Pointer to Ethernet device structure.
619 * true on exists, false on not.
622 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
624 struct mlx5_priv *priv = dev->data->dev_private;
625 struct mlx5_flex_parser_profiles *prf =
626 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
632 * Allocation of a flex parser for eCPRI. Once created, this parser related
633 * resources will be held until the device is closed.
636 * Pointer to Ethernet device structure.
639 * 0 on success, a negative errno value otherwise and rte_errno is set.
642 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
644 struct mlx5_priv *priv = dev->data->dev_private;
645 struct mlx5_flex_parser_profiles *prf =
646 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
647 struct mlx5_devx_graph_node_attr node = {
648 .modify_field_select = 0,
653 if (!priv->config.hca_attr.parse_graph_flex_node) {
654 DRV_LOG(ERR, "Dynamic flex parser is not supported "
655 "for device %s.", priv->dev_data->name);
658 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
659 /* 8 bytes now: 4B common header + 4B message body header. */
660 node.header_length_base_value = 0x8;
661 /* After MAC layer: Ether / VLAN. */
662 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
663 /* Type of compared condition should be 0xAEFE in the L2 layer. */
664 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
665 /* Sample #0: type in common header. */
666 node.sample[0].flow_match_sample_en = 1;
668 node.sample[0].flow_match_sample_offset_mode = 0x0;
669 /* Only the 2nd byte will be used. */
670 node.sample[0].flow_match_sample_field_base_offset = 0x0;
671 /* Sample #1: message payload. */
672 node.sample[1].flow_match_sample_en = 1;
674 node.sample[1].flow_match_sample_offset_mode = 0x0;
676 * Only the first two bytes will be used right now, and its offset will
677 * start after the common header that with the length of a DW(u32).
679 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
680 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
682 DRV_LOG(ERR, "Failed to create flex parser node object.");
683 return (rte_errno == 0) ? -ENODEV : -rte_errno;
686 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
688 DRV_LOG(ERR, "Failed to query sample IDs.");
689 return (rte_errno == 0) ? -ENODEV : -rte_errno;
691 prf->offset[0] = 0x0;
692 prf->offset[1] = sizeof(uint32_t);
693 prf->ids[0] = ids[0];
694 prf->ids[1] = ids[1];
699 * Destroy the flex parser node, including the parser itself, input / output
700 * arcs and DW samples. Resources could be reused then.
703 * Pointer to Ethernet device structure.
706 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
708 struct mlx5_priv *priv = dev->data->dev_private;
709 struct mlx5_flex_parser_profiles *prf =
710 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
713 mlx5_devx_cmd_destroy(prf->obj);
718 * Allocate Rx and Tx UARs in robust fashion.
719 * This routine handles the following UAR allocation issues:
721 * - tries to allocate the UAR with the most appropriate memory
722 * mapping type from the ones supported by the host
724 * - tries to allocate the UAR with non-NULL base address
725 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
726 * UAR base address if UAR was not the first object in the UAR page.
727 * It caused the PMD failure and we should try to get another UAR
728 * till we get the first one with non-NULL base address returned.
731 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
732 const struct mlx5_dev_config *config)
734 uint32_t uar_mapping, retry;
738 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
739 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
740 /* Control the mapping type according to the settings. */
741 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
742 MLX5DV_UAR_ALLOC_TYPE_NC :
743 MLX5DV_UAR_ALLOC_TYPE_BF;
745 RTE_SET_USED(config);
747 * It seems we have no way to control the memory mapping type
748 * for the UAR, the default "Write-Combining" type is supposed.
749 * The UAR initialization on queue creation queries the
750 * actual mapping type done by Verbs/kernel and setups the
751 * PMD datapath accordingly.
755 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
756 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
758 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
759 if (config->dbnc == MLX5_TXDB_CACHED ||
760 config->dbnc == MLX5_TXDB_HEURISTIC)
761 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
762 "is not supported by DevX");
764 * In some environments like virtual machine
765 * the Write Combining mapped might be not supported
766 * and UAR allocation fails. We try "Non-Cached"
767 * mapping for the case. The tx_burst routines take
768 * the UAR mapping type into account on UAR setup
771 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
772 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
773 sh->tx_uar = mlx5_glue->devx_alloc_uar
774 (sh->ctx, uar_mapping);
775 } else if (!sh->tx_uar &&
776 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
777 if (config->dbnc == MLX5_TXDB_NCACHED)
778 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
779 "is not supported by DevX");
781 * If Verbs/kernel does not support "Non-Cached"
782 * try the "Write-Combining".
784 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
785 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
786 sh->tx_uar = mlx5_glue->devx_alloc_uar
787 (sh->ctx, uar_mapping);
791 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
795 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
799 * The UARs are allocated by rdma_core within the
800 * IB device context, on context closure all UARs
801 * will be freed, should be no memory/object leakage.
803 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
806 /* Check whether we finally succeeded with valid UAR allocation. */
808 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
812 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
814 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
815 (sh->ctx, uar_mapping);
816 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
817 if (!sh->devx_rx_uar &&
818 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
820 * Rx UAR is used to control interrupts only,
821 * should be no datapath noticeable impact,
822 * can try "Non-Cached" mapping safely.
824 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
825 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
826 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
827 (sh->ctx, uar_mapping);
830 if (!sh->devx_rx_uar) {
831 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
835 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
839 * The UARs are allocated by rdma_core within the
840 * IB device context, on context closure all UARs
841 * will be freed, should be no memory/object leakage.
843 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
844 sh->devx_rx_uar = NULL;
846 /* Check whether we finally succeeded with valid UAR allocation. */
847 if (!sh->devx_rx_uar) {
848 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
856 * Allocate shared device context. If there is multiport device the
857 * master and representors will share this context, if there is single
858 * port dedicated device, the context will be used by only given
859 * port due to unification.
861 * Routine first searches the context for the specified device name,
862 * if found the shared context assumed and reference counter is incremented.
863 * If no context found the new one is created and initialized with specified
864 * device context and parameters.
867 * Pointer to the device attributes (name, port, etc).
869 * Pointer to device configuration structure.
872 * Pointer to mlx5_dev_ctx_shared object on success,
873 * otherwise NULL and rte_errno is set.
875 struct mlx5_dev_ctx_shared *
876 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
877 const struct mlx5_dev_config *config)
879 struct mlx5_dev_ctx_shared *sh;
882 struct mlx5_devx_tis_attr tis_attr = { 0 };
885 /* Secondary process should not create the shared context. */
886 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
887 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
888 /* Search for IB context by device name. */
889 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
890 if (!strcmp(sh->ibdev_name,
891 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
896 /* No device found, we have to create new shared context. */
897 MLX5_ASSERT(spawn->max_port);
898 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
899 sizeof(struct mlx5_dev_ctx_shared) +
901 sizeof(struct mlx5_dev_shared_port),
902 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
904 DRV_LOG(ERR, "shared context allocation failure");
908 err = mlx5_os_open_device(spawn, config, sh);
911 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
913 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
917 sh->max_port = spawn->max_port;
918 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
919 sizeof(sh->ibdev_name) - 1);
920 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
921 sizeof(sh->ibdev_path) - 1);
923 * Setting port_id to max unallowed value means
924 * there is no interrupt subhandler installed for
925 * the given port index i.
927 for (i = 0; i < sh->max_port; i++) {
928 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
929 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
931 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
932 if (sh->pd == NULL) {
933 DRV_LOG(ERR, "PD allocation failure");
938 /* Query the EQN for this core. */
939 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
942 DRV_LOG(ERR, "Failed to query event queue number %d.",
946 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
948 DRV_LOG(ERR, "Fail to extract pdn from PD");
951 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
953 DRV_LOG(ERR, "TD allocation failure");
957 tis_attr.transport_domain = sh->td->id;
958 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
960 DRV_LOG(ERR, "TIS allocation failure");
964 err = mlx5_alloc_rxtx_uars(sh, config);
967 MLX5_ASSERT(sh->tx_uar);
968 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
970 MLX5_ASSERT(sh->devx_rx_uar);
971 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
974 /* Initialize UAR access locks for 32bit implementations. */
975 rte_spinlock_init(&sh->uar_lock_cq);
976 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
977 rte_spinlock_init(&sh->uar_lock[i]);
980 * Once the device is added to the list of memory event
981 * callback, its global MR cache table cannot be expanded
982 * on the fly because of deadlock. If it overflows, lookup
983 * should be done by searching MR list linearly, which is slow.
985 * At this point the device is not added to the memory
986 * event list yet, context is just being created.
988 err = mlx5_mr_btree_init(&sh->share_cache.cache,
989 MLX5_MR_BTREE_CACHE_N * 2,
990 spawn->pci_dev->device.numa_node);
995 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
996 &sh->share_cache.dereg_mr_cb);
997 mlx5_os_dev_shared_handler_install(sh);
998 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
999 if (!sh->cnt_id_tbl) {
1003 mlx5_flow_aging_init(sh);
1004 mlx5_flow_counters_mng_init(sh);
1005 mlx5_flow_ipool_create(sh, config);
1006 /* Add device to memory callback list. */
1007 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1008 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1010 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1011 /* Add context to the global device list. */
1012 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1014 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1017 pthread_mutex_destroy(&sh->txpp.mutex);
1018 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1021 mlx5_l3t_destroy(sh->cnt_id_tbl);
1023 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1025 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1026 if (sh->devx_rx_uar)
1027 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1029 mlx5_glue->devx_free_uar(sh->tx_uar);
1031 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1033 claim_zero(mlx5_glue->close_device(sh->ctx));
1035 MLX5_ASSERT(err > 0);
1041 * Free shared IB device context. Decrement counter and if zero free
1042 * all allocated resources and close handles.
1045 * Pointer to mlx5_dev_ctx_shared object to free
1048 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1050 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1051 #ifdef RTE_LIBRTE_MLX5_DEBUG
1052 /* Check the object presence in the list. */
1053 struct mlx5_dev_ctx_shared *lctx;
1055 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1060 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1065 MLX5_ASSERT(sh->refcnt);
1066 /* Secondary process should not free the shared context. */
1067 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1070 /* Remove from memory callback device list. */
1071 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1072 LIST_REMOVE(sh, mem_event_cb);
1073 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1074 /* Release created Memory Regions. */
1075 mlx5_mr_release_cache(&sh->share_cache);
1076 /* Remove context from the global device list. */
1077 LIST_REMOVE(sh, next);
1078 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1080 * Ensure there is no async event handler installed.
1081 * Only primary process handles async device events.
1083 mlx5_flow_counters_mng_close(sh);
1084 if (sh->aso_age_mng) {
1085 mlx5_flow_aso_age_mng_close(sh);
1086 sh->aso_age_mng = NULL;
1088 mlx5_flow_ipool_destroy(sh);
1089 mlx5_os_dev_shared_handler_uninstall(sh);
1090 if (sh->cnt_id_tbl) {
1091 mlx5_l3t_destroy(sh->cnt_id_tbl);
1092 sh->cnt_id_tbl = NULL;
1095 mlx5_glue->devx_free_uar(sh->tx_uar);
1099 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1101 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1103 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1104 if (sh->devx_rx_uar)
1105 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1107 claim_zero(mlx5_glue->close_device(sh->ctx));
1108 pthread_mutex_destroy(&sh->txpp.mutex);
1112 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1116 * Destroy table hash list.
1119 * Pointer to the private device data structure.
1122 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1124 struct mlx5_dev_ctx_shared *sh = priv->sh;
1128 mlx5_hlist_destroy(sh->flow_tbls);
1132 * Initialize flow table hash list and create the root tables entry
1136 * Pointer to the private device data structure.
1139 * Zero on success, positive error code otherwise.
1142 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1145 /* Tables are only used in DV and DR modes. */
1146 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1147 struct mlx5_dev_ctx_shared *sh = priv->sh;
1148 char s[MLX5_HLIST_NAMESIZE];
1151 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1152 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1153 0, 0, flow_dv_tbl_create_cb, NULL,
1154 flow_dv_tbl_remove_cb);
1155 if (!sh->flow_tbls) {
1156 DRV_LOG(ERR, "flow tables with hash creation failed.");
1160 sh->flow_tbls->ctx = sh;
1161 #ifndef HAVE_MLX5DV_DR
1162 struct rte_flow_error error;
1163 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1166 * In case we have not DR support, the zero tables should be created
1167 * because DV expect to see them even if they cannot be created by
1170 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1171 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1172 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1178 mlx5_free_table_hash_list(priv);
1179 #endif /* HAVE_MLX5DV_DR */
1185 * Retrieve integer value from environment variable.
1188 * Environment variable name.
1191 * Integer value, 0 if the variable is not set.
1194 mlx5_getenv_int(const char *name)
1196 const char *val = getenv(name);
1204 * DPDK callback to add udp tunnel port
1207 * A pointer to eth_dev
1208 * @param[in] udp_tunnel
1209 * A pointer to udp tunnel
1212 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1215 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1216 struct rte_eth_udp_tunnel *udp_tunnel)
1218 MLX5_ASSERT(udp_tunnel != NULL);
1219 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1220 udp_tunnel->udp_port == 4789)
1222 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1223 udp_tunnel->udp_port == 4790)
1229 * Initialize process private data structure.
1232 * Pointer to Ethernet device structure.
1235 * 0 on success, a negative errno value otherwise and rte_errno is set.
1238 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1240 struct mlx5_priv *priv = dev->data->dev_private;
1241 struct mlx5_proc_priv *ppriv;
1245 * UAR register table follows the process private structure. BlueFlame
1246 * registers for Tx queues are stored in the table.
1249 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1250 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1251 dev->device->numa_node);
1256 ppriv->uar_table_sz = ppriv_size;
1257 dev->process_private = ppriv;
1262 * Un-initialize process private data structure.
1265 * Pointer to Ethernet device structure.
1268 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1270 if (!dev->process_private)
1272 mlx5_free(dev->process_private);
1273 dev->process_private = NULL;
1277 * DPDK callback to close the device.
1279 * Destroy all queues and objects, free memory.
1282 * Pointer to Ethernet device structure.
1285 mlx5_dev_close(struct rte_eth_dev *dev)
1287 struct mlx5_priv *priv = dev->data->dev_private;
1291 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1292 /* Check if process_private released. */
1293 if (!dev->process_private)
1295 mlx5_tx_uar_uninit_secondary(dev);
1296 mlx5_proc_priv_uninit(dev);
1297 rte_eth_dev_release_port(dev);
1302 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1304 ((priv->sh->ctx != NULL) ?
1305 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1307 * If default mreg copy action is removed at the stop stage,
1308 * the search will return none and nothing will be done anymore.
1310 mlx5_flow_stop_default(dev);
1311 mlx5_traffic_disable(dev);
1313 * If all the flows are already flushed in the device stop stage,
1314 * then this will return directly without any action.
1316 mlx5_flow_list_flush(dev, &priv->flows, true);
1317 mlx5_shared_action_flush(dev);
1318 mlx5_flow_meter_flush(dev, NULL);
1319 /* Prevent crashes when queues are still in use. */
1320 dev->rx_pkt_burst = removed_rx_burst;
1321 dev->tx_pkt_burst = removed_tx_burst;
1323 /* Disable datapath on secondary process. */
1324 mlx5_mp_os_req_stop_rxtx(dev);
1325 /* Free the eCPRI flex parser resource. */
1326 mlx5_flex_parser_ecpri_release(dev);
1327 if (priv->rxqs != NULL) {
1328 /* XXX race condition if mlx5_rx_burst() is still running. */
1330 for (i = 0; (i != priv->rxqs_n); ++i)
1331 mlx5_rxq_release(dev, i);
1335 if (priv->txqs != NULL) {
1336 /* XXX race condition if mlx5_tx_burst() is still running. */
1338 for (i = 0; (i != priv->txqs_n); ++i)
1339 mlx5_txq_release(dev, i);
1343 mlx5_proc_priv_uninit(dev);
1344 if (priv->drop_queue.hrxq)
1345 mlx5_drop_action_destroy(dev);
1346 if (priv->mreg_cp_tbl)
1347 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1348 mlx5_mprq_free_mp(dev);
1349 mlx5_os_free_shared_dr(priv);
1350 if (priv->rss_conf.rss_key != NULL)
1351 mlx5_free(priv->rss_conf.rss_key);
1352 if (priv->reta_idx != NULL)
1353 mlx5_free(priv->reta_idx);
1354 if (priv->config.vf)
1355 mlx5_os_mac_addr_flush(dev);
1356 if (priv->nl_socket_route >= 0)
1357 close(priv->nl_socket_route);
1358 if (priv->nl_socket_rdma >= 0)
1359 close(priv->nl_socket_rdma);
1360 if (priv->vmwa_context)
1361 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1362 ret = mlx5_hrxq_verify(dev);
1364 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1365 dev->data->port_id);
1366 ret = mlx5_ind_table_obj_verify(dev);
1368 DRV_LOG(WARNING, "port %u some indirection table still remain",
1369 dev->data->port_id);
1370 ret = mlx5_rxq_obj_verify(dev);
1372 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1373 dev->data->port_id);
1374 ret = mlx5_rxq_verify(dev);
1376 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1377 dev->data->port_id);
1378 ret = mlx5_txq_obj_verify(dev);
1380 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1381 dev->data->port_id);
1382 ret = mlx5_txq_verify(dev);
1384 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1385 dev->data->port_id);
1386 ret = mlx5_flow_verify(dev);
1388 DRV_LOG(WARNING, "port %u some flows still remain",
1389 dev->data->port_id);
1390 mlx5_cache_list_destroy(&priv->hrxqs);
1392 * Free the shared context in last turn, because the cleanup
1393 * routines above may use some shared fields, like
1394 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1395 * ifindex if Netlink fails.
1397 mlx5_free_shared_dev_ctx(priv->sh);
1398 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1402 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1403 struct mlx5_priv *opriv =
1404 rte_eth_devices[port_id].data->dev_private;
1407 opriv->domain_id != priv->domain_id ||
1408 &rte_eth_devices[port_id] == dev)
1414 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1416 memset(priv, 0, sizeof(*priv));
1417 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1419 * Reset mac_addrs to NULL such that it is not freed as part of
1420 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1421 * it is freed when dev_private is freed.
1423 dev->data->mac_addrs = NULL;
1428 * Verify and store value for device argument.
1431 * Key argument to verify.
1433 * Value associated with key.
1438 * 0 on success, a negative errno value otherwise and rte_errno is set.
1441 mlx5_args_check(const char *key, const char *val, void *opaque)
1443 struct mlx5_dev_config *config = opaque;
1447 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1448 if (!strcmp(MLX5_REPRESENTOR, key))
1451 tmp = strtol(val, NULL, 0);
1454 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1457 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1458 /* Negative values are acceptable for some keys only. */
1460 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1463 mod = tmp >= 0 ? tmp : -tmp;
1464 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1465 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1466 DRV_LOG(ERR, "invalid CQE compression "
1467 "format parameter");
1471 config->cqe_comp = !!tmp;
1472 config->cqe_comp_fmt = tmp;
1473 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1474 config->cqe_pad = !!tmp;
1475 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1476 config->hw_padding = !!tmp;
1477 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1478 config->mprq.enabled = !!tmp;
1479 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1480 config->mprq.stride_num_n = tmp;
1481 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1482 config->mprq.stride_size_n = tmp;
1483 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1484 config->mprq.max_memcpy_len = tmp;
1485 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1486 config->mprq.min_rxqs_num = tmp;
1487 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1488 DRV_LOG(WARNING, "%s: deprecated parameter,"
1489 " converted to txq_inline_max", key);
1490 config->txq_inline_max = tmp;
1491 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1492 config->txq_inline_max = tmp;
1493 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1494 config->txq_inline_min = tmp;
1495 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1496 config->txq_inline_mpw = tmp;
1497 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1498 config->txqs_inline = tmp;
1499 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1500 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1501 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1502 config->mps = !!tmp;
1503 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1504 if (tmp != MLX5_TXDB_CACHED &&
1505 tmp != MLX5_TXDB_NCACHED &&
1506 tmp != MLX5_TXDB_HEURISTIC) {
1507 DRV_LOG(ERR, "invalid Tx doorbell "
1508 "mapping parameter");
1513 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1514 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1515 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1516 DRV_LOG(WARNING, "%s: deprecated parameter,"
1517 " converted to txq_inline_mpw", key);
1518 config->txq_inline_mpw = tmp;
1519 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1520 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1521 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1523 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1527 config->tx_pp = tmp;
1528 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1529 config->tx_skew = tmp;
1530 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1531 config->rx_vec_en = !!tmp;
1532 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1533 config->l3_vxlan_en = !!tmp;
1534 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1535 config->vf_nl_en = !!tmp;
1536 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1537 config->dv_esw_en = !!tmp;
1538 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1539 config->dv_flow_en = !!tmp;
1540 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1541 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1542 tmp != MLX5_XMETA_MODE_META16 &&
1543 tmp != MLX5_XMETA_MODE_META32 &&
1544 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1545 DRV_LOG(ERR, "invalid extensive "
1546 "metadata parameter");
1550 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1551 config->dv_xmeta_en = tmp;
1553 config->dv_miss_info = 1;
1554 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1555 config->lacp_by_user = !!tmp;
1556 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1557 config->mr_ext_memseg_en = !!tmp;
1558 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1559 config->max_dump_files_num = tmp;
1560 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1561 config->lro.timeout = tmp;
1562 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1563 DRV_LOG(DEBUG, "class argument is %s.", val);
1564 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1565 config->log_hp_size = tmp;
1566 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1567 if (tmp != MLX5_RCM_NONE &&
1568 tmp != MLX5_RCM_LIGHT &&
1569 tmp != MLX5_RCM_AGGR) {
1570 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1574 config->reclaim_mode = tmp;
1575 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1576 config->sys_mem_en = !!tmp;
1577 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1578 config->decap_en = !!tmp;
1580 DRV_LOG(WARNING, "%s: unknown parameter", key);
1588 * Parse device parameters.
1591 * Pointer to device configuration structure.
1593 * Device arguments structure.
1596 * 0 on success, a negative errno value otherwise and rte_errno is set.
1599 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1601 const char **params = (const char *[]){
1602 MLX5_RXQ_CQE_COMP_EN,
1603 MLX5_RXQ_CQE_PAD_EN,
1604 MLX5_RXQ_PKT_PAD_EN,
1606 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1607 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1608 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1611 MLX5_TXQ_INLINE_MIN,
1612 MLX5_TXQ_INLINE_MAX,
1613 MLX5_TXQ_INLINE_MPW,
1614 MLX5_TXQS_MIN_INLINE,
1617 MLX5_TXQ_MPW_HDR_DSEG_EN,
1618 MLX5_TXQ_MAX_INLINE_LEN,
1630 MLX5_MR_EXT_MEMSEG_EN,
1632 MLX5_MAX_DUMP_FILES_NUM,
1633 MLX5_LRO_TIMEOUT_USEC,
1634 MLX5_CLASS_ARG_NAME,
1641 struct rte_kvargs *kvlist;
1645 if (devargs == NULL)
1647 /* Following UGLY cast is done to pass checkpatch. */
1648 kvlist = rte_kvargs_parse(devargs->args, params);
1649 if (kvlist == NULL) {
1653 /* Process parameters. */
1654 for (i = 0; (params[i] != NULL); ++i) {
1655 if (rte_kvargs_count(kvlist, params[i])) {
1656 ret = rte_kvargs_process(kvlist, params[i],
1657 mlx5_args_check, config);
1660 rte_kvargs_free(kvlist);
1665 rte_kvargs_free(kvlist);
1670 * Configures the minimal amount of data to inline into WQE
1671 * while sending packets.
1673 * - the txq_inline_min has the maximal priority, if this
1674 * key is specified in devargs
1675 * - if DevX is enabled the inline mode is queried from the
1676 * device (HCA attributes and NIC vport context if needed).
1677 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1678 * and none (0 bytes) for other NICs
1681 * Verbs device parameters (name, port, switch_info) to spawn.
1683 * Device configuration parameters.
1686 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1687 struct mlx5_dev_config *config)
1689 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1690 /* Application defines size of inlined data explicitly. */
1691 switch (spawn->pci_dev->id.device_id) {
1692 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1693 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1694 if (config->txq_inline_min <
1695 (int)MLX5_INLINE_HSIZE_L2) {
1697 "txq_inline_mix aligned to minimal"
1698 " ConnectX-4 required value %d",
1699 (int)MLX5_INLINE_HSIZE_L2);
1700 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1706 if (config->hca_attr.eth_net_offloads) {
1707 /* We have DevX enabled, inline mode queried successfully. */
1708 switch (config->hca_attr.wqe_inline_mode) {
1709 case MLX5_CAP_INLINE_MODE_L2:
1710 /* outer L2 header must be inlined. */
1711 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1713 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1714 /* No inline data are required by NIC. */
1715 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1716 config->hw_vlan_insert =
1717 config->hca_attr.wqe_vlan_insert;
1718 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1720 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1721 /* inline mode is defined by NIC vport context. */
1722 if (!config->hca_attr.eth_virt)
1724 switch (config->hca_attr.vport_inline_mode) {
1725 case MLX5_INLINE_MODE_NONE:
1726 config->txq_inline_min =
1727 MLX5_INLINE_HSIZE_NONE;
1729 case MLX5_INLINE_MODE_L2:
1730 config->txq_inline_min =
1731 MLX5_INLINE_HSIZE_L2;
1733 case MLX5_INLINE_MODE_IP:
1734 config->txq_inline_min =
1735 MLX5_INLINE_HSIZE_L3;
1737 case MLX5_INLINE_MODE_TCP_UDP:
1738 config->txq_inline_min =
1739 MLX5_INLINE_HSIZE_L4;
1741 case MLX5_INLINE_MODE_INNER_L2:
1742 config->txq_inline_min =
1743 MLX5_INLINE_HSIZE_INNER_L2;
1745 case MLX5_INLINE_MODE_INNER_IP:
1746 config->txq_inline_min =
1747 MLX5_INLINE_HSIZE_INNER_L3;
1749 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1750 config->txq_inline_min =
1751 MLX5_INLINE_HSIZE_INNER_L4;
1757 * We get here if we are unable to deduce
1758 * inline data size with DevX. Try PCI ID
1759 * to determine old NICs.
1761 switch (spawn->pci_dev->id.device_id) {
1762 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1763 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1764 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1765 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1766 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1767 config->hw_vlan_insert = 0;
1769 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1770 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1771 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1772 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1774 * These NICs support VLAN insertion from WQE and
1775 * report the wqe_vlan_insert flag. But there is the bug
1776 * and PFC control may be broken, so disable feature.
1778 config->hw_vlan_insert = 0;
1779 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1782 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1786 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1790 * Configures the metadata mask fields in the shared context.
1793 * Pointer to Ethernet device.
1796 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1798 struct mlx5_priv *priv = dev->data->dev_private;
1799 struct mlx5_dev_ctx_shared *sh = priv->sh;
1800 uint32_t meta, mark, reg_c0;
1802 reg_c0 = ~priv->vport_meta_mask;
1803 switch (priv->config.dv_xmeta_en) {
1804 case MLX5_XMETA_MODE_LEGACY:
1806 mark = MLX5_FLOW_MARK_MASK;
1808 case MLX5_XMETA_MODE_META16:
1809 meta = reg_c0 >> rte_bsf32(reg_c0);
1810 mark = MLX5_FLOW_MARK_MASK;
1812 case MLX5_XMETA_MODE_META32:
1814 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1822 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1823 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1824 sh->dv_mark_mask, mark);
1826 sh->dv_mark_mask = mark;
1827 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1828 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1829 sh->dv_meta_mask, meta);
1831 sh->dv_meta_mask = meta;
1832 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1833 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1834 sh->dv_meta_mask, reg_c0);
1836 sh->dv_regc0_mask = reg_c0;
1837 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1838 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1839 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1840 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1844 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1846 static const char *const dynf_names[] = {
1847 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1848 RTE_MBUF_DYNFLAG_METADATA_NAME,
1849 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1853 if (n < RTE_DIM(dynf_names))
1855 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1856 if (names[i] == NULL)
1858 strcpy(names[i], dynf_names[i]);
1860 return RTE_DIM(dynf_names);
1864 * Comparison callback to sort device data.
1866 * This is meant to be used with qsort().
1869 * Pointer to pointer to first data object.
1871 * Pointer to pointer to second data object.
1874 * 0 if both objects are equal, less than 0 if the first argument is less
1875 * than the second, greater than 0 otherwise.
1878 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1879 struct mlx5_dev_config *config)
1881 struct mlx5_dev_ctx_shared *sh = priv->sh;
1882 struct mlx5_dev_config *sh_conf = NULL;
1886 /* Nothing to compare for the single/first device. */
1887 if (sh->refcnt == 1)
1889 /* Find the device with shared context. */
1890 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1891 struct mlx5_priv *opriv =
1892 rte_eth_devices[port_id].data->dev_private;
1894 if (opriv && opriv != priv && opriv->sh == sh) {
1895 sh_conf = &opriv->config;
1901 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1902 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1903 " for shared %s context", sh->ibdev_name);
1907 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1908 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1909 " for shared %s context", sh->ibdev_name);
1917 * Look for the ethernet device belonging to mlx5 driver.
1919 * @param[in] port_id
1920 * port_id to start looking for device.
1921 * @param[in] pci_dev
1922 * Pointer to the hint PCI device. When device is being probed
1923 * the its siblings (master and preceding representors might
1924 * not have assigned driver yet (because the mlx5_os_pci_probe()
1925 * is not completed yet, for this case match on hint PCI
1926 * device may be used to detect sibling device.
1929 * port_id of found device, RTE_MAX_ETHPORT if not found.
1932 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1934 while (port_id < RTE_MAX_ETHPORTS) {
1935 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1937 if (dev->state != RTE_ETH_DEV_UNUSED &&
1939 (dev->device == &pci_dev->device ||
1940 (dev->device->driver &&
1941 dev->device->driver->name &&
1942 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1946 if (port_id >= RTE_MAX_ETHPORTS)
1947 return RTE_MAX_ETHPORTS;
1952 * DPDK callback to remove a PCI device.
1954 * This function removes all Ethernet devices belong to a given PCI device.
1956 * @param[in] pci_dev
1957 * Pointer to the PCI device.
1960 * 0 on success, the function cannot fail.
1963 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1968 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1970 * mlx5_dev_close() is not registered to secondary process,
1971 * call the close function explicitly for secondary process.
1973 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1974 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1976 ret |= rte_eth_dev_close(port_id);
1978 return ret == 0 ? 0 : -EIO;
1981 static const struct rte_pci_id mlx5_pci_id_map[] = {
1983 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1987 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1991 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1995 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2015 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2019 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2023 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2059 static struct mlx5_pci_driver mlx5_driver = {
2060 .driver_class = MLX5_CLASS_NET,
2063 .name = MLX5_DRIVER_NAME,
2065 .id_table = mlx5_pci_id_map,
2066 .probe = mlx5_os_pci_probe,
2067 .remove = mlx5_pci_remove,
2068 .dma_map = mlx5_dma_map,
2069 .dma_unmap = mlx5_dma_unmap,
2070 .drv_flags = PCI_DRV_FLAGS,
2074 /* Initialize driver log type. */
2075 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2078 * Driver initialization routine.
2080 RTE_INIT(rte_mlx5_pmd_init)
2083 /* Build the static tables for Verbs conversion. */
2084 mlx5_set_ptype_table();
2085 mlx5_set_cksum_table();
2086 mlx5_set_swp_types_table();
2088 mlx5_pci_driver_register(&mlx5_driver);
2091 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2092 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2093 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");