1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
37 #include <rte_rwlock.h>
38 #include <rte_spinlock.h>
41 #include "mlx5_utils.h"
42 #include "mlx5_rxtx.h"
43 #include "mlx5_autoconf.h"
44 #include "mlx5_defs.h"
45 #include "mlx5_glue.h"
48 /* Device parameter to enable RX completion queue compression. */
49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
58 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
60 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
61 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
63 /* Device parameter to configure inline send. */
64 #define MLX5_TXQ_INLINE "txq_inline"
67 * Device parameter to configure the number of TX queues threshold for
68 * enabling inline send.
70 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
72 /* Device parameter to enable multi-packet send WQEs. */
73 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
75 /* Device parameter to include 2 dsegs in the title WQEBB. */
76 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
78 /* Device parameter to limit the size of inlining packet. */
79 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
81 /* Device parameter to enable hardware Tx vector. */
82 #define MLX5_TX_VEC_EN "tx_vec_en"
84 /* Device parameter to enable hardware Rx vector. */
85 #define MLX5_RX_VEC_EN "rx_vec_en"
87 /* Allow L3 VXLAN flow creation. */
88 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
90 /* Activate Netlink support in VF mode. */
91 #define MLX5_VF_NL_EN "vf_nl_en"
93 #ifndef HAVE_IBV_MLX5_MOD_MPW
94 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
95 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
98 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
99 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
102 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
104 /* Shared memory between primary and secondary processes. */
105 struct mlx5_shared_data *mlx5_shared_data;
107 /* Spinlock for mlx5_shared_data allocation. */
108 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
110 /** Driver-specific log messages type. */
114 * Prepare shared data between primary and secondary process.
117 mlx5_prepare_shared_data(void)
119 const struct rte_memzone *mz;
121 rte_spinlock_lock(&mlx5_shared_data_lock);
122 if (mlx5_shared_data == NULL) {
123 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
124 /* Allocate shared memory. */
125 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
126 sizeof(*mlx5_shared_data),
129 /* Lookup allocated shared memory. */
130 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
133 rte_panic("Cannot allocate mlx5 shared data\n");
134 mlx5_shared_data = mz->addr;
135 /* Initialize shared data. */
136 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
137 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
138 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
140 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
141 mlx5_mr_mem_event_cb, NULL);
143 rte_spinlock_unlock(&mlx5_shared_data_lock);
147 * Retrieve integer value from environment variable.
150 * Environment variable name.
153 * Integer value, 0 if the variable is not set.
156 mlx5_getenv_int(const char *name)
158 const char *val = getenv(name);
166 * Verbs callback to allocate a memory. This function should allocate the space
167 * according to the size provided residing inside a huge page.
168 * Please note that all allocation must respect the alignment from libmlx5
169 * (i.e. currently sysconf(_SC_PAGESIZE)).
172 * The size in bytes of the memory to allocate.
174 * A pointer to the callback data.
177 * Allocated buffer, NULL otherwise and rte_errno is set.
180 mlx5_alloc_verbs_buf(size_t size, void *data)
182 struct priv *priv = data;
184 size_t alignment = sysconf(_SC_PAGESIZE);
185 unsigned int socket = SOCKET_ID_ANY;
187 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
188 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
190 socket = ctrl->socket;
191 } else if (priv->verbs_alloc_ctx.type ==
192 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
193 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
195 socket = ctrl->socket;
197 assert(data != NULL);
198 ret = rte_malloc_socket(__func__, size, alignment, socket);
205 * Verbs callback to free a memory.
208 * A pointer to the memory to free.
210 * A pointer to the callback data.
213 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
215 assert(data != NULL);
220 * DPDK callback to close the device.
222 * Destroy all queues and objects, free memory.
225 * Pointer to Ethernet device structure.
228 mlx5_dev_close(struct rte_eth_dev *dev)
230 struct priv *priv = dev->data->dev_private;
234 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
236 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
237 /* In case mlx5_dev_stop() has not been called. */
238 mlx5_dev_interrupt_handler_uninstall(dev);
239 mlx5_traffic_disable(dev);
240 /* Prevent crashes when queues are still in use. */
241 dev->rx_pkt_burst = removed_rx_burst;
242 dev->tx_pkt_burst = removed_tx_burst;
243 if (priv->rxqs != NULL) {
244 /* XXX race condition if mlx5_rx_burst() is still running. */
246 for (i = 0; (i != priv->rxqs_n); ++i)
247 mlx5_rxq_release(dev, i);
251 if (priv->txqs != NULL) {
252 /* XXX race condition if mlx5_tx_burst() is still running. */
254 for (i = 0; (i != priv->txqs_n); ++i)
255 mlx5_txq_release(dev, i);
259 mlx5_flow_delete_drop_queue(dev);
260 mlx5_mprq_free_mp(dev);
261 mlx5_mr_release(dev);
262 if (priv->pd != NULL) {
263 assert(priv->ctx != NULL);
264 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
265 claim_zero(mlx5_glue->close_device(priv->ctx));
267 assert(priv->ctx == NULL);
268 if (priv->rss_conf.rss_key != NULL)
269 rte_free(priv->rss_conf.rss_key);
270 if (priv->reta_idx != NULL)
271 rte_free(priv->reta_idx);
272 if (priv->primary_socket)
273 mlx5_socket_uninit(dev);
275 mlx5_nl_mac_addr_flush(dev);
276 if (priv->nl_socket >= 0)
277 close(priv->nl_socket);
278 ret = mlx5_hrxq_ibv_verify(dev);
280 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
282 ret = mlx5_ind_table_ibv_verify(dev);
284 DRV_LOG(WARNING, "port %u some indirection table still remain",
286 ret = mlx5_rxq_ibv_verify(dev);
288 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
290 ret = mlx5_rxq_verify(dev);
292 DRV_LOG(WARNING, "port %u some Rx queues still remain",
294 ret = mlx5_txq_ibv_verify(dev);
296 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
298 ret = mlx5_txq_verify(dev);
300 DRV_LOG(WARNING, "port %u some Tx queues still remain",
302 ret = mlx5_flow_verify(dev);
304 DRV_LOG(WARNING, "port %u some flows still remain",
306 memset(priv, 0, sizeof(*priv));
309 const struct eth_dev_ops mlx5_dev_ops = {
310 .dev_configure = mlx5_dev_configure,
311 .dev_start = mlx5_dev_start,
312 .dev_stop = mlx5_dev_stop,
313 .dev_set_link_down = mlx5_set_link_down,
314 .dev_set_link_up = mlx5_set_link_up,
315 .dev_close = mlx5_dev_close,
316 .promiscuous_enable = mlx5_promiscuous_enable,
317 .promiscuous_disable = mlx5_promiscuous_disable,
318 .allmulticast_enable = mlx5_allmulticast_enable,
319 .allmulticast_disable = mlx5_allmulticast_disable,
320 .link_update = mlx5_link_update,
321 .stats_get = mlx5_stats_get,
322 .stats_reset = mlx5_stats_reset,
323 .xstats_get = mlx5_xstats_get,
324 .xstats_reset = mlx5_xstats_reset,
325 .xstats_get_names = mlx5_xstats_get_names,
326 .dev_infos_get = mlx5_dev_infos_get,
327 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
328 .vlan_filter_set = mlx5_vlan_filter_set,
329 .rx_queue_setup = mlx5_rx_queue_setup,
330 .tx_queue_setup = mlx5_tx_queue_setup,
331 .rx_queue_release = mlx5_rx_queue_release,
332 .tx_queue_release = mlx5_tx_queue_release,
333 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
334 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
335 .mac_addr_remove = mlx5_mac_addr_remove,
336 .mac_addr_add = mlx5_mac_addr_add,
337 .mac_addr_set = mlx5_mac_addr_set,
338 .set_mc_addr_list = mlx5_set_mc_addr_list,
339 .mtu_set = mlx5_dev_set_mtu,
340 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
341 .vlan_offload_set = mlx5_vlan_offload_set,
342 .reta_update = mlx5_dev_rss_reta_update,
343 .reta_query = mlx5_dev_rss_reta_query,
344 .rss_hash_update = mlx5_rss_hash_update,
345 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
346 .filter_ctrl = mlx5_dev_filter_ctrl,
347 .rx_descriptor_status = mlx5_rx_descriptor_status,
348 .tx_descriptor_status = mlx5_tx_descriptor_status,
349 .rx_queue_intr_enable = mlx5_rx_intr_enable,
350 .rx_queue_intr_disable = mlx5_rx_intr_disable,
351 .is_removed = mlx5_is_removed,
354 static const struct eth_dev_ops mlx5_dev_sec_ops = {
355 .stats_get = mlx5_stats_get,
356 .stats_reset = mlx5_stats_reset,
357 .xstats_get = mlx5_xstats_get,
358 .xstats_reset = mlx5_xstats_reset,
359 .xstats_get_names = mlx5_xstats_get_names,
360 .dev_infos_get = mlx5_dev_infos_get,
361 .rx_descriptor_status = mlx5_rx_descriptor_status,
362 .tx_descriptor_status = mlx5_tx_descriptor_status,
365 /* Available operators in flow isolated mode. */
366 const struct eth_dev_ops mlx5_dev_ops_isolate = {
367 .dev_configure = mlx5_dev_configure,
368 .dev_start = mlx5_dev_start,
369 .dev_stop = mlx5_dev_stop,
370 .dev_set_link_down = mlx5_set_link_down,
371 .dev_set_link_up = mlx5_set_link_up,
372 .dev_close = mlx5_dev_close,
373 .link_update = mlx5_link_update,
374 .stats_get = mlx5_stats_get,
375 .stats_reset = mlx5_stats_reset,
376 .xstats_get = mlx5_xstats_get,
377 .xstats_reset = mlx5_xstats_reset,
378 .xstats_get_names = mlx5_xstats_get_names,
379 .dev_infos_get = mlx5_dev_infos_get,
380 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
381 .vlan_filter_set = mlx5_vlan_filter_set,
382 .rx_queue_setup = mlx5_rx_queue_setup,
383 .tx_queue_setup = mlx5_tx_queue_setup,
384 .rx_queue_release = mlx5_rx_queue_release,
385 .tx_queue_release = mlx5_tx_queue_release,
386 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
387 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
388 .mac_addr_remove = mlx5_mac_addr_remove,
389 .mac_addr_add = mlx5_mac_addr_add,
390 .mac_addr_set = mlx5_mac_addr_set,
391 .set_mc_addr_list = mlx5_set_mc_addr_list,
392 .mtu_set = mlx5_dev_set_mtu,
393 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
394 .vlan_offload_set = mlx5_vlan_offload_set,
395 .filter_ctrl = mlx5_dev_filter_ctrl,
396 .rx_descriptor_status = mlx5_rx_descriptor_status,
397 .tx_descriptor_status = mlx5_tx_descriptor_status,
398 .rx_queue_intr_enable = mlx5_rx_intr_enable,
399 .rx_queue_intr_disable = mlx5_rx_intr_disable,
400 .is_removed = mlx5_is_removed,
404 struct rte_pci_addr pci_addr; /* associated PCI address */
405 uint32_t ports; /* physical ports bitfield. */
409 * Get device index in mlx5_dev[] from PCI bus address.
411 * @param[in] pci_addr
412 * PCI bus address to look for.
415 * mlx5_dev[] index on success, -1 on failure.
418 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
423 assert(pci_addr != NULL);
424 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
425 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
426 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
427 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
428 (mlx5_dev[i].pci_addr.function == pci_addr->function))
430 if ((mlx5_dev[i].ports == 0) && (ret == -1))
437 * Verify and store value for device argument.
440 * Key argument to verify.
442 * Value associated with key.
447 * 0 on success, a negative errno value otherwise and rte_errno is set.
450 mlx5_args_check(const char *key, const char *val, void *opaque)
452 struct mlx5_dev_config *config = opaque;
456 tmp = strtoul(val, NULL, 0);
459 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
462 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
463 config->cqe_comp = !!tmp;
464 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
465 config->mprq.enabled = !!tmp;
466 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
467 config->mprq.stride_num_n = tmp;
468 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
469 config->mprq.max_memcpy_len = tmp;
470 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
471 config->mprq.min_rxqs_num = tmp;
472 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
473 config->txq_inline = tmp;
474 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
475 config->txqs_inline = tmp;
476 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
477 config->mps = !!tmp ? config->mps : 0;
478 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
479 config->mpw_hdr_dseg = !!tmp;
480 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
481 config->inline_max_packet_sz = tmp;
482 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
483 config->tx_vec_en = !!tmp;
484 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
485 config->rx_vec_en = !!tmp;
486 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
487 config->l3_vxlan_en = !!tmp;
488 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
489 config->vf_nl_en = !!tmp;
491 DRV_LOG(WARNING, "%s: unknown parameter", key);
499 * Parse device parameters.
502 * Pointer to device configuration structure.
504 * Device arguments structure.
507 * 0 on success, a negative errno value otherwise and rte_errno is set.
510 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
512 const char **params = (const char *[]){
513 MLX5_RXQ_CQE_COMP_EN,
515 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
516 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
519 MLX5_TXQS_MIN_INLINE,
521 MLX5_TXQ_MPW_HDR_DSEG_EN,
522 MLX5_TXQ_MAX_INLINE_LEN,
529 struct rte_kvargs *kvlist;
535 /* Following UGLY cast is done to pass checkpatch. */
536 kvlist = rte_kvargs_parse(devargs->args, params);
539 /* Process parameters. */
540 for (i = 0; (params[i] != NULL); ++i) {
541 if (rte_kvargs_count(kvlist, params[i])) {
542 ret = rte_kvargs_process(kvlist, params[i],
543 mlx5_args_check, config);
546 rte_kvargs_free(kvlist);
551 rte_kvargs_free(kvlist);
555 static struct rte_pci_driver mlx5_driver;
558 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
559 * local resource used by both primary and secondary to avoid duplicate
561 * The space has to be available on both primary and secondary process,
562 * TXQ UAR maps to this area using fixed mmap w/o double check.
564 static void *uar_base;
567 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
568 const struct rte_memseg *ms, void *arg)
575 *addr = RTE_MIN(*addr, ms->addr);
581 * Reserve UAR address space for primary process.
584 * Pointer to Ethernet device.
587 * 0 on success, a negative errno value otherwise and rte_errno is set.
590 mlx5_uar_init_primary(struct rte_eth_dev *dev)
592 struct priv *priv = dev->data->dev_private;
593 void *addr = (void *)0;
595 if (uar_base) { /* UAR address space mapped. */
596 priv->uar_base = uar_base;
599 /* find out lower bound of hugepage segments */
600 rte_memseg_walk(find_lower_va_bound, &addr);
602 /* keep distance to hugepages to minimize potential conflicts. */
603 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
604 /* anonymous mmap, no real memory consumption. */
605 addr = mmap(addr, MLX5_UAR_SIZE,
606 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
607 if (addr == MAP_FAILED) {
609 "port %u failed to reserve UAR address space, please"
610 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
615 /* Accept either same addr or a new addr returned from mmap if target
618 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
619 dev->data->port_id, addr);
620 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
621 uar_base = addr; /* process local, don't reserve again. */
626 * Reserve UAR address space for secondary process, align with
630 * Pointer to Ethernet device.
633 * 0 on success, a negative errno value otherwise and rte_errno is set.
636 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
638 struct priv *priv = dev->data->dev_private;
641 assert(priv->uar_base);
642 if (uar_base) { /* already reserved. */
643 assert(uar_base == priv->uar_base);
646 /* anonymous mmap, no real memory consumption. */
647 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
648 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
649 if (addr == MAP_FAILED) {
650 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
651 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
655 if (priv->uar_base != addr) {
657 "port %u UAR address %p size %llu occupied, please"
658 " adjust MLX5_UAR_OFFSET or try EAL parameter"
660 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
664 uar_base = addr; /* process local, don't reserve again */
665 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
666 dev->data->port_id, addr);
671 * DPDK callback to register a PCI device.
673 * This function creates an Ethernet device for each port of a given
677 * PCI driver structure (mlx5_driver).
679 * PCI device information.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
686 struct rte_pci_device *pci_dev)
688 struct ibv_device **list = NULL;
689 struct ibv_device *ibv_dev;
691 struct ibv_context *attr_ctx = NULL;
692 struct ibv_device_attr_ex device_attr;
695 unsigned int cqe_comp;
696 unsigned int tunnel_en = 0;
697 unsigned int mpls_en = 0;
698 unsigned int swp = 0;
699 unsigned int verb_priorities = 0;
700 unsigned int mprq = 0;
701 unsigned int mprq_min_stride_size_n = 0;
702 unsigned int mprq_max_stride_size_n = 0;
703 unsigned int mprq_min_stride_num_n = 0;
704 unsigned int mprq_max_stride_num_n = 0;
707 struct mlx5dv_context attrs_out = {0};
708 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
709 struct ibv_counter_set_description cs_desc;
712 /* Prepare shared data between primary and secondary process. */
713 mlx5_prepare_shared_data();
714 assert(pci_drv == &mlx5_driver);
715 /* Get mlx5_dev[] index. */
716 idx = mlx5_dev_idx(&pci_dev->addr);
718 DRV_LOG(ERR, "this driver cannot support any more adapters");
722 DRV_LOG(DEBUG, "using driver device index %d", idx);
723 /* Save PCI address. */
724 mlx5_dev[idx].pci_addr = pci_dev->addr;
725 list = mlx5_glue->get_device_list(&i);
731 "cannot list devices, is ib_uverbs loaded?");
736 * For each listed device, check related sysfs entry against
737 * the provided PCI ID.
740 struct rte_pci_addr pci_addr;
743 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
744 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
746 if ((pci_dev->addr.domain != pci_addr.domain) ||
747 (pci_dev->addr.bus != pci_addr.bus) ||
748 (pci_dev->addr.devid != pci_addr.devid) ||
749 (pci_dev->addr.function != pci_addr.function))
751 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
753 vf = ((pci_dev->id.device_id ==
754 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
755 (pci_dev->id.device_id ==
756 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
757 (pci_dev->id.device_id ==
758 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
759 (pci_dev->id.device_id ==
760 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
761 attr_ctx = mlx5_glue->open_device(list[i]);
766 if (attr_ctx == NULL) {
770 "cannot access device, is mlx5_ib loaded?");
775 "cannot use device, are drivers up to date?");
781 DRV_LOG(DEBUG, "device opened");
782 #ifdef HAVE_IBV_MLX5_MOD_SWP
783 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
786 * Multi-packet send is supported by ConnectX-4 Lx PF as well
787 * as all ConnectX-5 devices.
789 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
790 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
792 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
793 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
795 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
796 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
797 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
798 DRV_LOG(DEBUG, "enhanced MPW is supported");
799 mps = MLX5_MPW_ENHANCED;
801 DRV_LOG(DEBUG, "MPW is supported");
805 DRV_LOG(DEBUG, "MPW isn't supported");
806 mps = MLX5_MPW_DISABLED;
808 #ifdef HAVE_IBV_MLX5_MOD_SWP
809 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
810 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
811 DRV_LOG(DEBUG, "SWP support: %u", swp);
813 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
814 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
815 struct mlx5dv_striding_rq_caps mprq_caps =
816 attrs_out.striding_rq_caps;
818 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
819 mprq_caps.min_single_stride_log_num_of_bytes);
820 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
821 mprq_caps.max_single_stride_log_num_of_bytes);
822 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
823 mprq_caps.min_single_wqe_log_num_of_strides);
824 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
825 mprq_caps.max_single_wqe_log_num_of_strides);
826 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
827 mprq_caps.supported_qpts);
828 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
830 mprq_min_stride_size_n =
831 mprq_caps.min_single_stride_log_num_of_bytes;
832 mprq_max_stride_size_n =
833 mprq_caps.max_single_stride_log_num_of_bytes;
834 mprq_min_stride_num_n =
835 mprq_caps.min_single_wqe_log_num_of_strides;
836 mprq_max_stride_num_n =
837 mprq_caps.max_single_wqe_log_num_of_strides;
840 if (RTE_CACHE_LINE_SIZE == 128 &&
841 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
845 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
846 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
847 tunnel_en = ((attrs_out.tunnel_offloads_caps &
848 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
849 (attrs_out.tunnel_offloads_caps &
850 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
852 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
853 tunnel_en ? "" : "not ");
856 "tunnel offloading disabled due to old OFED/rdma-core version");
858 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
859 mpls_en = ((attrs_out.tunnel_offloads_caps &
860 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
861 (attrs_out.tunnel_offloads_caps &
862 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
863 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
864 mpls_en ? "" : "not ");
866 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
867 " old OFED/rdma-core version or firmware configuration");
869 err = mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr);
871 DEBUG("ibv_query_device_ex() failed");
874 DRV_LOG(INFO, "%u port(s) detected",
875 device_attr.orig_attr.phys_port_cnt);
876 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
877 char name[RTE_ETH_NAME_MAX_LEN];
879 uint32_t port = i + 1; /* ports are indexed from one */
880 uint32_t test = (1 << i);
881 struct ibv_context *ctx = NULL;
882 struct ibv_port_attr port_attr;
883 struct ibv_pd *pd = NULL;
884 struct priv *priv = NULL;
885 struct rte_eth_dev *eth_dev = NULL;
886 struct ibv_device_attr_ex device_attr_ex;
887 struct ether_addr mac;
888 struct mlx5_dev_config config = {
889 .cqe_comp = cqe_comp,
891 .tunnel_en = tunnel_en,
896 .txq_inline = MLX5_ARG_UNSET,
897 .txqs_inline = MLX5_ARG_UNSET,
898 .inline_max_packet_sz = MLX5_ARG_UNSET,
902 .enabled = 0, /* Disabled by default. */
903 .stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
904 mprq_min_stride_num_n),
905 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
906 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
910 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
911 pci_dev->addr.domain, pci_dev->addr.bus,
912 pci_dev->addr.devid, pci_dev->addr.function);
913 if (device_attr.orig_attr.phys_port_cnt > 1)
914 snprintf(name + len, sizeof(name), " port %u", i);
915 mlx5_dev[idx].ports |= test;
916 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
917 eth_dev = rte_eth_dev_attach_secondary(name);
918 if (eth_dev == NULL) {
919 DRV_LOG(ERR, "can not attach rte ethdev");
924 eth_dev->device = &pci_dev->device;
925 eth_dev->dev_ops = &mlx5_dev_sec_ops;
926 err = mlx5_uar_init_secondary(eth_dev);
931 /* Receive command fd from primary process */
932 err = mlx5_socket_connect(eth_dev);
937 /* Remap UAR for Tx queues. */
938 err = mlx5_tx_uar_remap(eth_dev, err);
944 * Ethdev pointer is still required as input since
945 * the primary device is not accessible from the
948 eth_dev->rx_pkt_burst =
949 mlx5_select_rx_function(eth_dev);
950 eth_dev->tx_pkt_burst =
951 mlx5_select_tx_function(eth_dev);
952 rte_eth_dev_probing_finish(eth_dev);
955 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
956 ctx = mlx5_glue->open_device(ibv_dev);
961 /* Check port status. */
962 err = mlx5_glue->query_port(ctx, port, &port_attr);
964 DRV_LOG(ERR, "port query failed: %s", strerror(err));
967 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
969 "port %d is not configured in Ethernet mode",
974 if (port_attr.state != IBV_PORT_ACTIVE)
975 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
977 mlx5_glue->port_state_str(port_attr.state),
979 /* Allocate protection domain. */
980 pd = mlx5_glue->alloc_pd(ctx);
982 DRV_LOG(ERR, "PD allocation failure");
986 mlx5_dev[idx].ports |= test;
987 /* from rte_ethdev.c */
988 priv = rte_zmalloc("ethdev private structure",
990 RTE_CACHE_LINE_SIZE);
992 DRV_LOG(ERR, "priv allocation failure");
997 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
998 sizeof(priv->ibdev_path));
999 priv->device_attr = device_attr;
1002 priv->mtu = ETHER_MTU;
1003 err = mlx5_args(&config, pci_dev->device.devargs);
1005 DRV_LOG(ERR, "failed to process device arguments: %s",
1010 err = mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex);
1012 DRV_LOG(ERR, "ibv_query_device_ex() failed");
1015 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
1016 IBV_DEVICE_RAW_IP_CSUM);
1017 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1018 (config.hw_csum ? "" : "not "));
1019 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1020 config.flow_counter_en = !!(device_attr.max_counter_sets);
1021 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1023 "counter type = %d, num of cs = %ld, attributes = %d",
1024 cs_desc.counter_type, cs_desc.num_of_cs,
1025 cs_desc.attributes);
1027 config.ind_table_max_size =
1028 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
1029 /* Remove this check once DPDK supports larger/variable
1030 * indirection tables. */
1031 if (config.ind_table_max_size >
1032 (unsigned int)ETH_RSS_RETA_SIZE_512)
1033 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1034 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1035 config.ind_table_max_size);
1036 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
1037 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1038 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1039 (config.hw_vlan_strip ? "" : "not "));
1041 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
1042 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1043 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1044 (config.hw_fcs_strip ? "" : "not "));
1046 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1047 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
1050 "hardware Rx end alignment padding is %ssupported",
1051 (config.hw_padding ? "" : "not "));
1053 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
1054 (device_attr_ex.tso_caps.supported_qpts &
1055 (1 << IBV_QPT_RAW_PACKET)));
1057 config.tso_max_payload_sz =
1058 device_attr_ex.tso_caps.max_tso;
1059 if (config.mps && !mps) {
1061 "multi-packet send not supported on this device"
1062 " (" MLX5_TXQ_MPW_EN ")");
1066 DRV_LOG(INFO, "%s MPS is %s",
1067 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1068 config.mps != MLX5_MPW_DISABLED ? "enabled" :
1070 if (config.cqe_comp && !cqe_comp) {
1071 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1072 config.cqe_comp = 0;
1074 config.mprq.enabled = config.mprq.enabled && mprq;
1075 if (config.mprq.enabled) {
1076 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1077 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1078 config.mprq.stride_num_n =
1079 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1080 mprq_min_stride_num_n);
1082 "the number of strides"
1083 " for Multi-Packet RQ is out of range,"
1084 " setting default value (%u)",
1085 1 << config.mprq.stride_num_n);
1087 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1088 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1090 eth_dev = rte_eth_dev_allocate(name);
1091 if (eth_dev == NULL) {
1092 DRV_LOG(ERR, "can not allocate rte ethdev");
1096 eth_dev->data->dev_private = priv;
1097 priv->dev_data = eth_dev->data;
1098 eth_dev->data->mac_addrs = priv->mac;
1099 eth_dev->device = &pci_dev->device;
1100 rte_eth_copy_pci_info(eth_dev, pci_dev);
1101 eth_dev->device->driver = &mlx5_driver.driver;
1102 err = mlx5_uar_init_primary(eth_dev);
1107 /* Configure the first MAC address by default. */
1108 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1110 "port %u cannot get MAC address, is mlx5_en"
1111 " loaded? (errno: %s)",
1112 eth_dev->data->port_id, strerror(errno));
1117 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1118 eth_dev->data->port_id,
1119 mac.addr_bytes[0], mac.addr_bytes[1],
1120 mac.addr_bytes[2], mac.addr_bytes[3],
1121 mac.addr_bytes[4], mac.addr_bytes[5]);
1124 char ifname[IF_NAMESIZE];
1126 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1127 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1128 eth_dev->data->port_id, ifname);
1130 DRV_LOG(DEBUG, "port %u ifname is unknown",
1131 eth_dev->data->port_id);
1134 /* Get actual MTU if possible. */
1135 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1140 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1143 * Initialize burst functions to prevent crashes before link-up.
1145 eth_dev->rx_pkt_burst = removed_rx_burst;
1146 eth_dev->tx_pkt_burst = removed_tx_burst;
1147 eth_dev->dev_ops = &mlx5_dev_ops;
1148 /* Register MAC address. */
1149 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1150 priv->nl_socket = -1;
1152 if (vf && config.vf_nl_en) {
1153 priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1154 if (priv->nl_socket < 0)
1155 priv->nl_socket = -1;
1156 mlx5_nl_mac_addr_sync(eth_dev);
1158 TAILQ_INIT(&priv->flows);
1159 TAILQ_INIT(&priv->ctrl_flows);
1160 /* Hint libmlx5 to use PMD allocator for data plane resources */
1161 struct mlx5dv_ctx_allocators alctr = {
1162 .alloc = &mlx5_alloc_verbs_buf,
1163 .free = &mlx5_free_verbs_buf,
1166 mlx5_glue->dv_set_context_attr(ctx,
1167 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1168 (void *)((uintptr_t)&alctr));
1169 /* Bring Ethernet device up. */
1170 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1171 eth_dev->data->port_id);
1172 mlx5_set_link_up(eth_dev);
1174 * Even though the interrupt handler is not installed yet,
1175 * interrupts will still trigger on the asyn_fd from
1176 * Verbs context returned by ibv_open_device().
1178 mlx5_link_update(eth_dev, 0);
1179 /* Store device configuration on private structure. */
1180 priv->config = config;
1181 /* Create drop queue. */
1182 err = mlx5_flow_create_drop_queue(eth_dev);
1184 DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1185 eth_dev->data->port_id, strerror(rte_errno));
1189 /* Supported Verbs flow priority number detection. */
1190 if (verb_priorities == 0)
1191 verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1192 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1193 DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1194 eth_dev->data->port_id, verb_priorities);
1197 priv->config.max_verbs_prio = verb_priorities;
1199 * Once the device is added to the list of memory event
1200 * callback, its global MR cache table cannot be expanded
1201 * on the fly because of deadlock. If it overflows, lookup
1202 * should be done by searching MR list linearly, which is slow.
1204 err = mlx5_mr_btree_init(&priv->mr.cache,
1205 MLX5_MR_BTREE_CACHE_N * 2,
1206 eth_dev->device->numa_node);
1211 /* Add device to memory callback list. */
1212 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1213 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1214 priv, mem_event_cb);
1215 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1216 rte_eth_dev_probing_finish(eth_dev);
1222 claim_zero(mlx5_glue->dealloc_pd(pd));
1224 claim_zero(mlx5_glue->close_device(ctx));
1225 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1226 rte_eth_dev_release_port(eth_dev);
1230 * XXX if something went wrong in the loop above, there is a resource
1231 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1232 * long as the dpdk does not provide a way to deallocate a ethdev and a
1233 * way to enumerate the registered ethdevs to free the previous ones.
1235 /* no port found, complain */
1236 if (!mlx5_dev[idx].ports) {
1242 claim_zero(mlx5_glue->close_device(attr_ctx));
1244 mlx5_glue->free_device_list(list);
1252 static const struct rte_pci_id mlx5_pci_id_map[] = {
1254 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1255 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1258 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1259 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1262 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1263 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1266 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1267 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1270 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1271 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1274 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1275 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1278 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1279 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1282 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1283 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1286 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1287 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1294 static struct rte_pci_driver mlx5_driver = {
1296 .name = MLX5_DRIVER_NAME
1298 .id_table = mlx5_pci_id_map,
1299 .probe = mlx5_pci_probe,
1300 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1303 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1306 * Suffix RTE_EAL_PMD_PATH with "-glue".
1308 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1309 * suffixing its last component.
1312 * Output buffer, should be large enough otherwise NULL is returned.
1317 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1320 mlx5_glue_path(char *buf, size_t size)
1322 static const char *const bad[] = { "/", ".", "..", NULL };
1323 const char *path = RTE_EAL_PMD_PATH;
1324 size_t len = strlen(path);
1328 while (len && path[len - 1] == '/')
1330 for (off = len; off && path[off - 1] != '/'; --off)
1332 for (i = 0; bad[i]; ++i)
1333 if (!strncmp(path + off, bad[i], (int)(len - off)))
1335 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1336 if (i == -1 || (size_t)i >= size)
1341 "unable to append \"-glue\" to last component of"
1342 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1343 " please re-configure DPDK");
1348 * Initialization routine for run-time dependency on rdma-core.
1351 mlx5_glue_init(void)
1353 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1354 const char *path[] = {
1356 * A basic security check is necessary before trusting
1357 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1359 (geteuid() == getuid() && getegid() == getgid() ?
1360 getenv("MLX5_GLUE_PATH") : NULL),
1362 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1363 * variant, otherwise let dlopen() look up libraries on its
1366 (*RTE_EAL_PMD_PATH ?
1367 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1370 void *handle = NULL;
1374 while (!handle && i != RTE_DIM(path)) {
1383 end = strpbrk(path[i], ":;");
1385 end = path[i] + strlen(path[i]);
1386 len = end - path[i];
1391 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1393 (!len || *(end - 1) == '/') ? "" : "/");
1396 if (sizeof(name) != (size_t)ret + 1)
1398 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1400 handle = dlopen(name, RTLD_LAZY);
1411 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1414 sym = dlsym(handle, "mlx5_glue");
1415 if (!sym || !*sym) {
1419 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1428 "cannot initialize PMD due to missing run-time dependency on"
1429 " rdma-core libraries (libibverbs, libmlx5)");
1436 * Driver initialization routine.
1438 RTE_INIT(rte_mlx5_pmd_init);
1440 rte_mlx5_pmd_init(void)
1442 /* Build the static tables for Verbs conversion. */
1443 mlx5_set_ptype_table();
1444 mlx5_set_cksum_table();
1445 mlx5_set_swp_types_table();
1447 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1448 * huge pages. Calling ibv_fork_init() during init allows
1449 * applications to use fork() safely for purposes other than
1450 * using this PMD, which is not supported in forked processes.
1452 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1453 /* Match the size of Rx completion entry to the size of a cacheline. */
1454 if (RTE_CACHE_LINE_SIZE == 128)
1455 setenv("MLX5_CQE_SIZE", "128", 0);
1456 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1457 if (mlx5_glue_init())
1462 /* Glue structure must not contain any NULL pointers. */
1466 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1467 assert(((const void *const *)mlx5_glue)[i]);
1470 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1472 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1473 mlx5_glue->version, MLX5_GLUE_VERSION);
1476 mlx5_glue->fork_init();
1477 rte_pci_register(&mlx5_driver);
1480 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1481 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1482 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1484 /** Initialize driver log type. */
1485 RTE_INIT(vdev_netvsc_init_log)
1487 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1488 if (mlx5_logtype >= 0)
1489 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);