4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_bus_pci.h>
58 #include <rte_common.h>
59 #include <rte_kvargs.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Device parameter to enable RX completion queue compression. */
68 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
70 /* Device parameter to configure inline send. */
71 #define MLX5_TXQ_INLINE "txq_inline"
74 * Device parameter to configure the number of TX queues threshold for
75 * enabling inline send.
77 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 /* Device parameter to enable multi-packet send WQEs. */
80 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
82 /* Device parameter to include 2 dsegs in the title WQEBB. */
83 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
85 /* Device parameter to limit the size of inlining packet. */
86 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
88 /* Device parameter to enable hardware TSO offload. */
89 #define MLX5_TSO "tso"
91 /* Device parameter to enable hardware Tx vector. */
92 #define MLX5_TX_VEC_EN "tx_vec_en"
94 /* Device parameter to enable hardware Rx vector. */
95 #define MLX5_RX_VEC_EN "rx_vec_en"
97 #ifndef HAVE_IBV_MLX5_MOD_MPW
98 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
99 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
102 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
103 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
107 * Retrieve integer value from environment variable.
110 * Environment variable name.
113 * Integer value, 0 if the variable is not set.
116 mlx5_getenv_int(const char *name)
118 const char *val = getenv(name);
126 * Verbs callback to allocate a memory. This function should allocate the space
127 * according to the size provided residing inside a huge page.
128 * Please note that all allocation must respect the alignment from libmlx5
129 * (i.e. currently sysconf(_SC_PAGESIZE)).
132 * The size in bytes of the memory to allocate.
134 * A pointer to the callback data.
137 * a pointer to the allocate space.
140 mlx5_alloc_verbs_buf(size_t size, void *data)
142 struct priv *priv = data;
144 size_t alignment = sysconf(_SC_PAGESIZE);
146 assert(data != NULL);
147 ret = rte_malloc_socket(__func__, size, alignment,
148 priv->dev->device->numa_node);
149 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
154 * Verbs callback to free a memory.
157 * A pointer to the memory to free.
159 * A pointer to the callback data.
162 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
164 assert(data != NULL);
165 DEBUG("Extern free request: %p", ptr);
170 * DPDK callback to close the device.
172 * Destroy all queues and objects, free memory.
175 * Pointer to Ethernet device structure.
178 mlx5_dev_close(struct rte_eth_dev *dev)
180 struct priv *priv = dev->data->dev_private;
185 DEBUG("%p: closing device \"%s\"",
187 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
188 /* In case mlx5_dev_stop() has not been called. */
189 priv_dev_interrupt_handler_uninstall(priv, dev);
190 priv_dev_traffic_disable(priv, dev);
191 /* Prevent crashes when queues are still in use. */
192 dev->rx_pkt_burst = removed_rx_burst;
193 dev->tx_pkt_burst = removed_tx_burst;
194 if (priv->rxqs != NULL) {
195 /* XXX race condition if mlx5_rx_burst() is still running. */
197 for (i = 0; (i != priv->rxqs_n); ++i)
198 mlx5_priv_rxq_release(priv, i);
202 if (priv->txqs != NULL) {
203 /* XXX race condition if mlx5_tx_burst() is still running. */
205 for (i = 0; (i != priv->txqs_n); ++i)
206 mlx5_priv_txq_release(priv, i);
210 if (priv->pd != NULL) {
211 assert(priv->ctx != NULL);
212 claim_zero(ibv_dealloc_pd(priv->pd));
213 claim_zero(ibv_close_device(priv->ctx));
215 assert(priv->ctx == NULL);
216 if (priv->rss_conf.rss_key != NULL)
217 rte_free(priv->rss_conf.rss_key);
218 if (priv->reta_idx != NULL)
219 rte_free(priv->reta_idx);
220 priv_socket_uninit(priv);
221 ret = mlx5_priv_hrxq_ibv_verify(priv);
223 WARN("%p: some Hash Rx queue still remain", (void *)priv);
224 ret = mlx5_priv_ind_table_ibv_verify(priv);
226 WARN("%p: some Indirection table still remain", (void *)priv);
227 ret = mlx5_priv_rxq_ibv_verify(priv);
229 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
230 ret = mlx5_priv_rxq_verify(priv);
232 WARN("%p: some Rx Queues still remain", (void *)priv);
233 ret = mlx5_priv_txq_ibv_verify(priv);
235 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
236 ret = mlx5_priv_txq_verify(priv);
238 WARN("%p: some Tx Queues still remain", (void *)priv);
239 ret = priv_flow_verify(priv);
241 WARN("%p: some flows still remain", (void *)priv);
242 ret = priv_mr_verify(priv);
244 WARN("%p: some Memory Region still remain", (void *)priv);
246 memset(priv, 0, sizeof(*priv));
249 const struct eth_dev_ops mlx5_dev_ops = {
250 .dev_configure = mlx5_dev_configure,
251 .dev_start = mlx5_dev_start,
252 .dev_stop = mlx5_dev_stop,
253 .dev_set_link_down = mlx5_set_link_down,
254 .dev_set_link_up = mlx5_set_link_up,
255 .dev_close = mlx5_dev_close,
256 .promiscuous_enable = mlx5_promiscuous_enable,
257 .promiscuous_disable = mlx5_promiscuous_disable,
258 .allmulticast_enable = mlx5_allmulticast_enable,
259 .allmulticast_disable = mlx5_allmulticast_disable,
260 .link_update = mlx5_link_update,
261 .stats_get = mlx5_stats_get,
262 .stats_reset = mlx5_stats_reset,
263 .xstats_get = mlx5_xstats_get,
264 .xstats_reset = mlx5_xstats_reset,
265 .xstats_get_names = mlx5_xstats_get_names,
266 .dev_infos_get = mlx5_dev_infos_get,
267 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
268 .vlan_filter_set = mlx5_vlan_filter_set,
269 .rx_queue_setup = mlx5_rx_queue_setup,
270 .tx_queue_setup = mlx5_tx_queue_setup,
271 .rx_queue_release = mlx5_rx_queue_release,
272 .tx_queue_release = mlx5_tx_queue_release,
273 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
274 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
275 .mac_addr_remove = mlx5_mac_addr_remove,
276 .mac_addr_add = mlx5_mac_addr_add,
277 .mac_addr_set = mlx5_mac_addr_set,
278 .mtu_set = mlx5_dev_set_mtu,
279 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
280 .vlan_offload_set = mlx5_vlan_offload_set,
281 .reta_update = mlx5_dev_rss_reta_update,
282 .reta_query = mlx5_dev_rss_reta_query,
283 .rss_hash_update = mlx5_rss_hash_update,
284 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
285 .filter_ctrl = mlx5_dev_filter_ctrl,
286 .rx_descriptor_status = mlx5_rx_descriptor_status,
287 .tx_descriptor_status = mlx5_tx_descriptor_status,
288 .rx_queue_intr_enable = mlx5_rx_intr_enable,
289 .rx_queue_intr_disable = mlx5_rx_intr_disable,
292 static const struct eth_dev_ops mlx5_dev_sec_ops = {
293 .stats_get = mlx5_stats_get,
294 .stats_reset = mlx5_stats_reset,
295 .xstats_get = mlx5_xstats_get,
296 .xstats_reset = mlx5_xstats_reset,
297 .xstats_get_names = mlx5_xstats_get_names,
298 .dev_infos_get = mlx5_dev_infos_get,
299 .rx_descriptor_status = mlx5_rx_descriptor_status,
300 .tx_descriptor_status = mlx5_tx_descriptor_status,
303 /* Available operators in flow isolated mode. */
304 const struct eth_dev_ops mlx5_dev_ops_isolate = {
305 .dev_configure = mlx5_dev_configure,
306 .dev_start = mlx5_dev_start,
307 .dev_stop = mlx5_dev_stop,
308 .dev_set_link_down = mlx5_set_link_down,
309 .dev_set_link_up = mlx5_set_link_up,
310 .dev_close = mlx5_dev_close,
311 .link_update = mlx5_link_update,
312 .stats_get = mlx5_stats_get,
313 .stats_reset = mlx5_stats_reset,
314 .xstats_get = mlx5_xstats_get,
315 .xstats_reset = mlx5_xstats_reset,
316 .xstats_get_names = mlx5_xstats_get_names,
317 .dev_infos_get = mlx5_dev_infos_get,
318 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
319 .vlan_filter_set = mlx5_vlan_filter_set,
320 .rx_queue_setup = mlx5_rx_queue_setup,
321 .tx_queue_setup = mlx5_tx_queue_setup,
322 .rx_queue_release = mlx5_rx_queue_release,
323 .tx_queue_release = mlx5_tx_queue_release,
324 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
325 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
326 .mac_addr_remove = mlx5_mac_addr_remove,
327 .mac_addr_add = mlx5_mac_addr_add,
328 .mac_addr_set = mlx5_mac_addr_set,
329 .mtu_set = mlx5_dev_set_mtu,
330 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
331 .vlan_offload_set = mlx5_vlan_offload_set,
332 .filter_ctrl = mlx5_dev_filter_ctrl,
333 .rx_descriptor_status = mlx5_rx_descriptor_status,
334 .tx_descriptor_status = mlx5_tx_descriptor_status,
335 .rx_queue_intr_enable = mlx5_rx_intr_enable,
336 .rx_queue_intr_disable = mlx5_rx_intr_disable,
340 struct rte_pci_addr pci_addr; /* associated PCI address */
341 uint32_t ports; /* physical ports bitfield. */
345 * Get device index in mlx5_dev[] from PCI bus address.
347 * @param[in] pci_addr
348 * PCI bus address to look for.
351 * mlx5_dev[] index on success, -1 on failure.
354 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
359 assert(pci_addr != NULL);
360 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
361 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
362 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
363 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
364 (mlx5_dev[i].pci_addr.function == pci_addr->function))
366 if ((mlx5_dev[i].ports == 0) && (ret == -1))
373 * Verify and store value for device argument.
376 * Key argument to verify.
378 * Value associated with key.
383 * 0 on success, negative errno value on failure.
386 mlx5_args_check(const char *key, const char *val, void *opaque)
388 struct mlx5_dev_config *config = opaque;
392 tmp = strtoul(val, NULL, 0);
394 WARN("%s: \"%s\" is not a valid integer", key, val);
397 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
398 config->cqe_comp = !!tmp;
399 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
400 config->txq_inline = tmp;
401 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
402 config->txqs_inline = tmp;
403 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
404 config->mps = !!tmp ? config->mps : 0;
405 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
406 config->mpw_hdr_dseg = !!tmp;
407 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
408 config->inline_max_packet_sz = tmp;
409 } else if (strcmp(MLX5_TSO, key) == 0) {
411 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
412 config->tx_vec_en = !!tmp;
413 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
414 config->rx_vec_en = !!tmp;
416 WARN("%s: unknown parameter", key);
423 * Parse device parameters.
426 * Pointer to device configuration structure.
428 * Device arguments structure.
431 * 0 on success, errno value on failure.
434 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
436 const char **params = (const char *[]){
437 MLX5_RXQ_CQE_COMP_EN,
439 MLX5_TXQS_MIN_INLINE,
441 MLX5_TXQ_MPW_HDR_DSEG_EN,
442 MLX5_TXQ_MAX_INLINE_LEN,
448 struct rte_kvargs *kvlist;
454 /* Following UGLY cast is done to pass checkpatch. */
455 kvlist = rte_kvargs_parse(devargs->args, params);
458 /* Process parameters. */
459 for (i = 0; (params[i] != NULL); ++i) {
460 if (rte_kvargs_count(kvlist, params[i])) {
461 ret = rte_kvargs_process(kvlist, params[i],
462 mlx5_args_check, config);
464 rte_kvargs_free(kvlist);
469 rte_kvargs_free(kvlist);
473 static struct rte_pci_driver mlx5_driver;
476 * DPDK callback to register a PCI device.
478 * This function creates an Ethernet device for each port of a given
482 * PCI driver structure (mlx5_driver).
484 * PCI device information.
487 * 0 on success, negative errno value on failure.
490 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
492 struct ibv_device **list;
493 struct ibv_device *ibv_dev;
495 struct ibv_context *attr_ctx = NULL;
496 struct ibv_device_attr_ex device_attr;
499 unsigned int cqe_comp;
500 unsigned int tunnel_en = 0;
503 struct mlx5dv_context attrs_out;
504 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
505 struct ibv_counter_set_description cs_desc;
509 assert(pci_drv == &mlx5_driver);
510 /* Get mlx5_dev[] index. */
511 idx = mlx5_dev_idx(&pci_dev->addr);
513 ERROR("this driver cannot support any more adapters");
516 DEBUG("using driver device index %d", idx);
518 /* Save PCI address. */
519 mlx5_dev[idx].pci_addr = pci_dev->addr;
520 list = ibv_get_device_list(&i);
524 ERROR("cannot list devices, is ib_uverbs loaded?");
529 * For each listed device, check related sysfs entry against
530 * the provided PCI ID.
533 struct rte_pci_addr pci_addr;
536 DEBUG("checking device \"%s\"", list[i]->name);
537 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
539 if ((pci_dev->addr.domain != pci_addr.domain) ||
540 (pci_dev->addr.bus != pci_addr.bus) ||
541 (pci_dev->addr.devid != pci_addr.devid) ||
542 (pci_dev->addr.function != pci_addr.function))
544 sriov = ((pci_dev->id.device_id ==
545 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
546 (pci_dev->id.device_id ==
547 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
548 (pci_dev->id.device_id ==
549 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
550 (pci_dev->id.device_id ==
551 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
552 switch (pci_dev->id.device_id) {
553 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
556 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
557 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
558 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
559 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
560 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
566 INFO("PCI information matches, using device \"%s\""
569 sriov ? "true" : "false");
570 attr_ctx = ibv_open_device(list[i]);
574 if (attr_ctx == NULL) {
575 ibv_free_device_list(list);
578 ERROR("cannot access device, is mlx5_ib loaded?");
581 ERROR("cannot use device, are drivers up to date?");
589 DEBUG("device opened");
591 * Multi-packet send is supported by ConnectX-4 Lx PF as well
592 * as all ConnectX-5 devices.
594 mlx5dv_query_device(attr_ctx, &attrs_out);
595 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
596 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
597 DEBUG("Enhanced MPW is supported");
598 mps = MLX5_MPW_ENHANCED;
600 DEBUG("MPW is supported");
604 DEBUG("MPW isn't supported");
605 mps = MLX5_MPW_DISABLED;
607 if (RTE_CACHE_LINE_SIZE == 128 &&
608 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
612 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
614 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
616 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
617 uint32_t port = i + 1; /* ports are indexed from one */
618 uint32_t test = (1 << i);
619 struct ibv_context *ctx = NULL;
620 struct ibv_port_attr port_attr;
621 struct ibv_pd *pd = NULL;
622 struct priv *priv = NULL;
623 struct rte_eth_dev *eth_dev;
624 struct ibv_device_attr_ex device_attr_ex;
625 struct ether_addr mac;
626 uint16_t num_vfs = 0;
627 struct ibv_device_attr_ex device_attr;
628 struct mlx5_dev_config config = {
629 .cqe_comp = cqe_comp,
631 .tunnel_en = tunnel_en,
636 .txq_inline = MLX5_ARG_UNSET,
637 .txqs_inline = MLX5_ARG_UNSET,
638 .inline_max_packet_sz = MLX5_ARG_UNSET,
641 mlx5_dev[idx].ports |= test;
643 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
644 /* from rte_ethdev.c */
645 char name[RTE_ETH_NAME_MAX_LEN];
647 snprintf(name, sizeof(name), "%s port %u",
648 ibv_get_device_name(ibv_dev), port);
649 eth_dev = rte_eth_dev_attach_secondary(name);
650 if (eth_dev == NULL) {
651 ERROR("can not attach rte ethdev");
655 eth_dev->device = &pci_dev->device;
656 eth_dev->dev_ops = &mlx5_dev_sec_ops;
657 priv = eth_dev->data->dev_private;
658 /* Receive command fd from primary process */
659 err = priv_socket_connect(priv);
664 /* Remap UAR for Tx queues. */
665 err = priv_tx_uar_remap(priv, err);
671 * Ethdev pointer is still required as input since
672 * the primary device is not accessible from the
675 eth_dev->rx_pkt_burst =
676 priv_select_rx_function(priv, eth_dev);
677 eth_dev->tx_pkt_burst =
678 priv_select_tx_function(priv, eth_dev);
682 DEBUG("using port %u (%08" PRIx32 ")", port, test);
684 ctx = ibv_open_device(ibv_dev);
690 ibv_query_device_ex(ctx, NULL, &device_attr);
691 /* Check port status. */
692 err = ibv_query_port(ctx, port, &port_attr);
694 ERROR("port query failed: %s", strerror(err));
698 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
699 ERROR("port %d is not configured in Ethernet mode",
705 if (port_attr.state != IBV_PORT_ACTIVE)
706 DEBUG("port %d is not active: \"%s\" (%d)",
707 port, ibv_port_state_str(port_attr.state),
710 /* Allocate protection domain. */
711 pd = ibv_alloc_pd(ctx);
713 ERROR("PD allocation failure");
718 mlx5_dev[idx].ports |= test;
720 /* from rte_ethdev.c */
721 priv = rte_zmalloc("ethdev private structure",
723 RTE_CACHE_LINE_SIZE);
725 ERROR("priv allocation failure");
731 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
732 sizeof(priv->ibdev_path));
733 priv->device_attr = device_attr;
736 priv->mtu = ETHER_MTU;
737 err = mlx5_args(&config, pci_dev->device.devargs);
739 ERROR("failed to process device arguments: %s",
743 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
744 ERROR("ibv_query_device_ex() failed");
748 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
749 IBV_DEVICE_RAW_IP_CSUM);
750 DEBUG("checksum offloading is %ssupported",
751 (config.hw_csum ? "" : "not "));
753 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
754 config.hw_csum_l2tun =
755 !!(exp_device_attr.exp_device_cap_flags &
756 IBV_DEVICE_VXLAN_SUPPORT);
758 DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
759 (config.hw_csum_l2tun ? "" : "not "));
761 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
762 config.flow_counter_en = !!(device_attr.max_counter_sets);
763 ibv_describe_counter_set(ctx, 0, &cs_desc);
764 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
765 cs_desc.counter_type, cs_desc.num_of_cs,
768 config.ind_table_max_size =
769 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
770 /* Remove this check once DPDK supports larger/variable
771 * indirection tables. */
772 if (config.ind_table_max_size >
773 (unsigned int)ETH_RSS_RETA_SIZE_512)
774 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
775 DEBUG("maximum RX indirection table size is %u",
776 config.ind_table_max_size);
777 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
778 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
779 DEBUG("VLAN stripping is %ssupported",
780 (config.hw_vlan_strip ? "" : "not "));
782 config.hw_fcs_strip =
783 !!(device_attr_ex.orig_attr.device_cap_flags &
784 IBV_WQ_FLAGS_SCATTER_FCS);
785 DEBUG("FCS stripping configuration is %ssupported",
786 (config.hw_fcs_strip ? "" : "not "));
788 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
789 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
791 DEBUG("hardware RX end alignment padding is %ssupported",
792 (config.hw_padding ? "" : "not "));
794 priv_get_num_vfs(priv, &num_vfs);
795 config.sriov = (num_vfs || sriov);
797 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
798 (device_attr_ex.tso_caps.supported_qpts &
799 (1 << IBV_QPT_RAW_PACKET)));
801 config.tso_max_payload_sz =
802 device_attr_ex.tso_caps.max_tso;
803 if (config.mps && !mps) {
804 ERROR("multi-packet send not supported on this device"
805 " (" MLX5_TXQ_MPW_EN ")");
808 } else if (config.mps && config.tso) {
809 WARN("multi-packet send not supported in conjunction "
810 "with TSO. MPS disabled");
814 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
815 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
816 if (config.cqe_comp && !cqe_comp) {
817 WARN("Rx CQE compression isn't supported");
820 /* Configure the first MAC address by default. */
821 if (priv_get_mac(priv, &mac.addr_bytes)) {
822 ERROR("cannot get MAC address, is mlx5_en loaded?"
823 " (errno: %s)", strerror(errno));
827 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
829 mac.addr_bytes[0], mac.addr_bytes[1],
830 mac.addr_bytes[2], mac.addr_bytes[3],
831 mac.addr_bytes[4], mac.addr_bytes[5]);
834 char ifname[IF_NAMESIZE];
836 if (priv_get_ifname(priv, &ifname) == 0)
837 DEBUG("port %u ifname is \"%s\"",
840 DEBUG("port %u ifname is unknown", priv->port);
843 /* Get actual MTU if possible. */
844 priv_get_mtu(priv, &priv->mtu);
845 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
847 /* from rte_ethdev.c */
849 char name[RTE_ETH_NAME_MAX_LEN];
851 snprintf(name, sizeof(name), "%s port %u",
852 ibv_get_device_name(ibv_dev), port);
853 eth_dev = rte_eth_dev_allocate(name);
855 if (eth_dev == NULL) {
856 ERROR("can not allocate rte ethdev");
860 eth_dev->data->dev_private = priv;
861 eth_dev->data->mac_addrs = priv->mac;
862 eth_dev->device = &pci_dev->device;
863 rte_eth_copy_pci_info(eth_dev, pci_dev);
864 eth_dev->device->driver = &mlx5_driver.driver;
866 eth_dev->dev_ops = &mlx5_dev_ops;
867 /* Register MAC address. */
868 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
869 TAILQ_INIT(&priv->flows);
870 TAILQ_INIT(&priv->ctrl_flows);
872 /* Hint libmlx5 to use PMD allocator for data plane resources */
873 struct mlx5dv_ctx_allocators alctr = {
874 .alloc = &mlx5_alloc_verbs_buf,
875 .free = &mlx5_free_verbs_buf,
878 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
879 (void *)((uintptr_t)&alctr));
881 /* Bring Ethernet device up. */
882 DEBUG("forcing Ethernet interface up");
883 priv_set_flags(priv, ~IFF_UP, IFF_UP);
884 mlx5_link_update(priv->dev, 1);
885 /* Store device configuration on private structure. */
886 priv->config = config;
893 claim_zero(ibv_dealloc_pd(pd));
895 claim_zero(ibv_close_device(ctx));
900 * XXX if something went wrong in the loop above, there is a resource
901 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
902 * long as the dpdk does not provide a way to deallocate a ethdev and a
903 * way to enumerate the registered ethdevs to free the previous ones.
906 /* no port found, complain */
907 if (!mlx5_dev[idx].ports) {
914 claim_zero(ibv_close_device(attr_ctx));
916 ibv_free_device_list(list);
921 static const struct rte_pci_id mlx5_pci_id_map[] = {
923 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
924 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
927 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
928 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
931 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
932 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
935 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
936 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
939 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
940 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
943 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
944 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
947 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
948 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
951 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
952 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
959 static struct rte_pci_driver mlx5_driver = {
961 .name = MLX5_DRIVER_NAME
963 .id_table = mlx5_pci_id_map,
964 .probe = mlx5_pci_probe,
965 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
969 * Driver initialization routine.
971 RTE_INIT(rte_mlx5_pmd_init);
973 rte_mlx5_pmd_init(void)
975 /* Build the static table for ptype conversion. */
976 mlx5_set_ptype_table();
978 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
979 * huge pages. Calling ibv_fork_init() during init allows
980 * applications to use fork() safely for purposes other than
981 * using this PMD, which is not supported in forked processes.
983 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
984 /* Match the size of Rx completion entry to the size of a cacheline. */
985 if (RTE_CACHE_LINE_SIZE == 128)
986 setenv("MLX5_CQE_SIZE", "128", 0);
988 rte_pci_register(&mlx5_driver);
991 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
992 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
993 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");