1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
43 PCI_VENDOR_ID_MELLANOX = 0x15b3,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
60 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
63 /* Request types for IPC. */
64 enum mlx5_mp_req_type {
65 MLX5_MP_REQ_VERBS_CMD_FD = 1,
66 MLX5_MP_REQ_CREATE_MR,
67 MLX5_MP_REQ_START_RXTX,
68 MLX5_MP_REQ_STOP_RXTX,
69 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
72 struct mlx5_mp_arg_queue_state_modify {
73 uint8_t is_wq; /* Set if WQ. */
74 uint16_t queue_id; /* DPDK queue ID. */
75 enum ibv_wq_state state; /* WQ requested state. */
78 /* Pameters for IPC. */
79 struct mlx5_mp_param {
80 enum mlx5_mp_req_type type;
85 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
86 struct mlx5_mp_arg_queue_state_modify state_modify;
87 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
91 /** Request timeout for IPC. */
92 #define MLX5_MP_REQ_TIMEOUT_SEC 5
94 /** Key string for IPC. */
95 #define MLX5_MP_NAME "net_mlx5_mp"
97 /* Recognized Infiniband device physical port name types. */
98 enum mlx5_phys_port_name_type {
99 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
100 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
101 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
102 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
103 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
106 /** Switch information returned by mlx5_nl_switch_info(). */
107 struct mlx5_switch_info {
108 uint32_t master:1; /**< Master device. */
109 uint32_t representor:1; /**< Representor device. */
110 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
111 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
112 int32_t port_name; /**< Representor port name. */
113 uint64_t switch_id; /**< Switch identifier. */
116 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
118 /* Shared data between primary and secondary processes. */
119 struct mlx5_shared_data {
121 /* Global spinlock for primary and secondary processes. */
122 int init_done; /* Whether primary has done initialization. */
123 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
124 struct mlx5_dev_list mem_event_cb_list;
125 rte_rwlock_t mem_event_rwlock;
128 /* Per-process data structure, not visible to other processes. */
129 struct mlx5_local_data {
130 int init_done; /* Whether a secondary has done initialization. */
133 extern struct mlx5_shared_data *mlx5_shared_data;
135 struct mlx5_counter_ctrl {
136 /* Name of the counter. */
137 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
138 /* Name of the counter on the device table. */
139 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
140 uint32_t ib:1; /**< Nonzero for IB counters. */
143 struct mlx5_xstats_ctrl {
144 /* Number of device stats. */
146 /* Number of device stats identified by PMD. */
147 uint16_t mlx5_stats_n;
148 /* Index in the device counters table. */
149 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
150 uint64_t base[MLX5_MAX_XSTATS];
151 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
154 struct mlx5_stats_ctrl {
155 /* Base for imissed counter. */
156 uint64_t imissed_base;
159 /* devX creation object */
160 struct mlx5_devx_obj {
161 struct mlx5dv_devx_obj *obj; /* The DV object. */
162 int id; /* The object ID. */
165 struct mlx5_devx_mkey_attr {
172 /* HCA qos attributes. */
173 struct mlx5_hca_qos_attr {
174 uint32_t sup:1; /* Whether QOS is supported. */
175 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
176 uint8_t log_max_flow_meter;
177 /* Power of the maximum supported meters. */
178 uint8_t flow_meter_reg_c_ids;
179 /* Bitmap of the reg_Cs available for flow meter to use. */
183 /* HCA supports this number of time periods for LRO. */
184 #define MLX5_LRO_NUM_SUPP_PERIODS 4
186 /* HCA attributes. */
187 struct mlx5_hca_attr {
188 uint32_t eswitch_manager:1;
189 uint32_t flow_counters_dump:1;
190 uint8_t flow_counter_bulk_alloc_bitmap;
191 uint32_t eth_net_offloads:1;
193 uint32_t wqe_vlan_insert:1;
194 uint32_t wqe_inline_mode:2;
195 uint32_t vport_inline_mode:3;
196 uint32_t tunnel_stateless_geneve_rx:1;
197 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
199 uint32_t tunnel_lro_gre:1;
200 uint32_t tunnel_lro_vxlan:1;
201 uint32_t lro_max_msg_sz_mode:2;
202 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
203 uint32_t flex_parser_protocols;
205 uint32_t log_max_hairpin_queues:5;
206 uint32_t log_max_hairpin_wq_data_sz:5;
207 uint32_t log_max_hairpin_num_packets:5;
209 struct mlx5_hca_qos_attr qos;
213 TAILQ_HEAD(mlx5_flows, rte_flow);
215 /* Default PMD specific parameter value. */
216 #define MLX5_ARG_UNSET (-1)
218 #define MLX5_LRO_SUPPORTED(dev) \
219 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
221 /* LRO configurations structure. */
222 struct mlx5_lro_config {
223 uint32_t supported:1; /* Whether LRO is supported. */
224 uint32_t timeout; /* User configuration. */
228 * Device configuration structure.
230 * Merged configuration from:
232 * - Device capabilities,
233 * - User device parameters disabled features.
235 struct mlx5_dev_config {
236 unsigned int hw_csum:1; /* Checksum offload is supported. */
237 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
238 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
239 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
240 unsigned int hw_padding:1; /* End alignment padding is supported. */
241 unsigned int vf:1; /* This is a VF. */
242 unsigned int tunnel_en:1;
243 /* Whether tunnel stateless offloads are supported. */
244 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
245 unsigned int cqe_comp:1; /* CQE compression is enabled. */
246 unsigned int cqe_pad:1; /* CQE padding is enabled. */
247 unsigned int tso:1; /* Whether TSO is supported. */
248 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
249 unsigned int mr_ext_memseg_en:1;
250 /* Whether memseg should be extended for MR creation. */
251 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
252 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
253 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
254 unsigned int dv_flow_en:1; /* Enable DV flow. */
255 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
256 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
257 unsigned int devx:1; /* Whether devx interface is available or not. */
258 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
260 unsigned int enabled:1; /* Whether MPRQ is enabled. */
261 unsigned int stride_num_n; /* Number of strides. */
262 unsigned int min_stride_size_n; /* Min size of a stride. */
263 unsigned int max_stride_size_n; /* Max size of a stride. */
264 unsigned int max_memcpy_len;
265 /* Maximum packet size to memcpy Rx packets. */
266 unsigned int min_rxqs_num;
267 /* Rx queue count threshold to enable MPRQ. */
268 } mprq; /* Configurations for Multi-Packet RQ. */
269 int mps; /* Multi-packet send supported mode. */
270 int dbnc; /* Skip doorbell register write barrier. */
271 unsigned int flow_prio; /* Number of flow priorities. */
272 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
273 /* Availibility of mreg_c's. */
274 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
275 unsigned int ind_table_max_size; /* Maximum indirection table size. */
276 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
277 int txqs_inline; /* Queue number threshold for inlining. */
278 int txq_inline_min; /* Minimal amount of data bytes to inline. */
279 int txq_inline_max; /* Max packet size for inlining with SEND. */
280 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
281 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
282 struct mlx5_lro_config lro; /* LRO configuration. */
285 struct mlx5_devx_wq_attr {
287 uint32_t wq_signature:1;
288 uint32_t end_padding_mode:2;
290 uint32_t hds_skip_first_sge:1;
291 uint32_t log2_hds_buf_size:3;
292 uint32_t page_offset:5;
295 uint32_t uar_page:24;
299 uint32_t log_wq_stride:4;
300 uint32_t log_wq_pg_sz:5;
301 uint32_t log_wq_sz:5;
302 uint32_t dbr_umem_valid:1;
303 uint32_t wq_umem_valid:1;
304 uint32_t log_hairpin_num_packets:5;
305 uint32_t log_hairpin_data_sz:5;
306 uint32_t single_wqe_log_num_of_strides:4;
307 uint32_t two_byte_shift_en:1;
308 uint32_t single_stride_log_num_of_bytes:3;
309 uint32_t dbr_umem_id;
311 uint64_t wq_umem_offset;
314 /* Create RQ attributes structure, used by create RQ operation. */
315 struct mlx5_devx_create_rq_attr {
317 uint32_t delay_drop_en:1;
318 uint32_t scatter_fcs:1;
320 uint32_t mem_rq_type:4;
322 uint32_t flush_in_error_en:1;
324 uint32_t user_index:24;
326 uint32_t counter_set_id:8;
328 struct mlx5_devx_wq_attr wq_attr;
331 /* Modify RQ attributes structure, used by modify RQ operation. */
332 struct mlx5_devx_modify_rq_attr {
334 uint32_t rq_state:4; /* Current RQ state. */
335 uint32_t state:4; /* Required RQ state. */
336 uint32_t scatter_fcs:1;
338 uint32_t counter_set_id:8;
339 uint32_t hairpin_peer_sq:24;
340 uint32_t hairpin_peer_vhca:16;
341 uint64_t modify_bitmask;
342 uint32_t lwm:16; /* Contained WQ lwm. */
345 struct mlx5_rx_hash_field_select {
346 uint32_t l3_prot_type:1;
347 uint32_t l4_prot_type:1;
348 uint32_t selected_fields:30;
351 /* TIR attributes structure, used by TIR operations. */
352 struct mlx5_devx_tir_attr {
353 uint32_t disp_type:4;
354 uint32_t lro_timeout_period_usecs:16;
355 uint32_t lro_enable_mask:4;
356 uint32_t lro_max_msg_sz:8;
357 uint32_t inline_rqn:24;
358 uint32_t rx_hash_symmetric:1;
359 uint32_t tunneled_offload_en:1;
360 uint32_t indirect_table:24;
361 uint32_t rx_hash_fn:4;
362 uint32_t self_lb_block:2;
363 uint32_t transport_domain:24;
364 uint32_t rx_hash_toeplitz_key[10];
365 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
366 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
369 /* RQT attributes structure, used by RQT operations. */
370 struct mlx5_devx_rqt_attr {
371 uint32_t rqt_max_size:16;
372 uint32_t rqt_actual_size:16;
376 /* TIS attributes structure. */
377 struct mlx5_devx_tis_attr {
378 uint32_t strict_lag_tx_port_affinity:1;
380 uint32_t lag_tx_port_affinity:4;
382 uint32_t transport_domain:24;
385 /* SQ attributes structure, used by SQ create operation. */
386 struct mlx5_devx_create_sq_attr {
388 uint32_t cd_master:1;
390 uint32_t flush_in_error_en:1;
391 uint32_t allow_multi_pkt_send_wqe:1;
392 uint32_t min_wqe_inline_mode:3;
395 uint32_t allow_swp:1;
397 uint32_t user_index:24;
399 uint32_t packet_pacing_rate_limit_index:16;
400 uint32_t tis_lst_sz:16;
402 struct mlx5_devx_wq_attr wq_attr;
405 /* SQ attributes structure, used by SQ modify operation. */
406 struct mlx5_devx_modify_sq_attr {
409 uint32_t hairpin_peer_rq:24;
410 uint32_t hairpin_peer_vhca:16;
414 * Type of object being allocated.
416 enum mlx5_verbs_alloc_type {
417 MLX5_VERBS_ALLOC_TYPE_NONE,
418 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
419 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
422 /* VLAN netdev for VLAN workaround. */
423 struct mlx5_vlan_dev {
425 uint32_t ifindex; /**< Own interface index. */
428 /* Structure for VF VLAN workaround. */
429 struct mlx5_vf_vlan {
435 * Array of VLAN devices created on the base of VF
436 * used for workaround in virtual environments.
438 struct mlx5_vlan_vmwa_context {
442 struct rte_eth_dev *dev;
443 struct mlx5_vlan_dev vlan_dev[4096];
447 * Verbs allocator needs a context to know in the callback which kind of
448 * resources it is allocating.
450 struct mlx5_verbs_alloc_ctx {
451 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
452 const void *obj; /* Pointer to the DPDK object. */
455 LIST_HEAD(mlx5_mr_list, mlx5_mr);
457 /* Flow drop context necessary due to Verbs API. */
459 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
460 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
463 #define MLX5_COUNTERS_PER_POOL 512
464 #define MLX5_MAX_PENDING_QUERIES 4
466 struct mlx5_flow_counter_pool;
468 struct flow_counter_stats {
473 /* Counters information. */
474 struct mlx5_flow_counter {
475 TAILQ_ENTRY(mlx5_flow_counter) next;
476 /**< Pointer to the next flow counter structure. */
477 uint32_t shared:1; /**< Share counter ID with other flow rules. */
479 /**< Whether the counter was allocated by batch command. */
480 uint32_t ref_cnt:30; /**< Reference counter. */
481 uint32_t id; /**< Counter ID. */
482 union { /**< Holds the counters for the rule. */
483 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
484 struct ibv_counter_set *cs;
485 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
486 struct ibv_counters *cs;
488 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
489 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
492 uint64_t hits; /**< Reset value of hits packets. */
493 int64_t query_gen; /**< Generation of the last release. */
495 uint64_t bytes; /**< Reset value of bytes. */
496 void *action; /**< Pointer to the dv action. */
499 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
501 /* Counter pool structure - query is in pool resolution. */
502 struct mlx5_flow_counter_pool {
503 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
504 struct mlx5_counters counters; /* Free counter list. */
506 struct mlx5_devx_obj *min_dcs;
507 rte_atomic64_t a64_dcs;
509 /* The devx object of the minimum counter ID. */
510 rte_atomic64_t query_gen;
511 uint32_t n_counters: 16; /* Number of devx allocated counters. */
512 rte_spinlock_t sl; /* The pool lock. */
513 struct mlx5_counter_stats_raw *raw;
514 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
515 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
518 struct mlx5_counter_stats_raw;
520 /* Memory management structure for group of counter statistics raws. */
521 struct mlx5_counter_stats_mem_mng {
522 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
523 struct mlx5_counter_stats_raw *raws;
524 struct mlx5_devx_obj *dm;
525 struct mlx5dv_devx_umem *umem;
528 /* Raw memory structure for the counter statistics values of a pool. */
529 struct mlx5_counter_stats_raw {
530 LIST_ENTRY(mlx5_counter_stats_raw) next;
532 struct mlx5_counter_stats_mem_mng *mem_mng;
533 volatile struct flow_counter_stats *data;
536 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
538 /* Container structure for counter pools. */
539 struct mlx5_pools_container {
540 rte_atomic16_t n_valid; /* Number of valid pools. */
541 uint16_t n; /* Number of pools. */
542 struct mlx5_counter_pools pool_list; /* Counter pool list. */
543 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
544 struct mlx5_counter_stats_mem_mng *init_mem_mng;
545 /* Hold the memory management for the next allocated pools raws. */
548 /* Counter global management structure. */
549 struct mlx5_flow_counter_mng {
550 uint8_t mhi[2]; /* master \ host container index. */
551 struct mlx5_pools_container ccont[2 * 2];
552 /* 2 containers for single and for batch for double-buffer. */
553 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
554 uint8_t pending_queries;
557 uint8_t query_thread_on;
558 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
559 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
562 /* Per port data of shared IB device. */
563 struct mlx5_ibv_shared_port {
565 uint32_t devx_ih_port_id;
567 * Interrupt handler port_id. Used by shared interrupt
568 * handler to find the corresponding rte_eth device
569 * by IB port index. If value is equal or greater
570 * RTE_MAX_ETHPORTS it means there is no subhandler
571 * installed for specified IB port index.
575 /* Table structure. */
576 struct mlx5_flow_tbl_resource {
577 void *obj; /**< Pointer to DR table object. */
578 rte_atomic32_t refcnt; /**< Reference counter. */
581 #define MLX5_MAX_TABLES UINT16_MAX
582 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
583 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
584 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
585 /* Reserve the last two tables for metadata register copy. */
586 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
587 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
588 /* Tables for metering splits should be added here. */
589 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
590 #define MLX5_MAX_TABLES_FDB UINT16_MAX
592 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
593 #define MLX5_DBR_SIZE 8
594 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
595 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
597 struct mlx5_devx_dbr_page {
598 /* Door-bell records, must be first member in structure. */
599 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
600 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
601 struct mlx5dv_devx_umem *umem;
602 uint32_t dbr_count; /* Number of door-bell records in use. */
603 /* 1 bit marks matching door-bell is in use. */
604 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
607 /* ID generation structure. */
608 struct mlx5_flow_id_pool {
609 uint32_t *free_arr; /**< Pointer to the a array of free values. */
611 /**< The next index that can be used without any free elements. */
612 uint32_t *curr; /**< Pointer to the index to pop. */
613 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
617 * Shared Infiniband device context for Master/Representors
618 * which belong to same IB device with multiple IB ports.
620 struct mlx5_ibv_shared {
621 LIST_ENTRY(mlx5_ibv_shared) next;
623 uint32_t devx:1; /* Opened with DV. */
624 uint32_t max_port; /* Maximal IB device port index. */
625 struct ibv_context *ctx; /* Verbs/DV context. */
626 struct ibv_pd *pd; /* Protection Domain. */
627 uint32_t pdn; /* Protection Domain number. */
628 uint32_t tdn; /* Transport Domain number. */
629 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
630 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
631 struct ibv_device_attr_ex device_attr; /* Device properties. */
632 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
633 /**< Called by memory event callback. */
635 uint32_t dev_gen; /* Generation number to flush local caches. */
636 rte_rwlock_t rwlock; /* MR Lock. */
637 struct mlx5_mr_btree cache; /* Global MR cache table. */
638 struct mlx5_mr_list mr_list; /* Registered MR list. */
639 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
641 /* Shared DV/DR flow data section. */
642 pthread_mutex_t dv_mutex; /* DV context mutex. */
643 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
644 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
645 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
646 uint32_t dv_refcnt; /* DV/DR data reference counter. */
647 void *fdb_domain; /* FDB Direct Rules name space handle. */
648 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
649 /* FDB Direct Rules tables. */
650 struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl;
651 /* FDB meter suffix rules table. */
652 void *rx_domain; /* RX Direct Rules name space handle. */
653 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
654 /* RX Direct Rules tables. */
655 struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl;
656 /* RX meter suffix rules table. */
657 void *tx_domain; /* TX Direct Rules name space handle. */
658 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
659 /* TX Direct Rules tables. */
660 struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl;
661 /* TX meter suffix rules table. */
662 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
663 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
664 /* TX Direct Rules tables/ */
665 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
666 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
667 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
668 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
669 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
670 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
671 port_id_action_list; /* List of port ID actions. */
672 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
673 push_vlan_action_list; /* List of push VLAN actions. */
674 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
675 /* Shared interrupt handler section. */
676 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
677 uint32_t intr_cnt; /* Interrupt handler reference counter. */
678 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
679 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
680 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
681 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
682 struct mlx5_devx_obj *tis; /* TIS object. */
683 struct mlx5_devx_obj *td; /* Transport domain. */
684 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
685 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
688 /* Per-process private structure. */
689 struct mlx5_proc_priv {
691 /* Size of UAR register table. */
693 /* Table of UAR registers for each process. */
696 /* MTR profile list. */
697 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
699 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
701 #define MLX5_PROC_PRIV(port_id) \
702 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
705 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
706 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
707 uint32_t ibv_port; /* IB device port number. */
708 struct rte_pci_device *pci_dev; /* Backend PCI device. */
709 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
710 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
711 /* Bit-field of MAC addresses owned by the PMD. */
712 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
713 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
714 /* Device properties. */
715 uint16_t mtu; /* Configured MTU. */
716 unsigned int isolated:1; /* Whether isolated mode is enabled. */
717 unsigned int representor:1; /* Device is a port representor. */
718 unsigned int master:1; /* Device is a E-Switch master. */
719 unsigned int dr_shared:1; /* DV/DR data is shared. */
720 unsigned int counter_fallback:1; /* Use counter fallback management. */
721 unsigned int mtr_en:1; /* Whether support meter. */
722 uint16_t domain_id; /* Switch domain identifier. */
723 uint16_t vport_id; /* Associated VF vport index (if any). */
724 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
725 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
726 int32_t representor_id; /* Port representor identifier. */
727 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
728 unsigned int if_index; /* Associated kernel network device index. */
730 unsigned int rxqs_n; /* RX queues array size. */
731 unsigned int txqs_n; /* TX queues array size. */
732 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
733 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
734 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
735 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
736 unsigned int (*reta_idx)[]; /* RETA index table. */
737 unsigned int reta_idx_n; /* RETA index size. */
738 struct mlx5_drop drop_queue; /* Flow drop queues. */
739 struct mlx5_flows flows; /* RTE Flow rules. */
740 struct mlx5_flows ctrl_flows; /* Control flow rules. */
741 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
742 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
743 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
744 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
745 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
746 /* Indirection tables. */
747 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
748 /* Pointer to next element. */
749 rte_atomic32_t refcnt; /**< Reference counter. */
750 struct ibv_flow_action *verbs_action;
751 /**< Verbs modify header action object. */
752 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
753 uint8_t max_lro_msg_size;
754 /* Tags resources cache. */
755 uint32_t link_speed_capa; /* Link speed capabilities. */
756 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
757 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
758 struct mlx5_dev_config config; /* Device configuration. */
759 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
760 /* Context for Verbs allocator. */
761 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
762 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
763 uint32_t nl_sn; /* Netlink message sequence number. */
764 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
765 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
766 struct mlx5_flow_id_pool *qrss_id_pool;
767 struct mlx5_hlist *mreg_cp_tbl;
768 /* Hash table of Rx metadata register copy table. */
769 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
770 uint8_t mtr_color_reg; /* Meter color match REG_C. */
771 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
772 struct mlx5_flow_meters flow_meters; /* MTR list. */
774 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
775 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
776 /* UAR same-page access control required in 32bit implementations. */
778 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
781 #define PORT_ID(priv) ((priv)->dev_data->port_id)
782 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
786 int mlx5_getenv_int(const char *);
787 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
788 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
789 struct mlx5_devx_dbr_page **dbr_page);
790 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
792 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
793 struct rte_eth_udp_tunnel *udp_tunnel);
794 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
796 /* Macro to iterate over all valid ports for mlx5 driver. */
797 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
798 for (port_id = mlx5_eth_find_next(0, pci_dev); \
799 port_id < RTE_MAX_ETHPORTS; \
800 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
804 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
805 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
806 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
807 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
808 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
809 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
811 int mlx5_dev_configure(struct rte_eth_dev *dev);
812 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
813 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
814 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
815 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
816 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
817 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
818 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
819 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
820 struct rte_eth_fc_conf *fc_conf);
821 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
822 struct rte_eth_fc_conf *fc_conf);
823 int mlx5_dev_to_pci_addr(const char *dev_path,
824 struct rte_pci_addr *pci_addr);
825 void mlx5_dev_link_status_handler(void *arg);
826 void mlx5_dev_interrupt_handler(void *arg);
827 void mlx5_dev_interrupt_handler_devx(void *arg);
828 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
829 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
830 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
831 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
832 int mlx5_set_link_down(struct rte_eth_dev *dev);
833 int mlx5_set_link_up(struct rte_eth_dev *dev);
834 int mlx5_is_removed(struct rte_eth_dev *dev);
835 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
836 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
837 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
838 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
839 int mlx5_sysfs_switch_info(unsigned int ifindex,
840 struct mlx5_switch_info *info);
841 void mlx5_sysfs_check_switch_info(bool device_dir,
842 struct mlx5_switch_info *switch_info);
843 void mlx5_nl_check_switch_info(bool nun_vf_set,
844 struct mlx5_switch_info *switch_info);
845 void mlx5_translate_port_name(const char *port_name_in,
846 struct mlx5_switch_info *port_info_out);
847 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
848 rte_intr_callback_fn cb_fn, void *cb_arg);
849 int mlx5_get_module_info(struct rte_eth_dev *dev,
850 struct rte_eth_dev_module_info *modinfo);
851 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
852 struct rte_dev_eeprom_info *info);
853 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
854 struct rte_eth_hairpin_cap *cap);
855 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
859 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
860 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
861 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
862 uint32_t index, uint32_t vmdq);
863 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
864 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
865 struct rte_ether_addr *mc_addr_set,
866 uint32_t nb_mc_addr);
870 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
871 struct rte_eth_rss_conf *rss_conf);
872 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
873 struct rte_eth_rss_conf *rss_conf);
874 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
875 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
876 struct rte_eth_rss_reta_entry64 *reta_conf,
878 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
879 struct rte_eth_rss_reta_entry64 *reta_conf,
884 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
885 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
886 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
887 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
891 void mlx5_stats_init(struct rte_eth_dev *dev);
892 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
893 int mlx5_stats_reset(struct rte_eth_dev *dev);
894 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
896 int mlx5_xstats_reset(struct rte_eth_dev *dev);
897 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
898 struct rte_eth_xstat_name *xstats_names,
903 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
904 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
905 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
909 int mlx5_dev_start(struct rte_eth_dev *dev);
910 void mlx5_dev_stop(struct rte_eth_dev *dev);
911 int mlx5_traffic_enable(struct rte_eth_dev *dev);
912 void mlx5_traffic_disable(struct rte_eth_dev *dev);
913 int mlx5_traffic_restart(struct rte_eth_dev *dev);
917 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
918 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
919 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
920 void mlx5_flow_print(struct rte_flow *flow);
921 int mlx5_flow_validate(struct rte_eth_dev *dev,
922 const struct rte_flow_attr *attr,
923 const struct rte_flow_item items[],
924 const struct rte_flow_action actions[],
925 struct rte_flow_error *error);
926 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
927 const struct rte_flow_attr *attr,
928 const struct rte_flow_item items[],
929 const struct rte_flow_action actions[],
930 struct rte_flow_error *error);
931 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
932 struct rte_flow_error *error);
933 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
934 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
935 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
936 const struct rte_flow_action *action, void *data,
937 struct rte_flow_error *error);
938 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
939 struct rte_flow_error *error);
940 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
941 enum rte_filter_type filter_type,
942 enum rte_filter_op filter_op,
944 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
945 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
946 int mlx5_flow_verify(struct rte_eth_dev *dev);
947 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
948 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
949 struct rte_flow_item_eth *eth_spec,
950 struct rte_flow_item_eth *eth_mask,
951 struct rte_flow_item_vlan *vlan_spec,
952 struct rte_flow_item_vlan *vlan_mask);
953 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
954 struct rte_flow_item_eth *eth_spec,
955 struct rte_flow_item_eth *eth_mask);
956 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
957 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
958 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
959 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
960 uint64_t async_id, int status);
961 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
962 void mlx5_flow_query_alarm(void *arg);
963 struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev);
964 void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt);
965 int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt,
966 bool clear, uint64_t *pkts, uint64_t *bytes);
969 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
970 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
971 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
972 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
973 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
974 struct mlx5_mp_arg_queue_state_modify *sm);
975 int mlx5_mp_init_primary(void);
976 void mlx5_mp_uninit_primary(void);
977 int mlx5_mp_init_secondary(void);
978 void mlx5_mp_uninit_secondary(void);
982 int mlx5_nl_init(int protocol);
983 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
985 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
987 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
988 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
989 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
990 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
991 unsigned int mlx5_nl_portnum(int nl, const char *name);
992 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
993 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
994 struct mlx5_switch_info *info);
996 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
998 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
999 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1000 struct mlx5_vf_vlan *vf_vlan);
1001 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1002 struct mlx5_vf_vlan *vf_vlan);
1004 /* mlx5_devx_cmds.c */
1006 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
1008 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
1009 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
1010 int clear, uint32_t n_counters,
1011 uint64_t *pkts, uint64_t *bytes,
1012 uint32_t mkey, void *addr,
1013 struct mlx5dv_devx_cmd_comp *cmd_comp,
1015 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
1016 struct mlx5_hca_attr *attr);
1017 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
1018 struct mlx5_devx_mkey_attr *attr);
1019 int mlx5_devx_get_out_command_status(void *out);
1020 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
1022 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
1023 struct mlx5_devx_create_rq_attr *rq_attr,
1025 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1026 struct mlx5_devx_modify_rq_attr *rq_attr);
1027 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
1028 struct mlx5_devx_tir_attr *tir_attr);
1029 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
1030 struct mlx5_devx_rqt_attr *rqt_attr);
1031 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq
1032 (struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);
1033 int mlx5_devx_cmd_modify_sq
1034 (struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);
1035 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis
1036 (struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);
1037 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
1039 /* mlx5_flow_meter.c */
1041 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1042 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1044 struct mlx5_flow_meter *mlx5_flow_meter_attach
1045 (struct mlx5_priv *priv,
1047 const struct rte_flow_attr *attr,
1048 struct rte_flow_error *error);
1049 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1051 #endif /* RTE_PMD_MLX5_H_ */