4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_H_
35 #define RTE_PMD_MLX5_H_
41 #include <netinet/in.h>
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_ether.h>
55 #include <rte_ethdev.h>
56 #include <rte_spinlock.h>
57 #include <rte_interrupts.h>
58 #include <rte_errno.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 #if !defined(HAVE_VERBS_IBV_EXP_CQ_COMPRESSED_CQE) || \
67 !defined(HAVE_VERBS_MLX5_ETH_VLAN_INLINE_HEADER_SIZE)
68 #error Mellanox OFED >= 3.3 is required, please refer to the documentation.
72 PCI_VENDOR_ID_MELLANOX = 0x15b3,
76 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
77 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
78 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
79 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
80 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
81 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
82 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
83 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
86 struct mlx5_xstats_ctrl {
87 /* Number of device stats. */
89 /* Index in the device counters table. */
90 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
91 uint64_t base[MLX5_MAX_XSTATS];
95 struct rte_eth_dev *dev; /* Ethernet device. */
96 struct ibv_context *ctx; /* Verbs context. */
97 struct ibv_device_attr device_attr; /* Device properties. */
98 struct ibv_pd *pd; /* Protection Domain. */
100 * MAC addresses array and configuration bit-field.
101 * An extra entry that cannot be modified by the DPDK is reserved
102 * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).
104 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES];
105 BITFIELD_DECLARE(mac_configured, uint32_t, MLX5_MAX_MAC_ADDRESSES);
106 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
107 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
108 /* Device properties. */
109 uint16_t mtu; /* Configured MTU. */
110 uint8_t port; /* Physical port number. */
111 unsigned int started:1; /* Device started, flows enabled. */
112 unsigned int promisc_req:1; /* Promiscuous mode requested. */
113 unsigned int allmulti_req:1; /* All multicast mode requested. */
114 unsigned int hw_csum:1; /* Checksum offload is supported. */
115 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
116 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
117 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
118 unsigned int hw_padding:1; /* End alignment padding is supported. */
119 unsigned int sriov:1; /* This is a VF or PF with VF devices. */
120 unsigned int mps:2; /* Multi-packet send mode (0: disabled). */
121 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
122 unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */
123 unsigned int pending_alarm:1; /* An alarm is pending. */
124 unsigned int tso:1; /* Whether TSO is supported. */
125 unsigned int tunnel_en:1;
126 unsigned int isolated:1; /* Whether isolated mode is enabled. */
127 unsigned int tx_vec_en:1; /* Whether Tx vector is enabled. */
128 unsigned int rx_vec_en:1; /* Whether Rx vector is enabled. */
129 /* Whether Tx offloads for tunneled packets are supported. */
130 unsigned int max_tso_payload_sz; /* Maximum TCP payload for TSO. */
131 unsigned int txq_inline; /* Maximum packet size for inlining. */
132 unsigned int txqs_inline; /* Queue number threshold for inlining. */
133 unsigned int inline_max_packet_sz; /* Max packet size for inlining. */
135 unsigned int rxqs_n; /* RX queues array size. */
136 unsigned int txqs_n; /* TX queues array size. */
137 struct rxq *(*rxqs)[]; /* RX queues. */
138 struct txq *(*txqs)[]; /* TX queues. */
139 /* Indirection tables referencing all RX WQs. */
140 struct ibv_exp_rwq_ind_table *(*ind_tables)[];
141 unsigned int ind_tables_n; /* Number of indirection tables. */
142 unsigned int ind_table_max_size; /* Maximum indirection table size. */
143 /* Hash RX QPs feeding the indirection table. */
144 struct hash_rxq (*hash_rxqs)[];
145 unsigned int hash_rxqs_n; /* Hash RX QPs array size. */
146 /* RSS configuration array indexed by hash RX queue type. */
147 struct rte_eth_rss_conf *(*rss_conf)[];
148 uint64_t rss_hf; /* RSS DPDK bit field of active RSS. */
149 struct rte_intr_handle intr_handle; /* Interrupt handler. */
150 unsigned int (*reta_idx)[]; /* RETA index table. */
151 unsigned int reta_idx_n; /* RETA index size. */
152 struct fdir_filter_list *fdir_filter_list; /* Flow director rules. */
153 struct fdir_queue *fdir_drop_queue; /* Flow director drop queue. */
154 struct rte_flow_drop *flow_drop_queue; /* Flow drop queue. */
155 TAILQ_HEAD(mlx5_flows, rte_flow) flows; /* RTE Flow rules. */
156 uint32_t link_speed_capa; /* Link speed capabilities. */
157 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
158 rte_spinlock_t lock; /* Lock for control functions. */
161 /* Local storage for secondary process data. */
162 struct mlx5_secondary_data {
163 struct rte_eth_dev_data data; /* Local device data. */
164 struct priv *primary_priv; /* Private structure from primary. */
165 struct rte_eth_dev_data *shared_dev_data; /* Shared device data. */
166 rte_spinlock_t lock; /* Port configuration lock. */
167 } mlx5_secondary_data[RTE_MAX_ETHPORTS];
170 * Lock private structure to protect it from concurrent access in the
174 * Pointer to private structure.
177 priv_lock(struct priv *priv)
179 rte_spinlock_lock(&priv->lock);
183 * Unlock private structure.
186 * Pointer to private structure.
189 priv_unlock(struct priv *priv)
191 rte_spinlock_unlock(&priv->lock);
196 int mlx5_getenv_int(const char *);
200 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
201 int mlx5_is_secondary(void);
202 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
203 int priv_ifreq(const struct priv *, int req, struct ifreq *);
204 int priv_is_ib_cntr(const char *);
205 int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *);
206 int priv_get_num_vfs(struct priv *, uint16_t *);
207 int priv_get_mtu(struct priv *, uint16_t *);
208 int priv_set_flags(struct priv *, unsigned int, unsigned int);
209 int mlx5_dev_configure(struct rte_eth_dev *);
210 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
211 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
212 int mlx5_link_update(struct rte_eth_dev *, int);
213 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
214 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
215 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
216 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
217 struct rte_pci_addr *);
218 void mlx5_dev_link_status_handler(void *);
219 void mlx5_dev_interrupt_handler(void *);
220 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
221 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
222 int mlx5_set_link_down(struct rte_eth_dev *dev);
223 int mlx5_set_link_up(struct rte_eth_dev *dev);
224 struct priv *mlx5_secondary_data_setup(struct priv *priv);
225 void priv_select_tx_function(struct priv *);
226 void priv_select_rx_function(struct priv *);
230 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
231 void hash_rxq_mac_addrs_del(struct hash_rxq *);
232 void priv_mac_addrs_disable(struct priv *);
233 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
234 int hash_rxq_mac_addrs_add(struct hash_rxq *);
235 int priv_mac_addr_add(struct priv *, unsigned int,
236 const uint8_t (*)[ETHER_ADDR_LEN]);
237 int priv_mac_addrs_enable(struct priv *);
238 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
240 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
244 int rss_hash_rss_conf_new_key(struct priv *, const uint8_t *, unsigned int,
246 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
247 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
248 int priv_rss_reta_index_resize(struct priv *, unsigned int);
249 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
250 struct rte_eth_rss_reta_entry64 *, uint16_t);
251 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
252 struct rte_eth_rss_reta_entry64 *, uint16_t);
256 int priv_special_flow_enable(struct priv *, enum hash_rxq_flow_type);
257 void priv_special_flow_disable(struct priv *, enum hash_rxq_flow_type);
258 int priv_special_flow_enable_all(struct priv *);
259 void priv_special_flow_disable_all(struct priv *);
260 void mlx5_promiscuous_enable(struct rte_eth_dev *);
261 void mlx5_promiscuous_disable(struct rte_eth_dev *);
262 void mlx5_allmulticast_enable(struct rte_eth_dev *);
263 void mlx5_allmulticast_disable(struct rte_eth_dev *);
267 void priv_xstats_init(struct priv *);
268 void mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
269 void mlx5_stats_reset(struct rte_eth_dev *);
270 int mlx5_xstats_get(struct rte_eth_dev *,
271 struct rte_eth_xstat *, unsigned int);
272 void mlx5_xstats_reset(struct rte_eth_dev *);
273 int mlx5_xstats_get_names(struct rte_eth_dev *,
274 struct rte_eth_xstat_name *, unsigned int);
278 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
279 void mlx5_vlan_offload_set(struct rte_eth_dev *, int);
280 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
284 int mlx5_dev_start(struct rte_eth_dev *);
285 void mlx5_dev_stop(struct rte_eth_dev *);
289 void priv_fdir_queue_destroy(struct priv *, struct fdir_queue *);
290 int fdir_init_filters_list(struct priv *);
291 void priv_fdir_delete_filters_list(struct priv *);
292 void priv_fdir_disable(struct priv *);
293 void priv_fdir_enable(struct priv *);
294 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
295 enum rte_filter_op, void *);
299 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
300 const struct rte_flow_item [],
301 const struct rte_flow_action [],
302 struct rte_flow_error *);
303 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
304 const struct rte_flow_attr *,
305 const struct rte_flow_item [],
306 const struct rte_flow_action [],
307 struct rte_flow_error *);
308 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
309 struct rte_flow_error *);
310 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
311 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
312 int priv_flow_start(struct priv *);
313 void priv_flow_stop(struct priv *);
314 int priv_flow_rxq_in_use(struct priv *, struct rxq *);
316 #endif /* RTE_PMD_MLX5_H_ */