4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_H_
35 #define RTE_PMD_MLX5_H_
41 #include <netinet/in.h>
45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
47 #pragma GCC diagnostic ignored "-pedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-pedantic"
54 /* DPDK headers don't like -pedantic. */
56 #pragma GCC diagnostic ignored "-pedantic"
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_spinlock.h>
61 #include <rte_interrupts.h>
63 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
72 PCI_VENDOR_ID_MELLANOX = 0x15b3,
76 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
77 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
78 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
79 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
83 struct rte_eth_dev *dev; /* Ethernet device. */
84 struct ibv_context *ctx; /* Verbs context. */
85 struct ibv_device_attr device_attr; /* Device properties. */
86 struct ibv_pd *pd; /* Protection Domain. */
88 * MAC addresses array and configuration bit-field.
89 * An extra entry that cannot be modified by the DPDK is reserved
90 * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).
92 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES];
93 BITFIELD_DECLARE(mac_configured, uint32_t, MLX5_MAX_MAC_ADDRESSES);
94 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
95 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
96 /* Device properties. */
97 uint16_t mtu; /* Configured MTU. */
98 uint8_t port; /* Physical port number. */
99 unsigned int started:1; /* Device started, flows enabled. */
100 unsigned int promisc_req:1; /* Promiscuous mode requested. */
101 unsigned int allmulti_req:1; /* All multicast mode requested. */
102 unsigned int hw_csum:1; /* Checksum offload is supported. */
103 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
104 unsigned int vf:1; /* This is a VF device. */
105 unsigned int pending_alarm:1; /* An alarm is pending. */
107 unsigned int rxqs_n; /* RX queues array size. */
108 unsigned int txqs_n; /* TX queues array size. */
109 struct rxq *(*rxqs)[]; /* RX queues. */
110 struct txq *(*txqs)[]; /* TX queues. */
111 /* Indirection tables referencing all RX WQs. */
112 struct ibv_exp_rwq_ind_table *(*ind_tables)[];
113 unsigned int ind_tables_n; /* Number of indirection tables. */
114 unsigned int ind_table_max_size; /* Maximum indirection table size. */
115 /* Hash RX QPs feeding the indirection table. */
116 struct hash_rxq (*hash_rxqs)[];
117 unsigned int hash_rxqs_n; /* Hash RX QPs array size. */
118 /* RSS configuration array indexed by hash RX queue type. */
119 struct rte_eth_rss_conf *(*rss_conf)[];
120 struct rte_intr_handle intr_handle; /* Interrupt handler. */
121 unsigned int (*reta_idx)[]; /* RETA index table. */
122 unsigned int reta_idx_n; /* RETA index size. */
123 rte_spinlock_t lock; /* Lock for control functions. */
127 * Lock private structure to protect it from concurrent access in the
131 * Pointer to private structure.
134 priv_lock(struct priv *priv)
136 rte_spinlock_lock(&priv->lock);
140 * Unlock private structure.
143 * Pointer to private structure.
146 priv_unlock(struct priv *priv)
148 rte_spinlock_unlock(&priv->lock);
153 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
154 int priv_ifreq(const struct priv *, int req, struct ifreq *);
155 int priv_get_mtu(struct priv *, uint16_t *);
156 int priv_set_flags(struct priv *, unsigned int, unsigned int);
157 int mlx5_dev_configure(struct rte_eth_dev *);
158 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
159 int mlx5_link_update(struct rte_eth_dev *, int);
160 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
161 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
162 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
163 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
164 struct rte_pci_addr *);
165 void mlx5_dev_link_status_handler(void *);
166 void mlx5_dev_interrupt_handler(struct rte_intr_handle *, void *);
167 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
168 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
172 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
173 void hash_rxq_mac_addrs_del(struct hash_rxq *);
174 void priv_mac_addrs_disable(struct priv *);
175 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
176 int hash_rxq_mac_addrs_add(struct hash_rxq *);
177 int priv_mac_addr_add(struct priv *, unsigned int,
178 const uint8_t (*)[ETHER_ADDR_LEN]);
179 int priv_mac_addrs_enable(struct priv *);
180 void mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
185 int rss_hash_rss_conf_new_key(struct priv *, const uint8_t *, unsigned int,
187 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
188 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
189 int priv_rss_reta_index_resize(struct priv *, unsigned int);
190 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
191 struct rte_eth_rss_reta_entry64 *, uint16_t);
192 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
193 struct rte_eth_rss_reta_entry64 *, uint16_t);
197 int priv_promiscuous_enable(struct priv *);
198 void mlx5_promiscuous_enable(struct rte_eth_dev *);
199 void priv_promiscuous_disable(struct priv *);
200 void mlx5_promiscuous_disable(struct rte_eth_dev *);
201 int priv_allmulticast_enable(struct priv *);
202 void mlx5_allmulticast_enable(struct rte_eth_dev *);
203 void priv_allmulticast_disable(struct priv *);
204 void mlx5_allmulticast_disable(struct rte_eth_dev *);
208 void mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
209 void mlx5_stats_reset(struct rte_eth_dev *);
213 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
217 int mlx5_dev_start(struct rte_eth_dev *);
218 void mlx5_dev_stop(struct rte_eth_dev *);
220 #endif /* RTE_PMD_MLX5_H_ */