1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
4 #include <rte_flow_driver.h>
5 #include <rte_malloc.h>
13 * Allocate flow counters via devx interface.
16 * ibv contexts returned from mlx5dv_open_device.
18 * Pointer to counters properties structure to be filled by the routine.
20 * Bulk counter numbers in 128 counters units.
23 * Pointer to counter object on success, a negative value otherwise and
26 struct mlx5_devx_obj *
27 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
29 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
30 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
31 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
37 MLX5_SET(alloc_flow_counter_in, in, opcode,
38 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
39 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
40 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
41 sizeof(in), out, sizeof(out));
43 DRV_LOG(ERR, "Can't allocate counters - error %d\n", errno);
48 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
53 * Query flow counters values.
56 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
58 * Whether hardware should clear the counters after the query or not.
59 * @param[in] n_counters
60 * 0 in case of 1 counter to read, otherwise the counter number to read.
62 * The number of packets that matched the flow.
64 * The number of bytes that matched the flow.
66 * The mkey key for batch query.
68 * The address in the mkey range for batch query.
70 * The completion object for asynchronous batch query.
72 * The ID to be returned in the asynchronous batch query response.
75 * 0 on success, a negative value otherwise.
78 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
79 int clear, uint32_t n_counters,
80 uint64_t *pkts, uint64_t *bytes,
81 uint32_t mkey, void *addr,
82 struct mlx5dv_devx_cmd_comp *cmd_comp,
85 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
86 MLX5_ST_SZ_BYTES(traffic_counter);
87 uint32_t out[out_len];
88 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
92 MLX5_SET(query_flow_counter_in, in, opcode,
93 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
94 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
95 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
96 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
99 MLX5_SET(query_flow_counter_in, in, num_of_counters,
101 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
102 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
103 MLX5_SET64(query_flow_counter_in, in, address,
104 (uint64_t)(uintptr_t)addr);
107 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
110 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
114 DRV_LOG(ERR, "Failed to query devx counters with rc %d\n ", rc);
119 stats = MLX5_ADDR_OF(query_flow_counter_out,
120 out, flow_statistics);
121 *pkts = MLX5_GET64(traffic_counter, stats, packets);
122 *bytes = MLX5_GET64(traffic_counter, stats, octets);
131 * ibv contexts returned from mlx5dv_open_device.
133 * Attributes of the requested mkey.
136 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
139 struct mlx5_devx_obj *
140 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
141 struct mlx5_devx_mkey_attr *attr)
143 uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
144 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
146 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
148 uint32_t translation_size;
154 pgsize = sysconf(_SC_PAGESIZE);
155 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
156 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
157 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
159 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
160 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
161 MLX5_SET(mkc, mkc, lw, 0x1);
162 MLX5_SET(mkc, mkc, lr, 0x1);
163 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
164 MLX5_SET(mkc, mkc, qpn, 0xffffff);
165 MLX5_SET(mkc, mkc, pd, attr->pd);
166 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
167 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
168 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
169 MLX5_SET64(mkc, mkc, len, attr->size);
170 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
171 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
174 DRV_LOG(ERR, "Can't create mkey - error %d\n", errno);
179 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
180 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
185 * Get status of devx command response.
186 * Mainly used for asynchronous commands.
189 * The out response buffer.
192 * 0 on success, non-zero value otherwise.
195 mlx5_devx_get_out_command_status(void *out)
201 status = MLX5_GET(query_flow_counter_out, out, status);
203 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
205 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x\n", status,
212 * Destroy any object allocated by a Devx API.
215 * Pointer to a general object.
218 * 0 on success, a negative value otherwise.
221 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
227 ret = mlx5_glue->devx_obj_destroy(obj->obj);
233 * Query NIC vport context.
234 * Fills minimal inline attribute.
237 * ibv contexts returned from mlx5dv_open_device.
241 * Attributes device values.
244 * 0 on success, a negative value otherwise.
247 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
249 struct mlx5_hca_attr *attr)
251 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
252 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
254 int status, syndrome, rc;
256 /* Query NIC vport context to determine inline mode. */
257 MLX5_SET(query_nic_vport_context_in, in, opcode,
258 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
259 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
261 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
262 rc = mlx5_glue->devx_general_cmd(ctx,
267 status = MLX5_GET(query_nic_vport_context_out, out, status);
268 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
270 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
271 "status %x, syndrome = %x",
275 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
277 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
278 min_wqe_inline_mode);
281 rc = (rc > 0) ? -rc : rc;
286 * Query HCA attributes.
287 * Using those attributes we can check on run time if the device
288 * is having the required capabilities.
291 * ibv contexts returned from mlx5dv_open_device.
293 * Attributes device values.
296 * 0 on success, a negative value otherwise.
299 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
300 struct mlx5_hca_attr *attr)
302 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
303 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
305 int status, syndrome, rc;
307 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
308 MLX5_SET(query_hca_cap_in, in, op_mod,
309 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
310 MLX5_HCA_CAP_OPMOD_GET_CUR);
312 rc = mlx5_glue->devx_general_cmd(ctx,
313 in, sizeof(in), out, sizeof(out));
316 status = MLX5_GET(query_hca_cap_out, out, status);
317 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
319 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
320 "status %x, syndrome = %x",
324 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
325 attr->flow_counter_bulk_alloc_bitmap =
326 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
327 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
329 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
330 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
332 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
333 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
334 flex_parser_protocols);
335 if (!attr->eth_net_offloads)
338 /* Query HCA offloads for Ethernet protocol. */
339 memset(in, 0, sizeof(in));
340 memset(out, 0, sizeof(out));
341 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
342 MLX5_SET(query_hca_cap_in, in, op_mod,
343 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
344 MLX5_HCA_CAP_OPMOD_GET_CUR);
346 rc = mlx5_glue->devx_general_cmd(ctx,
350 attr->eth_net_offloads = 0;
353 status = MLX5_GET(query_hca_cap_out, out, status);
354 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
356 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
357 "status %x, syndrome = %x",
359 attr->eth_net_offloads = 0;
362 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
363 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
364 hcattr, wqe_vlan_insert);
365 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
367 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
368 hcattr, tunnel_lro_gre);
369 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
370 hcattr, tunnel_lro_vxlan);
371 attr->lro_max_msg_sz_mode = MLX5_GET
372 (per_protocol_networking_offload_caps,
373 hcattr, lro_max_msg_sz_mode);
374 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
375 attr->lro_timer_supported_periods[i] =
376 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
377 lro_timer_supported_periods[i]);
379 attr->tunnel_stateless_geneve_rx =
380 MLX5_GET(per_protocol_networking_offload_caps,
381 hcattr, tunnel_stateless_geneve_rx);
382 attr->geneve_max_opt_len =
383 MLX5_GET(per_protocol_networking_offload_caps,
384 hcattr, max_geneve_opt_len);
385 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
386 hcattr, wqe_inline_mode);
387 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
389 if (attr->eth_virt) {
390 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
398 rc = (rc > 0) ? -rc : rc;
403 * Query TIS transport domain from QP verbs object using DevX API.
406 * Pointer to verbs QP returned by ibv_create_qp .
408 * TIS number of TIS to query.
410 * Pointer to TIS transport domain variable, to be set by the routine.
413 * 0 on success, a negative value otherwise.
416 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
419 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
420 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
424 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
425 MLX5_SET(query_tis_in, in, tisn, tis_num);
426 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
428 DRV_LOG(ERR, "Failed to query QP using DevX");
431 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
432 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
437 * Fill WQ data for DevX API command.
438 * Utility function for use when creating DevX objects containing a WQ.
441 * Pointer to WQ context to fill with data.
442 * @param [in] wq_attr
443 * Pointer to WQ attributes structure to fill in WQ context.
446 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
448 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
449 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
450 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
451 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
452 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
453 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
454 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
455 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
456 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
457 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
458 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
459 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
460 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
461 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
462 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
463 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
464 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
465 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
466 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
467 wq_attr->log_hairpin_num_packets);
468 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
469 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
470 wq_attr->single_wqe_log_num_of_strides);
471 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
472 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
473 wq_attr->single_stride_log_num_of_bytes);
474 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
475 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
476 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
480 * Create RQ using DevX API.
483 * ibv_context returned from mlx5dv_open_device.
484 * @param [in] rq_attr
485 * Pointer to create RQ attributes structure.
487 * CPU socket ID for allocations.
490 * The DevX object created, NULL otherwise and rte_errno is set.
492 struct mlx5_devx_obj *
493 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
494 struct mlx5_devx_create_rq_attr *rq_attr,
497 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
498 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
499 void *rq_ctx, *wq_ctx;
500 struct mlx5_devx_wq_attr *wq_attr;
501 struct mlx5_devx_obj *rq = NULL;
503 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
505 DRV_LOG(ERR, "Failed to allocate RQ data");
509 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
510 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
511 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
512 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
513 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
514 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
515 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
516 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
517 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
518 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
519 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
520 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
521 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
522 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
523 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
524 wq_attr = &rq_attr->wq_attr;
525 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
526 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
529 DRV_LOG(ERR, "Failed to create RQ using DevX");
534 rq->id = MLX5_GET(create_rq_out, out, rqn);
539 * Modify RQ using DevX API.
542 * Pointer to RQ object structure.
543 * @param [in] rq_attr
544 * Pointer to modify RQ attributes structure.
547 * 0 on success, a negative errno value otherwise and rte_errno is set.
550 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
551 struct mlx5_devx_modify_rq_attr *rq_attr)
553 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
554 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
555 void *rq_ctx, *wq_ctx;
558 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
559 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
560 MLX5_SET(modify_rq_in, in, rqn, rq->id);
561 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
562 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
563 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
564 if (rq_attr->modify_bitmask &
565 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
566 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
567 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
568 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
569 if (rq_attr->modify_bitmask &
570 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
571 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
572 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
573 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
574 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
575 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
576 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
578 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
581 DRV_LOG(ERR, "Failed to modify RQ using DevX");
589 * Create TIR using DevX API.
592 * ibv_context returned from mlx5dv_open_device.
593 * @param [in] tir_attr
594 * Pointer to TIR attributes structure.
597 * The DevX object created, NULL otherwise and rte_errno is set.
599 struct mlx5_devx_obj *
600 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
601 struct mlx5_devx_tir_attr *tir_attr)
603 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
604 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
605 void *tir_ctx, *outer, *inner;
606 struct mlx5_devx_obj *tir = NULL;
609 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
611 DRV_LOG(ERR, "Failed to allocate TIR data");
615 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
616 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
617 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
618 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
619 tir_attr->lro_timeout_period_usecs);
620 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
621 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
622 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
623 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
624 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
625 tir_attr->tunneled_offload_en);
626 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
627 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
628 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
629 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
630 for (i = 0; i < 10; i++) {
631 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
632 tir_attr->rx_hash_toeplitz_key[i]);
634 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
635 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
636 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
637 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
638 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
639 MLX5_SET(rx_hash_field_select, outer, selected_fields,
640 tir_attr->rx_hash_field_selector_outer.selected_fields);
641 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
642 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
643 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
644 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
645 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
646 MLX5_SET(rx_hash_field_select, inner, selected_fields,
647 tir_attr->rx_hash_field_selector_inner.selected_fields);
648 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
651 DRV_LOG(ERR, "Failed to create TIR using DevX");
656 tir->id = MLX5_GET(create_tir_out, out, tirn);
661 * Create RQT using DevX API.
664 * ibv_context returned from mlx5dv_open_device.
665 * @param [in] rqt_attr
666 * Pointer to RQT attributes structure.
669 * The DevX object created, NULL otherwise and rte_errno is set.
671 struct mlx5_devx_obj *
672 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
673 struct mlx5_devx_rqt_attr *rqt_attr)
676 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
677 rqt_attr->rqt_actual_size * sizeof(uint32_t);
678 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
680 struct mlx5_devx_obj *rqt = NULL;
683 in = rte_calloc(__func__, 1, inlen, 0);
685 DRV_LOG(ERR, "Failed to allocate RQT IN data");
689 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
691 DRV_LOG(ERR, "Failed to allocate RQT data");
696 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
697 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
698 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
699 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
700 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
701 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
702 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
705 DRV_LOG(ERR, "Failed to create RQT using DevX");
710 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);