1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Pattern outer Layer bits. */
31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
38 /* Pattern inner Layer bits. */
39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
46 /* Pattern tunnel Layer bits. */
47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
49 #define MLX5_FLOW_LAYER_GRE (1u << 14)
50 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
51 /* List of tunnel Layer bits continued below. */
53 /* General pattern items bits. */
54 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
55 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
57 /* Pattern MISC bits. */
58 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
59 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
60 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
62 /* Pattern tunnel Layer bits (continued). */
63 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
64 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
65 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
68 #define MLX5_FLOW_LAYER_OUTER_L3 \
69 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
70 #define MLX5_FLOW_LAYER_OUTER_L4 \
71 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
72 #define MLX5_FLOW_LAYER_OUTER \
73 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
74 MLX5_FLOW_LAYER_OUTER_L4)
76 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
77 #define MLX5_FLOW_LAYER_IPV4_LRO \
78 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
79 #define MLX5_FLOW_LAYER_IPV6_LRO \
80 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
83 #define MLX5_FLOW_LAYER_TUNNEL \
84 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
85 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
86 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP)
89 #define MLX5_FLOW_LAYER_INNER_L3 \
90 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
91 #define MLX5_FLOW_LAYER_INNER_L4 \
92 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
93 #define MLX5_FLOW_LAYER_INNER \
94 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
95 MLX5_FLOW_LAYER_INNER_L4)
98 #define MLX5_FLOW_LAYER_L2 \
99 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
100 #define MLX5_FLOW_LAYER_L3_IPV4 \
101 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 #define MLX5_FLOW_LAYER_L3_IPV6 \
103 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 #define MLX5_FLOW_LAYER_L3 \
105 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
106 #define MLX5_FLOW_LAYER_L4 \
107 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
110 #define MLX5_FLOW_ACTION_DROP (1u << 0)
111 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
112 #define MLX5_FLOW_ACTION_RSS (1u << 2)
113 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
114 #define MLX5_FLOW_ACTION_MARK (1u << 4)
115 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
116 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
117 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
118 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
119 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
120 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
121 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
122 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
123 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
124 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
125 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
126 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
127 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
128 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
129 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
130 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
131 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
132 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
133 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
134 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
135 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
136 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
137 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
138 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
139 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
140 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
141 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
143 #define MLX5_FLOW_FATE_ACTIONS \
144 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
145 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
147 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
148 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
149 MLX5_FLOW_ACTION_JUMP)
151 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
152 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
153 MLX5_FLOW_ACTION_RAW_ENCAP)
155 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
156 MLX5_FLOW_ACTION_NVGRE_DECAP | \
157 MLX5_FLOW_ACTION_RAW_DECAP)
159 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
160 MLX5_FLOW_ACTION_SET_IPV4_DST | \
161 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
162 MLX5_FLOW_ACTION_SET_IPV6_DST | \
163 MLX5_FLOW_ACTION_SET_TP_SRC | \
164 MLX5_FLOW_ACTION_SET_TP_DST | \
165 MLX5_FLOW_ACTION_SET_TTL | \
166 MLX5_FLOW_ACTION_DEC_TTL | \
167 MLX5_FLOW_ACTION_SET_MAC_SRC | \
168 MLX5_FLOW_ACTION_SET_MAC_DST | \
169 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
170 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
171 MLX5_FLOW_ACTION_INC_TCP_ACK | \
172 MLX5_FLOW_ACTION_DEC_TCP_ACK)
175 #define IPPROTO_MPLS 137
178 /* UDP port number for MPLS */
179 #define MLX5_UDP_PORT_MPLS 6635
181 /* UDP port numbers for VxLAN. */
182 #define MLX5_UDP_PORT_VXLAN 4789
183 #define MLX5_UDP_PORT_VXLAN_GPE 4790
185 /* Priority reserved for default flows. */
186 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
189 * Number of sub priorities.
190 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
191 * matching on the NIC (firmware dependent) L4 most have the higher priority
192 * followed by L3 and ending with L2.
194 #define MLX5_PRIORITY_MAP_L2 2
195 #define MLX5_PRIORITY_MAP_L3 1
196 #define MLX5_PRIORITY_MAP_L4 0
197 #define MLX5_PRIORITY_MAP_MAX 3
199 /* Valid layer type for IPV4 RSS. */
200 #define MLX5_IPV4_LAYER_TYPES \
201 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
202 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
203 ETH_RSS_NONFRAG_IPV4_OTHER)
205 /* IBV hash source bits for IPV4. */
206 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
208 /* Valid layer type for IPV6 RSS. */
209 #define MLX5_IPV6_LAYER_TYPES \
210 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
211 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
212 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
214 /* IBV hash source bits for IPV6. */
215 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
217 enum mlx5_flow_drv_type {
220 MLX5_FLOW_TYPE_VERBS,
224 /* Matcher PRM representation */
225 struct mlx5_flow_dv_match_params {
227 /**< Size of match value. Do NOT split size and key! */
228 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
229 /**< Matcher value. This value is used as the mask or as a key. */
232 /* Matcher structure. */
233 struct mlx5_flow_dv_matcher {
234 LIST_ENTRY(mlx5_flow_dv_matcher) next;
235 /* Pointer to the next element. */
236 rte_atomic32_t refcnt; /**< Reference counter. */
237 void *matcher_object; /**< Pointer to DV matcher */
238 uint16_t crc; /**< CRC of key. */
239 uint16_t priority; /**< Priority of matcher. */
240 uint8_t egress; /**< Egress matcher. */
241 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
242 uint32_t group; /**< The matcher group. */
243 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
246 #define MLX5_ENCAP_MAX_LEN 132
248 /* Encap/decap resource structure. */
249 struct mlx5_flow_dv_encap_decap_resource {
250 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
251 /* Pointer to next element. */
252 rte_atomic32_t refcnt; /**< Reference counter. */
254 /**< Verbs encap/decap action object. */
255 uint8_t buf[MLX5_ENCAP_MAX_LEN];
257 uint8_t reformat_type;
259 uint64_t flags; /**< Flags for RDMA API. */
262 /* Tag resource structure. */
263 struct mlx5_flow_dv_tag_resource {
264 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
265 /* Pointer to next element. */
266 rte_atomic32_t refcnt; /**< Reference counter. */
268 /**< Verbs tag action object. */
269 uint32_t tag; /**< the tag value. */
272 /* Number of modification commands. */
273 #define MLX5_MODIFY_NUM 8
275 /* Modify resource structure */
276 struct mlx5_flow_dv_modify_hdr_resource {
277 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
278 /* Pointer to next element. */
279 rte_atomic32_t refcnt; /**< Reference counter. */
280 struct ibv_flow_action *verbs_action;
281 /**< Verbs modify header action object. */
282 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
283 uint32_t actions_num; /**< Number of modification actions. */
284 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
285 /**< Modification actions. */
286 uint64_t flags; /**< Flags for RDMA API. */
289 /* Jump action resource structure. */
290 struct mlx5_flow_dv_jump_tbl_resource {
291 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
292 /* Pointer to next element. */
293 rte_atomic32_t refcnt; /**< Reference counter. */
294 void *action; /**< Pointer to the rdma core action. */
295 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
296 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
299 /* Port ID resource structure. */
300 struct mlx5_flow_dv_port_id_action_resource {
301 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
302 /* Pointer to next element. */
303 rte_atomic32_t refcnt; /**< Reference counter. */
305 /**< Verbs tag action object. */
306 uint32_t port_id; /**< Port ID value. */
310 * Max number of actions per DV flow.
311 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
312 * In rdma-core file providers/mlx5/verbs.c
314 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
316 /* DV flows structure. */
317 struct mlx5_flow_dv {
318 uint64_t hash_fields; /**< Fields that participate in the hash. */
319 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
321 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
322 struct mlx5_flow_dv_match_params value;
323 /**< Holds the value that the packet is compared to. */
324 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
325 /**< Pointer to encap/decap resource in cache. */
326 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
327 /**< Pointer to modify header resource in cache. */
328 struct ibv_flow *flow; /**< Installed flow. */
329 struct mlx5_flow_dv_jump_tbl_resource *jump;
330 /**< Pointer to the jump action resource. */
331 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
332 /**< Pointer to port ID action resource. */
333 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
334 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
337 int actions_n; /**< number of actions. */
340 /* Verbs specification header. */
341 struct ibv_spec_header {
342 enum ibv_flow_spec_type type;
346 /** Handles information leading to a drop fate. */
347 struct mlx5_flow_verbs {
348 LIST_ENTRY(mlx5_flow_verbs) next;
349 unsigned int size; /**< Size of the attribute. */
351 struct ibv_flow_attr *attr;
352 /**< Pointer to the Specification buffer. */
353 uint8_t *specs; /**< Pointer to the specifications. */
355 struct ibv_flow *flow; /**< Verbs flow pointer. */
356 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
357 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
360 /** Device flow structure. */
362 LIST_ENTRY(mlx5_flow) next;
363 struct rte_flow *flow; /**< Pointer to the main flow. */
365 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
367 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
368 struct mlx5_flow_dv dv;
370 struct mlx5_flow_verbs verbs;
374 /* Flow structure. */
376 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
377 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
378 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
379 struct mlx5_flow_dv_tag_resource *tag_resource;
380 /**< pointer to the tag action. */
381 struct rte_flow_action_rss rss;/**< RSS context. */
382 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
383 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
384 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
385 /**< Device flows that are part of the flow. */
387 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
388 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
389 uint8_t ingress; /**< 1 if the flow is ingress. */
390 uint32_t group; /**< The group index. */
391 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
394 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
395 const struct rte_flow_attr *attr,
396 const struct rte_flow_item items[],
397 const struct rte_flow_action actions[],
398 struct rte_flow_error *error);
399 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
400 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
401 const struct rte_flow_action actions[], struct rte_flow_error *error);
402 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
403 struct mlx5_flow *dev_flow,
404 const struct rte_flow_attr *attr,
405 const struct rte_flow_item items[],
406 const struct rte_flow_action actions[],
407 struct rte_flow_error *error);
408 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
409 struct rte_flow_error *error);
410 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
411 struct rte_flow *flow);
412 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
413 struct rte_flow *flow);
414 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
415 struct rte_flow *flow,
416 const struct rte_flow_action *actions,
418 struct rte_flow_error *error);
419 struct mlx5_flow_driver_ops {
420 mlx5_flow_validate_t validate;
421 mlx5_flow_prepare_t prepare;
422 mlx5_flow_translate_t translate;
423 mlx5_flow_apply_t apply;
424 mlx5_flow_remove_t remove;
425 mlx5_flow_destroy_t destroy;
426 mlx5_flow_query_t query;
429 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
430 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
431 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
432 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
436 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
437 uint64_t layer_types,
438 uint64_t hash_fields);
439 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
440 uint32_t subpriority);
441 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
442 const struct rte_flow_attr *attr,
443 struct rte_flow_error *error);
444 int mlx5_flow_validate_action_drop(uint64_t action_flags,
445 const struct rte_flow_attr *attr,
446 struct rte_flow_error *error);
447 int mlx5_flow_validate_action_flag(uint64_t action_flags,
448 const struct rte_flow_attr *attr,
449 struct rte_flow_error *error);
450 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
451 uint64_t action_flags,
452 const struct rte_flow_attr *attr,
453 struct rte_flow_error *error);
454 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
455 uint64_t action_flags,
456 struct rte_eth_dev *dev,
457 const struct rte_flow_attr *attr,
458 struct rte_flow_error *error);
459 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
460 uint64_t action_flags,
461 struct rte_eth_dev *dev,
462 const struct rte_flow_attr *attr,
464 struct rte_flow_error *error);
465 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
466 const struct rte_flow_attr *attributes,
467 struct rte_flow_error *error);
468 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
470 const uint8_t *nic_mask,
472 struct rte_flow_error *error);
473 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
475 struct rte_flow_error *error);
476 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
478 uint8_t target_protocol,
479 struct rte_flow_error *error);
480 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
482 const struct rte_flow_item *gre_item,
483 struct rte_flow_error *error);
484 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
486 const struct rte_flow_item_ipv4 *acc_mask,
487 struct rte_flow_error *error);
488 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
490 const struct rte_flow_item_ipv6 *acc_mask,
491 struct rte_flow_error *error);
492 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
493 const struct rte_flow_item *item,
496 struct rte_flow_error *error);
497 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
499 uint8_t target_protocol,
500 const struct rte_flow_item_tcp *flow_mask,
501 struct rte_flow_error *error);
502 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
504 uint8_t target_protocol,
505 struct rte_flow_error *error);
506 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
508 struct rte_flow_error *error);
509 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
511 struct rte_flow_error *error);
512 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
514 struct rte_eth_dev *dev,
515 struct rte_flow_error *error);
516 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
518 uint8_t target_protocol,
519 struct rte_flow_error *error);
520 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
522 uint8_t target_protocol,
523 struct rte_flow_error *error);
524 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
526 uint8_t target_protocol,
527 struct rte_flow_error *error);
528 #endif /* RTE_PMD_MLX5_FLOW_H_ */