1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_cycles.h>
30 #include <rte_vxlan.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_common_os.h"
39 #include "mlx5_flow.h"
40 #include "mlx5_flow_os.h"
41 #include "mlx5_rxtx.h"
43 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
86 * Initialize flow attributes structure according to flow items' types.
88 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
89 * mode. For tunnel mode, the items to be modified are the outermost ones.
92 * Pointer to item specification.
94 * Pointer to flow attributes structure.
96 * Pointer to the sub flow.
97 * @param[in] tunnel_decap
98 * Whether action is after tunnel decapsulation.
101 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
102 struct mlx5_flow *dev_flow, bool tunnel_decap)
104 uint64_t layers = dev_flow->handle->layers;
107 * If layers is already initialized, it means this dev_flow is the
108 * suffix flow, the layers flags is set by the prefix flow. Need to
109 * use the layer flags from prefix flow as the suffix flow may not
110 * have the user defined items as the flow is split.
113 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
115 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
117 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
119 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
124 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
125 uint8_t next_protocol = 0xff;
126 switch (item->type) {
127 case RTE_FLOW_ITEM_TYPE_GRE:
128 case RTE_FLOW_ITEM_TYPE_NVGRE:
129 case RTE_FLOW_ITEM_TYPE_VXLAN:
130 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
131 case RTE_FLOW_ITEM_TYPE_GENEVE:
132 case RTE_FLOW_ITEM_TYPE_MPLS:
136 case RTE_FLOW_ITEM_TYPE_IPV4:
139 if (item->mask != NULL &&
140 ((const struct rte_flow_item_ipv4 *)
141 item->mask)->hdr.next_proto_id)
143 ((const struct rte_flow_item_ipv4 *)
144 (item->spec))->hdr.next_proto_id &
145 ((const struct rte_flow_item_ipv4 *)
146 (item->mask))->hdr.next_proto_id;
147 if ((next_protocol == IPPROTO_IPIP ||
148 next_protocol == IPPROTO_IPV6) && tunnel_decap)
151 case RTE_FLOW_ITEM_TYPE_IPV6:
154 if (item->mask != NULL &&
155 ((const struct rte_flow_item_ipv6 *)
156 item->mask)->hdr.proto)
158 ((const struct rte_flow_item_ipv6 *)
159 (item->spec))->hdr.proto &
160 ((const struct rte_flow_item_ipv6 *)
161 (item->mask))->hdr.proto;
162 if ((next_protocol == IPPROTO_IPIP ||
163 next_protocol == IPPROTO_IPV6) && tunnel_decap)
166 case RTE_FLOW_ITEM_TYPE_UDP:
170 case RTE_FLOW_ITEM_TYPE_TCP:
182 * Convert rte_mtr_color to mlx5 color.
191 rte_col_2_mlx5_col(enum rte_color rcol)
194 case RTE_COLOR_GREEN:
195 return MLX5_FLOW_COLOR_GREEN;
196 case RTE_COLOR_YELLOW:
197 return MLX5_FLOW_COLOR_YELLOW;
199 return MLX5_FLOW_COLOR_RED;
203 return MLX5_FLOW_COLOR_UNDEFINED;
206 struct field_modify_info {
207 uint32_t size; /* Size of field in protocol header, in bytes. */
208 uint32_t offset; /* Offset of field in protocol header, in bytes. */
209 enum mlx5_modification_field id;
212 struct field_modify_info modify_eth[] = {
213 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
214 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
215 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
216 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
220 struct field_modify_info modify_vlan_out_first_vid[] = {
221 /* Size in bits !!! */
222 {12, 0, MLX5_MODI_OUT_FIRST_VID},
226 struct field_modify_info modify_ipv4[] = {
227 {1, 1, MLX5_MODI_OUT_IP_DSCP},
228 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
229 {4, 12, MLX5_MODI_OUT_SIPV4},
230 {4, 16, MLX5_MODI_OUT_DIPV4},
234 struct field_modify_info modify_ipv6[] = {
235 {1, 0, MLX5_MODI_OUT_IP_DSCP},
236 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
237 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
238 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
239 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
240 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
241 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
242 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
243 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
244 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
248 struct field_modify_info modify_udp[] = {
249 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
250 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
254 struct field_modify_info modify_tcp[] = {
255 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
256 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
257 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
258 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
263 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
264 uint8_t next_protocol, uint64_t *item_flags,
267 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
268 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
269 if (next_protocol == IPPROTO_IPIP) {
270 *item_flags |= MLX5_FLOW_LAYER_IPIP;
273 if (next_protocol == IPPROTO_IPV6) {
274 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
280 * Acquire the synchronizing object to protect multithreaded access
281 * to shared dv context. Lock occurs only if context is actually
282 * shared, i.e. we have multiport IB device and representors are
286 * Pointer to the rte_eth_dev structure.
289 flow_dv_shared_lock(struct rte_eth_dev *dev)
291 struct mlx5_priv *priv = dev->data->dev_private;
292 struct mlx5_dev_ctx_shared *sh = priv->sh;
294 if (sh->dv_refcnt > 1) {
297 ret = pthread_mutex_lock(&sh->dv_mutex);
304 flow_dv_shared_unlock(struct rte_eth_dev *dev)
306 struct mlx5_priv *priv = dev->data->dev_private;
307 struct mlx5_dev_ctx_shared *sh = priv->sh;
309 if (sh->dv_refcnt > 1) {
312 ret = pthread_mutex_unlock(&sh->dv_mutex);
318 /* Update VLAN's VID/PCP based on input rte_flow_action.
321 * Pointer to struct rte_flow_action.
323 * Pointer to struct rte_vlan_hdr.
326 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
327 struct rte_vlan_hdr *vlan)
330 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
332 ((const struct rte_flow_action_of_set_vlan_pcp *)
333 action->conf)->vlan_pcp;
334 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
335 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
336 vlan->vlan_tci |= vlan_tci;
337 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
338 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
339 vlan->vlan_tci |= rte_be_to_cpu_16
340 (((const struct rte_flow_action_of_set_vlan_vid *)
341 action->conf)->vlan_vid);
346 * Fetch 1, 2, 3 or 4 byte field from the byte array
347 * and return as unsigned integer in host-endian format.
350 * Pointer to data array.
352 * Size of field to extract.
355 * converted field in host endian format.
357 static inline uint32_t
358 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
367 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
370 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
371 ret = (ret << 8) | *(data + sizeof(uint16_t));
374 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
385 * Convert modify-header action to DV specification.
387 * Data length of each action is determined by provided field description
388 * and the item mask. Data bit offset and width of each action is determined
389 * by provided item mask.
392 * Pointer to item specification.
394 * Pointer to field modification information.
395 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
396 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
397 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
399 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
400 * Negative offset value sets the same offset as source offset.
401 * size field is ignored, value is taken from source field.
402 * @param[in,out] resource
403 * Pointer to the modify-header resource.
405 * Type of modification.
407 * Pointer to the error structure.
410 * 0 on success, a negative errno value otherwise and rte_errno is set.
413 flow_dv_convert_modify_action(struct rte_flow_item *item,
414 struct field_modify_info *field,
415 struct field_modify_info *dcopy,
416 struct mlx5_flow_dv_modify_hdr_resource *resource,
417 uint32_t type, struct rte_flow_error *error)
419 uint32_t i = resource->actions_num;
420 struct mlx5_modification_cmd *actions = resource->actions;
423 * The item and mask are provided in big-endian format.
424 * The fields should be presented as in big-endian format either.
425 * Mask must be always present, it defines the actual field width.
427 MLX5_ASSERT(item->mask);
428 MLX5_ASSERT(field->size);
435 if (i >= MLX5_MAX_MODIFY_NUM)
436 return rte_flow_error_set(error, EINVAL,
437 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
438 "too many items to modify");
439 /* Fetch variable byte size mask from the array. */
440 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
441 field->offset, field->size);
446 /* Deduce actual data width in bits from mask value. */
447 off_b = rte_bsf32(mask);
448 size_b = sizeof(uint32_t) * CHAR_BIT -
449 off_b - __builtin_clz(mask);
451 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
452 actions[i] = (struct mlx5_modification_cmd) {
458 /* Convert entire record to expected big-endian format. */
459 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
460 if (type == MLX5_MODIFICATION_TYPE_COPY) {
462 actions[i].dst_field = dcopy->id;
463 actions[i].dst_offset =
464 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
465 /* Convert entire record to big-endian format. */
466 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
468 MLX5_ASSERT(item->spec);
469 data = flow_dv_fetch_field((const uint8_t *)item->spec +
470 field->offset, field->size);
471 /* Shift out the trailing masked bits from data. */
472 data = (data & mask) >> off_b;
473 actions[i].data1 = rte_cpu_to_be_32(data);
477 } while (field->size);
478 if (resource->actions_num == i)
479 return rte_flow_error_set(error, EINVAL,
480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
481 "invalid modification flow item");
482 resource->actions_num = i;
487 * Convert modify-header set IPv4 address action to DV specification.
489 * @param[in,out] resource
490 * Pointer to the modify-header resource.
492 * Pointer to action specification.
494 * Pointer to the error structure.
497 * 0 on success, a negative errno value otherwise and rte_errno is set.
500 flow_dv_convert_action_modify_ipv4
501 (struct mlx5_flow_dv_modify_hdr_resource *resource,
502 const struct rte_flow_action *action,
503 struct rte_flow_error *error)
505 const struct rte_flow_action_set_ipv4 *conf =
506 (const struct rte_flow_action_set_ipv4 *)(action->conf);
507 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
508 struct rte_flow_item_ipv4 ipv4;
509 struct rte_flow_item_ipv4 ipv4_mask;
511 memset(&ipv4, 0, sizeof(ipv4));
512 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
513 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
514 ipv4.hdr.src_addr = conf->ipv4_addr;
515 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
517 ipv4.hdr.dst_addr = conf->ipv4_addr;
518 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
521 item.mask = &ipv4_mask;
522 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
523 MLX5_MODIFICATION_TYPE_SET, error);
527 * Convert modify-header set IPv6 address action to DV specification.
529 * @param[in,out] resource
530 * Pointer to the modify-header resource.
532 * Pointer to action specification.
534 * Pointer to the error structure.
537 * 0 on success, a negative errno value otherwise and rte_errno is set.
540 flow_dv_convert_action_modify_ipv6
541 (struct mlx5_flow_dv_modify_hdr_resource *resource,
542 const struct rte_flow_action *action,
543 struct rte_flow_error *error)
545 const struct rte_flow_action_set_ipv6 *conf =
546 (const struct rte_flow_action_set_ipv6 *)(action->conf);
547 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
548 struct rte_flow_item_ipv6 ipv6;
549 struct rte_flow_item_ipv6 ipv6_mask;
551 memset(&ipv6, 0, sizeof(ipv6));
552 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
553 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
554 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
555 sizeof(ipv6.hdr.src_addr));
556 memcpy(&ipv6_mask.hdr.src_addr,
557 &rte_flow_item_ipv6_mask.hdr.src_addr,
558 sizeof(ipv6.hdr.src_addr));
560 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
561 sizeof(ipv6.hdr.dst_addr));
562 memcpy(&ipv6_mask.hdr.dst_addr,
563 &rte_flow_item_ipv6_mask.hdr.dst_addr,
564 sizeof(ipv6.hdr.dst_addr));
567 item.mask = &ipv6_mask;
568 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
569 MLX5_MODIFICATION_TYPE_SET, error);
573 * Convert modify-header set MAC address action to DV specification.
575 * @param[in,out] resource
576 * Pointer to the modify-header resource.
578 * Pointer to action specification.
580 * Pointer to the error structure.
583 * 0 on success, a negative errno value otherwise and rte_errno is set.
586 flow_dv_convert_action_modify_mac
587 (struct mlx5_flow_dv_modify_hdr_resource *resource,
588 const struct rte_flow_action *action,
589 struct rte_flow_error *error)
591 const struct rte_flow_action_set_mac *conf =
592 (const struct rte_flow_action_set_mac *)(action->conf);
593 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
594 struct rte_flow_item_eth eth;
595 struct rte_flow_item_eth eth_mask;
597 memset(ð, 0, sizeof(eth));
598 memset(ð_mask, 0, sizeof(eth_mask));
599 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
600 memcpy(ð.src.addr_bytes, &conf->mac_addr,
601 sizeof(eth.src.addr_bytes));
602 memcpy(ð_mask.src.addr_bytes,
603 &rte_flow_item_eth_mask.src.addr_bytes,
604 sizeof(eth_mask.src.addr_bytes));
606 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
607 sizeof(eth.dst.addr_bytes));
608 memcpy(ð_mask.dst.addr_bytes,
609 &rte_flow_item_eth_mask.dst.addr_bytes,
610 sizeof(eth_mask.dst.addr_bytes));
613 item.mask = ð_mask;
614 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
615 MLX5_MODIFICATION_TYPE_SET, error);
619 * Convert modify-header set VLAN VID action to DV specification.
621 * @param[in,out] resource
622 * Pointer to the modify-header resource.
624 * Pointer to action specification.
626 * Pointer to the error structure.
629 * 0 on success, a negative errno value otherwise and rte_errno is set.
632 flow_dv_convert_action_modify_vlan_vid
633 (struct mlx5_flow_dv_modify_hdr_resource *resource,
634 const struct rte_flow_action *action,
635 struct rte_flow_error *error)
637 const struct rte_flow_action_of_set_vlan_vid *conf =
638 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
639 int i = resource->actions_num;
640 struct mlx5_modification_cmd *actions = resource->actions;
641 struct field_modify_info *field = modify_vlan_out_first_vid;
643 if (i >= MLX5_MAX_MODIFY_NUM)
644 return rte_flow_error_set(error, EINVAL,
645 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
646 "too many items to modify");
647 actions[i] = (struct mlx5_modification_cmd) {
648 .action_type = MLX5_MODIFICATION_TYPE_SET,
650 .length = field->size,
651 .offset = field->offset,
653 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
654 actions[i].data1 = conf->vlan_vid;
655 actions[i].data1 = actions[i].data1 << 16;
656 resource->actions_num = ++i;
661 * Convert modify-header set TP action to DV specification.
663 * @param[in,out] resource
664 * Pointer to the modify-header resource.
666 * Pointer to action specification.
668 * Pointer to rte_flow_item objects list.
670 * Pointer to flow attributes structure.
671 * @param[in] dev_flow
672 * Pointer to the sub flow.
673 * @param[in] tunnel_decap
674 * Whether action is after tunnel decapsulation.
676 * Pointer to the error structure.
679 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 flow_dv_convert_action_modify_tp
683 (struct mlx5_flow_dv_modify_hdr_resource *resource,
684 const struct rte_flow_action *action,
685 const struct rte_flow_item *items,
686 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
687 bool tunnel_decap, struct rte_flow_error *error)
689 const struct rte_flow_action_set_tp *conf =
690 (const struct rte_flow_action_set_tp *)(action->conf);
691 struct rte_flow_item item;
692 struct rte_flow_item_udp udp;
693 struct rte_flow_item_udp udp_mask;
694 struct rte_flow_item_tcp tcp;
695 struct rte_flow_item_tcp tcp_mask;
696 struct field_modify_info *field;
699 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
701 memset(&udp, 0, sizeof(udp));
702 memset(&udp_mask, 0, sizeof(udp_mask));
703 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
704 udp.hdr.src_port = conf->port;
705 udp_mask.hdr.src_port =
706 rte_flow_item_udp_mask.hdr.src_port;
708 udp.hdr.dst_port = conf->port;
709 udp_mask.hdr.dst_port =
710 rte_flow_item_udp_mask.hdr.dst_port;
712 item.type = RTE_FLOW_ITEM_TYPE_UDP;
714 item.mask = &udp_mask;
717 MLX5_ASSERT(attr->tcp);
718 memset(&tcp, 0, sizeof(tcp));
719 memset(&tcp_mask, 0, sizeof(tcp_mask));
720 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
721 tcp.hdr.src_port = conf->port;
722 tcp_mask.hdr.src_port =
723 rte_flow_item_tcp_mask.hdr.src_port;
725 tcp.hdr.dst_port = conf->port;
726 tcp_mask.hdr.dst_port =
727 rte_flow_item_tcp_mask.hdr.dst_port;
729 item.type = RTE_FLOW_ITEM_TYPE_TCP;
731 item.mask = &tcp_mask;
734 return flow_dv_convert_modify_action(&item, field, NULL, resource,
735 MLX5_MODIFICATION_TYPE_SET, error);
739 * Convert modify-header set TTL action to DV specification.
741 * @param[in,out] resource
742 * Pointer to the modify-header resource.
744 * Pointer to action specification.
746 * Pointer to rte_flow_item objects list.
748 * Pointer to flow attributes structure.
749 * @param[in] dev_flow
750 * Pointer to the sub flow.
751 * @param[in] tunnel_decap
752 * Whether action is after tunnel decapsulation.
754 * Pointer to the error structure.
757 * 0 on success, a negative errno value otherwise and rte_errno is set.
760 flow_dv_convert_action_modify_ttl
761 (struct mlx5_flow_dv_modify_hdr_resource *resource,
762 const struct rte_flow_action *action,
763 const struct rte_flow_item *items,
764 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
765 bool tunnel_decap, struct rte_flow_error *error)
767 const struct rte_flow_action_set_ttl *conf =
768 (const struct rte_flow_action_set_ttl *)(action->conf);
769 struct rte_flow_item item;
770 struct rte_flow_item_ipv4 ipv4;
771 struct rte_flow_item_ipv4 ipv4_mask;
772 struct rte_flow_item_ipv6 ipv6;
773 struct rte_flow_item_ipv6 ipv6_mask;
774 struct field_modify_info *field;
777 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
779 memset(&ipv4, 0, sizeof(ipv4));
780 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
781 ipv4.hdr.time_to_live = conf->ttl_value;
782 ipv4_mask.hdr.time_to_live = 0xFF;
783 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
785 item.mask = &ipv4_mask;
788 MLX5_ASSERT(attr->ipv6);
789 memset(&ipv6, 0, sizeof(ipv6));
790 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
791 ipv6.hdr.hop_limits = conf->ttl_value;
792 ipv6_mask.hdr.hop_limits = 0xFF;
793 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
795 item.mask = &ipv6_mask;
798 return flow_dv_convert_modify_action(&item, field, NULL, resource,
799 MLX5_MODIFICATION_TYPE_SET, error);
803 * Convert modify-header decrement TTL action to DV specification.
805 * @param[in,out] resource
806 * Pointer to the modify-header resource.
808 * Pointer to action specification.
810 * Pointer to rte_flow_item objects list.
812 * Pointer to flow attributes structure.
813 * @param[in] dev_flow
814 * Pointer to the sub flow.
815 * @param[in] tunnel_decap
816 * Whether action is after tunnel decapsulation.
818 * Pointer to the error structure.
821 * 0 on success, a negative errno value otherwise and rte_errno is set.
824 flow_dv_convert_action_modify_dec_ttl
825 (struct mlx5_flow_dv_modify_hdr_resource *resource,
826 const struct rte_flow_item *items,
827 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
828 bool tunnel_decap, struct rte_flow_error *error)
830 struct rte_flow_item item;
831 struct rte_flow_item_ipv4 ipv4;
832 struct rte_flow_item_ipv4 ipv4_mask;
833 struct rte_flow_item_ipv6 ipv6;
834 struct rte_flow_item_ipv6 ipv6_mask;
835 struct field_modify_info *field;
838 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
840 memset(&ipv4, 0, sizeof(ipv4));
841 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
842 ipv4.hdr.time_to_live = 0xFF;
843 ipv4_mask.hdr.time_to_live = 0xFF;
844 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
846 item.mask = &ipv4_mask;
849 MLX5_ASSERT(attr->ipv6);
850 memset(&ipv6, 0, sizeof(ipv6));
851 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
852 ipv6.hdr.hop_limits = 0xFF;
853 ipv6_mask.hdr.hop_limits = 0xFF;
854 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
856 item.mask = &ipv6_mask;
859 return flow_dv_convert_modify_action(&item, field, NULL, resource,
860 MLX5_MODIFICATION_TYPE_ADD, error);
864 * Convert modify-header increment/decrement TCP Sequence number
865 * to DV specification.
867 * @param[in,out] resource
868 * Pointer to the modify-header resource.
870 * Pointer to action specification.
872 * Pointer to the error structure.
875 * 0 on success, a negative errno value otherwise and rte_errno is set.
878 flow_dv_convert_action_modify_tcp_seq
879 (struct mlx5_flow_dv_modify_hdr_resource *resource,
880 const struct rte_flow_action *action,
881 struct rte_flow_error *error)
883 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
884 uint64_t value = rte_be_to_cpu_32(*conf);
885 struct rte_flow_item item;
886 struct rte_flow_item_tcp tcp;
887 struct rte_flow_item_tcp tcp_mask;
889 memset(&tcp, 0, sizeof(tcp));
890 memset(&tcp_mask, 0, sizeof(tcp_mask));
891 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
893 * The HW has no decrement operation, only increment operation.
894 * To simulate decrement X from Y using increment operation
895 * we need to add UINT32_MAX X times to Y.
896 * Each adding of UINT32_MAX decrements Y by 1.
899 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
900 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
901 item.type = RTE_FLOW_ITEM_TYPE_TCP;
903 item.mask = &tcp_mask;
904 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
905 MLX5_MODIFICATION_TYPE_ADD, error);
909 * Convert modify-header increment/decrement TCP Acknowledgment number
910 * to DV specification.
912 * @param[in,out] resource
913 * Pointer to the modify-header resource.
915 * Pointer to action specification.
917 * Pointer to the error structure.
920 * 0 on success, a negative errno value otherwise and rte_errno is set.
923 flow_dv_convert_action_modify_tcp_ack
924 (struct mlx5_flow_dv_modify_hdr_resource *resource,
925 const struct rte_flow_action *action,
926 struct rte_flow_error *error)
928 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
929 uint64_t value = rte_be_to_cpu_32(*conf);
930 struct rte_flow_item item;
931 struct rte_flow_item_tcp tcp;
932 struct rte_flow_item_tcp tcp_mask;
934 memset(&tcp, 0, sizeof(tcp));
935 memset(&tcp_mask, 0, sizeof(tcp_mask));
936 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
938 * The HW has no decrement operation, only increment operation.
939 * To simulate decrement X from Y using increment operation
940 * we need to add UINT32_MAX X times to Y.
941 * Each adding of UINT32_MAX decrements Y by 1.
944 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
945 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
946 item.type = RTE_FLOW_ITEM_TYPE_TCP;
948 item.mask = &tcp_mask;
949 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
950 MLX5_MODIFICATION_TYPE_ADD, error);
953 static enum mlx5_modification_field reg_to_field[] = {
954 [REG_NONE] = MLX5_MODI_OUT_NONE,
955 [REG_A] = MLX5_MODI_META_DATA_REG_A,
956 [REG_B] = MLX5_MODI_META_DATA_REG_B,
957 [REG_C_0] = MLX5_MODI_META_REG_C_0,
958 [REG_C_1] = MLX5_MODI_META_REG_C_1,
959 [REG_C_2] = MLX5_MODI_META_REG_C_2,
960 [REG_C_3] = MLX5_MODI_META_REG_C_3,
961 [REG_C_4] = MLX5_MODI_META_REG_C_4,
962 [REG_C_5] = MLX5_MODI_META_REG_C_5,
963 [REG_C_6] = MLX5_MODI_META_REG_C_6,
964 [REG_C_7] = MLX5_MODI_META_REG_C_7,
968 * Convert register set to DV specification.
970 * @param[in,out] resource
971 * Pointer to the modify-header resource.
973 * Pointer to action specification.
975 * Pointer to the error structure.
978 * 0 on success, a negative errno value otherwise and rte_errno is set.
981 flow_dv_convert_action_set_reg
982 (struct mlx5_flow_dv_modify_hdr_resource *resource,
983 const struct rte_flow_action *action,
984 struct rte_flow_error *error)
986 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
987 struct mlx5_modification_cmd *actions = resource->actions;
988 uint32_t i = resource->actions_num;
990 if (i >= MLX5_MAX_MODIFY_NUM)
991 return rte_flow_error_set(error, EINVAL,
992 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
993 "too many items to modify");
994 MLX5_ASSERT(conf->id != REG_NONE);
995 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
996 actions[i] = (struct mlx5_modification_cmd) {
997 .action_type = MLX5_MODIFICATION_TYPE_SET,
998 .field = reg_to_field[conf->id],
1000 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1001 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1003 resource->actions_num = i;
1008 * Convert SET_TAG action to DV specification.
1011 * Pointer to the rte_eth_dev structure.
1012 * @param[in,out] resource
1013 * Pointer to the modify-header resource.
1015 * Pointer to action specification.
1017 * Pointer to the error structure.
1020 * 0 on success, a negative errno value otherwise and rte_errno is set.
1023 flow_dv_convert_action_set_tag
1024 (struct rte_eth_dev *dev,
1025 struct mlx5_flow_dv_modify_hdr_resource *resource,
1026 const struct rte_flow_action_set_tag *conf,
1027 struct rte_flow_error *error)
1029 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1030 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1031 struct rte_flow_item item = {
1035 struct field_modify_info reg_c_x[] = {
1038 enum mlx5_modification_field reg_type;
1041 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1044 MLX5_ASSERT(ret != REG_NONE);
1045 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1046 reg_type = reg_to_field[ret];
1047 MLX5_ASSERT(reg_type > 0);
1048 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1049 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1050 MLX5_MODIFICATION_TYPE_SET, error);
1054 * Convert internal COPY_REG action to DV specification.
1057 * Pointer to the rte_eth_dev structure.
1058 * @param[in,out] res
1059 * Pointer to the modify-header resource.
1061 * Pointer to action specification.
1063 * Pointer to the error structure.
1066 * 0 on success, a negative errno value otherwise and rte_errno is set.
1069 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1070 struct mlx5_flow_dv_modify_hdr_resource *res,
1071 const struct rte_flow_action *action,
1072 struct rte_flow_error *error)
1074 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1075 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1076 struct rte_flow_item item = {
1080 struct field_modify_info reg_src[] = {
1081 {4, 0, reg_to_field[conf->src]},
1084 struct field_modify_info reg_dst = {
1086 .id = reg_to_field[conf->dst],
1088 /* Adjust reg_c[0] usage according to reported mask. */
1089 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1090 struct mlx5_priv *priv = dev->data->dev_private;
1091 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1093 MLX5_ASSERT(reg_c0);
1094 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1095 if (conf->dst == REG_C_0) {
1096 /* Copy to reg_c[0], within mask only. */
1097 reg_dst.offset = rte_bsf32(reg_c0);
1099 * Mask is ignoring the enianness, because
1100 * there is no conversion in datapath.
1102 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1103 /* Copy from destination lower bits to reg_c[0]. */
1104 mask = reg_c0 >> reg_dst.offset;
1106 /* Copy from destination upper bits to reg_c[0]. */
1107 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1108 rte_fls_u32(reg_c0));
1111 mask = rte_cpu_to_be_32(reg_c0);
1112 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1113 /* Copy from reg_c[0] to destination lower bits. */
1116 /* Copy from reg_c[0] to destination upper bits. */
1117 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1118 (rte_fls_u32(reg_c0) -
1123 return flow_dv_convert_modify_action(&item,
1124 reg_src, ®_dst, res,
1125 MLX5_MODIFICATION_TYPE_COPY,
1130 * Convert MARK action to DV specification. This routine is used
1131 * in extensive metadata only and requires metadata register to be
1132 * handled. In legacy mode hardware tag resource is engaged.
1135 * Pointer to the rte_eth_dev structure.
1137 * Pointer to MARK action specification.
1138 * @param[in,out] resource
1139 * Pointer to the modify-header resource.
1141 * Pointer to the error structure.
1144 * 0 on success, a negative errno value otherwise and rte_errno is set.
1147 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1148 const struct rte_flow_action_mark *conf,
1149 struct mlx5_flow_dv_modify_hdr_resource *resource,
1150 struct rte_flow_error *error)
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1154 priv->sh->dv_mark_mask);
1155 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1156 struct rte_flow_item item = {
1160 struct field_modify_info reg_c_x[] = {
1161 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1167 return rte_flow_error_set(error, EINVAL,
1168 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1169 NULL, "zero mark action mask");
1170 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1173 MLX5_ASSERT(reg > 0);
1174 if (reg == REG_C_0) {
1175 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1176 uint32_t shl_c0 = rte_bsf32(msk_c0);
1178 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1179 mask = rte_cpu_to_be_32(mask) & msk_c0;
1180 mask = rte_cpu_to_be_32(mask << shl_c0);
1182 reg_c_x[0].id = reg_to_field[reg];
1183 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1184 MLX5_MODIFICATION_TYPE_SET, error);
1188 * Get metadata register index for specified steering domain.
1191 * Pointer to the rte_eth_dev structure.
1193 * Attributes of flow to determine steering domain.
1195 * Pointer to the error structure.
1198 * positive index on success, a negative errno value otherwise
1199 * and rte_errno is set.
1201 static enum modify_reg
1202 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1203 const struct rte_flow_attr *attr,
1204 struct rte_flow_error *error)
1207 mlx5_flow_get_reg_id(dev, attr->transfer ?
1211 MLX5_METADATA_RX, 0, error);
1213 return rte_flow_error_set(error,
1214 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1215 NULL, "unavailable "
1216 "metadata register");
1221 * Convert SET_META action to DV specification.
1224 * Pointer to the rte_eth_dev structure.
1225 * @param[in,out] resource
1226 * Pointer to the modify-header resource.
1228 * Attributes of flow that includes this item.
1230 * Pointer to action specification.
1232 * Pointer to the error structure.
1235 * 0 on success, a negative errno value otherwise and rte_errno is set.
1238 flow_dv_convert_action_set_meta
1239 (struct rte_eth_dev *dev,
1240 struct mlx5_flow_dv_modify_hdr_resource *resource,
1241 const struct rte_flow_attr *attr,
1242 const struct rte_flow_action_set_meta *conf,
1243 struct rte_flow_error *error)
1245 uint32_t data = conf->data;
1246 uint32_t mask = conf->mask;
1247 struct rte_flow_item item = {
1251 struct field_modify_info reg_c_x[] = {
1254 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1259 * In datapath code there is no endianness
1260 * coversions for perfromance reasons, all
1261 * pattern conversions are done in rte_flow.
1263 if (reg == REG_C_0) {
1264 struct mlx5_priv *priv = dev->data->dev_private;
1265 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1268 MLX5_ASSERT(msk_c0);
1269 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1270 shl_c0 = rte_bsf32(msk_c0);
1272 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1276 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1278 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1279 /* The routine expects parameters in memory as big-endian ones. */
1280 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1281 MLX5_MODIFICATION_TYPE_SET, error);
1285 * Convert modify-header set IPv4 DSCP action to DV specification.
1287 * @param[in,out] resource
1288 * Pointer to the modify-header resource.
1290 * Pointer to action specification.
1292 * Pointer to the error structure.
1295 * 0 on success, a negative errno value otherwise and rte_errno is set.
1298 flow_dv_convert_action_modify_ipv4_dscp
1299 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1300 const struct rte_flow_action *action,
1301 struct rte_flow_error *error)
1303 const struct rte_flow_action_set_dscp *conf =
1304 (const struct rte_flow_action_set_dscp *)(action->conf);
1305 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1306 struct rte_flow_item_ipv4 ipv4;
1307 struct rte_flow_item_ipv4 ipv4_mask;
1309 memset(&ipv4, 0, sizeof(ipv4));
1310 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1311 ipv4.hdr.type_of_service = conf->dscp;
1312 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1314 item.mask = &ipv4_mask;
1315 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1316 MLX5_MODIFICATION_TYPE_SET, error);
1320 * Convert modify-header set IPv6 DSCP action to DV specification.
1322 * @param[in,out] resource
1323 * Pointer to the modify-header resource.
1325 * Pointer to action specification.
1327 * Pointer to the error structure.
1330 * 0 on success, a negative errno value otherwise and rte_errno is set.
1333 flow_dv_convert_action_modify_ipv6_dscp
1334 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1335 const struct rte_flow_action *action,
1336 struct rte_flow_error *error)
1338 const struct rte_flow_action_set_dscp *conf =
1339 (const struct rte_flow_action_set_dscp *)(action->conf);
1340 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1341 struct rte_flow_item_ipv6 ipv6;
1342 struct rte_flow_item_ipv6 ipv6_mask;
1344 memset(&ipv6, 0, sizeof(ipv6));
1345 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1347 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1348 * rdma-core only accept the DSCP bits byte aligned start from
1349 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1350 * bits in IPv6 case as rdma-core requires byte aligned value.
1352 ipv6.hdr.vtc_flow = conf->dscp;
1353 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1355 item.mask = &ipv6_mask;
1356 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1357 MLX5_MODIFICATION_TYPE_SET, error);
1361 * Validate MARK item.
1364 * Pointer to the rte_eth_dev structure.
1366 * Item specification.
1368 * Attributes of flow that includes this item.
1370 * Pointer to error structure.
1373 * 0 on success, a negative errno value otherwise and rte_errno is set.
1376 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1377 const struct rte_flow_item *item,
1378 const struct rte_flow_attr *attr __rte_unused,
1379 struct rte_flow_error *error)
1381 struct mlx5_priv *priv = dev->data->dev_private;
1382 struct mlx5_dev_config *config = &priv->config;
1383 const struct rte_flow_item_mark *spec = item->spec;
1384 const struct rte_flow_item_mark *mask = item->mask;
1385 const struct rte_flow_item_mark nic_mask = {
1386 .id = priv->sh->dv_mark_mask,
1390 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1391 return rte_flow_error_set(error, ENOTSUP,
1392 RTE_FLOW_ERROR_TYPE_ITEM, item,
1393 "extended metadata feature"
1395 if (!mlx5_flow_ext_mreg_supported(dev))
1396 return rte_flow_error_set(error, ENOTSUP,
1397 RTE_FLOW_ERROR_TYPE_ITEM, item,
1398 "extended metadata register"
1399 " isn't supported");
1401 return rte_flow_error_set(error, ENOTSUP,
1402 RTE_FLOW_ERROR_TYPE_ITEM, item,
1403 "extended metadata register"
1404 " isn't available");
1405 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1409 return rte_flow_error_set(error, EINVAL,
1410 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1412 "data cannot be empty");
1413 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1414 return rte_flow_error_set(error, EINVAL,
1415 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1417 "mark id exceeds the limit");
1421 return rte_flow_error_set(error, EINVAL,
1422 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1423 "mask cannot be zero");
1425 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1426 (const uint8_t *)&nic_mask,
1427 sizeof(struct rte_flow_item_mark),
1435 * Validate META item.
1438 * Pointer to the rte_eth_dev structure.
1440 * Item specification.
1442 * Attributes of flow that includes this item.
1444 * Pointer to error structure.
1447 * 0 on success, a negative errno value otherwise and rte_errno is set.
1450 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1451 const struct rte_flow_item *item,
1452 const struct rte_flow_attr *attr,
1453 struct rte_flow_error *error)
1455 struct mlx5_priv *priv = dev->data->dev_private;
1456 struct mlx5_dev_config *config = &priv->config;
1457 const struct rte_flow_item_meta *spec = item->spec;
1458 const struct rte_flow_item_meta *mask = item->mask;
1459 struct rte_flow_item_meta nic_mask = {
1466 return rte_flow_error_set(error, EINVAL,
1467 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1469 "data cannot be empty");
1470 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1471 if (!mlx5_flow_ext_mreg_supported(dev))
1472 return rte_flow_error_set(error, ENOTSUP,
1473 RTE_FLOW_ERROR_TYPE_ITEM, item,
1474 "extended metadata register"
1475 " isn't supported");
1476 reg = flow_dv_get_metadata_reg(dev, attr, error);
1480 return rte_flow_error_set(error, ENOTSUP,
1481 RTE_FLOW_ERROR_TYPE_ITEM, item,
1485 nic_mask.data = priv->sh->dv_meta_mask;
1486 } else if (attr->transfer) {
1487 return rte_flow_error_set(error, ENOTSUP,
1488 RTE_FLOW_ERROR_TYPE_ITEM, item,
1489 "extended metadata feature "
1490 "should be enabled when "
1491 "meta item is requested "
1492 "with e-switch mode ");
1495 mask = &rte_flow_item_meta_mask;
1497 return rte_flow_error_set(error, EINVAL,
1498 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1499 "mask cannot be zero");
1501 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1502 (const uint8_t *)&nic_mask,
1503 sizeof(struct rte_flow_item_meta),
1509 * Validate TAG item.
1512 * Pointer to the rte_eth_dev structure.
1514 * Item specification.
1516 * Attributes of flow that includes this item.
1518 * Pointer to error structure.
1521 * 0 on success, a negative errno value otherwise and rte_errno is set.
1524 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1525 const struct rte_flow_item *item,
1526 const struct rte_flow_attr *attr __rte_unused,
1527 struct rte_flow_error *error)
1529 const struct rte_flow_item_tag *spec = item->spec;
1530 const struct rte_flow_item_tag *mask = item->mask;
1531 const struct rte_flow_item_tag nic_mask = {
1532 .data = RTE_BE32(UINT32_MAX),
1537 if (!mlx5_flow_ext_mreg_supported(dev))
1538 return rte_flow_error_set(error, ENOTSUP,
1539 RTE_FLOW_ERROR_TYPE_ITEM, item,
1540 "extensive metadata register"
1541 " isn't supported");
1543 return rte_flow_error_set(error, EINVAL,
1544 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1546 "data cannot be empty");
1548 mask = &rte_flow_item_tag_mask;
1550 return rte_flow_error_set(error, EINVAL,
1551 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552 "mask cannot be zero");
1554 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1555 (const uint8_t *)&nic_mask,
1556 sizeof(struct rte_flow_item_tag),
1560 if (mask->index != 0xff)
1561 return rte_flow_error_set(error, EINVAL,
1562 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1563 "partial mask for tag index"
1564 " is not supported");
1565 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1568 MLX5_ASSERT(ret != REG_NONE);
1573 * Validate vport item.
1576 * Pointer to the rte_eth_dev structure.
1578 * Item specification.
1580 * Attributes of flow that includes this item.
1581 * @param[in] item_flags
1582 * Bit-fields that holds the items detected until now.
1584 * Pointer to error structure.
1587 * 0 on success, a negative errno value otherwise and rte_errno is set.
1590 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1591 const struct rte_flow_item *item,
1592 const struct rte_flow_attr *attr,
1593 uint64_t item_flags,
1594 struct rte_flow_error *error)
1596 const struct rte_flow_item_port_id *spec = item->spec;
1597 const struct rte_flow_item_port_id *mask = item->mask;
1598 const struct rte_flow_item_port_id switch_mask = {
1601 struct mlx5_priv *esw_priv;
1602 struct mlx5_priv *dev_priv;
1605 if (!attr->transfer)
1606 return rte_flow_error_set(error, EINVAL,
1607 RTE_FLOW_ERROR_TYPE_ITEM,
1609 "match on port id is valid only"
1610 " when transfer flag is enabled");
1611 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1612 return rte_flow_error_set(error, ENOTSUP,
1613 RTE_FLOW_ERROR_TYPE_ITEM, item,
1614 "multiple source ports are not"
1617 mask = &switch_mask;
1618 if (mask->id != 0xffffffff)
1619 return rte_flow_error_set(error, ENOTSUP,
1620 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1622 "no support for partial mask on"
1624 ret = mlx5_flow_item_acceptable
1625 (item, (const uint8_t *)mask,
1626 (const uint8_t *)&rte_flow_item_port_id_mask,
1627 sizeof(struct rte_flow_item_port_id),
1633 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1635 return rte_flow_error_set(error, rte_errno,
1636 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637 "failed to obtain E-Switch info for"
1639 dev_priv = mlx5_dev_to_eswitch_info(dev);
1641 return rte_flow_error_set(error, rte_errno,
1642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1644 "failed to obtain E-Switch info");
1645 if (esw_priv->domain_id != dev_priv->domain_id)
1646 return rte_flow_error_set(error, EINVAL,
1647 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1648 "cannot match on a port from a"
1649 " different E-Switch");
1654 * Validate VLAN item.
1657 * Item specification.
1658 * @param[in] item_flags
1659 * Bit-fields that holds the items detected until now.
1661 * Ethernet device flow is being created on.
1663 * Pointer to error structure.
1666 * 0 on success, a negative errno value otherwise and rte_errno is set.
1669 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1670 uint64_t item_flags,
1671 struct rte_eth_dev *dev,
1672 struct rte_flow_error *error)
1674 const struct rte_flow_item_vlan *mask = item->mask;
1675 const struct rte_flow_item_vlan nic_mask = {
1676 .tci = RTE_BE16(UINT16_MAX),
1677 .inner_type = RTE_BE16(UINT16_MAX),
1679 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1681 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1682 MLX5_FLOW_LAYER_INNER_L4) :
1683 (MLX5_FLOW_LAYER_OUTER_L3 |
1684 MLX5_FLOW_LAYER_OUTER_L4);
1685 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1686 MLX5_FLOW_LAYER_OUTER_VLAN;
1688 if (item_flags & vlanm)
1689 return rte_flow_error_set(error, EINVAL,
1690 RTE_FLOW_ERROR_TYPE_ITEM, item,
1691 "multiple VLAN layers not supported");
1692 else if ((item_flags & l34m) != 0)
1693 return rte_flow_error_set(error, EINVAL,
1694 RTE_FLOW_ERROR_TYPE_ITEM, item,
1695 "VLAN cannot follow L3/L4 layer");
1697 mask = &rte_flow_item_vlan_mask;
1698 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1699 (const uint8_t *)&nic_mask,
1700 sizeof(struct rte_flow_item_vlan),
1704 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1705 struct mlx5_priv *priv = dev->data->dev_private;
1707 if (priv->vmwa_context) {
1709 * Non-NULL context means we have a virtual machine
1710 * and SR-IOV enabled, we have to create VLAN interface
1711 * to make hypervisor to setup E-Switch vport
1712 * context correctly. We avoid creating the multiple
1713 * VLAN interfaces, so we cannot support VLAN tag mask.
1715 return rte_flow_error_set(error, EINVAL,
1716 RTE_FLOW_ERROR_TYPE_ITEM,
1718 "VLAN tag mask is not"
1719 " supported in virtual"
1727 * GTP flags are contained in 1 byte of the format:
1728 * -------------------------------------------
1729 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1730 * |-----------------------------------------|
1731 * | value | Version | PT | Res | E | S | PN |
1732 * -------------------------------------------
1734 * Matching is supported only for GTP flags E, S, PN.
1736 #define MLX5_GTP_FLAGS_MASK 0x07
1739 * Validate GTP item.
1742 * Pointer to the rte_eth_dev structure.
1744 * Item specification.
1745 * @param[in] item_flags
1746 * Bit-fields that holds the items detected until now.
1748 * Pointer to error structure.
1751 * 0 on success, a negative errno value otherwise and rte_errno is set.
1754 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1755 const struct rte_flow_item *item,
1756 uint64_t item_flags,
1757 struct rte_flow_error *error)
1759 struct mlx5_priv *priv = dev->data->dev_private;
1760 const struct rte_flow_item_gtp *spec = item->spec;
1761 const struct rte_flow_item_gtp *mask = item->mask;
1762 const struct rte_flow_item_gtp nic_mask = {
1763 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1765 .teid = RTE_BE32(0xffffffff),
1768 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1769 return rte_flow_error_set(error, ENOTSUP,
1770 RTE_FLOW_ERROR_TYPE_ITEM, item,
1771 "GTP support is not enabled");
1772 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1773 return rte_flow_error_set(error, ENOTSUP,
1774 RTE_FLOW_ERROR_TYPE_ITEM, item,
1775 "multiple tunnel layers not"
1777 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1778 return rte_flow_error_set(error, EINVAL,
1779 RTE_FLOW_ERROR_TYPE_ITEM, item,
1780 "no outer UDP layer found");
1782 mask = &rte_flow_item_gtp_mask;
1783 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1784 return rte_flow_error_set(error, ENOTSUP,
1785 RTE_FLOW_ERROR_TYPE_ITEM, item,
1786 "Match is supported for GTP"
1788 return mlx5_flow_item_acceptable
1789 (item, (const uint8_t *)mask,
1790 (const uint8_t *)&nic_mask,
1791 sizeof(struct rte_flow_item_gtp),
1796 * Validate the pop VLAN action.
1799 * Pointer to the rte_eth_dev structure.
1800 * @param[in] action_flags
1801 * Holds the actions detected until now.
1803 * Pointer to the pop vlan action.
1804 * @param[in] item_flags
1805 * The items found in this flow rule.
1807 * Pointer to flow attributes.
1809 * Pointer to error structure.
1812 * 0 on success, a negative errno value otherwise and rte_errno is set.
1815 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1816 uint64_t action_flags,
1817 const struct rte_flow_action *action,
1818 uint64_t item_flags,
1819 const struct rte_flow_attr *attr,
1820 struct rte_flow_error *error)
1822 const struct mlx5_priv *priv = dev->data->dev_private;
1826 if (!priv->sh->pop_vlan_action)
1827 return rte_flow_error_set(error, ENOTSUP,
1828 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1830 "pop vlan action is not supported");
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1835 "pop vlan action not supported for "
1837 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1838 return rte_flow_error_set(error, ENOTSUP,
1839 RTE_FLOW_ERROR_TYPE_ACTION, action,
1840 "no support for multiple VLAN "
1842 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1843 return rte_flow_error_set(error, ENOTSUP,
1844 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1846 "cannot pop vlan without a "
1847 "match on (outer) vlan in the flow");
1848 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1849 return rte_flow_error_set(error, EINVAL,
1850 RTE_FLOW_ERROR_TYPE_ACTION, action,
1851 "wrong action order, port_id should "
1852 "be after pop VLAN action");
1853 if (!attr->transfer && priv->representor)
1854 return rte_flow_error_set(error, ENOTSUP,
1855 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1856 "pop vlan action for VF representor "
1857 "not supported on NIC table");
1862 * Get VLAN default info from vlan match info.
1865 * the list of item specifications.
1867 * pointer VLAN info to fill to.
1870 * 0 on success, a negative errno value otherwise and rte_errno is set.
1873 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1874 struct rte_vlan_hdr *vlan)
1876 const struct rte_flow_item_vlan nic_mask = {
1877 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1878 MLX5DV_FLOW_VLAN_VID_MASK),
1879 .inner_type = RTE_BE16(0xffff),
1884 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1885 int type = items->type;
1887 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1888 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1891 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1892 const struct rte_flow_item_vlan *vlan_m = items->mask;
1893 const struct rte_flow_item_vlan *vlan_v = items->spec;
1895 /* If VLAN item in pattern doesn't contain data, return here. */
1900 /* Only full match values are accepted */
1901 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1902 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1903 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1905 rte_be_to_cpu_16(vlan_v->tci &
1906 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1908 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1909 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1910 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1912 rte_be_to_cpu_16(vlan_v->tci &
1913 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1915 if (vlan_m->inner_type == nic_mask.inner_type)
1916 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1917 vlan_m->inner_type);
1922 * Validate the push VLAN action.
1925 * Pointer to the rte_eth_dev structure.
1926 * @param[in] action_flags
1927 * Holds the actions detected until now.
1928 * @param[in] item_flags
1929 * The items found in this flow rule.
1931 * Pointer to the action structure.
1933 * Pointer to flow attributes
1935 * Pointer to error structure.
1938 * 0 on success, a negative errno value otherwise and rte_errno is set.
1941 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1942 uint64_t action_flags,
1943 const struct rte_flow_item_vlan *vlan_m,
1944 const struct rte_flow_action *action,
1945 const struct rte_flow_attr *attr,
1946 struct rte_flow_error *error)
1948 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1949 const struct mlx5_priv *priv = dev->data->dev_private;
1951 if (!attr->transfer && attr->ingress)
1952 return rte_flow_error_set(error, ENOTSUP,
1953 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1955 "push VLAN action not supported for "
1957 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1958 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1959 return rte_flow_error_set(error, EINVAL,
1960 RTE_FLOW_ERROR_TYPE_ACTION, action,
1961 "invalid vlan ethertype");
1962 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1963 return rte_flow_error_set(error, ENOTSUP,
1964 RTE_FLOW_ERROR_TYPE_ACTION, action,
1965 "no support for multiple VLAN "
1967 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1968 return rte_flow_error_set(error, EINVAL,
1969 RTE_FLOW_ERROR_TYPE_ACTION, action,
1970 "wrong action order, port_id should "
1971 "be after push VLAN");
1972 if (!attr->transfer && priv->representor)
1973 return rte_flow_error_set(error, ENOTSUP,
1974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1975 "push vlan action for VF representor "
1976 "not supported on NIC table");
1978 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1979 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1980 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1981 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1982 !(mlx5_flow_find_action
1983 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1984 return rte_flow_error_set(error, EINVAL,
1985 RTE_FLOW_ERROR_TYPE_ACTION, action,
1986 "not full match mask on VLAN PCP and "
1987 "there is no of_set_vlan_pcp action, "
1988 "push VLAN action cannot figure out "
1991 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1992 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1993 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1994 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1995 !(mlx5_flow_find_action
1996 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1997 return rte_flow_error_set(error, EINVAL,
1998 RTE_FLOW_ERROR_TYPE_ACTION, action,
1999 "not full match mask on VLAN VID and "
2000 "there is no of_set_vlan_vid action, "
2001 "push VLAN action cannot figure out "
2008 * Validate the set VLAN PCP.
2010 * @param[in] action_flags
2011 * Holds the actions detected until now.
2012 * @param[in] actions
2013 * Pointer to the list of actions remaining in the flow rule.
2015 * Pointer to error structure.
2018 * 0 on success, a negative errno value otherwise and rte_errno is set.
2021 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2022 const struct rte_flow_action actions[],
2023 struct rte_flow_error *error)
2025 const struct rte_flow_action *action = actions;
2026 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2028 if (conf->vlan_pcp > 7)
2029 return rte_flow_error_set(error, EINVAL,
2030 RTE_FLOW_ERROR_TYPE_ACTION, action,
2031 "VLAN PCP value is too big");
2032 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ACTION, action,
2035 "set VLAN PCP action must follow "
2036 "the push VLAN action");
2037 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2038 return rte_flow_error_set(error, ENOTSUP,
2039 RTE_FLOW_ERROR_TYPE_ACTION, action,
2040 "Multiple VLAN PCP modification are "
2042 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2043 return rte_flow_error_set(error, EINVAL,
2044 RTE_FLOW_ERROR_TYPE_ACTION, action,
2045 "wrong action order, port_id should "
2046 "be after set VLAN PCP");
2051 * Validate the set VLAN VID.
2053 * @param[in] item_flags
2054 * Holds the items detected in this rule.
2055 * @param[in] action_flags
2056 * Holds the actions detected until now.
2057 * @param[in] actions
2058 * Pointer to the list of actions remaining in the flow rule.
2060 * Pointer to error structure.
2063 * 0 on success, a negative errno value otherwise and rte_errno is set.
2066 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2067 uint64_t action_flags,
2068 const struct rte_flow_action actions[],
2069 struct rte_flow_error *error)
2071 const struct rte_flow_action *action = actions;
2072 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2074 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2075 return rte_flow_error_set(error, EINVAL,
2076 RTE_FLOW_ERROR_TYPE_ACTION, action,
2077 "VLAN VID value is too big");
2078 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2079 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2080 return rte_flow_error_set(error, ENOTSUP,
2081 RTE_FLOW_ERROR_TYPE_ACTION, action,
2082 "set VLAN VID action must follow push"
2083 " VLAN action or match on VLAN item");
2084 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2085 return rte_flow_error_set(error, ENOTSUP,
2086 RTE_FLOW_ERROR_TYPE_ACTION, action,
2087 "Multiple VLAN VID modifications are "
2089 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2090 return rte_flow_error_set(error, EINVAL,
2091 RTE_FLOW_ERROR_TYPE_ACTION, action,
2092 "wrong action order, port_id should "
2093 "be after set VLAN VID");
2098 * Validate the FLAG action.
2101 * Pointer to the rte_eth_dev structure.
2102 * @param[in] action_flags
2103 * Holds the actions detected until now.
2105 * Pointer to flow attributes
2107 * Pointer to error structure.
2110 * 0 on success, a negative errno value otherwise and rte_errno is set.
2113 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2114 uint64_t action_flags,
2115 const struct rte_flow_attr *attr,
2116 struct rte_flow_error *error)
2118 struct mlx5_priv *priv = dev->data->dev_private;
2119 struct mlx5_dev_config *config = &priv->config;
2122 /* Fall back if no extended metadata register support. */
2123 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2124 return mlx5_flow_validate_action_flag(action_flags, attr,
2126 /* Extensive metadata mode requires registers. */
2127 if (!mlx5_flow_ext_mreg_supported(dev))
2128 return rte_flow_error_set(error, ENOTSUP,
2129 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2130 "no metadata registers "
2131 "to support flag action");
2132 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2133 return rte_flow_error_set(error, ENOTSUP,
2134 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2135 "extended metadata register"
2136 " isn't available");
2137 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2140 MLX5_ASSERT(ret > 0);
2141 if (action_flags & MLX5_FLOW_ACTION_MARK)
2142 return rte_flow_error_set(error, EINVAL,
2143 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2144 "can't mark and flag in same flow");
2145 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2146 return rte_flow_error_set(error, EINVAL,
2147 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2149 " actions in same flow");
2154 * Validate MARK action.
2157 * Pointer to the rte_eth_dev structure.
2159 * Pointer to action.
2160 * @param[in] action_flags
2161 * Holds the actions detected until now.
2163 * Pointer to flow attributes
2165 * Pointer to error structure.
2168 * 0 on success, a negative errno value otherwise and rte_errno is set.
2171 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2172 const struct rte_flow_action *action,
2173 uint64_t action_flags,
2174 const struct rte_flow_attr *attr,
2175 struct rte_flow_error *error)
2177 struct mlx5_priv *priv = dev->data->dev_private;
2178 struct mlx5_dev_config *config = &priv->config;
2179 const struct rte_flow_action_mark *mark = action->conf;
2182 /* Fall back if no extended metadata register support. */
2183 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2184 return mlx5_flow_validate_action_mark(action, action_flags,
2186 /* Extensive metadata mode requires registers. */
2187 if (!mlx5_flow_ext_mreg_supported(dev))
2188 return rte_flow_error_set(error, ENOTSUP,
2189 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2190 "no metadata registers "
2191 "to support mark action");
2192 if (!priv->sh->dv_mark_mask)
2193 return rte_flow_error_set(error, ENOTSUP,
2194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2195 "extended metadata register"
2196 " isn't available");
2197 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2200 MLX5_ASSERT(ret > 0);
2202 return rte_flow_error_set(error, EINVAL,
2203 RTE_FLOW_ERROR_TYPE_ACTION, action,
2204 "configuration cannot be null");
2205 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2206 return rte_flow_error_set(error, EINVAL,
2207 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2209 "mark id exceeds the limit");
2210 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2211 return rte_flow_error_set(error, EINVAL,
2212 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2213 "can't flag and mark in same flow");
2214 if (action_flags & MLX5_FLOW_ACTION_MARK)
2215 return rte_flow_error_set(error, EINVAL,
2216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2217 "can't have 2 mark actions in same"
2223 * Validate SET_META action.
2226 * Pointer to the rte_eth_dev structure.
2228 * Pointer to the action structure.
2229 * @param[in] action_flags
2230 * Holds the actions detected until now.
2232 * Pointer to flow attributes
2234 * Pointer to error structure.
2237 * 0 on success, a negative errno value otherwise and rte_errno is set.
2240 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2241 const struct rte_flow_action *action,
2242 uint64_t action_flags __rte_unused,
2243 const struct rte_flow_attr *attr,
2244 struct rte_flow_error *error)
2246 const struct rte_flow_action_set_meta *conf;
2247 uint32_t nic_mask = UINT32_MAX;
2250 if (!mlx5_flow_ext_mreg_supported(dev))
2251 return rte_flow_error_set(error, ENOTSUP,
2252 RTE_FLOW_ERROR_TYPE_ACTION, action,
2253 "extended metadata register"
2254 " isn't supported");
2255 reg = flow_dv_get_metadata_reg(dev, attr, error);
2258 if (reg != REG_A && reg != REG_B) {
2259 struct mlx5_priv *priv = dev->data->dev_private;
2261 nic_mask = priv->sh->dv_meta_mask;
2263 if (!(action->conf))
2264 return rte_flow_error_set(error, EINVAL,
2265 RTE_FLOW_ERROR_TYPE_ACTION, action,
2266 "configuration cannot be null");
2267 conf = (const struct rte_flow_action_set_meta *)action->conf;
2269 return rte_flow_error_set(error, EINVAL,
2270 RTE_FLOW_ERROR_TYPE_ACTION, action,
2271 "zero mask doesn't have any effect");
2272 if (conf->mask & ~nic_mask)
2273 return rte_flow_error_set(error, EINVAL,
2274 RTE_FLOW_ERROR_TYPE_ACTION, action,
2275 "meta data must be within reg C0");
2280 * Validate SET_TAG action.
2283 * Pointer to the rte_eth_dev structure.
2285 * Pointer to the action structure.
2286 * @param[in] action_flags
2287 * Holds the actions detected until now.
2289 * Pointer to flow attributes
2291 * Pointer to error structure.
2294 * 0 on success, a negative errno value otherwise and rte_errno is set.
2297 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2298 const struct rte_flow_action *action,
2299 uint64_t action_flags,
2300 const struct rte_flow_attr *attr,
2301 struct rte_flow_error *error)
2303 const struct rte_flow_action_set_tag *conf;
2304 const uint64_t terminal_action_flags =
2305 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2306 MLX5_FLOW_ACTION_RSS;
2309 if (!mlx5_flow_ext_mreg_supported(dev))
2310 return rte_flow_error_set(error, ENOTSUP,
2311 RTE_FLOW_ERROR_TYPE_ACTION, action,
2312 "extensive metadata register"
2313 " isn't supported");
2314 if (!(action->conf))
2315 return rte_flow_error_set(error, EINVAL,
2316 RTE_FLOW_ERROR_TYPE_ACTION, action,
2317 "configuration cannot be null");
2318 conf = (const struct rte_flow_action_set_tag *)action->conf;
2320 return rte_flow_error_set(error, EINVAL,
2321 RTE_FLOW_ERROR_TYPE_ACTION, action,
2322 "zero mask doesn't have any effect");
2323 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2326 if (!attr->transfer && attr->ingress &&
2327 (action_flags & terminal_action_flags))
2328 return rte_flow_error_set(error, EINVAL,
2329 RTE_FLOW_ERROR_TYPE_ACTION, action,
2330 "set_tag has no effect"
2331 " with terminal actions");
2336 * Validate count action.
2339 * Pointer to rte_eth_dev structure.
2341 * Pointer to error structure.
2344 * 0 on success, a negative errno value otherwise and rte_errno is set.
2347 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2348 struct rte_flow_error *error)
2350 struct mlx5_priv *priv = dev->data->dev_private;
2352 if (!priv->config.devx)
2354 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2358 return rte_flow_error_set
2360 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2362 "count action not supported");
2366 * Validate the L2 encap action.
2369 * Pointer to the rte_eth_dev structure.
2370 * @param[in] action_flags
2371 * Holds the actions detected until now.
2373 * Pointer to the action structure.
2375 * Pointer to flow attributes.
2377 * Pointer to error structure.
2380 * 0 on success, a negative errno value otherwise and rte_errno is set.
2383 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2384 uint64_t action_flags,
2385 const struct rte_flow_action *action,
2386 const struct rte_flow_attr *attr,
2387 struct rte_flow_error *error)
2389 const struct mlx5_priv *priv = dev->data->dev_private;
2391 if (!(action->conf))
2392 return rte_flow_error_set(error, EINVAL,
2393 RTE_FLOW_ERROR_TYPE_ACTION, action,
2394 "configuration cannot be null");
2395 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2396 return rte_flow_error_set(error, EINVAL,
2397 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2398 "can only have a single encap action "
2400 if (!attr->transfer && priv->representor)
2401 return rte_flow_error_set(error, ENOTSUP,
2402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2403 "encap action for VF representor "
2404 "not supported on NIC table");
2409 * Validate a decap action.
2412 * Pointer to the rte_eth_dev structure.
2413 * @param[in] action_flags
2414 * Holds the actions detected until now.
2416 * Pointer to flow attributes
2418 * Pointer to error structure.
2421 * 0 on success, a negative errno value otherwise and rte_errno is set.
2424 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2425 uint64_t action_flags,
2426 const struct rte_flow_attr *attr,
2427 struct rte_flow_error *error)
2429 const struct mlx5_priv *priv = dev->data->dev_private;
2431 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2432 return rte_flow_error_set(error, ENOTSUP,
2433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2435 MLX5_FLOW_ACTION_DECAP ? "can only "
2436 "have a single decap action" : "decap "
2437 "after encap is not supported");
2438 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2439 return rte_flow_error_set(error, EINVAL,
2440 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2441 "can't have decap action after"
2444 return rte_flow_error_set(error, ENOTSUP,
2445 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2447 "decap action not supported for "
2449 if (!attr->transfer && priv->representor)
2450 return rte_flow_error_set(error, ENOTSUP,
2451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2452 "decap action for VF representor "
2453 "not supported on NIC table");
2457 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2460 * Validate the raw encap and decap actions.
2463 * Pointer to the rte_eth_dev structure.
2465 * Pointer to the decap action.
2467 * Pointer to the encap action.
2469 * Pointer to flow attributes
2470 * @param[in/out] action_flags
2471 * Holds the actions detected until now.
2472 * @param[out] actions_n
2473 * pointer to the number of actions counter.
2475 * Pointer to error structure.
2478 * 0 on success, a negative errno value otherwise and rte_errno is set.
2481 flow_dv_validate_action_raw_encap_decap
2482 (struct rte_eth_dev *dev,
2483 const struct rte_flow_action_raw_decap *decap,
2484 const struct rte_flow_action_raw_encap *encap,
2485 const struct rte_flow_attr *attr, uint64_t *action_flags,
2486 int *actions_n, struct rte_flow_error *error)
2488 const struct mlx5_priv *priv = dev->data->dev_private;
2491 if (encap && (!encap->size || !encap->data))
2492 return rte_flow_error_set(error, EINVAL,
2493 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2494 "raw encap data cannot be empty");
2495 if (decap && encap) {
2496 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2497 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2500 else if (encap->size <=
2501 MLX5_ENCAPSULATION_DECISION_SIZE &&
2503 MLX5_ENCAPSULATION_DECISION_SIZE)
2506 else if (encap->size >
2507 MLX5_ENCAPSULATION_DECISION_SIZE &&
2509 MLX5_ENCAPSULATION_DECISION_SIZE)
2510 /* 2 L2 actions: encap and decap. */
2513 return rte_flow_error_set(error,
2515 RTE_FLOW_ERROR_TYPE_ACTION,
2516 NULL, "unsupported too small "
2517 "raw decap and too small raw "
2518 "encap combination");
2521 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2525 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2529 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ACTION,
2533 "small raw encap size");
2534 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2535 return rte_flow_error_set(error, EINVAL,
2536 RTE_FLOW_ERROR_TYPE_ACTION,
2538 "more than one encap action");
2539 if (!attr->transfer && priv->representor)
2540 return rte_flow_error_set
2542 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2543 "encap action for VF representor "
2544 "not supported on NIC table");
2545 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2552 * Find existing encap/decap resource or create and register a new one.
2554 * @param[in, out] dev
2555 * Pointer to rte_eth_dev structure.
2556 * @param[in, out] resource
2557 * Pointer to encap/decap resource.
2558 * @parm[in, out] dev_flow
2559 * Pointer to the dev_flow.
2561 * pointer to error structure.
2564 * 0 on success otherwise -errno and errno is set.
2567 flow_dv_encap_decap_resource_register
2568 (struct rte_eth_dev *dev,
2569 struct mlx5_flow_dv_encap_decap_resource *resource,
2570 struct mlx5_flow *dev_flow,
2571 struct rte_flow_error *error)
2573 struct mlx5_priv *priv = dev->data->dev_private;
2574 struct mlx5_dev_ctx_shared *sh = priv->sh;
2575 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2576 struct mlx5dv_dr_domain *domain;
2580 resource->flags = dev_flow->dv.group ? 0 : 1;
2581 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2582 domain = sh->fdb_domain;
2583 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2584 domain = sh->rx_domain;
2586 domain = sh->tx_domain;
2587 /* Lookup a matching resource from cache. */
2588 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2589 cache_resource, next) {
2590 if (resource->reformat_type == cache_resource->reformat_type &&
2591 resource->ft_type == cache_resource->ft_type &&
2592 resource->flags == cache_resource->flags &&
2593 resource->size == cache_resource->size &&
2594 !memcmp((const void *)resource->buf,
2595 (const void *)cache_resource->buf,
2597 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2598 (void *)cache_resource,
2599 rte_atomic32_read(&cache_resource->refcnt));
2600 rte_atomic32_inc(&cache_resource->refcnt);
2601 dev_flow->handle->dvh.rix_encap_decap = idx;
2602 dev_flow->dv.encap_decap = cache_resource;
2606 /* Register new encap/decap resource. */
2607 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2608 &dev_flow->handle->dvh.rix_encap_decap);
2609 if (!cache_resource)
2610 return rte_flow_error_set(error, ENOMEM,
2611 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2612 "cannot allocate resource memory");
2613 *cache_resource = *resource;
2614 ret = mlx5_flow_os_create_flow_action_packet_reformat
2615 (sh->ctx, domain, cache_resource,
2616 &cache_resource->action);
2618 rte_free(cache_resource);
2619 return rte_flow_error_set(error, ENOMEM,
2620 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2621 NULL, "cannot create action");
2623 rte_atomic32_init(&cache_resource->refcnt);
2624 rte_atomic32_inc(&cache_resource->refcnt);
2625 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2626 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2628 dev_flow->dv.encap_decap = cache_resource;
2629 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2630 (void *)cache_resource,
2631 rte_atomic32_read(&cache_resource->refcnt));
2636 * Find existing table jump resource or create and register a new one.
2638 * @param[in, out] dev
2639 * Pointer to rte_eth_dev structure.
2640 * @param[in, out] tbl
2641 * Pointer to flow table resource.
2642 * @parm[in, out] dev_flow
2643 * Pointer to the dev_flow.
2645 * pointer to error structure.
2648 * 0 on success otherwise -errno and errno is set.
2651 flow_dv_jump_tbl_resource_register
2652 (struct rte_eth_dev *dev __rte_unused,
2653 struct mlx5_flow_tbl_resource *tbl,
2654 struct mlx5_flow *dev_flow,
2655 struct rte_flow_error *error)
2657 struct mlx5_flow_tbl_data_entry *tbl_data =
2658 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2662 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2664 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2665 (tbl->obj, &tbl_data->jump.action);
2667 return rte_flow_error_set(error, ENOMEM,
2668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2669 NULL, "cannot create jump action");
2670 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2671 (void *)&tbl_data->jump, cnt);
2673 /* old jump should not make the table ref++. */
2674 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2675 MLX5_ASSERT(tbl_data->jump.action);
2676 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2677 (void *)&tbl_data->jump, cnt);
2679 rte_atomic32_inc(&tbl_data->jump.refcnt);
2680 dev_flow->handle->rix_jump = tbl_data->idx;
2681 dev_flow->dv.jump = &tbl_data->jump;
2686 * Find existing default miss resource or create and register a new one.
2688 * @param[in, out] dev
2689 * Pointer to rte_eth_dev structure.
2691 * pointer to error structure.
2694 * 0 on success otherwise -errno and errno is set.
2697 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2698 struct rte_flow_error *error)
2700 struct mlx5_priv *priv = dev->data->dev_private;
2701 struct mlx5_dev_ctx_shared *sh = priv->sh;
2702 struct mlx5_flow_default_miss_resource *cache_resource =
2704 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2707 MLX5_ASSERT(cache_resource->action);
2708 cache_resource->action =
2709 mlx5_glue->dr_create_flow_action_default_miss();
2710 if (!cache_resource->action)
2711 return rte_flow_error_set(error, ENOMEM,
2712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2713 "cannot create default miss action");
2714 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2715 (void *)cache_resource->action, cnt);
2717 rte_atomic32_inc(&cache_resource->refcnt);
2722 * Find existing table port ID resource or create and register a new one.
2724 * @param[in, out] dev
2725 * Pointer to rte_eth_dev structure.
2726 * @param[in, out] resource
2727 * Pointer to port ID action resource.
2728 * @parm[in, out] dev_flow
2729 * Pointer to the dev_flow.
2731 * pointer to error structure.
2734 * 0 on success otherwise -errno and errno is set.
2737 flow_dv_port_id_action_resource_register
2738 (struct rte_eth_dev *dev,
2739 struct mlx5_flow_dv_port_id_action_resource *resource,
2740 struct mlx5_flow *dev_flow,
2741 struct rte_flow_error *error)
2743 struct mlx5_priv *priv = dev->data->dev_private;
2744 struct mlx5_dev_ctx_shared *sh = priv->sh;
2745 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2749 /* Lookup a matching resource from cache. */
2750 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2751 idx, cache_resource, next) {
2752 if (resource->port_id == cache_resource->port_id) {
2753 DRV_LOG(DEBUG, "port id action resource resource %p: "
2755 (void *)cache_resource,
2756 rte_atomic32_read(&cache_resource->refcnt));
2757 rte_atomic32_inc(&cache_resource->refcnt);
2758 dev_flow->handle->rix_port_id_action = idx;
2759 dev_flow->dv.port_id_action = cache_resource;
2763 /* Register new port id action resource. */
2764 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2765 &dev_flow->handle->rix_port_id_action);
2766 if (!cache_resource)
2767 return rte_flow_error_set(error, ENOMEM,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2769 "cannot allocate resource memory");
2770 *cache_resource = *resource;
2771 ret = mlx5_flow_os_create_flow_action_dest_port
2772 (priv->sh->fdb_domain, resource->port_id,
2773 &cache_resource->action);
2775 rte_free(cache_resource);
2776 return rte_flow_error_set(error, ENOMEM,
2777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 NULL, "cannot create action");
2780 rte_atomic32_init(&cache_resource->refcnt);
2781 rte_atomic32_inc(&cache_resource->refcnt);
2782 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2783 dev_flow->handle->rix_port_id_action, cache_resource,
2785 dev_flow->dv.port_id_action = cache_resource;
2786 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2787 (void *)cache_resource,
2788 rte_atomic32_read(&cache_resource->refcnt));
2793 * Find existing push vlan resource or create and register a new one.
2795 * @param [in, out] dev
2796 * Pointer to rte_eth_dev structure.
2797 * @param[in, out] resource
2798 * Pointer to port ID action resource.
2799 * @parm[in, out] dev_flow
2800 * Pointer to the dev_flow.
2802 * pointer to error structure.
2805 * 0 on success otherwise -errno and errno is set.
2808 flow_dv_push_vlan_action_resource_register
2809 (struct rte_eth_dev *dev,
2810 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2811 struct mlx5_flow *dev_flow,
2812 struct rte_flow_error *error)
2814 struct mlx5_priv *priv = dev->data->dev_private;
2815 struct mlx5_dev_ctx_shared *sh = priv->sh;
2816 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2817 struct mlx5dv_dr_domain *domain;
2821 /* Lookup a matching resource from cache. */
2822 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2823 sh->push_vlan_action_list, idx, cache_resource, next) {
2824 if (resource->vlan_tag == cache_resource->vlan_tag &&
2825 resource->ft_type == cache_resource->ft_type) {
2826 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2828 (void *)cache_resource,
2829 rte_atomic32_read(&cache_resource->refcnt));
2830 rte_atomic32_inc(&cache_resource->refcnt);
2831 dev_flow->handle->dvh.rix_push_vlan = idx;
2832 dev_flow->dv.push_vlan_res = cache_resource;
2836 /* Register new push_vlan action resource. */
2837 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2838 &dev_flow->handle->dvh.rix_push_vlan);
2839 if (!cache_resource)
2840 return rte_flow_error_set(error, ENOMEM,
2841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2842 "cannot allocate resource memory");
2843 *cache_resource = *resource;
2844 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2845 domain = sh->fdb_domain;
2846 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2847 domain = sh->rx_domain;
2849 domain = sh->tx_domain;
2850 ret = mlx5_flow_os_create_flow_action_push_vlan
2851 (domain, resource->vlan_tag,
2852 &cache_resource->action);
2854 rte_free(cache_resource);
2855 return rte_flow_error_set(error, ENOMEM,
2856 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2857 NULL, "cannot create action");
2859 rte_atomic32_init(&cache_resource->refcnt);
2860 rte_atomic32_inc(&cache_resource->refcnt);
2861 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2862 &sh->push_vlan_action_list,
2863 dev_flow->handle->dvh.rix_push_vlan,
2864 cache_resource, next);
2865 dev_flow->dv.push_vlan_res = cache_resource;
2866 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2867 (void *)cache_resource,
2868 rte_atomic32_read(&cache_resource->refcnt));
2872 * Get the size of specific rte_flow_item_type
2874 * @param[in] item_type
2875 * Tested rte_flow_item_type.
2878 * sizeof struct item_type, 0 if void or irrelevant.
2881 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2885 switch (item_type) {
2886 case RTE_FLOW_ITEM_TYPE_ETH:
2887 retval = sizeof(struct rte_flow_item_eth);
2889 case RTE_FLOW_ITEM_TYPE_VLAN:
2890 retval = sizeof(struct rte_flow_item_vlan);
2892 case RTE_FLOW_ITEM_TYPE_IPV4:
2893 retval = sizeof(struct rte_flow_item_ipv4);
2895 case RTE_FLOW_ITEM_TYPE_IPV6:
2896 retval = sizeof(struct rte_flow_item_ipv6);
2898 case RTE_FLOW_ITEM_TYPE_UDP:
2899 retval = sizeof(struct rte_flow_item_udp);
2901 case RTE_FLOW_ITEM_TYPE_TCP:
2902 retval = sizeof(struct rte_flow_item_tcp);
2904 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905 retval = sizeof(struct rte_flow_item_vxlan);
2907 case RTE_FLOW_ITEM_TYPE_GRE:
2908 retval = sizeof(struct rte_flow_item_gre);
2910 case RTE_FLOW_ITEM_TYPE_NVGRE:
2911 retval = sizeof(struct rte_flow_item_nvgre);
2913 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2914 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2916 case RTE_FLOW_ITEM_TYPE_MPLS:
2917 retval = sizeof(struct rte_flow_item_mpls);
2919 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2927 #define MLX5_ENCAP_IPV4_VERSION 0x40
2928 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2929 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2930 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2931 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2932 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2933 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2936 * Convert the encap action data from list of rte_flow_item to raw buffer
2939 * Pointer to rte_flow_item objects list.
2941 * Pointer to the output buffer.
2943 * Pointer to the output buffer size.
2945 * Pointer to the error structure.
2948 * 0 on success, a negative errno value otherwise and rte_errno is set.
2951 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2952 size_t *size, struct rte_flow_error *error)
2954 struct rte_ether_hdr *eth = NULL;
2955 struct rte_vlan_hdr *vlan = NULL;
2956 struct rte_ipv4_hdr *ipv4 = NULL;
2957 struct rte_ipv6_hdr *ipv6 = NULL;
2958 struct rte_udp_hdr *udp = NULL;
2959 struct rte_vxlan_hdr *vxlan = NULL;
2960 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2961 struct rte_gre_hdr *gre = NULL;
2963 size_t temp_size = 0;
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 NULL, "invalid empty data");
2969 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2970 len = flow_dv_get_item_len(items->type);
2971 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2972 return rte_flow_error_set(error, EINVAL,
2973 RTE_FLOW_ERROR_TYPE_ACTION,
2974 (void *)items->type,
2975 "items total size is too big"
2976 " for encap action");
2977 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2978 switch (items->type) {
2979 case RTE_FLOW_ITEM_TYPE_ETH:
2980 eth = (struct rte_ether_hdr *)&buf[temp_size];
2982 case RTE_FLOW_ITEM_TYPE_VLAN:
2983 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2985 return rte_flow_error_set(error, EINVAL,
2986 RTE_FLOW_ERROR_TYPE_ACTION,
2987 (void *)items->type,
2988 "eth header not found");
2989 if (!eth->ether_type)
2990 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2992 case RTE_FLOW_ITEM_TYPE_IPV4:
2993 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2995 return rte_flow_error_set(error, EINVAL,
2996 RTE_FLOW_ERROR_TYPE_ACTION,
2997 (void *)items->type,
2998 "neither eth nor vlan"
3000 if (vlan && !vlan->eth_proto)
3001 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3002 else if (eth && !eth->ether_type)
3003 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3004 if (!ipv4->version_ihl)
3005 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3006 MLX5_ENCAP_IPV4_IHL_MIN;
3007 if (!ipv4->time_to_live)
3008 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3010 case RTE_FLOW_ITEM_TYPE_IPV6:
3011 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3013 return rte_flow_error_set(error, EINVAL,
3014 RTE_FLOW_ERROR_TYPE_ACTION,
3015 (void *)items->type,
3016 "neither eth nor vlan"
3018 if (vlan && !vlan->eth_proto)
3019 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3020 else if (eth && !eth->ether_type)
3021 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3022 if (!ipv6->vtc_flow)
3024 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3025 if (!ipv6->hop_limits)
3026 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3028 case RTE_FLOW_ITEM_TYPE_UDP:
3029 udp = (struct rte_udp_hdr *)&buf[temp_size];
3031 return rte_flow_error_set(error, EINVAL,
3032 RTE_FLOW_ERROR_TYPE_ACTION,
3033 (void *)items->type,
3034 "ip header not found");
3035 if (ipv4 && !ipv4->next_proto_id)
3036 ipv4->next_proto_id = IPPROTO_UDP;
3037 else if (ipv6 && !ipv6->proto)
3038 ipv6->proto = IPPROTO_UDP;
3040 case RTE_FLOW_ITEM_TYPE_VXLAN:
3041 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3043 return rte_flow_error_set(error, EINVAL,
3044 RTE_FLOW_ERROR_TYPE_ACTION,
3045 (void *)items->type,
3046 "udp header not found");
3048 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3049 if (!vxlan->vx_flags)
3051 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3053 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3054 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3056 return rte_flow_error_set(error, EINVAL,
3057 RTE_FLOW_ERROR_TYPE_ACTION,
3058 (void *)items->type,
3059 "udp header not found");
3060 if (!vxlan_gpe->proto)
3061 return rte_flow_error_set(error, EINVAL,
3062 RTE_FLOW_ERROR_TYPE_ACTION,
3063 (void *)items->type,
3064 "next protocol not found");
3067 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3068 if (!vxlan_gpe->vx_flags)
3069 vxlan_gpe->vx_flags =
3070 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3072 case RTE_FLOW_ITEM_TYPE_GRE:
3073 case RTE_FLOW_ITEM_TYPE_NVGRE:
3074 gre = (struct rte_gre_hdr *)&buf[temp_size];
3076 return rte_flow_error_set(error, EINVAL,
3077 RTE_FLOW_ERROR_TYPE_ACTION,
3078 (void *)items->type,
3079 "next protocol not found");
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION,
3083 (void *)items->type,
3084 "ip header not found");
3085 if (ipv4 && !ipv4->next_proto_id)
3086 ipv4->next_proto_id = IPPROTO_GRE;
3087 else if (ipv6 && !ipv6->proto)
3088 ipv6->proto = IPPROTO_GRE;
3090 case RTE_FLOW_ITEM_TYPE_VOID:
3093 return rte_flow_error_set(error, EINVAL,
3094 RTE_FLOW_ERROR_TYPE_ACTION,
3095 (void *)items->type,
3096 "unsupported item type");
3106 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3108 struct rte_ether_hdr *eth = NULL;
3109 struct rte_vlan_hdr *vlan = NULL;
3110 struct rte_ipv6_hdr *ipv6 = NULL;
3111 struct rte_udp_hdr *udp = NULL;
3115 eth = (struct rte_ether_hdr *)data;
3116 next_hdr = (char *)(eth + 1);
3117 proto = RTE_BE16(eth->ether_type);
3120 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3121 vlan = (struct rte_vlan_hdr *)next_hdr;
3122 proto = RTE_BE16(vlan->eth_proto);
3123 next_hdr += sizeof(struct rte_vlan_hdr);
3126 /* HW calculates IPv4 csum. no need to proceed */
3127 if (proto == RTE_ETHER_TYPE_IPV4)
3130 /* non IPv4/IPv6 header. not supported */
3131 if (proto != RTE_ETHER_TYPE_IPV6) {
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION,
3134 NULL, "Cannot offload non IPv4/IPv6");
3137 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3139 /* ignore non UDP */
3140 if (ipv6->proto != IPPROTO_UDP)
3143 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3144 udp->dgram_cksum = 0;
3150 * Convert L2 encap action to DV specification.
3153 * Pointer to rte_eth_dev structure.
3155 * Pointer to action structure.
3156 * @param[in, out] dev_flow
3157 * Pointer to the mlx5_flow.
3158 * @param[in] transfer
3159 * Mark if the flow is E-Switch flow.
3161 * Pointer to the error structure.
3164 * 0 on success, a negative errno value otherwise and rte_errno is set.
3167 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3168 const struct rte_flow_action *action,
3169 struct mlx5_flow *dev_flow,
3171 struct rte_flow_error *error)
3173 const struct rte_flow_item *encap_data;
3174 const struct rte_flow_action_raw_encap *raw_encap_data;
3175 struct mlx5_flow_dv_encap_decap_resource res = {
3177 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3178 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3179 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3182 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3184 (const struct rte_flow_action_raw_encap *)action->conf;
3185 res.size = raw_encap_data->size;
3186 memcpy(res.buf, raw_encap_data->data, res.size);
3188 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3190 ((const struct rte_flow_action_vxlan_encap *)
3191 action->conf)->definition;
3194 ((const struct rte_flow_action_nvgre_encap *)
3195 action->conf)->definition;
3196 if (flow_dv_convert_encap_data(encap_data, res.buf,
3200 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3202 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3203 return rte_flow_error_set(error, EINVAL,
3204 RTE_FLOW_ERROR_TYPE_ACTION,
3205 NULL, "can't create L2 encap action");
3210 * Convert L2 decap action to DV specification.
3213 * Pointer to rte_eth_dev structure.
3214 * @param[in, out] dev_flow
3215 * Pointer to the mlx5_flow.
3216 * @param[in] transfer
3217 * Mark if the flow is E-Switch flow.
3219 * Pointer to the error structure.
3222 * 0 on success, a negative errno value otherwise and rte_errno is set.
3225 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3226 struct mlx5_flow *dev_flow,
3228 struct rte_flow_error *error)
3230 struct mlx5_flow_dv_encap_decap_resource res = {
3233 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3234 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3235 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3238 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3239 return rte_flow_error_set(error, EINVAL,
3240 RTE_FLOW_ERROR_TYPE_ACTION,
3241 NULL, "can't create L2 decap action");
3246 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3249 * Pointer to rte_eth_dev structure.
3251 * Pointer to action structure.
3252 * @param[in, out] dev_flow
3253 * Pointer to the mlx5_flow.
3255 * Pointer to the flow attributes.
3257 * Pointer to the error structure.
3260 * 0 on success, a negative errno value otherwise and rte_errno is set.
3263 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3264 const struct rte_flow_action *action,
3265 struct mlx5_flow *dev_flow,
3266 const struct rte_flow_attr *attr,
3267 struct rte_flow_error *error)
3269 const struct rte_flow_action_raw_encap *encap_data;
3270 struct mlx5_flow_dv_encap_decap_resource res;
3272 memset(&res, 0, sizeof(res));
3273 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3274 res.size = encap_data->size;
3275 memcpy(res.buf, encap_data->data, res.size);
3276 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3277 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3278 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3280 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3283 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3284 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3285 return rte_flow_error_set(error, EINVAL,
3286 RTE_FLOW_ERROR_TYPE_ACTION,
3287 NULL, "can't create encap action");
3292 * Create action push VLAN.
3295 * Pointer to rte_eth_dev structure.
3297 * Pointer to the flow attributes.
3299 * Pointer to the vlan to push to the Ethernet header.
3300 * @param[in, out] dev_flow
3301 * Pointer to the mlx5_flow.
3303 * Pointer to the error structure.
3306 * 0 on success, a negative errno value otherwise and rte_errno is set.
3309 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3310 const struct rte_flow_attr *attr,
3311 const struct rte_vlan_hdr *vlan,
3312 struct mlx5_flow *dev_flow,
3313 struct rte_flow_error *error)
3315 struct mlx5_flow_dv_push_vlan_action_resource res;
3317 memset(&res, 0, sizeof(res));
3319 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3322 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3324 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3325 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3326 return flow_dv_push_vlan_action_resource_register
3327 (dev, &res, dev_flow, error);
3331 * Validate the modify-header actions.
3333 * @param[in] action_flags
3334 * Holds the actions detected until now.
3336 * Pointer to the modify action.
3338 * Pointer to error structure.
3341 * 0 on success, a negative errno value otherwise and rte_errno is set.
3344 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3345 const struct rte_flow_action *action,
3346 struct rte_flow_error *error)
3348 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3349 return rte_flow_error_set(error, EINVAL,
3350 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3351 NULL, "action configuration not set");
3352 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3353 return rte_flow_error_set(error, EINVAL,
3354 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3355 "can't have encap action before"
3361 * Validate the modify-header MAC address actions.
3363 * @param[in] action_flags
3364 * Holds the actions detected until now.
3366 * Pointer to the modify action.
3367 * @param[in] item_flags
3368 * Holds the items detected.
3370 * Pointer to error structure.
3373 * 0 on success, a negative errno value otherwise and rte_errno is set.
3376 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3377 const struct rte_flow_action *action,
3378 const uint64_t item_flags,
3379 struct rte_flow_error *error)
3383 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3385 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3386 return rte_flow_error_set(error, EINVAL,
3387 RTE_FLOW_ERROR_TYPE_ACTION,
3389 "no L2 item in pattern");
3395 * Validate the modify-header IPv4 address actions.
3397 * @param[in] action_flags
3398 * Holds the actions detected until now.
3400 * Pointer to the modify action.
3401 * @param[in] item_flags
3402 * Holds the items detected.
3404 * Pointer to error structure.
3407 * 0 on success, a negative errno value otherwise and rte_errno is set.
3410 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3411 const struct rte_flow_action *action,
3412 const uint64_t item_flags,
3413 struct rte_flow_error *error)
3418 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3420 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3421 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3422 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3423 if (!(item_flags & layer))
3424 return rte_flow_error_set(error, EINVAL,
3425 RTE_FLOW_ERROR_TYPE_ACTION,
3427 "no ipv4 item in pattern");
3433 * Validate the modify-header IPv6 address actions.
3435 * @param[in] action_flags
3436 * Holds the actions detected until now.
3438 * Pointer to the modify action.
3439 * @param[in] item_flags
3440 * Holds the items detected.
3442 * Pointer to error structure.
3445 * 0 on success, a negative errno value otherwise and rte_errno is set.
3448 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3449 const struct rte_flow_action *action,
3450 const uint64_t item_flags,
3451 struct rte_flow_error *error)
3456 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3458 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3459 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3460 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3461 if (!(item_flags & layer))
3462 return rte_flow_error_set(error, EINVAL,
3463 RTE_FLOW_ERROR_TYPE_ACTION,
3465 "no ipv6 item in pattern");
3471 * Validate the modify-header TP actions.
3473 * @param[in] action_flags
3474 * Holds the actions detected until now.
3476 * Pointer to the modify action.
3477 * @param[in] item_flags
3478 * Holds the items detected.
3480 * Pointer to error structure.
3483 * 0 on success, a negative errno value otherwise and rte_errno is set.
3486 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3487 const struct rte_flow_action *action,
3488 const uint64_t item_flags,
3489 struct rte_flow_error *error)
3494 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3496 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497 MLX5_FLOW_LAYER_INNER_L4 :
3498 MLX5_FLOW_LAYER_OUTER_L4;
3499 if (!(item_flags & layer))
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "no transport layer "
3509 * Validate the modify-header actions of increment/decrement
3510 * TCP Sequence-number.
3512 * @param[in] action_flags
3513 * Holds the actions detected until now.
3515 * Pointer to the modify action.
3516 * @param[in] item_flags
3517 * Holds the items detected.
3519 * Pointer to error structure.
3522 * 0 on success, a negative errno value otherwise and rte_errno is set.
3525 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3526 const struct rte_flow_action *action,
3527 const uint64_t item_flags,
3528 struct rte_flow_error *error)
3533 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3535 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3536 MLX5_FLOW_LAYER_INNER_L4_TCP :
3537 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3538 if (!(item_flags & layer))
3539 return rte_flow_error_set(error, EINVAL,
3540 RTE_FLOW_ERROR_TYPE_ACTION,
3541 NULL, "no TCP item in"
3543 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3544 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3545 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3546 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3547 return rte_flow_error_set(error, EINVAL,
3548 RTE_FLOW_ERROR_TYPE_ACTION,
3550 "cannot decrease and increase"
3551 " TCP sequence number"
3552 " at the same time");
3558 * Validate the modify-header actions of increment/decrement
3559 * TCP Acknowledgment number.
3561 * @param[in] action_flags
3562 * Holds the actions detected until now.
3564 * Pointer to the modify action.
3565 * @param[in] item_flags
3566 * Holds the items detected.
3568 * Pointer to error structure.
3571 * 0 on success, a negative errno value otherwise and rte_errno is set.
3574 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3575 const struct rte_flow_action *action,
3576 const uint64_t item_flags,
3577 struct rte_flow_error *error)
3582 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3584 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3585 MLX5_FLOW_LAYER_INNER_L4_TCP :
3586 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3587 if (!(item_flags & layer))
3588 return rte_flow_error_set(error, EINVAL,
3589 RTE_FLOW_ERROR_TYPE_ACTION,
3590 NULL, "no TCP item in"
3592 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3593 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3594 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3595 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3596 return rte_flow_error_set(error, EINVAL,
3597 RTE_FLOW_ERROR_TYPE_ACTION,
3599 "cannot decrease and increase"
3600 " TCP acknowledgment number"
3601 " at the same time");
3607 * Validate the modify-header TTL actions.
3609 * @param[in] action_flags
3610 * Holds the actions detected until now.
3612 * Pointer to the modify action.
3613 * @param[in] item_flags
3614 * Holds the items detected.
3616 * Pointer to error structure.
3619 * 0 on success, a negative errno value otherwise and rte_errno is set.
3622 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3623 const struct rte_flow_action *action,
3624 const uint64_t item_flags,
3625 struct rte_flow_error *error)
3630 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3632 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3633 MLX5_FLOW_LAYER_INNER_L3 :
3634 MLX5_FLOW_LAYER_OUTER_L3;
3635 if (!(item_flags & layer))
3636 return rte_flow_error_set(error, EINVAL,
3637 RTE_FLOW_ERROR_TYPE_ACTION,
3639 "no IP protocol in pattern");
3645 * Validate jump action.
3648 * Pointer to the jump action.
3649 * @param[in] action_flags
3650 * Holds the actions detected until now.
3651 * @param[in] attributes
3652 * Pointer to flow attributes
3653 * @param[in] external
3654 * Action belongs to flow rule created by request external to PMD.
3656 * Pointer to error structure.
3659 * 0 on success, a negative errno value otherwise and rte_errno is set.
3662 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3663 uint64_t action_flags,
3664 const struct rte_flow_attr *attributes,
3665 bool external, struct rte_flow_error *error)
3667 uint32_t target_group, table;
3670 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3671 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3672 return rte_flow_error_set(error, EINVAL,
3673 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3674 "can't have 2 fate actions in"
3676 if (action_flags & MLX5_FLOW_ACTION_METER)
3677 return rte_flow_error_set(error, ENOTSUP,
3678 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3679 "jump with meter not support");
3681 return rte_flow_error_set(error, EINVAL,
3682 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3683 NULL, "action configuration not set");
3685 ((const struct rte_flow_action_jump *)action->conf)->group;
3686 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3687 true, &table, error);
3690 if (attributes->group == target_group)
3691 return rte_flow_error_set(error, EINVAL,
3692 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693 "target group must be other than"
3694 " the current flow group");
3699 * Validate the port_id action.
3702 * Pointer to rte_eth_dev structure.
3703 * @param[in] action_flags
3704 * Bit-fields that holds the actions detected until now.
3706 * Port_id RTE action structure.
3708 * Attributes of flow that includes this action.
3710 * Pointer to error structure.
3713 * 0 on success, a negative errno value otherwise and rte_errno is set.
3716 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3717 uint64_t action_flags,
3718 const struct rte_flow_action *action,
3719 const struct rte_flow_attr *attr,
3720 struct rte_flow_error *error)
3722 const struct rte_flow_action_port_id *port_id;
3723 struct mlx5_priv *act_priv;
3724 struct mlx5_priv *dev_priv;
3727 if (!attr->transfer)
3728 return rte_flow_error_set(error, ENOTSUP,
3729 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3731 "port id action is valid in transfer"
3733 if (!action || !action->conf)
3734 return rte_flow_error_set(error, ENOTSUP,
3735 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3737 "port id action parameters must be"
3739 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3740 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3741 return rte_flow_error_set(error, EINVAL,
3742 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3743 "can have only one fate actions in"
3745 dev_priv = mlx5_dev_to_eswitch_info(dev);
3747 return rte_flow_error_set(error, rte_errno,
3748 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3750 "failed to obtain E-Switch info");
3751 port_id = action->conf;
3752 port = port_id->original ? dev->data->port_id : port_id->id;
3753 act_priv = mlx5_port_to_eswitch_info(port, false);
3755 return rte_flow_error_set
3757 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3758 "failed to obtain E-Switch port id for port");
3759 if (act_priv->domain_id != dev_priv->domain_id)
3760 return rte_flow_error_set
3762 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3763 "port does not belong to"
3764 " E-Switch being configured");
3769 * Get the maximum number of modify header actions.
3772 * Pointer to rte_eth_dev structure.
3774 * Flags bits to check if root level.
3777 * Max number of modify header actions device can support.
3779 static inline unsigned int
3780 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3784 * There's no way to directly query the max capacity from FW.
3785 * The maximal value on root table should be assumed to be supported.
3787 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3788 return MLX5_MAX_MODIFY_NUM;
3790 return MLX5_ROOT_TBL_MODIFY_NUM;
3794 * Validate the meter action.
3797 * Pointer to rte_eth_dev structure.
3798 * @param[in] action_flags
3799 * Bit-fields that holds the actions detected until now.
3801 * Pointer to the meter action.
3803 * Attributes of flow that includes this action.
3805 * Pointer to error structure.
3808 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3811 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3812 uint64_t action_flags,
3813 const struct rte_flow_action *action,
3814 const struct rte_flow_attr *attr,
3815 struct rte_flow_error *error)
3817 struct mlx5_priv *priv = dev->data->dev_private;
3818 const struct rte_flow_action_meter *am = action->conf;
3819 struct mlx5_flow_meter *fm;
3822 return rte_flow_error_set(error, EINVAL,
3823 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3824 "meter action conf is NULL");
3826 if (action_flags & MLX5_FLOW_ACTION_METER)
3827 return rte_flow_error_set(error, ENOTSUP,
3828 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3829 "meter chaining not support");
3830 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3831 return rte_flow_error_set(error, ENOTSUP,
3832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3833 "meter with jump not support");
3835 return rte_flow_error_set(error, ENOTSUP,
3836 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3838 "meter action not supported");
3839 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3844 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3845 (!fm->ingress && !attr->ingress && attr->egress) ||
3846 (!fm->egress && !attr->egress && attr->ingress))))
3847 return rte_flow_error_set(error, EINVAL,
3848 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3849 "Flow attributes are either invalid "
3850 "or have a conflict with current "
3851 "meter attributes");
3856 * Validate the age action.
3858 * @param[in] action_flags
3859 * Holds the actions detected until now.
3861 * Pointer to the age action.
3863 * Pointer to the Ethernet device structure.
3865 * Pointer to error structure.
3868 * 0 on success, a negative errno value otherwise and rte_errno is set.
3871 flow_dv_validate_action_age(uint64_t action_flags,
3872 const struct rte_flow_action *action,
3873 struct rte_eth_dev *dev,
3874 struct rte_flow_error *error)
3876 struct mlx5_priv *priv = dev->data->dev_private;
3877 const struct rte_flow_action_age *age = action->conf;
3879 if (!priv->config.devx || priv->counter_fallback)
3880 return rte_flow_error_set(error, ENOTSUP,
3881 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3883 "age action not supported");
3884 if (!(action->conf))
3885 return rte_flow_error_set(error, EINVAL,
3886 RTE_FLOW_ERROR_TYPE_ACTION, action,
3887 "configuration cannot be null");
3888 if (age->timeout >= UINT16_MAX / 2 / 10)
3889 return rte_flow_error_set(error, ENOTSUP,
3890 RTE_FLOW_ERROR_TYPE_ACTION, action,
3891 "Max age time: 3275 seconds");
3892 if (action_flags & MLX5_FLOW_ACTION_AGE)
3893 return rte_flow_error_set(error, EINVAL,
3894 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3895 "Duplicate age ctions set");
3900 * Validate the modify-header IPv4 DSCP actions.
3902 * @param[in] action_flags
3903 * Holds the actions detected until now.
3905 * Pointer to the modify action.
3906 * @param[in] item_flags
3907 * Holds the items detected.
3909 * Pointer to error structure.
3912 * 0 on success, a negative errno value otherwise and rte_errno is set.
3915 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3916 const struct rte_flow_action *action,
3917 const uint64_t item_flags,
3918 struct rte_flow_error *error)
3922 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3924 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3925 return rte_flow_error_set(error, EINVAL,
3926 RTE_FLOW_ERROR_TYPE_ACTION,
3928 "no ipv4 item in pattern");
3934 * Validate the modify-header IPv6 DSCP actions.
3936 * @param[in] action_flags
3937 * Holds the actions detected until now.
3939 * Pointer to the modify action.
3940 * @param[in] item_flags
3941 * Holds the items detected.
3943 * Pointer to error structure.
3946 * 0 on success, a negative errno value otherwise and rte_errno is set.
3949 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3950 const struct rte_flow_action *action,
3951 const uint64_t item_flags,
3952 struct rte_flow_error *error)
3956 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3958 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3959 return rte_flow_error_set(error, EINVAL,
3960 RTE_FLOW_ERROR_TYPE_ACTION,
3962 "no ipv6 item in pattern");
3968 * Find existing modify-header resource or create and register a new one.
3970 * @param dev[in, out]
3971 * Pointer to rte_eth_dev structure.
3972 * @param[in, out] resource
3973 * Pointer to modify-header resource.
3974 * @parm[in, out] dev_flow
3975 * Pointer to the dev_flow.
3977 * pointer to error structure.
3980 * 0 on success otherwise -errno and errno is set.
3983 flow_dv_modify_hdr_resource_register
3984 (struct rte_eth_dev *dev,
3985 struct mlx5_flow_dv_modify_hdr_resource *resource,
3986 struct mlx5_flow *dev_flow,
3987 struct rte_flow_error *error)
3989 struct mlx5_priv *priv = dev->data->dev_private;
3990 struct mlx5_dev_ctx_shared *sh = priv->sh;
3991 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3992 struct mlx5dv_dr_domain *ns;
3993 uint32_t actions_len;
3996 resource->flags = dev_flow->dv.group ? 0 :
3997 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3998 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4000 return rte_flow_error_set(error, EOVERFLOW,
4001 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4002 "too many modify header items");
4003 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4004 ns = sh->fdb_domain;
4005 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4009 /* Lookup a matching resource from cache. */
4010 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4011 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4012 if (resource->ft_type == cache_resource->ft_type &&
4013 resource->actions_num == cache_resource->actions_num &&
4014 resource->flags == cache_resource->flags &&
4015 !memcmp((const void *)resource->actions,
4016 (const void *)cache_resource->actions,
4018 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4019 (void *)cache_resource,
4020 rte_atomic32_read(&cache_resource->refcnt));
4021 rte_atomic32_inc(&cache_resource->refcnt);
4022 dev_flow->handle->dvh.modify_hdr = cache_resource;
4026 /* Register new modify-header resource. */
4027 cache_resource = rte_calloc(__func__, 1,
4028 sizeof(*cache_resource) + actions_len, 0);
4029 if (!cache_resource)
4030 return rte_flow_error_set(error, ENOMEM,
4031 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4032 "cannot allocate resource memory");
4033 *cache_resource = *resource;
4034 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4035 ret = mlx5_flow_os_create_flow_action_modify_header
4036 (sh->ctx, ns, cache_resource,
4037 actions_len, &cache_resource->action);
4039 rte_free(cache_resource);
4040 return rte_flow_error_set(error, ENOMEM,
4041 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4042 NULL, "cannot create action");
4044 rte_atomic32_init(&cache_resource->refcnt);
4045 rte_atomic32_inc(&cache_resource->refcnt);
4046 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4047 dev_flow->handle->dvh.modify_hdr = cache_resource;
4048 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4049 (void *)cache_resource,
4050 rte_atomic32_read(&cache_resource->refcnt));
4055 * Get DV flow counter by index.
4058 * Pointer to the Ethernet device structure.
4060 * mlx5 flow counter index in the container.
4062 * mlx5 flow counter pool in the container,
4065 * Pointer to the counter, NULL otherwise.
4067 static struct mlx5_flow_counter *
4068 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4070 struct mlx5_flow_counter_pool **ppool)
4072 struct mlx5_priv *priv = dev->data->dev_private;
4073 struct mlx5_pools_container *cont;
4074 struct mlx5_flow_counter_pool *pool;
4075 uint32_t batch = 0, age = 0;
4078 age = MLX_CNT_IS_AGE(idx);
4079 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4080 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4081 idx -= MLX5_CNT_BATCH_OFFSET;
4084 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4085 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4086 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4090 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4094 * Check the devx counter belongs to the pool.
4097 * Pointer to the counter pool.
4099 * The counter devx ID.
4102 * True if counter belongs to the pool, false otherwise.
4105 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4107 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4108 MLX5_COUNTERS_PER_POOL;
4110 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4116 * Get a pool by devx counter ID.
4119 * Pointer to the counter container.
4121 * The counter devx ID.
4124 * The counter pool pointer if exists, NULL otherwise,
4126 static struct mlx5_flow_counter_pool *
4127 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4131 /* Check last used pool. */
4132 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4133 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4134 return cont->pools[cont->last_pool_idx];
4135 /* ID out of range means no suitable pool in the container. */
4136 if (id > cont->max_id || id < cont->min_id)
4139 * Find the pool from the end of the container, since mostly counter
4140 * ID is sequence increasing, and the last pool should be the needed
4143 i = rte_atomic16_read(&cont->n_valid);
4145 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4147 if (flow_dv_is_counter_in_pool(pool, id))
4154 * Allocate a new memory for the counter values wrapped by all the needed
4158 * Pointer to the Ethernet device structure.
4160 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4163 * The new memory management pointer on success, otherwise NULL and rte_errno
4166 static struct mlx5_counter_stats_mem_mng *
4167 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4169 struct mlx5_priv *priv = dev->data->dev_private;
4170 struct mlx5_dev_ctx_shared *sh = priv->sh;
4171 struct mlx5_devx_mkey_attr mkey_attr;
4172 struct mlx5_counter_stats_mem_mng *mem_mng;
4173 volatile struct flow_counter_stats *raw_data;
4174 int size = (sizeof(struct flow_counter_stats) *
4175 MLX5_COUNTERS_PER_POOL +
4176 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4177 sizeof(struct mlx5_counter_stats_mem_mng);
4178 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4185 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4186 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4187 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4188 IBV_ACCESS_LOCAL_WRITE);
4189 if (!mem_mng->umem) {
4194 mkey_attr.addr = (uintptr_t)mem;
4195 mkey_attr.size = size;
4196 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4197 mkey_attr.pd = sh->pdn;
4198 mkey_attr.log_entity_size = 0;
4199 mkey_attr.pg_access = 0;
4200 mkey_attr.klm_array = NULL;
4201 mkey_attr.klm_num = 0;
4202 if (priv->config.hca_attr.relaxed_ordering_write &&
4203 priv->config.hca_attr.relaxed_ordering_read &&
4204 !haswell_broadwell_cpu)
4205 mkey_attr.relaxed_ordering = 1;
4206 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4208 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4213 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4214 raw_data = (volatile struct flow_counter_stats *)mem;
4215 for (i = 0; i < raws_n; ++i) {
4216 mem_mng->raws[i].mem_mng = mem_mng;
4217 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4219 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4224 * Resize a counter container.
4227 * Pointer to the Ethernet device structure.
4229 * Whether the pool is for counter that was allocated by batch command.
4231 * Whether the pool is for Aging counter.
4234 * 0 on success, otherwise negative errno value and rte_errno is set.
4237 flow_dv_container_resize(struct rte_eth_dev *dev,
4238 uint32_t batch, uint32_t age)
4240 struct mlx5_priv *priv = dev->data->dev_private;
4241 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4243 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4244 void *old_pools = cont->pools;
4245 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4246 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4247 void *pools = rte_calloc(__func__, 1, mem_size, 0);
4254 memcpy(pools, old_pools, cont->n *
4255 sizeof(struct mlx5_flow_counter_pool *));
4257 * Fallback mode query the counter directly, no background query
4258 * resources are needed.
4260 if (!priv->counter_fallback) {
4263 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4264 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4269 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4270 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4272 MLX5_CNT_CONTAINER_RESIZE +
4275 rte_spinlock_lock(&cont->resize_sl);
4277 cont->mem_mng = mem_mng;
4278 cont->pools = pools;
4279 rte_spinlock_unlock(&cont->resize_sl);
4281 rte_free(old_pools);
4286 * Query a devx flow counter.
4289 * Pointer to the Ethernet device structure.
4291 * Index to the flow counter.
4293 * The statistics value of packets.
4295 * The statistics value of bytes.
4298 * 0 on success, otherwise a negative errno value and rte_errno is set.
4301 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4304 struct mlx5_priv *priv = dev->data->dev_private;
4305 struct mlx5_flow_counter_pool *pool = NULL;
4306 struct mlx5_flow_counter *cnt;
4307 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4310 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4312 if (counter < MLX5_CNT_BATCH_OFFSET) {
4313 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4314 if (priv->counter_fallback)
4315 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4316 0, pkts, bytes, 0, NULL, NULL, 0);
4319 rte_spinlock_lock(&pool->sl);
4321 * The single counters allocation may allocate smaller ID than the
4322 * current allocated in parallel to the host reading.
4323 * In this case the new counter values must be reported as 0.
4325 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4329 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4330 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4331 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4333 rte_spinlock_unlock(&pool->sl);
4338 * Create and initialize a new counter pool.
4341 * Pointer to the Ethernet device structure.
4343 * The devX counter handle.
4345 * Whether the pool is for counter that was allocated by batch command.
4347 * Whether the pool is for counter that was allocated for aging.
4348 * @param[in/out] cont_cur
4349 * Pointer to the container pointer, it will be update in pool resize.
4352 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4354 static struct mlx5_flow_counter_pool *
4355 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4356 uint32_t batch, uint32_t age)
4358 struct mlx5_priv *priv = dev->data->dev_private;
4359 struct mlx5_flow_counter_pool *pool;
4360 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4362 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4363 uint32_t size = sizeof(*pool);
4365 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4367 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4368 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4369 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4370 pool = rte_calloc(__func__, 1, size, 0);
4375 pool->min_dcs = dcs;
4376 if (!priv->counter_fallback)
4377 pool->raw = cont->mem_mng->raws + n_valid %
4378 MLX5_CNT_CONTAINER_RESIZE;
4379 pool->raw_hw = NULL;
4381 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4382 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4383 pool->query_gen = 0;
4384 rte_spinlock_init(&pool->sl);
4385 TAILQ_INIT(&pool->counters[0]);
4386 TAILQ_INIT(&pool->counters[1]);
4387 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4388 pool->index = n_valid;
4389 cont->pools[n_valid] = pool;
4391 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4393 if (base < cont->min_id)
4394 cont->min_id = base;
4395 if (base > cont->max_id)
4396 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4397 cont->last_pool_idx = pool->index;
4399 /* Pool initialization must be updated before host thread access. */
4401 rte_atomic16_add(&cont->n_valid, 1);
4406 * Update the minimum dcs-id for aged or no-aged counter pool.
4409 * Pointer to the Ethernet device structure.
4411 * Current counter pool.
4413 * Whether the pool is for counter that was allocated by batch command.
4415 * Whether the counter is for aging.
4418 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4419 struct mlx5_flow_counter_pool *pool,
4420 uint32_t batch, uint32_t age)
4422 struct mlx5_priv *priv = dev->data->dev_private;
4423 struct mlx5_flow_counter_pool *other;
4424 struct mlx5_pools_container *cont;
4426 cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4427 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4430 if (pool->min_dcs->id < other->min_dcs->id) {
4431 rte_atomic64_set(&other->a64_dcs,
4432 rte_atomic64_read(&pool->a64_dcs));
4434 rte_atomic64_set(&pool->a64_dcs,
4435 rte_atomic64_read(&other->a64_dcs));
4439 * Prepare a new counter and/or a new counter pool.
4442 * Pointer to the Ethernet device structure.
4443 * @param[out] cnt_free
4444 * Where to put the pointer of a new counter.
4446 * Whether the pool is for counter that was allocated by batch command.
4448 * Whether the pool is for counter that was allocated for aging.
4451 * The counter pool pointer and @p cnt_free is set on success,
4452 * NULL otherwise and rte_errno is set.
4454 static struct mlx5_flow_counter_pool *
4455 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4456 struct mlx5_flow_counter **cnt_free,
4457 uint32_t batch, uint32_t age)
4459 struct mlx5_priv *priv = dev->data->dev_private;
4460 struct mlx5_pools_container *cont;
4461 struct mlx5_flow_counter_pool *pool;
4462 struct mlx5_counters tmp_tq;
4463 struct mlx5_devx_obj *dcs = NULL;
4464 struct mlx5_flow_counter *cnt;
4467 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4469 /* bulk_bitmap must be 0 for single counter allocation. */
4470 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4473 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4475 pool = flow_dv_pool_create(dev, dcs, batch, age);
4477 mlx5_devx_cmd_destroy(dcs);
4480 } else if (dcs->id < pool->min_dcs->id) {
4481 rte_atomic64_set(&pool->a64_dcs,
4482 (int64_t)(uintptr_t)dcs);
4484 flow_dv_counter_update_min_dcs(dev,
4486 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4487 cnt = MLX5_POOL_GET_CNT(pool, i);
4489 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4493 /* bulk_bitmap is in 128 counters units. */
4494 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4495 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4497 rte_errno = ENODATA;
4500 pool = flow_dv_pool_create(dev, dcs, batch, age);
4502 mlx5_devx_cmd_destroy(dcs);
4505 TAILQ_INIT(&tmp_tq);
4506 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4507 cnt = MLX5_POOL_GET_CNT(pool, i);
4509 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4511 rte_spinlock_lock(&cont->csl);
4512 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4513 rte_spinlock_unlock(&cont->csl);
4514 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4515 (*cnt_free)->pool = pool;
4520 * Search for existed shared counter.
4523 * Pointer to the Ethernet device structure.
4525 * The shared counter ID to search.
4527 * mlx5 flow counter pool in the container,
4530 * NULL if not existed, otherwise pointer to the shared extend counter.
4532 static struct mlx5_flow_counter_ext *
4533 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4534 struct mlx5_flow_counter_pool **ppool)
4536 struct mlx5_priv *priv = dev->data->dev_private;
4537 union mlx5_l3t_data data;
4540 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4542 cnt_idx = data.dword;
4544 * Shared counters don't have age info. The counter extend is after
4545 * the counter datat structure.
4547 return (struct mlx5_flow_counter_ext *)
4548 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4552 * Allocate a flow counter.
4555 * Pointer to the Ethernet device structure.
4557 * Indicate if this counter is shared with other flows.
4559 * Counter identifier.
4561 * Counter flow group.
4563 * Whether the counter was allocated for aging.
4566 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4569 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4570 uint16_t group, uint32_t age)
4572 struct mlx5_priv *priv = dev->data->dev_private;
4573 struct mlx5_flow_counter_pool *pool = NULL;
4574 struct mlx5_flow_counter *cnt_free = NULL;
4575 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4577 * Currently group 0 flow counter cannot be assigned to a flow if it is
4578 * not the first one in the batch counter allocation, so it is better
4579 * to allocate counters one by one for these flows in a separate
4581 * A counter can be shared between different groups so need to take
4582 * shared counters from the single container.
4584 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4585 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4589 if (!priv->config.devx) {
4590 rte_errno = ENOTSUP;
4594 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4596 if (cnt_ext->ref_cnt + 1 == 0) {
4601 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4602 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4607 /* Get free counters from container. */
4608 rte_spinlock_lock(&cont->csl);
4609 cnt_free = TAILQ_FIRST(&cont->counters);
4611 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4612 rte_spinlock_unlock(&cont->csl);
4613 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4616 pool = cnt_free->pool;
4618 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4619 /* Create a DV counter action only in the first time usage. */
4620 if (!cnt_free->action) {
4622 struct mlx5_devx_obj *dcs;
4626 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4627 dcs = pool->min_dcs;
4632 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4639 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4640 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4641 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4642 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4643 /* Update the counter reset values. */
4644 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4648 cnt_ext->shared = shared;
4649 cnt_ext->ref_cnt = 1;
4652 union mlx5_l3t_data data;
4654 data.dword = cnt_idx;
4655 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4659 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4660 /* Start the asynchronous batch query by the host thread. */
4661 mlx5_set_query_alarm(priv->sh);
4665 cnt_free->pool = pool;
4666 rte_spinlock_lock(&cont->csl);
4667 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4668 rte_spinlock_unlock(&cont->csl);
4674 * Get age param from counter index.
4677 * Pointer to the Ethernet device structure.
4678 * @param[in] counter
4679 * Index to the counter handler.
4682 * The aging parameter specified for the counter index.
4684 static struct mlx5_age_param*
4685 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4688 struct mlx5_flow_counter *cnt;
4689 struct mlx5_flow_counter_pool *pool = NULL;
4691 flow_dv_counter_get_by_idx(dev, counter, &pool);
4692 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4693 cnt = MLX5_POOL_GET_CNT(pool, counter);
4694 return MLX5_CNT_TO_AGE(cnt);
4698 * Remove a flow counter from aged counter list.
4701 * Pointer to the Ethernet device structure.
4702 * @param[in] counter
4703 * Index to the counter handler.
4705 * Pointer to the counter handler.
4708 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4709 uint32_t counter, struct mlx5_flow_counter *cnt)
4711 struct mlx5_age_info *age_info;
4712 struct mlx5_age_param *age_param;
4713 struct mlx5_priv *priv = dev->data->dev_private;
4715 age_info = GET_PORT_AGE_INFO(priv);
4716 age_param = flow_dv_counter_idx_get_age(dev, counter);
4717 if (rte_atomic16_cmpset((volatile uint16_t *)
4719 AGE_CANDIDATE, AGE_FREE)
4722 * We need the lock even it is age timeout,
4723 * since counter may still in process.
4725 rte_spinlock_lock(&age_info->aged_sl);
4726 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4727 rte_spinlock_unlock(&age_info->aged_sl);
4729 rte_atomic16_set(&age_param->state, AGE_FREE);
4732 * Release a flow counter.
4735 * Pointer to the Ethernet device structure.
4736 * @param[in] counter
4737 * Index to the counter handler.
4740 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4742 struct mlx5_priv *priv = dev->data->dev_private;
4743 struct mlx5_flow_counter_pool *pool = NULL;
4744 struct mlx5_flow_counter *cnt;
4745 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4749 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4751 if (counter < MLX5_CNT_BATCH_OFFSET) {
4752 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4754 if (--cnt_ext->ref_cnt)
4756 if (cnt_ext->shared)
4757 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4761 if (IS_AGE_POOL(pool))
4762 flow_dv_counter_remove_from_age(dev, counter, cnt);
4765 * Put the counter back to list to be updated in none fallback mode.
4766 * Currently, we are using two list alternately, while one is in query,
4767 * add the freed counter to the other list based on the pool query_gen
4768 * value. After query finishes, add counter the list to the global
4769 * container counter list. The list changes while query starts. In
4770 * this case, lock will not be needed as query callback and release
4771 * function both operate with the different list.
4774 if (!priv->counter_fallback)
4775 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4777 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4778 (priv->sh, 0, 0))->counters),
4783 * Verify the @p attributes will be correctly understood by the NIC and store
4784 * them in the @p flow if everything is correct.
4787 * Pointer to dev struct.
4788 * @param[in] attributes
4789 * Pointer to flow attributes
4790 * @param[in] external
4791 * This flow rule is created by request external to PMD.
4793 * Pointer to error structure.
4796 * - 0 on success and non root table.
4797 * - 1 on success and root table.
4798 * - a negative errno value otherwise and rte_errno is set.
4801 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4802 const struct rte_flow_attr *attributes,
4803 bool external __rte_unused,
4804 struct rte_flow_error *error)
4806 struct mlx5_priv *priv = dev->data->dev_private;
4807 uint32_t priority_max = priv->config.flow_prio - 1;
4810 #ifndef HAVE_MLX5DV_DR
4811 if (attributes->group)
4812 return rte_flow_error_set(error, ENOTSUP,
4813 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4815 "groups are not supported");
4819 ret = mlx5_flow_group_to_table(attributes, external,
4820 attributes->group, !!priv->fdb_def_rule,
4825 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4827 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4828 attributes->priority >= priority_max)
4829 return rte_flow_error_set(error, ENOTSUP,
4830 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4832 "priority out of range");
4833 if (attributes->transfer) {
4834 if (!priv->config.dv_esw_en)
4835 return rte_flow_error_set
4837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4838 "E-Switch dr is not supported");
4839 if (!(priv->representor || priv->master))
4840 return rte_flow_error_set
4841 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4842 NULL, "E-Switch configuration can only be"
4843 " done by a master or a representor device");
4844 if (attributes->egress)
4845 return rte_flow_error_set
4847 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4848 "egress is not supported");
4850 if (!(attributes->egress ^ attributes->ingress))
4851 return rte_flow_error_set(error, ENOTSUP,
4852 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4853 "must specify exactly one of "
4854 "ingress or egress");
4859 * Internal validation function. For validating both actions and items.
4862 * Pointer to the rte_eth_dev structure.
4864 * Pointer to the flow attributes.
4866 * Pointer to the list of items.
4867 * @param[in] actions
4868 * Pointer to the list of actions.
4869 * @param[in] external
4870 * This flow rule is created by request external to PMD.
4871 * @param[in] hairpin
4872 * Number of hairpin TX actions, 0 means classic flow.
4874 * Pointer to the error structure.
4877 * 0 on success, a negative errno value otherwise and rte_errno is set.
4880 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4881 const struct rte_flow_item items[],
4882 const struct rte_flow_action actions[],
4883 bool external, int hairpin, struct rte_flow_error *error)
4886 uint64_t action_flags = 0;
4887 uint64_t item_flags = 0;
4888 uint64_t last_item = 0;
4889 uint8_t next_protocol = 0xff;
4890 uint16_t ether_type = 0;
4892 uint8_t item_ipv6_proto = 0;
4893 const struct rte_flow_item *gre_item = NULL;
4894 const struct rte_flow_action_raw_decap *decap;
4895 const struct rte_flow_action_raw_encap *encap;
4896 const struct rte_flow_action_rss *rss;
4897 const struct rte_flow_item_tcp nic_tcp_mask = {
4900 .src_port = RTE_BE16(UINT16_MAX),
4901 .dst_port = RTE_BE16(UINT16_MAX),
4904 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4906 .src_addr = RTE_BE32(0xffffffff),
4907 .dst_addr = RTE_BE32(0xffffffff),
4908 .type_of_service = 0xff,
4909 .next_proto_id = 0xff,
4910 .time_to_live = 0xff,
4913 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4916 "\xff\xff\xff\xff\xff\xff\xff\xff"
4917 "\xff\xff\xff\xff\xff\xff\xff\xff",
4919 "\xff\xff\xff\xff\xff\xff\xff\xff"
4920 "\xff\xff\xff\xff\xff\xff\xff\xff",
4921 .vtc_flow = RTE_BE32(0xffffffff),
4926 struct mlx5_priv *priv = dev->data->dev_private;
4927 struct mlx5_dev_config *dev_conf = &priv->config;
4928 uint16_t queue_index = 0xFFFF;
4929 const struct rte_flow_item_vlan *vlan_m = NULL;
4930 int16_t rw_act_num = 0;
4935 ret = flow_dv_validate_attributes(dev, attr, external, error);
4938 is_root = (uint64_t)ret;
4939 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4940 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4941 int type = items->type;
4943 if (!mlx5_flow_os_item_supported(type))
4944 return rte_flow_error_set(error, ENOTSUP,
4945 RTE_FLOW_ERROR_TYPE_ITEM,
4946 NULL, "item not supported");
4948 case RTE_FLOW_ITEM_TYPE_VOID:
4950 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4951 ret = flow_dv_validate_item_port_id
4952 (dev, items, attr, item_flags, error);
4955 last_item = MLX5_FLOW_ITEM_PORT_ID;
4957 case RTE_FLOW_ITEM_TYPE_ETH:
4958 ret = mlx5_flow_validate_item_eth(items, item_flags,
4962 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4963 MLX5_FLOW_LAYER_OUTER_L2;
4964 if (items->mask != NULL && items->spec != NULL) {
4966 ((const struct rte_flow_item_eth *)
4969 ((const struct rte_flow_item_eth *)
4971 ether_type = rte_be_to_cpu_16(ether_type);
4976 case RTE_FLOW_ITEM_TYPE_VLAN:
4977 ret = flow_dv_validate_item_vlan(items, item_flags,
4981 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4982 MLX5_FLOW_LAYER_OUTER_VLAN;
4983 if (items->mask != NULL && items->spec != NULL) {
4985 ((const struct rte_flow_item_vlan *)
4986 items->spec)->inner_type;
4988 ((const struct rte_flow_item_vlan *)
4989 items->mask)->inner_type;
4990 ether_type = rte_be_to_cpu_16(ether_type);
4994 /* Store outer VLAN mask for of_push_vlan action. */
4996 vlan_m = items->mask;
4998 case RTE_FLOW_ITEM_TYPE_IPV4:
4999 mlx5_flow_tunnel_ip_check(items, next_protocol,
5000 &item_flags, &tunnel);
5001 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5008 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5009 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5010 if (items->mask != NULL &&
5011 ((const struct rte_flow_item_ipv4 *)
5012 items->mask)->hdr.next_proto_id) {
5014 ((const struct rte_flow_item_ipv4 *)
5015 (items->spec))->hdr.next_proto_id;
5017 ((const struct rte_flow_item_ipv4 *)
5018 (items->mask))->hdr.next_proto_id;
5020 /* Reset for inner layer. */
5021 next_protocol = 0xff;
5024 case RTE_FLOW_ITEM_TYPE_IPV6:
5025 mlx5_flow_tunnel_ip_check(items, next_protocol,
5026 &item_flags, &tunnel);
5027 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5034 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5035 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5036 if (items->mask != NULL &&
5037 ((const struct rte_flow_item_ipv6 *)
5038 items->mask)->hdr.proto) {
5040 ((const struct rte_flow_item_ipv6 *)
5041 items->spec)->hdr.proto;
5043 ((const struct rte_flow_item_ipv6 *)
5044 items->spec)->hdr.proto;
5046 ((const struct rte_flow_item_ipv6 *)
5047 items->mask)->hdr.proto;
5049 /* Reset for inner layer. */
5050 next_protocol = 0xff;
5053 case RTE_FLOW_ITEM_TYPE_TCP:
5054 ret = mlx5_flow_validate_item_tcp
5061 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5062 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5064 case RTE_FLOW_ITEM_TYPE_UDP:
5065 ret = mlx5_flow_validate_item_udp(items, item_flags,
5070 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5071 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5073 case RTE_FLOW_ITEM_TYPE_GRE:
5074 ret = mlx5_flow_validate_item_gre(items, item_flags,
5075 next_protocol, error);
5079 last_item = MLX5_FLOW_LAYER_GRE;
5081 case RTE_FLOW_ITEM_TYPE_NVGRE:
5082 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5087 last_item = MLX5_FLOW_LAYER_NVGRE;
5089 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5090 ret = mlx5_flow_validate_item_gre_key
5091 (items, item_flags, gre_item, error);
5094 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5096 case RTE_FLOW_ITEM_TYPE_VXLAN:
5097 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5101 last_item = MLX5_FLOW_LAYER_VXLAN;
5103 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5104 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5109 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5111 case RTE_FLOW_ITEM_TYPE_GENEVE:
5112 ret = mlx5_flow_validate_item_geneve(items,
5117 last_item = MLX5_FLOW_LAYER_GENEVE;
5119 case RTE_FLOW_ITEM_TYPE_MPLS:
5120 ret = mlx5_flow_validate_item_mpls(dev, items,
5125 last_item = MLX5_FLOW_LAYER_MPLS;
5128 case RTE_FLOW_ITEM_TYPE_MARK:
5129 ret = flow_dv_validate_item_mark(dev, items, attr,
5133 last_item = MLX5_FLOW_ITEM_MARK;
5135 case RTE_FLOW_ITEM_TYPE_META:
5136 ret = flow_dv_validate_item_meta(dev, items, attr,
5140 last_item = MLX5_FLOW_ITEM_METADATA;
5142 case RTE_FLOW_ITEM_TYPE_ICMP:
5143 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5148 last_item = MLX5_FLOW_LAYER_ICMP;
5150 case RTE_FLOW_ITEM_TYPE_ICMP6:
5151 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5156 item_ipv6_proto = IPPROTO_ICMPV6;
5157 last_item = MLX5_FLOW_LAYER_ICMP6;
5159 case RTE_FLOW_ITEM_TYPE_TAG:
5160 ret = flow_dv_validate_item_tag(dev, items,
5164 last_item = MLX5_FLOW_ITEM_TAG;
5166 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5167 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5169 case RTE_FLOW_ITEM_TYPE_GTP:
5170 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5174 last_item = MLX5_FLOW_LAYER_GTP;
5177 return rte_flow_error_set(error, ENOTSUP,
5178 RTE_FLOW_ERROR_TYPE_ITEM,
5179 NULL, "item not supported");
5181 item_flags |= last_item;
5183 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5184 int type = actions->type;
5186 if (!mlx5_flow_os_action_supported(type))
5187 return rte_flow_error_set(error, ENOTSUP,
5188 RTE_FLOW_ERROR_TYPE_ACTION,
5190 "action not supported");
5191 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5192 return rte_flow_error_set(error, ENOTSUP,
5193 RTE_FLOW_ERROR_TYPE_ACTION,
5194 actions, "too many actions");
5196 case RTE_FLOW_ACTION_TYPE_VOID:
5198 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5199 ret = flow_dv_validate_action_port_id(dev,
5206 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5209 case RTE_FLOW_ACTION_TYPE_FLAG:
5210 ret = flow_dv_validate_action_flag(dev, action_flags,
5214 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5215 /* Count all modify-header actions as one. */
5216 if (!(action_flags &
5217 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5219 action_flags |= MLX5_FLOW_ACTION_FLAG |
5220 MLX5_FLOW_ACTION_MARK_EXT;
5222 action_flags |= MLX5_FLOW_ACTION_FLAG;
5225 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5227 case RTE_FLOW_ACTION_TYPE_MARK:
5228 ret = flow_dv_validate_action_mark(dev, actions,
5233 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5234 /* Count all modify-header actions as one. */
5235 if (!(action_flags &
5236 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5238 action_flags |= MLX5_FLOW_ACTION_MARK |
5239 MLX5_FLOW_ACTION_MARK_EXT;
5241 action_flags |= MLX5_FLOW_ACTION_MARK;
5244 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5246 case RTE_FLOW_ACTION_TYPE_SET_META:
5247 ret = flow_dv_validate_action_set_meta(dev, actions,
5252 /* Count all modify-header actions as one action. */
5253 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5255 action_flags |= MLX5_FLOW_ACTION_SET_META;
5256 rw_act_num += MLX5_ACT_NUM_SET_META;
5258 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5259 ret = flow_dv_validate_action_set_tag(dev, actions,
5264 /* Count all modify-header actions as one action. */
5265 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5267 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5268 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5270 case RTE_FLOW_ACTION_TYPE_DROP:
5271 ret = mlx5_flow_validate_action_drop(action_flags,
5275 action_flags |= MLX5_FLOW_ACTION_DROP;
5278 case RTE_FLOW_ACTION_TYPE_QUEUE:
5279 ret = mlx5_flow_validate_action_queue(actions,
5284 queue_index = ((const struct rte_flow_action_queue *)
5285 (actions->conf))->index;
5286 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5289 case RTE_FLOW_ACTION_TYPE_RSS:
5290 rss = actions->conf;
5291 ret = mlx5_flow_validate_action_rss(actions,
5297 if (rss != NULL && rss->queue_num)
5298 queue_index = rss->queue[0];
5299 action_flags |= MLX5_FLOW_ACTION_RSS;
5302 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5304 mlx5_flow_validate_action_default_miss(action_flags,
5308 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5311 case RTE_FLOW_ACTION_TYPE_COUNT:
5312 ret = flow_dv_validate_action_count(dev, error);
5315 action_flags |= MLX5_FLOW_ACTION_COUNT;
5318 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5319 if (flow_dv_validate_action_pop_vlan(dev,
5325 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5328 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5329 ret = flow_dv_validate_action_push_vlan(dev,
5336 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5339 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5340 ret = flow_dv_validate_action_set_vlan_pcp
5341 (action_flags, actions, error);
5344 /* Count PCP with push_vlan command. */
5345 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5347 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5348 ret = flow_dv_validate_action_set_vlan_vid
5349 (item_flags, action_flags,
5353 /* Count VID with push_vlan command. */
5354 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5355 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5357 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5358 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5359 ret = flow_dv_validate_action_l2_encap(dev,
5365 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5368 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5369 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5370 ret = flow_dv_validate_action_decap(dev, action_flags,
5374 action_flags |= MLX5_FLOW_ACTION_DECAP;
5377 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5378 ret = flow_dv_validate_action_raw_encap_decap
5379 (dev, NULL, actions->conf, attr, &action_flags,
5384 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5385 decap = actions->conf;
5386 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5388 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5392 encap = actions->conf;
5394 ret = flow_dv_validate_action_raw_encap_decap
5396 decap ? decap : &empty_decap, encap,
5397 attr, &action_flags, &actions_n,
5402 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5403 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5404 ret = flow_dv_validate_action_modify_mac(action_flags,
5410 /* Count all modify-header actions as one action. */
5411 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5413 action_flags |= actions->type ==
5414 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5415 MLX5_FLOW_ACTION_SET_MAC_SRC :
5416 MLX5_FLOW_ACTION_SET_MAC_DST;
5418 * Even if the source and destination MAC addresses have
5419 * overlap in the header with 4B alignment, the convert
5420 * function will handle them separately and 4 SW actions
5421 * will be created. And 2 actions will be added each
5422 * time no matter how many bytes of address will be set.
5424 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5426 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5427 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5428 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5434 /* Count all modify-header actions as one action. */
5435 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5437 action_flags |= actions->type ==
5438 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5439 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5440 MLX5_FLOW_ACTION_SET_IPV4_DST;
5441 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5443 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5444 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5445 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5451 if (item_ipv6_proto == IPPROTO_ICMPV6)
5452 return rte_flow_error_set(error, ENOTSUP,
5453 RTE_FLOW_ERROR_TYPE_ACTION,
5455 "Can't change header "
5456 "with ICMPv6 proto");
5457 /* Count all modify-header actions as one action. */
5458 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5460 action_flags |= actions->type ==
5461 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5462 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5463 MLX5_FLOW_ACTION_SET_IPV6_DST;
5464 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5466 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5467 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5468 ret = flow_dv_validate_action_modify_tp(action_flags,
5474 /* Count all modify-header actions as one action. */
5475 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5477 action_flags |= actions->type ==
5478 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5479 MLX5_FLOW_ACTION_SET_TP_SRC :
5480 MLX5_FLOW_ACTION_SET_TP_DST;
5481 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5483 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5484 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5485 ret = flow_dv_validate_action_modify_ttl(action_flags,
5491 /* Count all modify-header actions as one action. */
5492 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5494 action_flags |= actions->type ==
5495 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5496 MLX5_FLOW_ACTION_SET_TTL :
5497 MLX5_FLOW_ACTION_DEC_TTL;
5498 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5500 case RTE_FLOW_ACTION_TYPE_JUMP:
5501 ret = flow_dv_validate_action_jump(actions,
5508 action_flags |= MLX5_FLOW_ACTION_JUMP;
5510 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5511 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5512 ret = flow_dv_validate_action_modify_tcp_seq
5519 /* Count all modify-header actions as one action. */
5520 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5522 action_flags |= actions->type ==
5523 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5524 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5525 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5526 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5528 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5529 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5530 ret = flow_dv_validate_action_modify_tcp_ack
5537 /* Count all modify-header actions as one action. */
5538 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5540 action_flags |= actions->type ==
5541 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5542 MLX5_FLOW_ACTION_INC_TCP_ACK :
5543 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5544 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5546 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5548 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5549 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5550 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5552 case RTE_FLOW_ACTION_TYPE_METER:
5553 ret = mlx5_flow_validate_action_meter(dev,
5559 action_flags |= MLX5_FLOW_ACTION_METER;
5561 /* Meter action will add one more TAG action. */
5562 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5564 case RTE_FLOW_ACTION_TYPE_AGE:
5565 ret = flow_dv_validate_action_age(action_flags,
5570 action_flags |= MLX5_FLOW_ACTION_AGE;
5573 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5574 ret = flow_dv_validate_action_modify_ipv4_dscp
5581 /* Count all modify-header actions as one action. */
5582 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5584 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5585 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5587 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5588 ret = flow_dv_validate_action_modify_ipv6_dscp
5595 /* Count all modify-header actions as one action. */
5596 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5598 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5599 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5602 return rte_flow_error_set(error, ENOTSUP,
5603 RTE_FLOW_ERROR_TYPE_ACTION,
5605 "action not supported");
5609 * Validate the drop action mutual exclusion with other actions.
5610 * Drop action is mutually-exclusive with any other action, except for
5613 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5614 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5615 return rte_flow_error_set(error, EINVAL,
5616 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5617 "Drop action is mutually-exclusive "
5618 "with any other action, except for "
5620 /* Eswitch has few restrictions on using items and actions */
5621 if (attr->transfer) {
5622 if (!mlx5_flow_ext_mreg_supported(dev) &&
5623 action_flags & MLX5_FLOW_ACTION_FLAG)
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_ACTION,
5627 "unsupported action FLAG");
5628 if (!mlx5_flow_ext_mreg_supported(dev) &&
5629 action_flags & MLX5_FLOW_ACTION_MARK)
5630 return rte_flow_error_set(error, ENOTSUP,
5631 RTE_FLOW_ERROR_TYPE_ACTION,
5633 "unsupported action MARK");
5634 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5635 return rte_flow_error_set(error, ENOTSUP,
5636 RTE_FLOW_ERROR_TYPE_ACTION,
5638 "unsupported action QUEUE");
5639 if (action_flags & MLX5_FLOW_ACTION_RSS)
5640 return rte_flow_error_set(error, ENOTSUP,
5641 RTE_FLOW_ERROR_TYPE_ACTION,
5643 "unsupported action RSS");
5644 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5645 return rte_flow_error_set(error, EINVAL,
5646 RTE_FLOW_ERROR_TYPE_ACTION,
5648 "no fate action is found");
5650 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5651 return rte_flow_error_set(error, EINVAL,
5652 RTE_FLOW_ERROR_TYPE_ACTION,
5654 "no fate action is found");
5656 /* Continue validation for Xcap actions.*/
5657 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5658 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5659 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5660 MLX5_FLOW_XCAP_ACTIONS)
5661 return rte_flow_error_set(error, ENOTSUP,
5662 RTE_FLOW_ERROR_TYPE_ACTION,
5663 NULL, "encap and decap "
5664 "combination aren't supported");
5665 if (!attr->transfer && attr->ingress && (action_flags &
5666 MLX5_FLOW_ACTION_ENCAP))
5667 return rte_flow_error_set(error, ENOTSUP,
5668 RTE_FLOW_ERROR_TYPE_ACTION,
5669 NULL, "encap is not supported"
5670 " for ingress traffic");
5672 /* Hairpin flow will add one more TAG action. */
5674 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5675 /* extra metadata enabled: one more TAG action will be add. */
5676 if (dev_conf->dv_flow_en &&
5677 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5678 mlx5_flow_ext_mreg_supported(dev))
5679 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5680 if ((uint32_t)rw_act_num >
5681 flow_dv_modify_hdr_action_max(dev, is_root)) {
5682 return rte_flow_error_set(error, ENOTSUP,
5683 RTE_FLOW_ERROR_TYPE_ACTION,
5684 NULL, "too many header modify"
5685 " actions to support");
5691 * Internal preparation function. Allocates the DV flow size,
5692 * this size is constant.
5695 * Pointer to the rte_eth_dev structure.
5697 * Pointer to the flow attributes.
5699 * Pointer to the list of items.
5700 * @param[in] actions
5701 * Pointer to the list of actions.
5703 * Pointer to the error structure.
5706 * Pointer to mlx5_flow object on success,
5707 * otherwise NULL and rte_errno is set.
5709 static struct mlx5_flow *
5710 flow_dv_prepare(struct rte_eth_dev *dev,
5711 const struct rte_flow_attr *attr __rte_unused,
5712 const struct rte_flow_item items[] __rte_unused,
5713 const struct rte_flow_action actions[] __rte_unused,
5714 struct rte_flow_error *error)
5716 uint32_t handle_idx = 0;
5717 struct mlx5_flow *dev_flow;
5718 struct mlx5_flow_handle *dev_handle;
5719 struct mlx5_priv *priv = dev->data->dev_private;
5721 /* In case of corrupting the memory. */
5722 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5723 rte_flow_error_set(error, ENOSPC,
5724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5725 "not free temporary device flow");
5728 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5731 rte_flow_error_set(error, ENOMEM,
5732 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5733 "not enough memory to create flow handle");
5736 /* No multi-thread supporting. */
5737 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5738 dev_flow->handle = dev_handle;
5739 dev_flow->handle_idx = handle_idx;
5740 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5742 * The matching value needs to be cleared to 0 before using. In the
5743 * past, it will be automatically cleared when using rte_*alloc
5744 * API. The time consumption will be almost the same as before.
5746 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5747 dev_flow->ingress = attr->ingress;
5748 dev_flow->dv.transfer = attr->transfer;
5752 #ifdef RTE_LIBRTE_MLX5_DEBUG
5754 * Sanity check for match mask and value. Similar to check_valid_spec() in
5755 * kernel driver. If unmasked bit is present in value, it returns failure.
5758 * pointer to match mask buffer.
5759 * @param match_value
5760 * pointer to match value buffer.
5763 * 0 if valid, -EINVAL otherwise.
5766 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5768 uint8_t *m = match_mask;
5769 uint8_t *v = match_value;
5772 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5775 "match_value differs from match_criteria"
5776 " %p[%u] != %p[%u]",
5777 match_value, i, match_mask, i);
5786 * Add match of ip_version.
5790 * @param[in] headers_v
5791 * Values header pointer.
5792 * @param[in] headers_m
5793 * Masks header pointer.
5794 * @param[in] ip_version
5795 * The IP version to set.
5798 flow_dv_set_match_ip_version(uint32_t group,
5804 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5806 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5808 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5809 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5810 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5814 * Add Ethernet item to matcher and to the value.
5816 * @param[in, out] matcher
5818 * @param[in, out] key
5819 * Flow matcher value.
5821 * Flow pattern to translate.
5823 * Item is inner pattern.
5826 flow_dv_translate_item_eth(void *matcher, void *key,
5827 const struct rte_flow_item *item, int inner,
5830 const struct rte_flow_item_eth *eth_m = item->mask;
5831 const struct rte_flow_item_eth *eth_v = item->spec;
5832 const struct rte_flow_item_eth nic_mask = {
5833 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5834 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5835 .type = RTE_BE16(0xffff),
5847 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5849 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5851 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5853 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5855 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5856 ð_m->dst, sizeof(eth_m->dst));
5857 /* The value must be in the range of the mask. */
5858 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5859 for (i = 0; i < sizeof(eth_m->dst); ++i)
5860 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5861 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5862 ð_m->src, sizeof(eth_m->src));
5863 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5864 /* The value must be in the range of the mask. */
5865 for (i = 0; i < sizeof(eth_m->dst); ++i)
5866 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5868 /* When ethertype is present set mask for tagged VLAN. */
5869 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5870 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5871 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5872 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5873 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5875 /* Return here to avoid setting match on ethertype. */
5880 * HW supports match on one Ethertype, the Ethertype following the last
5881 * VLAN tag of the packet (see PRM).
5882 * Set match on ethertype only if ETH header is not followed by VLAN.
5883 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5884 * ethertype, and use ip_version field instead.
5886 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5887 eth_m->type == 0xFFFF) {
5888 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5889 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5890 eth_m->type == 0xFFFF) {
5891 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5893 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5894 rte_be_to_cpu_16(eth_m->type));
5895 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5897 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5902 * Add VLAN item to matcher and to the value.
5904 * @param[in, out] dev_flow
5906 * @param[in, out] matcher
5908 * @param[in, out] key
5909 * Flow matcher value.
5911 * Flow pattern to translate.
5913 * Item is inner pattern.
5916 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5917 void *matcher, void *key,
5918 const struct rte_flow_item *item,
5919 int inner, uint32_t group)
5921 const struct rte_flow_item_vlan *vlan_m = item->mask;
5922 const struct rte_flow_item_vlan *vlan_v = item->spec;
5929 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5931 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5933 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5935 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5937 * This is workaround, masks are not supported,
5938 * and pre-validated.
5941 dev_flow->handle->vf_vlan.tag =
5942 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5945 * When VLAN item exists in flow, mark packet as tagged,
5946 * even if TCI is not specified.
5948 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5949 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5953 vlan_m = &rte_flow_item_vlan_mask;
5954 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5955 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5956 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5958 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5959 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5960 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5961 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5963 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5964 * ethertype, and use ip_version field instead.
5966 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5967 vlan_m->inner_type == 0xFFFF) {
5968 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5969 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5970 vlan_m->inner_type == 0xFFFF) {
5971 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5973 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5974 rte_be_to_cpu_16(vlan_m->inner_type));
5975 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5976 rte_be_to_cpu_16(vlan_m->inner_type &
5977 vlan_v->inner_type));
5982 * Add IPV4 item to matcher and to the value.
5984 * @param[in, out] matcher
5986 * @param[in, out] key
5987 * Flow matcher value.
5989 * Flow pattern to translate.
5990 * @param[in] item_flags
5991 * Bit-fields that holds the items detected until now.
5993 * Item is inner pattern.
5995 * The group to insert the rule.
5998 flow_dv_translate_item_ipv4(void *matcher, void *key,
5999 const struct rte_flow_item *item,
6000 const uint64_t item_flags,
6001 int inner, uint32_t group)
6003 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6004 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6005 const struct rte_flow_item_ipv4 nic_mask = {
6007 .src_addr = RTE_BE32(0xffffffff),
6008 .dst_addr = RTE_BE32(0xffffffff),
6009 .type_of_service = 0xff,
6010 .next_proto_id = 0xff,
6011 .time_to_live = 0xff,
6021 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6023 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6025 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6027 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6029 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6031 * On outer header (which must contains L2), or inner header with L2,
6032 * set cvlan_tag mask bit to mark this packet as untagged.
6033 * This should be done even if item->spec is empty.
6035 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6036 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6041 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6042 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6043 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6044 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6045 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6046 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6047 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6048 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6049 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6050 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6051 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6052 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6053 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6054 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6055 ipv4_m->hdr.type_of_service);
6056 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6057 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6058 ipv4_m->hdr.type_of_service >> 2);
6059 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6060 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6061 ipv4_m->hdr.next_proto_id);
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6063 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6064 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6065 ipv4_m->hdr.time_to_live);
6066 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6067 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6071 * Add IPV6 item to matcher and to the value.
6073 * @param[in, out] matcher
6075 * @param[in, out] key
6076 * Flow matcher value.
6078 * Flow pattern to translate.
6079 * @param[in] item_flags
6080 * Bit-fields that holds the items detected until now.
6082 * Item is inner pattern.
6084 * The group to insert the rule.
6087 flow_dv_translate_item_ipv6(void *matcher, void *key,
6088 const struct rte_flow_item *item,
6089 const uint64_t item_flags,
6090 int inner, uint32_t group)
6092 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6093 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6094 const struct rte_flow_item_ipv6 nic_mask = {
6097 "\xff\xff\xff\xff\xff\xff\xff\xff"
6098 "\xff\xff\xff\xff\xff\xff\xff\xff",
6100 "\xff\xff\xff\xff\xff\xff\xff\xff"
6101 "\xff\xff\xff\xff\xff\xff\xff\xff",
6102 .vtc_flow = RTE_BE32(0xffffffff),
6109 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6110 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6119 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6121 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6123 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6125 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6127 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6129 * On outer header (which must contains L2), or inner header with L2,
6130 * set cvlan_tag mask bit to mark this packet as untagged.
6131 * This should be done even if item->spec is empty.
6133 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6134 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6139 size = sizeof(ipv6_m->hdr.dst_addr);
6140 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6141 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6142 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6143 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6144 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6145 for (i = 0; i < size; ++i)
6146 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6147 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6148 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6149 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6150 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6151 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6152 for (i = 0; i < size; ++i)
6153 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6155 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6156 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6157 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6158 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6159 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6160 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6163 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6165 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6168 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6170 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6174 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6176 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6177 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6180 ipv6_m->hdr.hop_limits);
6181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6182 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6186 * Add TCP item to matcher and to the value.
6188 * @param[in, out] matcher
6190 * @param[in, out] key
6191 * Flow matcher value.
6193 * Flow pattern to translate.
6195 * Item is inner pattern.
6198 flow_dv_translate_item_tcp(void *matcher, void *key,
6199 const struct rte_flow_item *item,
6202 const struct rte_flow_item_tcp *tcp_m = item->mask;
6203 const struct rte_flow_item_tcp *tcp_v = item->spec;
6208 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6210 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6212 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6214 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6221 tcp_m = &rte_flow_item_tcp_mask;
6222 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6223 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6224 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6225 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6226 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6227 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6228 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6229 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6230 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6231 tcp_m->hdr.tcp_flags);
6232 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6233 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6237 * Add UDP item to matcher and to the value.
6239 * @param[in, out] matcher
6241 * @param[in, out] key
6242 * Flow matcher value.
6244 * Flow pattern to translate.
6246 * Item is inner pattern.
6249 flow_dv_translate_item_udp(void *matcher, void *key,
6250 const struct rte_flow_item *item,
6253 const struct rte_flow_item_udp *udp_m = item->mask;
6254 const struct rte_flow_item_udp *udp_v = item->spec;
6259 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6261 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6263 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6265 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6268 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6272 udp_m = &rte_flow_item_udp_mask;
6273 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6274 rte_be_to_cpu_16(udp_m->hdr.src_port));
6275 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6276 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6277 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6278 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6280 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6284 * Add GRE optional Key item to matcher and to the value.
6286 * @param[in, out] matcher
6288 * @param[in, out] key
6289 * Flow matcher value.
6291 * Flow pattern to translate.
6293 * Item is inner pattern.
6296 flow_dv_translate_item_gre_key(void *matcher, void *key,
6297 const struct rte_flow_item *item)
6299 const rte_be32_t *key_m = item->mask;
6300 const rte_be32_t *key_v = item->spec;
6301 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6302 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6303 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6305 /* GRE K bit must be on and should already be validated */
6306 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6307 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6311 key_m = &gre_key_default_mask;
6312 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6313 rte_be_to_cpu_32(*key_m) >> 8);
6314 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6315 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6316 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6317 rte_be_to_cpu_32(*key_m) & 0xFF);
6318 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6319 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6323 * Add GRE item to matcher and to the value.
6325 * @param[in, out] matcher
6327 * @param[in, out] key
6328 * Flow matcher value.
6330 * Flow pattern to translate.
6332 * Item is inner pattern.
6335 flow_dv_translate_item_gre(void *matcher, void *key,
6336 const struct rte_flow_item *item,
6339 const struct rte_flow_item_gre *gre_m = item->mask;
6340 const struct rte_flow_item_gre *gre_v = item->spec;
6343 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6344 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6351 uint16_t s_present:1;
6352 uint16_t k_present:1;
6353 uint16_t rsvd_bit1:1;
6354 uint16_t c_present:1;
6358 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6361 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6363 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6365 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6367 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6369 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6374 gre_m = &rte_flow_item_gre_mask;
6375 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6376 rte_be_to_cpu_16(gre_m->protocol));
6377 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6378 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6379 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6380 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6381 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6382 gre_crks_rsvd0_ver_m.c_present);
6383 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6384 gre_crks_rsvd0_ver_v.c_present &
6385 gre_crks_rsvd0_ver_m.c_present);
6386 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6387 gre_crks_rsvd0_ver_m.k_present);
6388 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6389 gre_crks_rsvd0_ver_v.k_present &
6390 gre_crks_rsvd0_ver_m.k_present);
6391 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6392 gre_crks_rsvd0_ver_m.s_present);
6393 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6394 gre_crks_rsvd0_ver_v.s_present &
6395 gre_crks_rsvd0_ver_m.s_present);
6399 * Add NVGRE item to matcher and to the value.
6401 * @param[in, out] matcher
6403 * @param[in, out] key
6404 * Flow matcher value.
6406 * Flow pattern to translate.
6408 * Item is inner pattern.
6411 flow_dv_translate_item_nvgre(void *matcher, void *key,
6412 const struct rte_flow_item *item,
6415 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6416 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6417 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6418 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6419 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6420 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6426 /* For NVGRE, GRE header fields must be set with defined values. */
6427 const struct rte_flow_item_gre gre_spec = {
6428 .c_rsvd0_ver = RTE_BE16(0x2000),
6429 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6431 const struct rte_flow_item_gre gre_mask = {
6432 .c_rsvd0_ver = RTE_BE16(0xB000),
6433 .protocol = RTE_BE16(UINT16_MAX),
6435 const struct rte_flow_item gre_item = {
6440 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6444 nvgre_m = &rte_flow_item_nvgre_mask;
6445 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6446 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6447 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6448 memcpy(gre_key_m, tni_flow_id_m, size);
6449 for (i = 0; i < size; ++i)
6450 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6454 * Add VXLAN item to matcher and to the value.
6456 * @param[in, out] matcher
6458 * @param[in, out] key
6459 * Flow matcher value.
6461 * Flow pattern to translate.
6463 * Item is inner pattern.
6466 flow_dv_translate_item_vxlan(void *matcher, void *key,
6467 const struct rte_flow_item *item,
6470 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6471 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6474 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6475 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6483 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6485 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6487 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6489 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6491 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6492 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6493 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6500 vxlan_m = &rte_flow_item_vxlan_mask;
6501 size = sizeof(vxlan_m->vni);
6502 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6503 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6504 memcpy(vni_m, vxlan_m->vni, size);
6505 for (i = 0; i < size; ++i)
6506 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6510 * Add VXLAN-GPE item to matcher and to the value.
6512 * @param[in, out] matcher
6514 * @param[in, out] key
6515 * Flow matcher value.
6517 * Flow pattern to translate.
6519 * Item is inner pattern.
6523 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6524 const struct rte_flow_item *item, int inner)
6526 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6527 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6531 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6533 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6539 uint8_t flags_m = 0xff;
6540 uint8_t flags_v = 0xc;
6543 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6545 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6547 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6549 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6551 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6552 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6553 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6555 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6560 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6561 size = sizeof(vxlan_m->vni);
6562 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6563 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6564 memcpy(vni_m, vxlan_m->vni, size);
6565 for (i = 0; i < size; ++i)
6566 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6567 if (vxlan_m->flags) {
6568 flags_m = vxlan_m->flags;
6569 flags_v = vxlan_v->flags;
6571 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6572 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6573 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6575 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6580 * Add Geneve item to matcher and to the value.
6582 * @param[in, out] matcher
6584 * @param[in, out] key
6585 * Flow matcher value.
6587 * Flow pattern to translate.
6589 * Item is inner pattern.
6593 flow_dv_translate_item_geneve(void *matcher, void *key,
6594 const struct rte_flow_item *item, int inner)
6596 const struct rte_flow_item_geneve *geneve_m = item->mask;
6597 const struct rte_flow_item_geneve *geneve_v = item->spec;
6600 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6601 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6612 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6614 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6616 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6618 dport = MLX5_UDP_PORT_GENEVE;
6619 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6626 geneve_m = &rte_flow_item_geneve_mask;
6627 size = sizeof(geneve_m->vni);
6628 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6629 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6630 memcpy(vni_m, geneve_m->vni, size);
6631 for (i = 0; i < size; ++i)
6632 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6633 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6634 rte_be_to_cpu_16(geneve_m->protocol));
6635 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6636 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6637 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6638 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6639 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6640 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6641 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6642 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6643 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6644 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6645 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6646 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6647 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6651 * Add MPLS item to matcher and to the value.
6653 * @param[in, out] matcher
6655 * @param[in, out] key
6656 * Flow matcher value.
6658 * Flow pattern to translate.
6659 * @param[in] prev_layer
6660 * The protocol layer indicated in previous item.
6662 * Item is inner pattern.
6665 flow_dv_translate_item_mpls(void *matcher, void *key,
6666 const struct rte_flow_item *item,
6667 uint64_t prev_layer,
6670 const uint32_t *in_mpls_m = item->mask;
6671 const uint32_t *in_mpls_v = item->spec;
6672 uint32_t *out_mpls_m = 0;
6673 uint32_t *out_mpls_v = 0;
6674 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6675 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6676 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6678 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6679 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6680 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6682 switch (prev_layer) {
6683 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6686 MLX5_UDP_PORT_MPLS);
6688 case MLX5_FLOW_LAYER_GRE:
6689 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6690 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6691 RTE_ETHER_TYPE_MPLS);
6694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6702 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6703 switch (prev_layer) {
6704 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6706 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6707 outer_first_mpls_over_udp);
6709 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6710 outer_first_mpls_over_udp);
6712 case MLX5_FLOW_LAYER_GRE:
6714 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6715 outer_first_mpls_over_gre);
6717 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6718 outer_first_mpls_over_gre);
6721 /* Inner MPLS not over GRE is not supported. */
6724 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6728 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6734 if (out_mpls_m && out_mpls_v) {
6735 *out_mpls_m = *in_mpls_m;
6736 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6741 * Add metadata register item to matcher
6743 * @param[in, out] matcher
6745 * @param[in, out] key
6746 * Flow matcher value.
6747 * @param[in] reg_type
6748 * Type of device metadata register
6755 flow_dv_match_meta_reg(void *matcher, void *key,
6756 enum modify_reg reg_type,
6757 uint32_t data, uint32_t mask)
6760 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6762 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6768 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6769 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6772 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6773 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6777 * The metadata register C0 field might be divided into
6778 * source vport index and META item value, we should set
6779 * this field according to specified mask, not as whole one.
6781 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6783 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6784 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6787 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6790 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6791 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6794 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6795 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6798 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6799 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6802 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6803 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6806 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6807 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6810 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6811 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6814 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6815 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6824 * Add MARK item to matcher
6827 * The device to configure through.
6828 * @param[in, out] matcher
6830 * @param[in, out] key
6831 * Flow matcher value.
6833 * Flow pattern to translate.
6836 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6837 void *matcher, void *key,
6838 const struct rte_flow_item *item)
6840 struct mlx5_priv *priv = dev->data->dev_private;
6841 const struct rte_flow_item_mark *mark;
6845 mark = item->mask ? (const void *)item->mask :
6846 &rte_flow_item_mark_mask;
6847 mask = mark->id & priv->sh->dv_mark_mask;
6848 mark = (const void *)item->spec;
6850 value = mark->id & priv->sh->dv_mark_mask & mask;
6852 enum modify_reg reg;
6854 /* Get the metadata register index for the mark. */
6855 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6856 MLX5_ASSERT(reg > 0);
6857 if (reg == REG_C_0) {
6858 struct mlx5_priv *priv = dev->data->dev_private;
6859 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6860 uint32_t shl_c0 = rte_bsf32(msk_c0);
6866 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6871 * Add META item to matcher
6874 * The devich to configure through.
6875 * @param[in, out] matcher
6877 * @param[in, out] key
6878 * Flow matcher value.
6880 * Attributes of flow that includes this item.
6882 * Flow pattern to translate.
6885 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6886 void *matcher, void *key,
6887 const struct rte_flow_attr *attr,
6888 const struct rte_flow_item *item)
6890 const struct rte_flow_item_meta *meta_m;
6891 const struct rte_flow_item_meta *meta_v;
6893 meta_m = (const void *)item->mask;
6895 meta_m = &rte_flow_item_meta_mask;
6896 meta_v = (const void *)item->spec;
6899 uint32_t value = meta_v->data;
6900 uint32_t mask = meta_m->data;
6902 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6906 * In datapath code there is no endianness
6907 * coversions for perfromance reasons, all
6908 * pattern conversions are done in rte_flow.
6910 value = rte_cpu_to_be_32(value);
6911 mask = rte_cpu_to_be_32(mask);
6912 if (reg == REG_C_0) {
6913 struct mlx5_priv *priv = dev->data->dev_private;
6914 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6915 uint32_t shl_c0 = rte_bsf32(msk_c0);
6916 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6917 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6924 MLX5_ASSERT(msk_c0);
6925 MLX5_ASSERT(!(~msk_c0 & mask));
6927 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6932 * Add vport metadata Reg C0 item to matcher
6934 * @param[in, out] matcher
6936 * @param[in, out] key
6937 * Flow matcher value.
6939 * Flow pattern to translate.
6942 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6943 uint32_t value, uint32_t mask)
6945 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6949 * Add tag item to matcher
6952 * The devich to configure through.
6953 * @param[in, out] matcher
6955 * @param[in, out] key
6956 * Flow matcher value.
6958 * Flow pattern to translate.
6961 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6962 void *matcher, void *key,
6963 const struct rte_flow_item *item)
6965 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6966 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6967 uint32_t mask, value;
6970 value = tag_v->data;
6971 mask = tag_m ? tag_m->data : UINT32_MAX;
6972 if (tag_v->id == REG_C_0) {
6973 struct mlx5_priv *priv = dev->data->dev_private;
6974 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6975 uint32_t shl_c0 = rte_bsf32(msk_c0);
6981 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6985 * Add TAG item to matcher
6988 * The devich to configure through.
6989 * @param[in, out] matcher
6991 * @param[in, out] key
6992 * Flow matcher value.
6994 * Flow pattern to translate.
6997 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6998 void *matcher, void *key,
6999 const struct rte_flow_item *item)
7001 const struct rte_flow_item_tag *tag_v = item->spec;
7002 const struct rte_flow_item_tag *tag_m = item->mask;
7003 enum modify_reg reg;
7006 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7007 /* Get the metadata register index for the tag. */
7008 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7009 MLX5_ASSERT(reg > 0);
7010 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7014 * Add source vport match to the specified matcher.
7016 * @param[in, out] matcher
7018 * @param[in, out] key
7019 * Flow matcher value.
7021 * Source vport value to match
7026 flow_dv_translate_item_source_vport(void *matcher, void *key,
7027 int16_t port, uint16_t mask)
7029 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7030 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7032 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7033 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7037 * Translate port-id item to eswitch match on port-id.
7040 * The devich to configure through.
7041 * @param[in, out] matcher
7043 * @param[in, out] key
7044 * Flow matcher value.
7046 * Flow pattern to translate.
7049 * 0 on success, a negative errno value otherwise.
7052 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7053 void *key, const struct rte_flow_item *item)
7055 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7056 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7057 struct mlx5_priv *priv;
7060 mask = pid_m ? pid_m->id : 0xffff;
7061 id = pid_v ? pid_v->id : dev->data->port_id;
7062 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7065 /* Translate to vport field or to metadata, depending on mode. */
7066 if (priv->vport_meta_mask)
7067 flow_dv_translate_item_meta_vport(matcher, key,
7068 priv->vport_meta_tag,
7069 priv->vport_meta_mask);
7071 flow_dv_translate_item_source_vport(matcher, key,
7072 priv->vport_id, mask);
7077 * Add ICMP6 item to matcher and to the value.
7079 * @param[in, out] matcher
7081 * @param[in, out] key
7082 * Flow matcher value.
7084 * Flow pattern to translate.
7086 * Item is inner pattern.
7089 flow_dv_translate_item_icmp6(void *matcher, void *key,
7090 const struct rte_flow_item *item,
7093 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7094 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7097 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7099 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7101 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7103 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7105 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7107 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7109 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7110 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7114 icmp6_m = &rte_flow_item_icmp6_mask;
7116 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7117 * If only the protocol is specified, no need to match the frag.
7119 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7120 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7121 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7122 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7123 icmp6_v->type & icmp6_m->type);
7124 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7125 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7126 icmp6_v->code & icmp6_m->code);
7130 * Add ICMP item to matcher and to the value.
7132 * @param[in, out] matcher
7134 * @param[in, out] key
7135 * Flow matcher value.
7137 * Flow pattern to translate.
7139 * Item is inner pattern.
7142 flow_dv_translate_item_icmp(void *matcher, void *key,
7143 const struct rte_flow_item *item,
7146 const struct rte_flow_item_icmp *icmp_m = item->mask;
7147 const struct rte_flow_item_icmp *icmp_v = item->spec;
7150 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7152 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7154 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7156 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7158 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7160 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7162 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7163 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7167 icmp_m = &rte_flow_item_icmp_mask;
7169 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7170 * If only the protocol is specified, no need to match the frag.
7172 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7173 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7174 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7175 icmp_m->hdr.icmp_type);
7176 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7177 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7178 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7179 icmp_m->hdr.icmp_code);
7180 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7181 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7185 * Add GTP item to matcher and to the value.
7187 * @param[in, out] matcher
7189 * @param[in, out] key
7190 * Flow matcher value.
7192 * Flow pattern to translate.
7194 * Item is inner pattern.
7197 flow_dv_translate_item_gtp(void *matcher, void *key,
7198 const struct rte_flow_item *item, int inner)
7200 const struct rte_flow_item_gtp *gtp_m = item->mask;
7201 const struct rte_flow_item_gtp *gtp_v = item->spec;
7204 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7206 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7207 uint16_t dport = RTE_GTPU_UDP_PORT;
7210 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7212 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7214 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7216 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7218 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7219 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7225 gtp_m = &rte_flow_item_gtp_mask;
7226 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7227 gtp_m->v_pt_rsv_flags);
7228 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7229 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7230 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7231 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7232 gtp_v->msg_type & gtp_m->msg_type);
7233 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7234 rte_be_to_cpu_32(gtp_m->teid));
7235 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7236 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7239 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7241 #define HEADER_IS_ZERO(match_criteria, headers) \
7242 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7243 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7246 * Calculate flow matcher enable bitmap.
7248 * @param match_criteria
7249 * Pointer to flow matcher criteria.
7252 * Bitmap of enabled fields.
7255 flow_dv_matcher_enable(uint32_t *match_criteria)
7257 uint8_t match_criteria_enable;
7259 match_criteria_enable =
7260 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7261 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7262 match_criteria_enable |=
7263 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7264 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7265 match_criteria_enable |=
7266 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7267 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7268 match_criteria_enable |=
7269 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7270 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7271 match_criteria_enable |=
7272 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7273 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7274 return match_criteria_enable;
7281 * @param[in, out] dev
7282 * Pointer to rte_eth_dev structure.
7283 * @param[in] table_id
7286 * Direction of the table.
7287 * @param[in] transfer
7288 * E-Switch or NIC flow.
7290 * pointer to error structure.
7293 * Returns tables resource based on the index, NULL in case of failed.
7295 static struct mlx5_flow_tbl_resource *
7296 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7297 uint32_t table_id, uint8_t egress,
7299 struct rte_flow_error *error)
7301 struct mlx5_priv *priv = dev->data->dev_private;
7302 struct mlx5_dev_ctx_shared *sh = priv->sh;
7303 struct mlx5_flow_tbl_resource *tbl;
7304 union mlx5_flow_tbl_key table_key = {
7306 .table_id = table_id,
7308 .domain = !!transfer,
7309 .direction = !!egress,
7312 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7314 struct mlx5_flow_tbl_data_entry *tbl_data;
7320 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7322 tbl = &tbl_data->tbl;
7323 rte_atomic32_inc(&tbl->refcnt);
7326 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7328 rte_flow_error_set(error, ENOMEM,
7329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7331 "cannot allocate flow table data entry");
7334 tbl_data->idx = idx;
7335 tbl = &tbl_data->tbl;
7336 pos = &tbl_data->entry;
7338 domain = sh->fdb_domain;
7340 domain = sh->tx_domain;
7342 domain = sh->rx_domain;
7343 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7345 rte_flow_error_set(error, ENOMEM,
7346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7347 NULL, "cannot create flow table object");
7348 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7352 * No multi-threads now, but still better to initialize the reference
7353 * count before insert it into the hash list.
7355 rte_atomic32_init(&tbl->refcnt);
7356 /* Jump action reference count is initialized here. */
7357 rte_atomic32_init(&tbl_data->jump.refcnt);
7358 pos->key = table_key.v64;
7359 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7361 rte_flow_error_set(error, -ret,
7362 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7363 "cannot insert flow table data entry");
7364 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7365 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7367 rte_atomic32_inc(&tbl->refcnt);
7372 * Release a flow table.
7375 * Pointer to rte_eth_dev structure.
7377 * Table resource to be released.
7380 * Returns 0 if table was released, else return 1;
7383 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7384 struct mlx5_flow_tbl_resource *tbl)
7386 struct mlx5_priv *priv = dev->data->dev_private;
7387 struct mlx5_dev_ctx_shared *sh = priv->sh;
7388 struct mlx5_flow_tbl_data_entry *tbl_data =
7389 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7393 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7394 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7396 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7398 /* remove the entry from the hash list and free memory. */
7399 mlx5_hlist_remove(sh->flow_tbls, pos);
7400 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7408 * Register the flow matcher.
7410 * @param[in, out] dev
7411 * Pointer to rte_eth_dev structure.
7412 * @param[in, out] matcher
7413 * Pointer to flow matcher.
7414 * @param[in, out] key
7415 * Pointer to flow table key.
7416 * @parm[in, out] dev_flow
7417 * Pointer to the dev_flow.
7419 * pointer to error structure.
7422 * 0 on success otherwise -errno and errno is set.
7425 flow_dv_matcher_register(struct rte_eth_dev *dev,
7426 struct mlx5_flow_dv_matcher *matcher,
7427 union mlx5_flow_tbl_key *key,
7428 struct mlx5_flow *dev_flow,
7429 struct rte_flow_error *error)
7431 struct mlx5_priv *priv = dev->data->dev_private;
7432 struct mlx5_dev_ctx_shared *sh = priv->sh;
7433 struct mlx5_flow_dv_matcher *cache_matcher;
7434 struct mlx5dv_flow_matcher_attr dv_attr = {
7435 .type = IBV_FLOW_ATTR_NORMAL,
7436 .match_mask = (void *)&matcher->mask,
7438 struct mlx5_flow_tbl_resource *tbl;
7439 struct mlx5_flow_tbl_data_entry *tbl_data;
7442 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7443 key->domain, error);
7445 return -rte_errno; /* No need to refill the error info */
7446 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7447 /* Lookup from cache. */
7448 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7449 if (matcher->crc == cache_matcher->crc &&
7450 matcher->priority == cache_matcher->priority &&
7451 !memcmp((const void *)matcher->mask.buf,
7452 (const void *)cache_matcher->mask.buf,
7453 cache_matcher->mask.size)) {
7455 "%s group %u priority %hd use %s "
7456 "matcher %p: refcnt %d++",
7457 key->domain ? "FDB" : "NIC", key->table_id,
7458 cache_matcher->priority,
7459 key->direction ? "tx" : "rx",
7460 (void *)cache_matcher,
7461 rte_atomic32_read(&cache_matcher->refcnt));
7462 rte_atomic32_inc(&cache_matcher->refcnt);
7463 dev_flow->handle->dvh.matcher = cache_matcher;
7464 /* old matcher should not make the table ref++. */
7465 flow_dv_tbl_resource_release(dev, tbl);
7469 /* Register new matcher. */
7470 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7471 if (!cache_matcher) {
7472 flow_dv_tbl_resource_release(dev, tbl);
7473 return rte_flow_error_set(error, ENOMEM,
7474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7475 "cannot allocate matcher memory");
7477 *cache_matcher = *matcher;
7478 dv_attr.match_criteria_enable =
7479 flow_dv_matcher_enable(cache_matcher->mask.buf);
7480 dv_attr.priority = matcher->priority;
7482 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7483 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7484 &cache_matcher->matcher_object);
7486 rte_free(cache_matcher);
7487 #ifdef HAVE_MLX5DV_DR
7488 flow_dv_tbl_resource_release(dev, tbl);
7490 return rte_flow_error_set(error, ENOMEM,
7491 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7492 NULL, "cannot create matcher");
7494 /* Save the table information */
7495 cache_matcher->tbl = tbl;
7496 rte_atomic32_init(&cache_matcher->refcnt);
7497 /* only matcher ref++, table ref++ already done above in get API. */
7498 rte_atomic32_inc(&cache_matcher->refcnt);
7499 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7500 dev_flow->handle->dvh.matcher = cache_matcher;
7501 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7502 key->domain ? "FDB" : "NIC", key->table_id,
7503 cache_matcher->priority,
7504 key->direction ? "tx" : "rx", (void *)cache_matcher,
7505 rte_atomic32_read(&cache_matcher->refcnt));
7510 * Find existing tag resource or create and register a new one.
7512 * @param dev[in, out]
7513 * Pointer to rte_eth_dev structure.
7514 * @param[in, out] tag_be24
7515 * Tag value in big endian then R-shift 8.
7516 * @parm[in, out] dev_flow
7517 * Pointer to the dev_flow.
7519 * pointer to error structure.
7522 * 0 on success otherwise -errno and errno is set.
7525 flow_dv_tag_resource_register
7526 (struct rte_eth_dev *dev,
7528 struct mlx5_flow *dev_flow,
7529 struct rte_flow_error *error)
7531 struct mlx5_priv *priv = dev->data->dev_private;
7532 struct mlx5_dev_ctx_shared *sh = priv->sh;
7533 struct mlx5_flow_dv_tag_resource *cache_resource;
7534 struct mlx5_hlist_entry *entry;
7537 /* Lookup a matching resource from cache. */
7538 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7540 cache_resource = container_of
7541 (entry, struct mlx5_flow_dv_tag_resource, entry);
7542 rte_atomic32_inc(&cache_resource->refcnt);
7543 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7544 dev_flow->dv.tag_resource = cache_resource;
7545 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7546 (void *)cache_resource,
7547 rte_atomic32_read(&cache_resource->refcnt));
7550 /* Register new resource. */
7551 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7552 &dev_flow->handle->dvh.rix_tag);
7553 if (!cache_resource)
7554 return rte_flow_error_set(error, ENOMEM,
7555 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7556 "cannot allocate resource memory");
7557 cache_resource->entry.key = (uint64_t)tag_be24;
7558 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7559 &cache_resource->action);
7561 rte_free(cache_resource);
7562 return rte_flow_error_set(error, ENOMEM,
7563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7564 NULL, "cannot create action");
7566 rte_atomic32_init(&cache_resource->refcnt);
7567 rte_atomic32_inc(&cache_resource->refcnt);
7568 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7569 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7570 rte_free(cache_resource);
7571 return rte_flow_error_set(error, EEXIST,
7572 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7573 NULL, "cannot insert tag");
7575 dev_flow->dv.tag_resource = cache_resource;
7576 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7577 (void *)cache_resource,
7578 rte_atomic32_read(&cache_resource->refcnt));
7586 * Pointer to Ethernet device.
7591 * 1 while a reference on it exists, 0 when freed.
7594 flow_dv_tag_release(struct rte_eth_dev *dev,
7597 struct mlx5_priv *priv = dev->data->dev_private;
7598 struct mlx5_dev_ctx_shared *sh = priv->sh;
7599 struct mlx5_flow_dv_tag_resource *tag;
7601 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7604 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7605 dev->data->port_id, (void *)tag,
7606 rte_atomic32_read(&tag->refcnt));
7607 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7608 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7609 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7610 DRV_LOG(DEBUG, "port %u tag %p: removed",
7611 dev->data->port_id, (void *)tag);
7612 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7619 * Translate port ID action to vport.
7622 * Pointer to rte_eth_dev structure.
7624 * Pointer to the port ID action.
7625 * @param[out] dst_port_id
7626 * The target port ID.
7628 * Pointer to the error structure.
7631 * 0 on success, a negative errno value otherwise and rte_errno is set.
7634 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7635 const struct rte_flow_action *action,
7636 uint32_t *dst_port_id,
7637 struct rte_flow_error *error)
7640 struct mlx5_priv *priv;
7641 const struct rte_flow_action_port_id *conf =
7642 (const struct rte_flow_action_port_id *)action->conf;
7644 port = conf->original ? dev->data->port_id : conf->id;
7645 priv = mlx5_port_to_eswitch_info(port, false);
7647 return rte_flow_error_set(error, -rte_errno,
7648 RTE_FLOW_ERROR_TYPE_ACTION,
7650 "No eswitch info was found for port");
7651 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7653 * This parameter is transferred to
7654 * mlx5dv_dr_action_create_dest_ib_port().
7656 *dst_port_id = priv->dev_port;
7659 * Legacy mode, no LAG configurations is supported.
7660 * This parameter is transferred to
7661 * mlx5dv_dr_action_create_dest_vport().
7663 *dst_port_id = priv->vport_id;
7669 * Create a counter with aging configuration.
7672 * Pointer to rte_eth_dev structure.
7674 * Pointer to the counter action configuration.
7676 * Pointer to the aging action configuration.
7679 * Index to flow counter on success, 0 otherwise.
7682 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7683 struct mlx5_flow *dev_flow,
7684 const struct rte_flow_action_count *count,
7685 const struct rte_flow_action_age *age)
7688 struct mlx5_age_param *age_param;
7690 counter = flow_dv_counter_alloc(dev,
7691 count ? count->shared : 0,
7692 count ? count->id : 0,
7693 dev_flow->dv.group, !!age);
7694 if (!counter || age == NULL)
7696 age_param = flow_dv_counter_idx_get_age(dev, counter);
7698 * The counter age accuracy may have a bit delay. Have 3/4
7699 * second bias on the timeount in order to let it age in time.
7701 age_param->context = age->context ? age->context :
7702 (void *)(uintptr_t)(dev_flow->flow_idx);
7704 * The counter age accuracy may have a bit delay. Have 3/4
7705 * second bias on the timeount in order to let it age in time.
7707 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7708 /* Set expire time in unit of 0.1 sec. */
7709 age_param->port_id = dev->data->port_id;
7710 age_param->expire = age_param->timeout +
7711 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7712 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7716 * Add Tx queue matcher
7719 * Pointer to the dev struct.
7720 * @param[in, out] matcher
7722 * @param[in, out] key
7723 * Flow matcher value.
7725 * Flow pattern to translate.
7727 * Item is inner pattern.
7730 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7731 void *matcher, void *key,
7732 const struct rte_flow_item *item)
7734 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7735 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7737 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7739 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7740 struct mlx5_txq_ctrl *txq;
7744 queue_m = (const void *)item->mask;
7747 queue_v = (const void *)item->spec;
7750 txq = mlx5_txq_get(dev, queue_v->queue);
7753 queue = txq->obj->sq->id;
7754 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7755 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7756 queue & queue_m->queue);
7757 mlx5_txq_release(dev, queue_v->queue);
7761 * Set the hash fields according to the @p flow information.
7763 * @param[in] dev_flow
7764 * Pointer to the mlx5_flow.
7765 * @param[in] rss_desc
7766 * Pointer to the mlx5_flow_rss_desc.
7769 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7770 struct mlx5_flow_rss_desc *rss_desc)
7772 uint64_t items = dev_flow->handle->layers;
7774 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7776 dev_flow->hash_fields = 0;
7777 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7778 if (rss_desc->level >= 2) {
7779 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7783 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7784 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7785 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7786 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7787 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7788 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7789 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7791 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7793 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7794 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7795 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7796 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7797 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7798 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7799 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7801 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7804 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7805 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7806 if (rss_types & ETH_RSS_UDP) {
7807 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7808 dev_flow->hash_fields |=
7809 IBV_RX_HASH_SRC_PORT_UDP;
7810 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7811 dev_flow->hash_fields |=
7812 IBV_RX_HASH_DST_PORT_UDP;
7814 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7816 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7817 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7818 if (rss_types & ETH_RSS_TCP) {
7819 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7820 dev_flow->hash_fields |=
7821 IBV_RX_HASH_SRC_PORT_TCP;
7822 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7823 dev_flow->hash_fields |=
7824 IBV_RX_HASH_DST_PORT_TCP;
7826 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7832 * Fill the flow with DV spec, lock free
7833 * (mutex should be acquired by caller).
7836 * Pointer to rte_eth_dev structure.
7837 * @param[in, out] dev_flow
7838 * Pointer to the sub flow.
7840 * Pointer to the flow attributes.
7842 * Pointer to the list of items.
7843 * @param[in] actions
7844 * Pointer to the list of actions.
7846 * Pointer to the error structure.
7849 * 0 on success, a negative errno value otherwise and rte_errno is set.
7852 __flow_dv_translate(struct rte_eth_dev *dev,
7853 struct mlx5_flow *dev_flow,
7854 const struct rte_flow_attr *attr,
7855 const struct rte_flow_item items[],
7856 const struct rte_flow_action actions[],
7857 struct rte_flow_error *error)
7859 struct mlx5_priv *priv = dev->data->dev_private;
7860 struct mlx5_dev_config *dev_conf = &priv->config;
7861 struct rte_flow *flow = dev_flow->flow;
7862 struct mlx5_flow_handle *handle = dev_flow->handle;
7863 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7865 [!!priv->flow_nested_idx];
7866 uint64_t item_flags = 0;
7867 uint64_t last_item = 0;
7868 uint64_t action_flags = 0;
7869 uint64_t priority = attr->priority;
7870 struct mlx5_flow_dv_matcher matcher = {
7872 .size = sizeof(matcher.mask.buf),
7876 bool actions_end = false;
7878 struct mlx5_flow_dv_modify_hdr_resource res;
7879 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7880 sizeof(struct mlx5_modification_cmd) *
7881 (MLX5_MAX_MODIFY_NUM + 1)];
7883 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7884 const struct rte_flow_action_count *count = NULL;
7885 const struct rte_flow_action_age *age = NULL;
7886 union flow_dv_attr flow_attr = { .attr = 0 };
7888 union mlx5_flow_tbl_key tbl_key;
7889 uint32_t modify_action_position = UINT32_MAX;
7890 void *match_mask = matcher.mask.buf;
7891 void *match_value = dev_flow->dv.value.buf;
7892 uint8_t next_protocol = 0xff;
7893 struct rte_vlan_hdr vlan = { 0 };
7897 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7898 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7899 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7900 !!priv->fdb_def_rule, &table, error);
7903 dev_flow->dv.group = table;
7905 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7906 if (priority == MLX5_FLOW_PRIO_RSVD)
7907 priority = dev_conf->flow_prio - 1;
7908 /* number of actions must be set to 0 in case of dirty stack. */
7909 mhdr_res->actions_num = 0;
7910 for (; !actions_end ; actions++) {
7911 const struct rte_flow_action_queue *queue;
7912 const struct rte_flow_action_rss *rss;
7913 const struct rte_flow_action *action = actions;
7914 const uint8_t *rss_key;
7915 const struct rte_flow_action_jump *jump_data;
7916 const struct rte_flow_action_meter *mtr;
7917 struct mlx5_flow_tbl_resource *tbl;
7918 uint32_t port_id = 0;
7919 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7920 int action_type = actions->type;
7921 const struct rte_flow_action *found_action = NULL;
7922 struct mlx5_flow_meter *fm = NULL;
7924 if (!mlx5_flow_os_action_supported(action_type))
7925 return rte_flow_error_set(error, ENOTSUP,
7926 RTE_FLOW_ERROR_TYPE_ACTION,
7928 "action not supported");
7929 switch (action_type) {
7930 case RTE_FLOW_ACTION_TYPE_VOID:
7932 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7933 if (flow_dv_translate_action_port_id(dev, action,
7936 port_id_resource.port_id = port_id;
7937 MLX5_ASSERT(!handle->rix_port_id_action);
7938 if (flow_dv_port_id_action_resource_register
7939 (dev, &port_id_resource, dev_flow, error))
7941 dev_flow->dv.actions[actions_n++] =
7942 dev_flow->dv.port_id_action->action;
7943 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7944 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7946 case RTE_FLOW_ACTION_TYPE_FLAG:
7947 action_flags |= MLX5_FLOW_ACTION_FLAG;
7948 dev_flow->handle->mark = 1;
7949 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7950 struct rte_flow_action_mark mark = {
7951 .id = MLX5_FLOW_MARK_DEFAULT,
7954 if (flow_dv_convert_action_mark(dev, &mark,
7958 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7961 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7963 * Only one FLAG or MARK is supported per device flow
7964 * right now. So the pointer to the tag resource must be
7965 * zero before the register process.
7967 MLX5_ASSERT(!handle->dvh.rix_tag);
7968 if (flow_dv_tag_resource_register(dev, tag_be,
7971 MLX5_ASSERT(dev_flow->dv.tag_resource);
7972 dev_flow->dv.actions[actions_n++] =
7973 dev_flow->dv.tag_resource->action;
7975 case RTE_FLOW_ACTION_TYPE_MARK:
7976 action_flags |= MLX5_FLOW_ACTION_MARK;
7977 dev_flow->handle->mark = 1;
7978 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7979 const struct rte_flow_action_mark *mark =
7980 (const struct rte_flow_action_mark *)
7983 if (flow_dv_convert_action_mark(dev, mark,
7987 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7991 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7992 /* Legacy (non-extensive) MARK action. */
7993 tag_be = mlx5_flow_mark_set
7994 (((const struct rte_flow_action_mark *)
7995 (actions->conf))->id);
7996 MLX5_ASSERT(!handle->dvh.rix_tag);
7997 if (flow_dv_tag_resource_register(dev, tag_be,
8000 MLX5_ASSERT(dev_flow->dv.tag_resource);
8001 dev_flow->dv.actions[actions_n++] =
8002 dev_flow->dv.tag_resource->action;
8004 case RTE_FLOW_ACTION_TYPE_SET_META:
8005 if (flow_dv_convert_action_set_meta
8006 (dev, mhdr_res, attr,
8007 (const struct rte_flow_action_set_meta *)
8008 actions->conf, error))
8010 action_flags |= MLX5_FLOW_ACTION_SET_META;
8012 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8013 if (flow_dv_convert_action_set_tag
8015 (const struct rte_flow_action_set_tag *)
8016 actions->conf, error))
8018 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8020 case RTE_FLOW_ACTION_TYPE_DROP:
8021 action_flags |= MLX5_FLOW_ACTION_DROP;
8022 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8024 case RTE_FLOW_ACTION_TYPE_QUEUE:
8025 queue = actions->conf;
8026 rss_desc->queue_num = 1;
8027 rss_desc->queue[0] = queue->index;
8028 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8029 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8031 case RTE_FLOW_ACTION_TYPE_RSS:
8032 rss = actions->conf;
8033 memcpy(rss_desc->queue, rss->queue,
8034 rss->queue_num * sizeof(uint16_t));
8035 rss_desc->queue_num = rss->queue_num;
8036 /* NULL RSS key indicates default RSS key. */
8037 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8038 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8040 * rss->level and rss.types should be set in advance
8041 * when expanding items for RSS.
8043 action_flags |= MLX5_FLOW_ACTION_RSS;
8044 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8046 case RTE_FLOW_ACTION_TYPE_AGE:
8047 case RTE_FLOW_ACTION_TYPE_COUNT:
8048 if (!dev_conf->devx) {
8049 return rte_flow_error_set
8051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8053 "count action not supported");
8055 /* Save information first, will apply later. */
8056 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8057 count = action->conf;
8060 action_flags |= MLX5_FLOW_ACTION_COUNT;
8062 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8063 dev_flow->dv.actions[actions_n++] =
8064 priv->sh->pop_vlan_action;
8065 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8067 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8068 if (!(action_flags &
8069 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8070 flow_dev_get_vlan_info_from_items(items, &vlan);
8071 vlan.eth_proto = rte_be_to_cpu_16
8072 ((((const struct rte_flow_action_of_push_vlan *)
8073 actions->conf)->ethertype));
8074 found_action = mlx5_flow_find_action
8076 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8078 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8079 found_action = mlx5_flow_find_action
8081 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8083 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8084 if (flow_dv_create_action_push_vlan
8085 (dev, attr, &vlan, dev_flow, error))
8087 dev_flow->dv.actions[actions_n++] =
8088 dev_flow->dv.push_vlan_res->action;
8089 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8091 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8092 /* of_vlan_push action handled this action */
8093 MLX5_ASSERT(action_flags &
8094 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8096 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8097 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8099 flow_dev_get_vlan_info_from_items(items, &vlan);
8100 mlx5_update_vlan_vid_pcp(actions, &vlan);
8101 /* If no VLAN push - this is a modify header action */
8102 if (flow_dv_convert_action_modify_vlan_vid
8103 (mhdr_res, actions, error))
8105 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8107 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8108 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8109 if (flow_dv_create_action_l2_encap(dev, actions,
8114 dev_flow->dv.actions[actions_n++] =
8115 dev_flow->dv.encap_decap->action;
8116 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8118 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8119 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8120 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8124 dev_flow->dv.actions[actions_n++] =
8125 dev_flow->dv.encap_decap->action;
8126 action_flags |= MLX5_FLOW_ACTION_DECAP;
8128 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8129 /* Handle encap with preceding decap. */
8130 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8131 if (flow_dv_create_action_raw_encap
8132 (dev, actions, dev_flow, attr, error))
8134 dev_flow->dv.actions[actions_n++] =
8135 dev_flow->dv.encap_decap->action;
8137 /* Handle encap without preceding decap. */
8138 if (flow_dv_create_action_l2_encap
8139 (dev, actions, dev_flow, attr->transfer,
8142 dev_flow->dv.actions[actions_n++] =
8143 dev_flow->dv.encap_decap->action;
8145 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8147 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8148 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8150 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8151 if (flow_dv_create_action_l2_decap
8152 (dev, dev_flow, attr->transfer, error))
8154 dev_flow->dv.actions[actions_n++] =
8155 dev_flow->dv.encap_decap->action;
8157 /* If decap is followed by encap, handle it at encap. */
8158 action_flags |= MLX5_FLOW_ACTION_DECAP;
8160 case RTE_FLOW_ACTION_TYPE_JUMP:
8161 jump_data = action->conf;
8162 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8164 !!priv->fdb_def_rule,
8168 tbl = flow_dv_tbl_resource_get(dev, table,
8170 attr->transfer, error);
8172 return rte_flow_error_set
8174 RTE_FLOW_ERROR_TYPE_ACTION,
8176 "cannot create jump action.");
8177 if (flow_dv_jump_tbl_resource_register
8178 (dev, tbl, dev_flow, error)) {
8179 flow_dv_tbl_resource_release(dev, tbl);
8180 return rte_flow_error_set
8182 RTE_FLOW_ERROR_TYPE_ACTION,
8184 "cannot create jump action.");
8186 dev_flow->dv.actions[actions_n++] =
8187 dev_flow->dv.jump->action;
8188 action_flags |= MLX5_FLOW_ACTION_JUMP;
8189 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8191 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8192 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8193 if (flow_dv_convert_action_modify_mac
8194 (mhdr_res, actions, error))
8196 action_flags |= actions->type ==
8197 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8198 MLX5_FLOW_ACTION_SET_MAC_SRC :
8199 MLX5_FLOW_ACTION_SET_MAC_DST;
8201 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8202 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8203 if (flow_dv_convert_action_modify_ipv4
8204 (mhdr_res, actions, error))
8206 action_flags |= actions->type ==
8207 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8208 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8209 MLX5_FLOW_ACTION_SET_IPV4_DST;
8211 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8212 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8213 if (flow_dv_convert_action_modify_ipv6
8214 (mhdr_res, actions, error))
8216 action_flags |= actions->type ==
8217 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8218 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8219 MLX5_FLOW_ACTION_SET_IPV6_DST;
8221 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8222 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8223 if (flow_dv_convert_action_modify_tp
8224 (mhdr_res, actions, items,
8225 &flow_attr, dev_flow, !!(action_flags &
8226 MLX5_FLOW_ACTION_DECAP), error))
8228 action_flags |= actions->type ==
8229 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8230 MLX5_FLOW_ACTION_SET_TP_SRC :
8231 MLX5_FLOW_ACTION_SET_TP_DST;
8233 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8234 if (flow_dv_convert_action_modify_dec_ttl
8235 (mhdr_res, items, &flow_attr, dev_flow,
8237 MLX5_FLOW_ACTION_DECAP), error))
8239 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8241 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8242 if (flow_dv_convert_action_modify_ttl
8243 (mhdr_res, actions, items, &flow_attr,
8244 dev_flow, !!(action_flags &
8245 MLX5_FLOW_ACTION_DECAP), error))
8247 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8249 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8250 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8251 if (flow_dv_convert_action_modify_tcp_seq
8252 (mhdr_res, actions, error))
8254 action_flags |= actions->type ==
8255 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8256 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8257 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8260 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8261 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8262 if (flow_dv_convert_action_modify_tcp_ack
8263 (mhdr_res, actions, error))
8265 action_flags |= actions->type ==
8266 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8267 MLX5_FLOW_ACTION_INC_TCP_ACK :
8268 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8270 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8271 if (flow_dv_convert_action_set_reg
8272 (mhdr_res, actions, error))
8274 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8276 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8277 if (flow_dv_convert_action_copy_mreg
8278 (dev, mhdr_res, actions, error))
8280 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8282 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8283 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8284 dev_flow->handle->fate_action =
8285 MLX5_FLOW_FATE_DEFAULT_MISS;
8287 case RTE_FLOW_ACTION_TYPE_METER:
8288 mtr = actions->conf;
8290 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8293 return rte_flow_error_set(error,
8295 RTE_FLOW_ERROR_TYPE_ACTION,
8298 "or invalid parameters");
8299 flow->meter = fm->idx;
8301 /* Set the meter action. */
8303 fm = mlx5_ipool_get(priv->sh->ipool
8304 [MLX5_IPOOL_MTR], flow->meter);
8306 return rte_flow_error_set(error,
8308 RTE_FLOW_ERROR_TYPE_ACTION,
8311 "or invalid parameters");
8313 dev_flow->dv.actions[actions_n++] =
8314 fm->mfts->meter_action;
8315 action_flags |= MLX5_FLOW_ACTION_METER;
8317 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8318 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8321 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8323 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8324 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8327 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8329 case RTE_FLOW_ACTION_TYPE_END:
8331 if (mhdr_res->actions_num) {
8332 /* create modify action if needed. */
8333 if (flow_dv_modify_hdr_resource_register
8334 (dev, mhdr_res, dev_flow, error))
8336 dev_flow->dv.actions[modify_action_position] =
8337 handle->dvh.modify_hdr->action;
8339 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8341 flow_dv_translate_create_counter(dev,
8342 dev_flow, count, age);
8345 return rte_flow_error_set
8347 RTE_FLOW_ERROR_TYPE_ACTION,
8349 "cannot create counter"
8351 dev_flow->dv.actions[actions_n++] =
8352 (flow_dv_counter_get_by_idx(dev,
8353 flow->counter, NULL))->action;
8359 if (mhdr_res->actions_num &&
8360 modify_action_position == UINT32_MAX)
8361 modify_action_position = actions_n++;
8363 dev_flow->dv.actions_n = actions_n;
8364 dev_flow->act_flags = action_flags;
8365 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8366 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8367 int item_type = items->type;
8369 if (!mlx5_flow_os_item_supported(item_type))
8370 return rte_flow_error_set(error, ENOTSUP,
8371 RTE_FLOW_ERROR_TYPE_ITEM,
8372 NULL, "item not supported");
8373 switch (item_type) {
8374 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8375 flow_dv_translate_item_port_id(dev, match_mask,
8376 match_value, items);
8377 last_item = MLX5_FLOW_ITEM_PORT_ID;
8379 case RTE_FLOW_ITEM_TYPE_ETH:
8380 flow_dv_translate_item_eth(match_mask, match_value,
8382 dev_flow->dv.group);
8383 matcher.priority = action_flags &
8384 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8385 !dev_flow->external ?
8386 MLX5_PRIORITY_MAP_L3 :
8387 MLX5_PRIORITY_MAP_L2;
8388 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8389 MLX5_FLOW_LAYER_OUTER_L2;
8391 case RTE_FLOW_ITEM_TYPE_VLAN:
8392 flow_dv_translate_item_vlan(dev_flow,
8393 match_mask, match_value,
8395 dev_flow->dv.group);
8396 matcher.priority = MLX5_PRIORITY_MAP_L2;
8397 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8398 MLX5_FLOW_LAYER_INNER_VLAN) :
8399 (MLX5_FLOW_LAYER_OUTER_L2 |
8400 MLX5_FLOW_LAYER_OUTER_VLAN);
8402 case RTE_FLOW_ITEM_TYPE_IPV4:
8403 mlx5_flow_tunnel_ip_check(items, next_protocol,
8404 &item_flags, &tunnel);
8405 flow_dv_translate_item_ipv4(match_mask, match_value,
8406 items, item_flags, tunnel,
8407 dev_flow->dv.group);
8408 matcher.priority = MLX5_PRIORITY_MAP_L3;
8409 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8410 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8411 if (items->mask != NULL &&
8412 ((const struct rte_flow_item_ipv4 *)
8413 items->mask)->hdr.next_proto_id) {
8415 ((const struct rte_flow_item_ipv4 *)
8416 (items->spec))->hdr.next_proto_id;
8418 ((const struct rte_flow_item_ipv4 *)
8419 (items->mask))->hdr.next_proto_id;
8421 /* Reset for inner layer. */
8422 next_protocol = 0xff;
8425 case RTE_FLOW_ITEM_TYPE_IPV6:
8426 mlx5_flow_tunnel_ip_check(items, next_protocol,
8427 &item_flags, &tunnel);
8428 flow_dv_translate_item_ipv6(match_mask, match_value,
8429 items, item_flags, tunnel,
8430 dev_flow->dv.group);
8431 matcher.priority = MLX5_PRIORITY_MAP_L3;
8432 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8433 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8434 if (items->mask != NULL &&
8435 ((const struct rte_flow_item_ipv6 *)
8436 items->mask)->hdr.proto) {
8438 ((const struct rte_flow_item_ipv6 *)
8439 items->spec)->hdr.proto;
8441 ((const struct rte_flow_item_ipv6 *)
8442 items->mask)->hdr.proto;
8444 /* Reset for inner layer. */
8445 next_protocol = 0xff;
8448 case RTE_FLOW_ITEM_TYPE_TCP:
8449 flow_dv_translate_item_tcp(match_mask, match_value,
8451 matcher.priority = MLX5_PRIORITY_MAP_L4;
8452 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8453 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8455 case RTE_FLOW_ITEM_TYPE_UDP:
8456 flow_dv_translate_item_udp(match_mask, match_value,
8458 matcher.priority = MLX5_PRIORITY_MAP_L4;
8459 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8460 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8462 case RTE_FLOW_ITEM_TYPE_GRE:
8463 flow_dv_translate_item_gre(match_mask, match_value,
8465 matcher.priority = rss_desc->level >= 2 ?
8466 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8467 last_item = MLX5_FLOW_LAYER_GRE;
8469 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8470 flow_dv_translate_item_gre_key(match_mask,
8471 match_value, items);
8472 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8474 case RTE_FLOW_ITEM_TYPE_NVGRE:
8475 flow_dv_translate_item_nvgre(match_mask, match_value,
8477 matcher.priority = rss_desc->level >= 2 ?
8478 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8479 last_item = MLX5_FLOW_LAYER_GRE;
8481 case RTE_FLOW_ITEM_TYPE_VXLAN:
8482 flow_dv_translate_item_vxlan(match_mask, match_value,
8484 matcher.priority = rss_desc->level >= 2 ?
8485 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8486 last_item = MLX5_FLOW_LAYER_VXLAN;
8488 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8489 flow_dv_translate_item_vxlan_gpe(match_mask,
8492 matcher.priority = rss_desc->level >= 2 ?
8493 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8494 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8496 case RTE_FLOW_ITEM_TYPE_GENEVE:
8497 flow_dv_translate_item_geneve(match_mask, match_value,
8499 matcher.priority = rss_desc->level >= 2 ?
8500 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8501 last_item = MLX5_FLOW_LAYER_GENEVE;
8503 case RTE_FLOW_ITEM_TYPE_MPLS:
8504 flow_dv_translate_item_mpls(match_mask, match_value,
8505 items, last_item, tunnel);
8506 matcher.priority = rss_desc->level >= 2 ?
8507 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8508 last_item = MLX5_FLOW_LAYER_MPLS;
8510 case RTE_FLOW_ITEM_TYPE_MARK:
8511 flow_dv_translate_item_mark(dev, match_mask,
8512 match_value, items);
8513 last_item = MLX5_FLOW_ITEM_MARK;
8515 case RTE_FLOW_ITEM_TYPE_META:
8516 flow_dv_translate_item_meta(dev, match_mask,
8517 match_value, attr, items);
8518 last_item = MLX5_FLOW_ITEM_METADATA;
8520 case RTE_FLOW_ITEM_TYPE_ICMP:
8521 flow_dv_translate_item_icmp(match_mask, match_value,
8523 last_item = MLX5_FLOW_LAYER_ICMP;
8525 case RTE_FLOW_ITEM_TYPE_ICMP6:
8526 flow_dv_translate_item_icmp6(match_mask, match_value,
8528 last_item = MLX5_FLOW_LAYER_ICMP6;
8530 case RTE_FLOW_ITEM_TYPE_TAG:
8531 flow_dv_translate_item_tag(dev, match_mask,
8532 match_value, items);
8533 last_item = MLX5_FLOW_ITEM_TAG;
8535 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8536 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8537 match_value, items);
8538 last_item = MLX5_FLOW_ITEM_TAG;
8540 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8541 flow_dv_translate_item_tx_queue(dev, match_mask,
8544 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8546 case RTE_FLOW_ITEM_TYPE_GTP:
8547 flow_dv_translate_item_gtp(match_mask, match_value,
8549 matcher.priority = rss_desc->level >= 2 ?
8550 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8551 last_item = MLX5_FLOW_LAYER_GTP;
8556 item_flags |= last_item;
8559 * When E-Switch mode is enabled, we have two cases where we need to
8560 * set the source port manually.
8561 * The first one, is in case of Nic steering rule, and the second is
8562 * E-Switch rule where no port_id item was found. In both cases
8563 * the source port is set according the current port in use.
8565 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8566 (priv->representor || priv->master)) {
8567 if (flow_dv_translate_item_port_id(dev, match_mask,
8571 #ifdef RTE_LIBRTE_MLX5_DEBUG
8572 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8573 dev_flow->dv.value.buf));
8576 * Layers may be already initialized from prefix flow if this dev_flow
8577 * is the suffix flow.
8579 handle->layers |= item_flags;
8580 if (action_flags & MLX5_FLOW_ACTION_RSS)
8581 flow_dv_hashfields_set(dev_flow, rss_desc);
8582 /* Register matcher. */
8583 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8585 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8587 /* reserved field no needs to be set to 0 here. */
8588 tbl_key.domain = attr->transfer;
8589 tbl_key.direction = attr->egress;
8590 tbl_key.table_id = dev_flow->dv.group;
8591 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8597 * Apply the flow to the NIC, lock free,
8598 * (mutex should be acquired by caller).
8601 * Pointer to the Ethernet device structure.
8602 * @param[in, out] flow
8603 * Pointer to flow structure.
8605 * Pointer to error structure.
8608 * 0 on success, a negative errno value otherwise and rte_errno is set.
8611 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8612 struct rte_flow_error *error)
8614 struct mlx5_flow_dv_workspace *dv;
8615 struct mlx5_flow_handle *dh;
8616 struct mlx5_flow_handle_dv *dv_h;
8617 struct mlx5_flow *dev_flow;
8618 struct mlx5_priv *priv = dev->data->dev_private;
8619 uint32_t handle_idx;
8624 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8625 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8627 dh = dev_flow->handle;
8630 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8632 dv->actions[n++] = priv->sh->esw_drop_action;
8634 struct mlx5_hrxq *drop_hrxq;
8635 drop_hrxq = mlx5_hrxq_drop_new(dev);
8639 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8641 "cannot get drop hash queue");
8645 * Drop queues will be released by the specify
8646 * mlx5_hrxq_drop_release() function. Assign
8647 * the special index to hrxq to mark the queue
8648 * has been allocated.
8650 dh->rix_hrxq = UINT32_MAX;
8651 dv->actions[n++] = drop_hrxq->action;
8653 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8654 struct mlx5_hrxq *hrxq;
8656 struct mlx5_flow_rss_desc *rss_desc =
8657 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8658 [!!priv->flow_nested_idx];
8660 MLX5_ASSERT(rss_desc->queue_num);
8661 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8662 MLX5_RSS_HASH_KEY_LEN,
8663 dev_flow->hash_fields,
8665 rss_desc->queue_num);
8667 hrxq_idx = mlx5_hrxq_new
8668 (dev, rss_desc->key,
8669 MLX5_RSS_HASH_KEY_LEN,
8670 dev_flow->hash_fields,
8672 rss_desc->queue_num,
8674 MLX5_FLOW_LAYER_TUNNEL));
8676 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8681 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8682 "cannot get hash queue");
8685 dh->rix_hrxq = hrxq_idx;
8686 dv->actions[n++] = hrxq->action;
8687 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8688 if (flow_dv_default_miss_resource_register
8692 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8693 "cannot create default miss resource");
8694 goto error_default_miss;
8696 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8697 dv->actions[n++] = priv->sh->default_miss.action;
8699 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8700 (void *)&dv->value, n,
8701 dv->actions, &dh->drv_flow);
8703 rte_flow_error_set(error, errno,
8704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8706 "hardware refuses to create flow");
8709 if (priv->vmwa_context &&
8710 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8712 * The rule contains the VLAN pattern.
8713 * For VF we are going to create VLAN
8714 * interface to make hypervisor set correct
8715 * e-Switch vport context.
8717 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8722 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8723 flow_dv_default_miss_resource_release(dev);
8725 err = rte_errno; /* Save rte_errno before cleanup. */
8726 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8727 handle_idx, dh, next) {
8728 /* hrxq is union, don't clear it if the flag is not set. */
8730 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8731 mlx5_hrxq_drop_release(dev);
8733 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8734 mlx5_hrxq_release(dev, dh->rix_hrxq);
8738 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8739 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8741 rte_errno = err; /* Restore rte_errno. */
8746 * Release the flow matcher.
8749 * Pointer to Ethernet device.
8751 * Pointer to mlx5_flow_handle.
8754 * 1 while a reference on it exists, 0 when freed.
8757 flow_dv_matcher_release(struct rte_eth_dev *dev,
8758 struct mlx5_flow_handle *handle)
8760 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8762 MLX5_ASSERT(matcher->matcher_object);
8763 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8764 dev->data->port_id, (void *)matcher,
8765 rte_atomic32_read(&matcher->refcnt));
8766 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8767 claim_zero(mlx5_flow_os_destroy_flow_matcher
8768 (matcher->matcher_object));
8769 LIST_REMOVE(matcher, next);
8770 /* table ref-- in release interface. */
8771 flow_dv_tbl_resource_release(dev, matcher->tbl);
8773 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8774 dev->data->port_id, (void *)matcher);
8781 * Release an encap/decap resource.
8784 * Pointer to Ethernet device.
8786 * Pointer to mlx5_flow_handle.
8789 * 1 while a reference on it exists, 0 when freed.
8792 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8793 struct mlx5_flow_handle *handle)
8795 struct mlx5_priv *priv = dev->data->dev_private;
8796 uint32_t idx = handle->dvh.rix_encap_decap;
8797 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8799 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8801 if (!cache_resource)
8803 MLX5_ASSERT(cache_resource->action);
8804 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8805 (void *)cache_resource,
8806 rte_atomic32_read(&cache_resource->refcnt));
8807 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8808 claim_zero(mlx5_flow_os_destroy_flow_action
8809 (cache_resource->action));
8810 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8811 &priv->sh->encaps_decaps, idx,
8812 cache_resource, next);
8813 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8814 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8815 (void *)cache_resource);
8822 * Release an jump to table action resource.
8825 * Pointer to Ethernet device.
8827 * Pointer to mlx5_flow_handle.
8830 * 1 while a reference on it exists, 0 when freed.
8833 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8834 struct mlx5_flow_handle *handle)
8836 struct mlx5_priv *priv = dev->data->dev_private;
8837 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8838 struct mlx5_flow_tbl_data_entry *tbl_data;
8840 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8844 cache_resource = &tbl_data->jump;
8845 MLX5_ASSERT(cache_resource->action);
8846 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8847 (void *)cache_resource,
8848 rte_atomic32_read(&cache_resource->refcnt));
8849 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8850 claim_zero(mlx5_flow_os_destroy_flow_action
8851 (cache_resource->action));
8852 /* jump action memory free is inside the table release. */
8853 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8854 DRV_LOG(DEBUG, "jump table resource %p: removed",
8855 (void *)cache_resource);
8862 * Release a default miss resource.
8865 * Pointer to Ethernet device.
8867 * 1 while a reference on it exists, 0 when freed.
8870 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
8872 struct mlx5_priv *priv = dev->data->dev_private;
8873 struct mlx5_dev_ctx_shared *sh = priv->sh;
8874 struct mlx5_flow_default_miss_resource *cache_resource =
8877 MLX5_ASSERT(cache_resource->action);
8878 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
8879 (void *)cache_resource->action,
8880 rte_atomic32_read(&cache_resource->refcnt));
8881 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8882 claim_zero(mlx5_glue->destroy_flow_action
8883 (cache_resource->action));
8884 DRV_LOG(DEBUG, "default miss resource %p: removed",
8885 (void *)cache_resource->action);
8892 * Release a modify-header resource.
8895 * Pointer to mlx5_flow_handle.
8898 * 1 while a reference on it exists, 0 when freed.
8901 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8903 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8904 handle->dvh.modify_hdr;
8906 MLX5_ASSERT(cache_resource->action);
8907 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8908 (void *)cache_resource,
8909 rte_atomic32_read(&cache_resource->refcnt));
8910 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8911 claim_zero(mlx5_flow_os_destroy_flow_action
8912 (cache_resource->action));
8913 LIST_REMOVE(cache_resource, next);
8914 rte_free(cache_resource);
8915 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8916 (void *)cache_resource);
8923 * Release port ID action resource.
8926 * Pointer to Ethernet device.
8928 * Pointer to mlx5_flow_handle.
8931 * 1 while a reference on it exists, 0 when freed.
8934 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8935 struct mlx5_flow_handle *handle)
8937 struct mlx5_priv *priv = dev->data->dev_private;
8938 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8939 uint32_t idx = handle->rix_port_id_action;
8941 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8943 if (!cache_resource)
8945 MLX5_ASSERT(cache_resource->action);
8946 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8947 (void *)cache_resource,
8948 rte_atomic32_read(&cache_resource->refcnt));
8949 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8950 claim_zero(mlx5_flow_os_destroy_flow_action
8951 (cache_resource->action));
8952 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8953 &priv->sh->port_id_action_list, idx,
8954 cache_resource, next);
8955 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8956 DRV_LOG(DEBUG, "port id action resource %p: removed",
8957 (void *)cache_resource);
8964 * Release push vlan action resource.
8967 * Pointer to Ethernet device.
8969 * Pointer to mlx5_flow_handle.
8972 * 1 while a reference on it exists, 0 when freed.
8975 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8976 struct mlx5_flow_handle *handle)
8978 struct mlx5_priv *priv = dev->data->dev_private;
8979 uint32_t idx = handle->dvh.rix_push_vlan;
8980 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8982 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8984 if (!cache_resource)
8986 MLX5_ASSERT(cache_resource->action);
8987 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8988 (void *)cache_resource,
8989 rte_atomic32_read(&cache_resource->refcnt));
8990 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8991 claim_zero(mlx5_flow_os_destroy_flow_action
8992 (cache_resource->action));
8993 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8994 &priv->sh->push_vlan_action_list, idx,
8995 cache_resource, next);
8996 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8997 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8998 (void *)cache_resource);
9005 * Release the fate resource.
9008 * Pointer to Ethernet device.
9010 * Pointer to mlx5_flow_handle.
9013 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9014 struct mlx5_flow_handle *handle)
9016 if (!handle->rix_fate)
9018 switch (handle->fate_action) {
9019 case MLX5_FLOW_FATE_DROP:
9020 mlx5_hrxq_drop_release(dev);
9022 case MLX5_FLOW_FATE_QUEUE:
9023 mlx5_hrxq_release(dev, handle->rix_hrxq);
9025 case MLX5_FLOW_FATE_JUMP:
9026 flow_dv_jump_tbl_resource_release(dev, handle);
9028 case MLX5_FLOW_FATE_PORT_ID:
9029 flow_dv_port_id_action_resource_release(dev, handle);
9031 case MLX5_FLOW_FATE_DEFAULT_MISS:
9032 flow_dv_default_miss_resource_release(dev);
9035 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9038 handle->rix_fate = 0;
9042 * Remove the flow from the NIC but keeps it in memory.
9043 * Lock free, (mutex should be acquired by caller).
9046 * Pointer to Ethernet device.
9047 * @param[in, out] flow
9048 * Pointer to flow structure.
9051 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9053 struct mlx5_flow_handle *dh;
9054 uint32_t handle_idx;
9055 struct mlx5_priv *priv = dev->data->dev_private;
9059 handle_idx = flow->dev_handles;
9060 while (handle_idx) {
9061 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9066 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9067 dh->drv_flow = NULL;
9069 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9070 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9071 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9072 flow_dv_fate_resource_release(dev, dh);
9073 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9074 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9075 handle_idx = dh->next.next;
9080 * Remove the flow from the NIC and the memory.
9081 * Lock free, (mutex should be acquired by caller).
9084 * Pointer to the Ethernet device structure.
9085 * @param[in, out] flow
9086 * Pointer to flow structure.
9089 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9091 struct mlx5_flow_handle *dev_handle;
9092 struct mlx5_priv *priv = dev->data->dev_private;
9096 __flow_dv_remove(dev, flow);
9097 if (flow->counter) {
9098 flow_dv_counter_release(dev, flow->counter);
9102 struct mlx5_flow_meter *fm;
9104 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9107 mlx5_flow_meter_detach(fm);
9110 while (flow->dev_handles) {
9111 uint32_t tmp_idx = flow->dev_handles;
9113 dev_handle = mlx5_ipool_get(priv->sh->ipool
9114 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9117 flow->dev_handles = dev_handle->next.next;
9118 if (dev_handle->dvh.matcher)
9119 flow_dv_matcher_release(dev, dev_handle);
9120 if (dev_handle->dvh.rix_encap_decap)
9121 flow_dv_encap_decap_resource_release(dev, dev_handle);
9122 if (dev_handle->dvh.modify_hdr)
9123 flow_dv_modify_hdr_resource_release(dev_handle);
9124 if (dev_handle->dvh.rix_push_vlan)
9125 flow_dv_push_vlan_action_resource_release(dev,
9127 if (dev_handle->dvh.rix_tag)
9128 flow_dv_tag_release(dev,
9129 dev_handle->dvh.rix_tag);
9130 flow_dv_fate_resource_release(dev, dev_handle);
9131 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9137 * Query a dv flow rule for its statistics via devx.
9140 * Pointer to Ethernet device.
9142 * Pointer to the sub flow.
9144 * data retrieved by the query.
9146 * Perform verbose error reporting if not NULL.
9149 * 0 on success, a negative errno value otherwise and rte_errno is set.
9152 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9153 void *data, struct rte_flow_error *error)
9155 struct mlx5_priv *priv = dev->data->dev_private;
9156 struct rte_flow_query_count *qc = data;
9158 if (!priv->config.devx)
9159 return rte_flow_error_set(error, ENOTSUP,
9160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9162 "counters are not supported");
9163 if (flow->counter) {
9164 uint64_t pkts, bytes;
9165 struct mlx5_flow_counter *cnt;
9167 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9169 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9173 return rte_flow_error_set(error, -err,
9174 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9175 NULL, "cannot read counters");
9178 qc->hits = pkts - cnt->hits;
9179 qc->bytes = bytes - cnt->bytes;
9186 return rte_flow_error_set(error, EINVAL,
9187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9189 "counters are not available");
9195 * @see rte_flow_query()
9199 flow_dv_query(struct rte_eth_dev *dev,
9200 struct rte_flow *flow __rte_unused,
9201 const struct rte_flow_action *actions __rte_unused,
9202 void *data __rte_unused,
9203 struct rte_flow_error *error __rte_unused)
9207 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9208 switch (actions->type) {
9209 case RTE_FLOW_ACTION_TYPE_VOID:
9211 case RTE_FLOW_ACTION_TYPE_COUNT:
9212 ret = flow_dv_query_count(dev, flow, data, error);
9215 return rte_flow_error_set(error, ENOTSUP,
9216 RTE_FLOW_ERROR_TYPE_ACTION,
9218 "action not supported");
9225 * Destroy the meter table set.
9226 * Lock free, (mutex should be acquired by caller).
9229 * Pointer to Ethernet device.
9231 * Pointer to the meter table set.
9237 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9238 struct mlx5_meter_domains_infos *tbl)
9240 struct mlx5_priv *priv = dev->data->dev_private;
9241 struct mlx5_meter_domains_infos *mtd =
9242 (struct mlx5_meter_domains_infos *)tbl;
9244 if (!mtd || !priv->config.dv_flow_en)
9246 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9247 claim_zero(mlx5_flow_os_destroy_flow
9248 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9249 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9250 claim_zero(mlx5_flow_os_destroy_flow
9251 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9252 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9253 claim_zero(mlx5_flow_os_destroy_flow
9254 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9255 if (mtd->egress.color_matcher)
9256 claim_zero(mlx5_flow_os_destroy_flow_matcher
9257 (mtd->egress.color_matcher));
9258 if (mtd->egress.any_matcher)
9259 claim_zero(mlx5_flow_os_destroy_flow_matcher
9260 (mtd->egress.any_matcher));
9261 if (mtd->egress.tbl)
9262 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9263 if (mtd->egress.sfx_tbl)
9264 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9265 if (mtd->ingress.color_matcher)
9266 claim_zero(mlx5_flow_os_destroy_flow_matcher
9267 (mtd->ingress.color_matcher));
9268 if (mtd->ingress.any_matcher)
9269 claim_zero(mlx5_flow_os_destroy_flow_matcher
9270 (mtd->ingress.any_matcher));
9271 if (mtd->ingress.tbl)
9272 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9273 if (mtd->ingress.sfx_tbl)
9274 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9275 if (mtd->transfer.color_matcher)
9276 claim_zero(mlx5_flow_os_destroy_flow_matcher
9277 (mtd->transfer.color_matcher));
9278 if (mtd->transfer.any_matcher)
9279 claim_zero(mlx5_flow_os_destroy_flow_matcher
9280 (mtd->transfer.any_matcher));
9281 if (mtd->transfer.tbl)
9282 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9283 if (mtd->transfer.sfx_tbl)
9284 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9286 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9291 /* Number of meter flow actions, count and jump or count and drop. */
9292 #define METER_ACTIONS 2
9295 * Create specify domain meter table and suffix table.
9298 * Pointer to Ethernet device.
9299 * @param[in,out] mtb
9300 * Pointer to DV meter table set.
9303 * @param[in] transfer
9305 * @param[in] color_reg_c_idx
9306 * Reg C index for color match.
9309 * 0 on success, -1 otherwise and rte_errno is set.
9312 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9313 struct mlx5_meter_domains_infos *mtb,
9314 uint8_t egress, uint8_t transfer,
9315 uint32_t color_reg_c_idx)
9317 struct mlx5_priv *priv = dev->data->dev_private;
9318 struct mlx5_dev_ctx_shared *sh = priv->sh;
9319 struct mlx5_flow_dv_match_params mask = {
9320 .size = sizeof(mask.buf),
9322 struct mlx5_flow_dv_match_params value = {
9323 .size = sizeof(value.buf),
9325 struct mlx5dv_flow_matcher_attr dv_attr = {
9326 .type = IBV_FLOW_ATTR_NORMAL,
9328 .match_criteria_enable = 0,
9329 .match_mask = (void *)&mask,
9331 void *actions[METER_ACTIONS];
9332 struct mlx5_meter_domain_info *dtb;
9333 struct rte_flow_error error;
9338 dtb = &mtb->transfer;
9342 dtb = &mtb->ingress;
9343 /* Create the meter table with METER level. */
9344 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9345 egress, transfer, &error);
9347 DRV_LOG(ERR, "Failed to create meter policer table.");
9350 /* Create the meter suffix table with SUFFIX level. */
9351 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9352 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9353 egress, transfer, &error);
9354 if (!dtb->sfx_tbl) {
9355 DRV_LOG(ERR, "Failed to create meter suffix table.");
9358 /* Create matchers, Any and Color. */
9359 dv_attr.priority = 3;
9360 dv_attr.match_criteria_enable = 0;
9361 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9364 DRV_LOG(ERR, "Failed to create meter"
9365 " policer default matcher.");
9368 dv_attr.priority = 0;
9369 dv_attr.match_criteria_enable =
9370 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9371 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9372 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9373 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9374 &dtb->color_matcher);
9376 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9379 if (mtb->count_actns[RTE_MTR_DROPPED])
9380 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9381 actions[i++] = mtb->drop_actn;
9382 /* Default rule: lowest priority, match any, actions: drop. */
9383 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9385 &dtb->policer_rules[RTE_MTR_DROPPED]);
9387 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9396 * Create the needed meter and suffix tables.
9397 * Lock free, (mutex should be acquired by caller).
9400 * Pointer to Ethernet device.
9402 * Pointer to the flow meter.
9405 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9407 static struct mlx5_meter_domains_infos *
9408 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9409 const struct mlx5_flow_meter *fm)
9411 struct mlx5_priv *priv = dev->data->dev_private;
9412 struct mlx5_meter_domains_infos *mtb;
9416 if (!priv->mtr_en) {
9417 rte_errno = ENOTSUP;
9420 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9422 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9425 /* Create meter count actions */
9426 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9427 struct mlx5_flow_counter *cnt;
9428 if (!fm->policer_stats.cnt[i])
9430 cnt = flow_dv_counter_get_by_idx(dev,
9431 fm->policer_stats.cnt[i], NULL);
9432 mtb->count_actns[i] = cnt->action;
9434 /* Create drop action. */
9435 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9437 DRV_LOG(ERR, "Failed to create drop action.");
9440 /* Egress meter table. */
9441 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9443 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9446 /* Ingress meter table. */
9447 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9449 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9452 /* FDB meter table. */
9453 if (priv->config.dv_esw_en) {
9454 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9455 priv->mtr_color_reg);
9457 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9463 flow_dv_destroy_mtr_tbl(dev, mtb);
9468 * Destroy domain policer rule.
9471 * Pointer to domain table.
9474 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9478 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9479 if (dt->policer_rules[i]) {
9480 claim_zero(mlx5_flow_os_destroy_flow
9481 (dt->policer_rules[i]));
9482 dt->policer_rules[i] = NULL;
9485 if (dt->jump_actn) {
9486 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9487 dt->jump_actn = NULL;
9492 * Destroy policer rules.
9495 * Pointer to Ethernet device.
9497 * Pointer to flow meter structure.
9499 * Pointer to flow attributes.
9505 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9506 const struct mlx5_flow_meter *fm,
9507 const struct rte_flow_attr *attr)
9509 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9514 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9516 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9518 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9523 * Create specify domain meter policer rule.
9526 * Pointer to flow meter structure.
9528 * Pointer to DV meter table set.
9529 * @param[in] mtr_reg_c
9530 * Color match REG_C.
9533 * 0 on success, -1 otherwise.
9536 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9537 struct mlx5_meter_domain_info *dtb,
9540 struct mlx5_flow_dv_match_params matcher = {
9541 .size = sizeof(matcher.buf),
9543 struct mlx5_flow_dv_match_params value = {
9544 .size = sizeof(value.buf),
9546 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9547 void *actions[METER_ACTIONS];
9551 /* Create jump action. */
9552 if (!dtb->jump_actn)
9553 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9554 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9556 DRV_LOG(ERR, "Failed to create policer jump action.");
9559 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9562 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9563 rte_col_2_mlx5_col(i), UINT8_MAX);
9564 if (mtb->count_actns[i])
9565 actions[j++] = mtb->count_actns[i];
9566 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9567 actions[j++] = mtb->drop_actn;
9569 actions[j++] = dtb->jump_actn;
9570 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9571 (void *)&value, j, actions,
9572 &dtb->policer_rules[i]);
9574 DRV_LOG(ERR, "Failed to create policer rule.");
9585 * Create policer rules.
9588 * Pointer to Ethernet device.
9590 * Pointer to flow meter structure.
9592 * Pointer to flow attributes.
9595 * 0 on success, -1 otherwise.
9598 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9599 struct mlx5_flow_meter *fm,
9600 const struct rte_flow_attr *attr)
9602 struct mlx5_priv *priv = dev->data->dev_private;
9603 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9607 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9608 priv->mtr_color_reg);
9610 DRV_LOG(ERR, "Failed to create egress policer.");
9614 if (attr->ingress) {
9615 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9616 priv->mtr_color_reg);
9618 DRV_LOG(ERR, "Failed to create ingress policer.");
9622 if (attr->transfer) {
9623 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9624 priv->mtr_color_reg);
9626 DRV_LOG(ERR, "Failed to create transfer policer.");
9632 flow_dv_destroy_policer_rules(dev, fm, attr);
9637 * Query a devx counter.
9640 * Pointer to the Ethernet device structure.
9642 * Index to the flow counter.
9644 * Set to clear the counter statistics.
9646 * The statistics value of packets.
9648 * The statistics value of bytes.
9651 * 0 on success, otherwise return -1.
9654 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9655 uint64_t *pkts, uint64_t *bytes)
9657 struct mlx5_priv *priv = dev->data->dev_private;
9658 struct mlx5_flow_counter *cnt;
9659 uint64_t inn_pkts, inn_bytes;
9662 if (!priv->config.devx)
9665 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9668 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9669 *pkts = inn_pkts - cnt->hits;
9670 *bytes = inn_bytes - cnt->bytes;
9672 cnt->hits = inn_pkts;
9673 cnt->bytes = inn_bytes;
9679 * Get aged-out flows.
9682 * Pointer to the Ethernet device structure.
9683 * @param[in] context
9684 * The address of an array of pointers to the aged-out flows contexts.
9685 * @param[in] nb_contexts
9686 * The length of context array pointers.
9688 * Perform verbose error reporting if not NULL. Initialized in case of
9692 * how many contexts get in success, otherwise negative errno value.
9693 * if nb_contexts is 0, return the amount of all aged contexts.
9694 * if nb_contexts is not 0 , return the amount of aged flows reported
9695 * in the context array.
9696 * @note: only stub for now
9699 flow_get_aged_flows(struct rte_eth_dev *dev,
9701 uint32_t nb_contexts,
9702 struct rte_flow_error *error)
9704 struct mlx5_priv *priv = dev->data->dev_private;
9705 struct mlx5_age_info *age_info;
9706 struct mlx5_age_param *age_param;
9707 struct mlx5_flow_counter *counter;
9710 if (nb_contexts && !context)
9711 return rte_flow_error_set(error, EINVAL,
9712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9714 "Should assign at least one flow or"
9715 " context to get if nb_contexts != 0");
9716 age_info = GET_PORT_AGE_INFO(priv);
9717 rte_spinlock_lock(&age_info->aged_sl);
9718 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9721 age_param = MLX5_CNT_TO_AGE(counter);
9722 context[nb_flows - 1] = age_param->context;
9723 if (!(--nb_contexts))
9727 rte_spinlock_unlock(&age_info->aged_sl);
9728 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9733 * Mutex-protected thunk to lock-free __flow_dv_translate().
9736 flow_dv_translate(struct rte_eth_dev *dev,
9737 struct mlx5_flow *dev_flow,
9738 const struct rte_flow_attr *attr,
9739 const struct rte_flow_item items[],
9740 const struct rte_flow_action actions[],
9741 struct rte_flow_error *error)
9745 flow_dv_shared_lock(dev);
9746 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9747 flow_dv_shared_unlock(dev);
9752 * Mutex-protected thunk to lock-free __flow_dv_apply().
9755 flow_dv_apply(struct rte_eth_dev *dev,
9756 struct rte_flow *flow,
9757 struct rte_flow_error *error)
9761 flow_dv_shared_lock(dev);
9762 ret = __flow_dv_apply(dev, flow, error);
9763 flow_dv_shared_unlock(dev);
9768 * Mutex-protected thunk to lock-free __flow_dv_remove().
9771 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9773 flow_dv_shared_lock(dev);
9774 __flow_dv_remove(dev, flow);
9775 flow_dv_shared_unlock(dev);
9779 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9782 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9784 flow_dv_shared_lock(dev);
9785 __flow_dv_destroy(dev, flow);
9786 flow_dv_shared_unlock(dev);
9790 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9793 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9797 flow_dv_shared_lock(dev);
9798 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9799 flow_dv_shared_unlock(dev);
9804 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9807 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9809 flow_dv_shared_lock(dev);
9810 flow_dv_counter_release(dev, cnt);
9811 flow_dv_shared_unlock(dev);
9814 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9815 .validate = flow_dv_validate,
9816 .prepare = flow_dv_prepare,
9817 .translate = flow_dv_translate,
9818 .apply = flow_dv_apply,
9819 .remove = flow_dv_remove,
9820 .destroy = flow_dv_destroy,
9821 .query = flow_dv_query,
9822 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9823 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9824 .create_policer_rules = flow_dv_create_policer_rules,
9825 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9826 .counter_alloc = flow_dv_counter_allocate,
9827 .counter_free = flow_dv_counter_free,
9828 .counter_query = flow_dv_counter_query,
9829 .get_aged_flows = flow_get_aged_flows,
9832 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */