1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* Maximum number of packets a multi-packet WQE can handle. */
43 #define MLX5_MPW_DSEG_MAX 5
46 #define MLX5_WQE_DWORD_SIZE 16
49 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
51 /* Max size of a WQE session. */
52 #define MLX5_WQE_SIZE_MAX 960U
54 /* Compute the number of DS. */
55 #define MLX5_WQE_DS(n) \
56 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
58 /* Room for inline data in multi-packet WQE. */
59 #define MLX5_MWQE64_INL_DATA 28
61 /* Default minimum number of Tx queues for inlining packets. */
62 #define MLX5_EMPW_MIN_TXQS 8
64 /* Default max packet length to be inlined. */
65 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
68 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
69 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
71 /* CQE value to inform that VLAN is stripped. */
72 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
75 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
78 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
81 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
84 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
87 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
89 /* IP is fragmented. */
90 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
92 /* L2 header is valid. */
93 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
95 /* L3 header is valid. */
96 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
98 /* L4 header is valid. */
99 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
101 /* Outer packet, 0 IPv4, 1 IPv6. */
102 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
104 /* Tunnel packet bit in the CQE. */
105 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
107 /* Inner L3 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
110 /* Inner L4 checksum offload (Tunneled packets only). */
111 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
113 /* Outer L4 type is TCP. */
114 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
116 /* Outer L4 type is UDP. */
117 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
119 /* Outer L3 type is IPV4. */
120 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
122 /* Outer L3 type is IPV6. */
123 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
125 /* Inner L4 type is TCP. */
126 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
128 /* Inner L4 type is UDP. */
129 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
131 /* Inner L3 type is IPV4. */
132 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
134 /* Inner L3 type is IPV6. */
135 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
137 /* Is flow mark valid. */
138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
139 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
141 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
144 /* INVALID is used by packets matching no flow rules. */
145 #define MLX5_FLOW_MARK_INVALID 0
147 /* Maximum allowed value to mark a packet. */
148 #define MLX5_FLOW_MARK_MAX 0xfffff0
150 /* Default mark value used when none is provided. */
151 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
153 /* Maximum number of DS in WQE. */
154 #define MLX5_DSEG_MAX 63
156 /* Subset of struct mlx5_wqe_eth_seg. */
157 struct mlx5_wqe_eth_seg_small {
162 uint32_t flow_table_metadata;
163 uint16_t inline_hdr_sz;
164 uint8_t inline_hdr[2];
165 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
167 struct mlx5_wqe_inl_small {
170 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
172 struct mlx5_wqe_ctrl {
177 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
179 /* Small common part of the WQE. */
182 struct mlx5_wqe_eth_seg_small eseg;
185 /* Vectorize WQE header. */
195 } __rte_aligned(MLX5_WQE_SIZE);
201 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
204 /* MPW session status. */
205 enum mlx5_mpw_state {
206 MLX5_MPW_STATE_OPENED,
207 MLX5_MPW_INL_STATE_OPENED,
208 MLX5_MPW_ENHANCED_STATE_OPENED,
209 MLX5_MPW_STATE_CLOSED,
212 /* MPW session descriptor. */
214 enum mlx5_mpw_state state;
217 unsigned int total_len;
218 volatile struct mlx5_wqe *wqe;
220 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
221 volatile uint8_t *raw;
225 /* WQE for Multi-Packet RQ. */
226 struct mlx5_wqe_mprq {
227 struct mlx5_wqe_srq_next_seg next_seg;
228 struct mlx5_wqe_data_seg dseg;
231 #define MLX5_MPRQ_LEN_MASK 0x000ffff
232 #define MLX5_MPRQ_LEN_SHIFT 0
233 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
234 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
235 #define MLX5_MPRQ_FILLER_MASK 0x80000000
236 #define MLX5_MPRQ_FILLER_SHIFT 31
238 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
240 /* CQ element structure - should be equal to the cache line size */
242 #if (RTE_CACHE_LINE_SIZE == 128)
249 uint32_t rx_hash_res;
250 uint8_t rx_hash_type;
252 uint16_t hdr_type_etc;
257 uint32_t sop_drop_qpn;
258 uint16_t wqe_counter;
263 /* Adding direct verbs to data-path. */
265 /* CQ sequence number mask. */
266 #define MLX5_CQ_SQN_MASK 0x3
268 /* CQ sequence number index. */
269 #define MLX5_CQ_SQN_OFFSET 28
271 /* CQ doorbell index mask. */
272 #define MLX5_CI_MASK 0xffffff
274 /* CQ doorbell offset. */
275 #define MLX5_CQ_ARM_DB 1
277 /* CQ doorbell offset*/
278 #define MLX5_CQ_DOORBELL 0x20
280 /* CQE format value. */
281 #define MLX5_COMPRESSED 0x3
283 /* Write a specific data value to a field. */
284 #define MLX5_MODIFICATION_TYPE_SET 1
286 /* Add a specific data value to a field. */
287 #define MLX5_MODIFICATION_TYPE_ADD 2
289 /* The field of packet to be modified. */
290 enum mlx5_modification_field {
291 MLX5_MODI_OUT_SMAC_47_16 = 1,
292 MLX5_MODI_OUT_SMAC_15_0,
293 MLX5_MODI_OUT_ETHERTYPE,
294 MLX5_MODI_OUT_DMAC_47_16,
295 MLX5_MODI_OUT_DMAC_15_0,
296 MLX5_MODI_OUT_IP_DSCP,
297 MLX5_MODI_OUT_TCP_FLAGS,
298 MLX5_MODI_OUT_TCP_SPORT,
299 MLX5_MODI_OUT_TCP_DPORT,
300 MLX5_MODI_OUT_IPV4_TTL,
301 MLX5_MODI_OUT_UDP_SPORT,
302 MLX5_MODI_OUT_UDP_DPORT,
303 MLX5_MODI_OUT_SIPV6_127_96,
304 MLX5_MODI_OUT_SIPV6_95_64,
305 MLX5_MODI_OUT_SIPV6_63_32,
306 MLX5_MODI_OUT_SIPV6_31_0,
307 MLX5_MODI_OUT_DIPV6_127_96,
308 MLX5_MODI_OUT_DIPV6_95_64,
309 MLX5_MODI_OUT_DIPV6_63_32,
310 MLX5_MODI_OUT_DIPV6_31_0,
313 MLX5_MODI_IN_SMAC_47_16 = 0x31,
314 MLX5_MODI_IN_SMAC_15_0,
315 MLX5_MODI_IN_ETHERTYPE,
316 MLX5_MODI_IN_DMAC_47_16,
317 MLX5_MODI_IN_DMAC_15_0,
318 MLX5_MODI_IN_IP_DSCP,
319 MLX5_MODI_IN_TCP_FLAGS,
320 MLX5_MODI_IN_TCP_SPORT,
321 MLX5_MODI_IN_TCP_DPORT,
322 MLX5_MODI_IN_IPV4_TTL,
323 MLX5_MODI_IN_UDP_SPORT,
324 MLX5_MODI_IN_UDP_DPORT,
325 MLX5_MODI_IN_SIPV6_127_96,
326 MLX5_MODI_IN_SIPV6_95_64,
327 MLX5_MODI_IN_SIPV6_63_32,
328 MLX5_MODI_IN_SIPV6_31_0,
329 MLX5_MODI_IN_DIPV6_127_96,
330 MLX5_MODI_IN_DIPV6_95_64,
331 MLX5_MODI_IN_DIPV6_63_32,
332 MLX5_MODI_IN_DIPV6_31_0,
335 MLX5_MODI_OUT_IPV6_HOPLIMIT,
336 MLX5_MODI_IN_IPV6_HOPLIMIT,
337 MLX5_MODI_META_DATA_REG_A,
338 MLX5_MODI_META_DATA_REG_B = 0x50,
341 /* Modification sub command. */
342 struct mlx5_modification_cmd {
346 unsigned int length:5;
347 unsigned int rsvd0:3;
348 unsigned int offset:5;
349 unsigned int rsvd1:3;
350 unsigned int field:12;
351 unsigned int action_type:4;
360 typedef uint32_t u32;
361 typedef uint16_t u16;
364 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
365 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
366 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
367 (&(__mlx5_nullp(typ)->fld)))
368 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
369 (__mlx5_bit_off(typ, fld) & 0x1f))
370 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
371 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
372 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
373 __mlx5_dw_bit_off(typ, fld))
374 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
375 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
376 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
377 (__mlx5_bit_off(typ, fld) & 0xf))
378 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
379 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
380 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
381 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
382 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
384 /* insert a value to a struct */
385 #define MLX5_SET(typ, p, fld, v) \
388 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
389 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
390 __mlx5_dw_off(typ, fld))) & \
391 (~__mlx5_dw_mask(typ, fld))) | \
392 (((_v) & __mlx5_mask(typ, fld)) << \
393 __mlx5_dw_bit_off(typ, fld))); \
395 #define MLX5_GET(typ, p, fld) \
396 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
397 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
398 __mlx5_mask(typ, fld))
399 #define MLX5_GET16(typ, p, fld) \
400 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
401 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
402 __mlx5_mask16(typ, fld))
403 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
404 __mlx5_64_off(typ, fld)))
405 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
407 struct mlx5_ifc_fte_match_set_misc_bits {
408 u8 reserved_at_0[0x8];
410 u8 reserved_at_20[0x10];
411 u8 source_port[0x10];
412 u8 outer_second_prio[0x3];
413 u8 outer_second_cfi[0x1];
414 u8 outer_second_vid[0xc];
415 u8 inner_second_prio[0x3];
416 u8 inner_second_cfi[0x1];
417 u8 inner_second_vid[0xc];
418 u8 outer_second_cvlan_tag[0x1];
419 u8 inner_second_cvlan_tag[0x1];
420 u8 outer_second_svlan_tag[0x1];
421 u8 inner_second_svlan_tag[0x1];
422 u8 reserved_at_64[0xc];
423 u8 gre_protocol[0x10];
427 u8 reserved_at_b8[0x8];
428 u8 reserved_at_c0[0x20];
429 u8 reserved_at_e0[0xc];
430 u8 outer_ipv6_flow_label[0x14];
431 u8 reserved_at_100[0xc];
432 u8 inner_ipv6_flow_label[0x14];
433 u8 reserved_at_120[0xe0];
436 struct mlx5_ifc_ipv4_layout_bits {
437 u8 reserved_at_0[0x60];
441 struct mlx5_ifc_ipv6_layout_bits {
445 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
446 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
447 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
448 u8 reserved_at_0[0x80];
451 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
470 u8 reserved_at_c0[0x20];
473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
477 struct mlx5_ifc_fte_match_mpls_bits {
484 struct mlx5_ifc_fte_match_set_misc2_bits {
485 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
486 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
487 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
488 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
489 u8 reserved_at_80[0x100];
490 u8 metadata_reg_a[0x20];
491 u8 reserved_at_1a0[0x60];
494 struct mlx5_ifc_fte_match_set_misc3_bits {
495 u8 inner_tcp_seq_num[0x20];
496 u8 outer_tcp_seq_num[0x20];
497 u8 inner_tcp_ack_num[0x20];
498 u8 outer_tcp_ack_num[0x20];
499 u8 reserved_at_auto1[0x8];
500 u8 outer_vxlan_gpe_vni[0x18];
501 u8 outer_vxlan_gpe_next_protocol[0x8];
502 u8 outer_vxlan_gpe_flags[0x8];
503 u8 reserved_at_a8[0x10];
504 u8 icmp_header_data[0x20];
505 u8 icmpv6_header_data[0x20];
510 u8 reserved_at_1a0[0xe0];
514 struct mlx5_ifc_fte_match_param_bits {
515 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
516 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
517 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
518 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
519 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
523 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
524 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
525 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
526 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
527 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
531 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
532 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
533 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
537 struct mlx5_ifc_alloc_flow_counter_out_bits {
539 u8 reserved_at_8[0x18];
541 u8 flow_counter_id[0x20];
542 u8 reserved_at_60[0x20];
545 struct mlx5_ifc_alloc_flow_counter_in_bits {
547 u8 reserved_at_10[0x10];
548 u8 reserved_at_20[0x10];
550 u8 reserved_at_40[0x40];
553 struct mlx5_ifc_dealloc_flow_counter_out_bits {
555 u8 reserved_at_8[0x18];
557 u8 reserved_at_40[0x40];
560 struct mlx5_ifc_dealloc_flow_counter_in_bits {
562 u8 reserved_at_10[0x10];
563 u8 reserved_at_20[0x10];
565 u8 flow_counter_id[0x20];
566 u8 reserved_at_60[0x20];
569 struct mlx5_ifc_traffic_counter_bits {
574 struct mlx5_ifc_query_flow_counter_out_bits {
576 u8 reserved_at_8[0x18];
578 u8 reserved_at_40[0x40];
579 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
582 struct mlx5_ifc_query_flow_counter_in_bits {
584 u8 reserved_at_10[0x10];
585 u8 reserved_at_20[0x10];
587 u8 reserved_at_40[0x80];
589 u8 reserved_at_c1[0xf];
590 u8 num_of_counters[0x10];
591 u8 flow_counter_id[0x20];
595 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
596 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
600 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
601 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
604 struct mlx5_ifc_cmd_hca_cap_bits {
605 u8 reserved_at_0[0x30];
607 u8 reserved_at_40[0x40];
608 u8 log_max_srq_sz[0x8];
609 u8 log_max_qp_sz[0x8];
610 u8 reserved_at_90[0xb];
612 u8 reserved_at_a0[0xb];
614 u8 reserved_at_b0[0x10];
615 u8 reserved_at_c0[0x8];
616 u8 log_max_cq_sz[0x8];
617 u8 reserved_at_d0[0xb];
619 u8 log_max_eq_sz[0x8];
620 u8 reserved_at_e8[0x2];
621 u8 log_max_mkey[0x6];
622 u8 reserved_at_f0[0x8];
623 u8 dump_fill_mkey[0x1];
624 u8 reserved_at_f9[0x3];
626 u8 max_indirection[0x8];
627 u8 fixed_buffer_size[0x1];
628 u8 log_max_mrw_sz[0x7];
629 u8 force_teardown[0x1];
630 u8 reserved_at_111[0x1];
631 u8 log_max_bsf_list_size[0x6];
632 u8 umr_extended_translation_offset[0x1];
634 u8 log_max_klm_list_size[0x6];
635 u8 reserved_at_120[0xa];
636 u8 log_max_ra_req_dc[0x6];
637 u8 reserved_at_130[0xa];
638 u8 log_max_ra_res_dc[0x6];
639 u8 reserved_at_140[0xa];
640 u8 log_max_ra_req_qp[0x6];
641 u8 reserved_at_150[0xa];
642 u8 log_max_ra_res_qp[0x6];
644 u8 cc_query_allowed[0x1];
645 u8 cc_modify_allowed[0x1];
647 u8 cache_line_128byte[0x1];
648 u8 reserved_at_165[0xa];
650 u8 gid_table_size[0x10];
651 u8 out_of_seq_cnt[0x1];
652 u8 vport_counters[0x1];
653 u8 retransmission_q_counters[0x1];
655 u8 modify_rq_counter_set_id[0x1];
656 u8 rq_delay_drop[0x1];
658 u8 pkey_table_size[0x10];
659 u8 vport_group_manager[0x1];
660 u8 vhca_group_manager[0x1];
663 u8 vnic_env_queue_counters[0x1];
665 u8 nic_flow_table[0x1];
666 u8 eswitch_manager[0x1];
667 u8 device_memory[0x1];
670 u8 local_ca_ack_delay[0x5];
671 u8 port_module_event[0x1];
672 u8 enhanced_error_q_counters[0x1];
674 u8 reserved_at_1b3[0x1];
675 u8 disable_link_up[0x1];
679 u8 reserved_at_1c0[0x1];
683 u8 reserved_at_1c8[0x4];
685 u8 temp_warn_event[0x1];
687 u8 general_notification_event[0x1];
688 u8 reserved_at_1d3[0x2];
692 u8 reserved_at_1d8[0x1];
700 u8 stat_rate_support[0x10];
701 u8 reserved_at_1f0[0xc];
703 u8 compact_address_vector[0x1];
705 u8 reserved_at_202[0x1];
706 u8 ipoib_enhanced_offloads[0x1];
707 u8 ipoib_basic_offloads[0x1];
708 u8 reserved_at_205[0x1];
709 u8 repeated_block_disabled[0x1];
710 u8 umr_modify_entity_size_disabled[0x1];
711 u8 umr_modify_atomic_disabled[0x1];
712 u8 umr_indirect_mkey_disabled[0x1];
714 u8 reserved_at_20c[0x3];
715 u8 drain_sigerr[0x1];
716 u8 cmdif_checksum[0x2];
718 u8 reserved_at_213[0x1];
719 u8 wq_signature[0x1];
720 u8 sctr_data_cqe[0x1];
721 u8 reserved_at_216[0x1];
727 u8 eth_net_offloads[0x1];
730 u8 reserved_at_21f[0x1];
733 u8 cq_moderation[0x1];
734 u8 reserved_at_223[0x3];
738 u8 reserved_at_229[0x1];
739 u8 scqe_break_moderation[0x1];
740 u8 cq_period_start_from_cqe[0x1];
742 u8 reserved_at_22d[0x1];
745 u8 umr_ptr_rlky[0x1];
747 u8 reserved_at_232[0x4];
750 u8 set_deth_sqpn[0x1];
751 u8 reserved_at_239[0x3];
757 u8 reserved_at_241[0x9];
759 u8 reserved_at_250[0x8];
762 u8 driver_version[0x1];
763 u8 pad_tx_eth_packet[0x1];
764 u8 reserved_at_263[0x8];
765 u8 log_bf_reg_size[0x5];
766 u8 reserved_at_270[0xb];
768 u8 num_lag_ports[0x4];
769 u8 reserved_at_280[0x10];
770 u8 max_wqe_sz_sq[0x10];
771 u8 reserved_at_2a0[0x10];
772 u8 max_wqe_sz_rq[0x10];
773 u8 max_flow_counter_31_16[0x10];
774 u8 max_wqe_sz_sq_dc[0x10];
775 u8 reserved_at_2e0[0x7];
777 u8 reserved_at_300[0x10];
778 u8 flow_counter_bulk_alloc[0x08];
780 u8 reserved_at_320[0x3];
781 u8 log_max_transport_domain[0x5];
782 u8 reserved_at_328[0x3];
784 u8 reserved_at_330[0xb];
785 u8 log_max_xrcd[0x5];
786 u8 nic_receive_steering_discard[0x1];
787 u8 receive_discard_vport_down[0x1];
788 u8 transmit_discard_vport_down[0x1];
789 u8 reserved_at_343[0x5];
790 u8 log_max_flow_counter_bulk[0x8];
791 u8 max_flow_counter_15_0[0x10];
792 u8 reserved_at_360[0x3];
794 u8 reserved_at_368[0x3];
796 u8 reserved_at_370[0x3];
798 u8 reserved_at_378[0x3];
800 u8 basic_cyclic_rcv_wqe[0x1];
801 u8 reserved_at_381[0x2];
803 u8 reserved_at_388[0x3];
805 u8 reserved_at_390[0x3];
806 u8 log_max_rqt_size[0x5];
807 u8 reserved_at_398[0x3];
808 u8 log_max_tis_per_sq[0x5];
809 u8 ext_stride_num_range[0x1];
810 u8 reserved_at_3a1[0x2];
811 u8 log_max_stride_sz_rq[0x5];
812 u8 reserved_at_3a8[0x3];
813 u8 log_min_stride_sz_rq[0x5];
814 u8 reserved_at_3b0[0x3];
815 u8 log_max_stride_sz_sq[0x5];
816 u8 reserved_at_3b8[0x3];
817 u8 log_min_stride_sz_sq[0x5];
819 u8 reserved_at_3c1[0x2];
820 u8 log_max_hairpin_queues[0x5];
821 u8 reserved_at_3c8[0x3];
822 u8 log_max_hairpin_wq_data_sz[0x5];
823 u8 reserved_at_3d0[0x3];
824 u8 log_max_hairpin_num_packets[0x5];
825 u8 reserved_at_3d8[0x3];
826 u8 log_max_wq_sz[0x5];
827 u8 nic_vport_change_event[0x1];
828 u8 disable_local_lb_uc[0x1];
829 u8 disable_local_lb_mc[0x1];
830 u8 log_min_hairpin_wq_data_sz[0x5];
831 u8 reserved_at_3e8[0x3];
832 u8 log_max_vlan_list[0x5];
833 u8 reserved_at_3f0[0x3];
834 u8 log_max_current_mc_list[0x5];
835 u8 reserved_at_3f8[0x3];
836 u8 log_max_current_uc_list[0x5];
837 u8 general_obj_types[0x40];
838 u8 reserved_at_440[0x20];
839 u8 reserved_at_460[0x10];
840 u8 max_num_eqs[0x10];
841 u8 reserved_at_480[0x3];
842 u8 log_max_l2_table[0x5];
843 u8 reserved_at_488[0x8];
844 u8 log_uar_page_sz[0x10];
845 u8 reserved_at_4a0[0x20];
846 u8 device_frequency_mhz[0x20];
847 u8 device_frequency_khz[0x20];
848 u8 reserved_at_500[0x20];
849 u8 num_of_uars_per_page[0x20];
850 u8 flex_parser_protocols[0x20];
851 u8 reserved_at_560[0x20];
852 u8 reserved_at_580[0x3c];
853 u8 mini_cqe_resp_stride_index[0x1];
854 u8 cqe_128_always[0x1];
855 u8 cqe_compression_128[0x1];
856 u8 cqe_compression[0x1];
857 u8 cqe_compression_timeout[0x10];
858 u8 cqe_compression_max_num[0x10];
859 u8 reserved_at_5e0[0x10];
860 u8 tag_matching[0x1];
861 u8 rndv_offload_rc[0x1];
862 u8 rndv_offload_dc[0x1];
863 u8 log_tag_matching_list_sz[0x5];
864 u8 reserved_at_5f8[0x3];
866 u8 affiliate_nic_vport_criteria[0x8];
867 u8 native_port_num[0x8];
868 u8 num_vhca_ports[0x8];
869 u8 reserved_at_618[0x6];
871 u8 reserved_at_61f[0x1e1];
874 struct mlx5_ifc_qos_cap_bits {
875 u8 packet_pacing[0x1];
876 u8 esw_scheduling[0x1];
877 u8 esw_bw_share[0x1];
878 u8 esw_rate_limit[0x1];
879 u8 reserved_at_4[0x1];
880 u8 packet_pacing_burst_bound[0x1];
881 u8 packet_pacing_typical_size[0x1];
882 u8 flow_meter_srtcm[0x1];
883 u8 reserved_at_8[0x8];
884 u8 log_max_flow_meter[0x8];
885 u8 flow_meter_reg_id[0x8];
886 u8 reserved_at_25[0x20];
887 u8 packet_pacing_max_rate[0x20];
888 u8 packet_pacing_min_rate[0x20];
889 u8 reserved_at_80[0x10];
890 u8 packet_pacing_rate_table_size[0x10];
891 u8 esw_element_type[0x10];
892 u8 esw_tsar_type[0x10];
893 u8 reserved_at_c0[0x10];
894 u8 max_qos_para_vport[0x10];
895 u8 max_tsar_bw_share[0x20];
896 u8 reserved_at_100[0x6e8];
899 union mlx5_ifc_hca_cap_union_bits {
900 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
901 struct mlx5_ifc_qos_cap_bits qos_cap;
902 u8 reserved_at_0[0x8000];
905 struct mlx5_ifc_query_hca_cap_out_bits {
907 u8 reserved_at_8[0x18];
909 u8 reserved_at_40[0x40];
910 union mlx5_ifc_hca_cap_union_bits capability;
913 struct mlx5_ifc_query_hca_cap_in_bits {
915 u8 reserved_at_10[0x10];
916 u8 reserved_at_20[0x10];
918 u8 reserved_at_40[0x40];
921 /* CQE format mask. */
922 #define MLX5E_CQE_FORMAT_MASK 0xc
925 #define MLX5_OPC_MOD_MPW 0x01
927 /* Compressed Rx CQE structure. */
928 struct mlx5_mini_cqe8 {
930 uint32_t rx_hash_result;
936 uint16_t wqe_counter;
937 uint8_t s_wqe_opcode;
945 * Convert a user mark to flow mark.
948 * Mark value to convert.
951 * Converted mark value.
953 static inline uint32_t
954 mlx5_flow_mark_set(uint32_t val)
959 * Add one to the user value to differentiate un-marked flows from
960 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
963 if (val != MLX5_FLOW_MARK_DEFAULT)
965 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
967 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
968 * word, byte-swapped by the kernel on little-endian systems. In this
969 * case, left-shifting the resulting big-endian value ensures the
970 * least significant 24 bits are retained when converting it back.
972 ret = rte_cpu_to_be_32(val) >> 8;
980 * Convert a mark to user mark.
983 * Mark value to convert.
986 * Converted mark value.
988 static inline uint32_t
989 mlx5_flow_mark_get(uint32_t val)
992 * Subtract one from the retrieved value. It was added by
993 * mlx5_flow_mark_set() to distinguish unmarked flows.
995 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
996 return (val >> 8) - 1;
1002 #endif /* RTE_PMD_MLX5_PRM_H_ */