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34 #ifndef RTE_PMD_MLX5_PRM_H_
35 #define RTE_PMD_MLX5_PRM_H_
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/mlx5_hw.h>
46 #pragma GCC diagnostic error "-Wpedantic"
50 #include "mlx5_autoconf.h"
52 /* Get CQE owner bit. */
53 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
56 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
59 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
61 /* Get CQE solicited event. */
62 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
64 /* Invalidate a CQE. */
65 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
67 /* CQE value to inform that VLAN is stripped. */
68 #define MLX5_CQE_VLAN_STRIPPED 0x1
70 /* Maximum number of packets a multi-packet WQE can handle. */
71 #define MLX5_MPW_DSEG_MAX 5
74 #define MLX5_WQE_DWORD_SIZE 16
77 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
79 /* Compute the number of DS. */
80 #define MLX5_WQE_DS(n) \
81 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
83 /* Room for inline data in multi-packet WQE. */
84 #define MLX5_MWQE64_INL_DATA 28
86 #ifndef HAVE_VERBS_MLX5_OPCODE_TSO
87 #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
91 #define MLX5_CQE_RX_IPV4_PACKET (1u << 2)
94 #define MLX5_CQE_RX_IPV6_PACKET (1u << 3)
96 /* Outer IPv4 packet. */
97 #define MLX5_CQE_RX_OUTER_IPV4_PACKET (1u << 7)
99 /* Outer IPv6 packet. */
100 #define MLX5_CQE_RX_OUTER_IPV6_PACKET (1u << 8)
102 /* Tunnel packet bit in the CQE. */
103 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 4)
105 /* Outer IP checksum OK. */
106 #define MLX5_CQE_RX_OUTER_IP_CSUM_OK (1u << 5)
108 /* Outer UDP header and checksum OK. */
109 #define MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK (1u << 6)
111 /* INVALID is used by packets matching no flow rules. */
112 #define MLX5_FLOW_MARK_INVALID 0
114 /* Maximum allowed value to mark a packet. */
115 #define MLX5_FLOW_MARK_MAX 0xfffff0
117 /* Default mark value used when none is provided. */
118 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
120 /* Subset of struct mlx5_wqe_eth_seg. */
121 struct mlx5_wqe_eth_seg_small {
127 uint16_t inline_hdr_sz;
128 uint8_t inline_hdr[2];
129 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
131 struct mlx5_wqe_inl_small {
134 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
136 struct mlx5_wqe_ctrl {
141 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
143 /* Small common part of the WQE. */
146 struct mlx5_wqe_eth_seg_small eseg;
149 /* Vectorize WQE header. */
159 } __rte_aligned(MLX5_WQE_SIZE);
161 /* MPW session status. */
162 enum mlx5_mpw_state {
163 MLX5_MPW_STATE_OPENED,
164 MLX5_MPW_INL_STATE_OPENED,
165 MLX5_MPW_STATE_CLOSED,
168 /* MPW session descriptor. */
170 enum mlx5_mpw_state state;
173 unsigned int total_len;
174 volatile struct mlx5_wqe *wqe;
176 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
177 volatile uint8_t *raw;
181 /* CQ element structure - should be equal to the cache line size */
183 #if (RTE_CACHE_LINE_SIZE == 128)
188 uint32_t rx_hash_res;
189 uint8_t rx_hash_type;
192 uint8_t l4_hdr_type_etc;
197 uint32_t sop_drop_qpn;
198 uint16_t wqe_counter;
204 * Convert a user mark to flow mark.
207 * Mark value to convert.
210 * Converted mark value.
212 static inline uint32_t
213 mlx5_flow_mark_set(uint32_t val)
218 * Add one to the user value to differentiate un-marked flows from
222 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
224 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
225 * word, byte-swapped by the kernel on little-endian systems. In this
226 * case, left-shifting the resulting big-endian value ensures the
227 * least significant 24 bits are retained when converting it back.
229 ret = rte_cpu_to_be_32(val) >> 8;
233 assert(ret <= MLX5_FLOW_MARK_MAX);
238 * Convert a mark to user mark.
241 * Mark value to convert.
244 * Converted mark value.
246 static inline uint32_t
247 mlx5_flow_mark_get(uint32_t val)
250 * Subtract one from the retrieved value. It was added by
251 * mlx5_flow_mark_set() to distinguish unmarked flows.
253 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
254 return (val >> 8) - 1;
260 #endif /* RTE_PMD_MLX5_PRM_H_ */