4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 #include <sys/queue.h>
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
48 #include <infiniband/mlx5dv.h>
50 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev.h>
56 #include <rte_common.h>
57 #include <rte_interrupts.h>
58 #include <rte_debug.h>
62 #include "mlx5_rxtx.h"
63 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Default RSS hash key also used for ConnectX-3. */
68 uint8_t rss_hash_default_key[] = {
69 0x2c, 0xc6, 0x81, 0xd1,
70 0x5b, 0xdb, 0xf4, 0xf7,
71 0xfc, 0xa2, 0x83, 0x19,
72 0xdb, 0x1a, 0x3e, 0x94,
73 0x6b, 0x9e, 0x38, 0xd9,
74 0x2c, 0x9c, 0x03, 0xd1,
75 0xad, 0x99, 0x44, 0xa7,
76 0xd9, 0x56, 0x3d, 0x59,
77 0x06, 0x3c, 0x25, 0xf3,
78 0xfc, 0x1f, 0xdc, 0x2a,
81 /* Length of the default RSS hash key. */
82 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
85 * Allocate RX queue elements.
88 * Pointer to RX queue structure.
91 * 0 on success, errno value on failure.
94 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
96 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
97 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
101 /* Iterate on segments. */
102 for (i = 0; (i != elts_n); ++i) {
103 struct rte_mbuf *buf;
105 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
107 ERROR("%p: empty mbuf pool", (void *)rxq_ctrl);
111 /* Headroom is reserved by rte_pktmbuf_alloc(). */
112 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
113 /* Buffer is supposed to be empty. */
114 assert(rte_pktmbuf_data_len(buf) == 0);
115 assert(rte_pktmbuf_pkt_len(buf) == 0);
117 /* Only the first segment keeps headroom. */
119 SET_DATA_OFF(buf, 0);
120 PORT(buf) = rxq_ctrl->rxq.port_id;
121 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
122 PKT_LEN(buf) = DATA_LEN(buf);
124 (*rxq_ctrl->rxq.elts)[i] = buf;
126 /* If Rx vector is activated. */
127 if (rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
128 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
129 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
132 /* Initialize default rearm_data for vPMD. */
133 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
134 rte_mbuf_refcnt_set(mbuf_init, 1);
135 mbuf_init->nb_segs = 1;
136 mbuf_init->port = rxq->port_id;
138 * prevent compiler reordering:
139 * rearm_data covers previous fields.
141 rte_compiler_barrier();
142 rxq->mbuf_initializer =
143 *(uint64_t *)&mbuf_init->rearm_data;
144 /* Padding with a fake mbuf for vectorized Rx. */
145 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
146 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
148 DEBUG("%p: allocated and configured %u segments (max %u packets)",
149 (void *)rxq_ctrl, elts_n, elts_n / (1 << rxq_ctrl->rxq.sges_n));
154 for (i = 0; (i != elts_n); ++i) {
155 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
156 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
157 (*rxq_ctrl->rxq.elts)[i] = NULL;
159 DEBUG("%p: failed, freed everything", (void *)rxq_ctrl);
165 * Free RX queue elements.
168 * Pointer to RX queue structure.
171 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
173 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
174 const uint16_t q_n = (1 << rxq->elts_n);
175 const uint16_t q_mask = q_n - 1;
176 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
179 DEBUG("%p: freeing WRs", (void *)rxq_ctrl);
180 if (rxq->elts == NULL)
183 * Some mbuf in the Ring belongs to the application. They cannot be
186 if (rxq_check_vec_support(rxq) > 0) {
187 for (i = 0; i < used; ++i)
188 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
189 rxq->rq_pi = rxq->rq_ci;
191 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
192 if ((*rxq->elts)[i] != NULL)
193 rte_pktmbuf_free_seg((*rxq->elts)[i]);
194 (*rxq->elts)[i] = NULL;
199 * Clean up a RX queue.
201 * Destroy objects, free allocated memory and reset the structure for reuse.
204 * Pointer to RX queue structure.
207 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
209 DEBUG("cleaning up %p", (void *)rxq_ctrl);
211 mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
212 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
218 * Pointer to Ethernet device structure.
222 * Number of descriptors to configure in queue.
224 * NUMA socket on which memory must be allocated.
226 * Thresholds parameters.
228 * Memory pool for buffer allocations.
231 * 0 on success, negative errno value on failure.
234 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
235 unsigned int socket, const struct rte_eth_rxconf *conf,
236 struct rte_mempool *mp)
238 struct priv *priv = dev->data->dev_private;
239 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
240 struct mlx5_rxq_ctrl *rxq_ctrl =
241 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
245 if (mlx5_is_secondary())
246 return -E_RTE_SECONDARY;
248 if (!rte_is_power_of_2(desc)) {
249 desc = 1 << log2above(desc);
250 WARN("%p: increased number of descriptors in RX queue %u"
251 " to the next power of two (%d)",
252 (void *)dev, idx, desc);
254 DEBUG("%p: configuring queue %u for %u descriptors",
255 (void *)dev, idx, desc);
256 if (idx >= priv->rxqs_n) {
257 ERROR("%p: queue index out of range (%u >= %u)",
258 (void *)dev, idx, priv->rxqs_n);
262 if (!mlx5_priv_rxq_releasable(priv, idx)) {
264 ERROR("%p: unable to release queue index %u",
268 mlx5_priv_rxq_release(priv, idx);
269 rxq_ctrl = mlx5_priv_rxq_new(priv, idx, desc, socket, mp);
271 ERROR("%p: unable to allocate queue index %u",
276 DEBUG("%p: adding RX queue %p to list",
277 (void *)dev, (void *)rxq_ctrl);
278 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
285 * DPDK callback to release a RX queue.
288 * Generic RX queue pointer.
291 mlx5_rx_queue_release(void *dpdk_rxq)
293 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
294 struct mlx5_rxq_ctrl *rxq_ctrl;
297 if (mlx5_is_secondary())
302 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
303 priv = rxq_ctrl->priv;
305 if (!mlx5_priv_rxq_releasable(priv, rxq_ctrl->rxq.stats.idx))
306 rte_panic("Rx queue %p is still used by a flow and cannot be"
307 " removed\n", (void *)rxq_ctrl);
308 mlx5_priv_rxq_release(priv, rxq_ctrl->rxq.stats.idx);
313 * Allocate queue vector and fill epoll fd list for Rx interrupts.
316 * Pointer to private structure.
319 * 0 on success, negative on failure.
322 priv_rx_intr_vec_enable(struct priv *priv)
325 unsigned int rxqs_n = priv->rxqs_n;
326 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
327 unsigned int count = 0;
328 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
330 assert(!mlx5_is_secondary());
331 if (!priv->dev->data->dev_conf.intr_conf.rxq)
333 priv_rx_intr_vec_disable(priv);
334 intr_handle->intr_vec = malloc(sizeof(intr_handle->intr_vec[rxqs_n]));
335 if (intr_handle->intr_vec == NULL) {
336 ERROR("failed to allocate memory for interrupt vector,"
337 " Rx interrupts will not be supported");
340 intr_handle->type = RTE_INTR_HANDLE_EXT;
341 for (i = 0; i != n; ++i) {
342 /* This rxq ibv must not be released in this function. */
343 struct mlx5_rxq_ibv *rxq_ibv = mlx5_priv_rxq_ibv_get(priv, i);
348 /* Skip queues that cannot request interrupts. */
349 if (!rxq_ibv || !rxq_ibv->channel) {
350 /* Use invalid intr_vec[] index to disable entry. */
351 intr_handle->intr_vec[i] =
352 RTE_INTR_VEC_RXTX_OFFSET +
353 RTE_MAX_RXTX_INTR_VEC_ID;
356 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
357 ERROR("too many Rx queues for interrupt vector size"
358 " (%d), Rx interrupts cannot be enabled",
359 RTE_MAX_RXTX_INTR_VEC_ID);
360 priv_rx_intr_vec_disable(priv);
363 fd = rxq_ibv->channel->fd;
364 flags = fcntl(fd, F_GETFL);
365 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
367 ERROR("failed to make Rx interrupt file descriptor"
368 " %d non-blocking for queue index %d", fd, i);
369 priv_rx_intr_vec_disable(priv);
372 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
373 intr_handle->efds[count] = fd;
377 priv_rx_intr_vec_disable(priv);
379 intr_handle->nb_efd = count;
384 * Clean up Rx interrupts handler.
387 * Pointer to private structure.
390 priv_rx_intr_vec_disable(struct priv *priv)
392 struct rte_intr_handle *intr_handle = priv->dev->intr_handle;
394 unsigned int rxqs_n = priv->rxqs_n;
395 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
397 if (!priv->dev->data->dev_conf.intr_conf.rxq)
399 for (i = 0; i != n; ++i) {
400 struct mlx5_rxq_ctrl *rxq_ctrl;
401 struct mlx5_rxq_data *rxq_data;
403 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
404 RTE_MAX_RXTX_INTR_VEC_ID)
407 * Need to access directly the queue to release the reference
408 * kept in priv_rx_intr_vec_enable().
410 rxq_data = (*priv->rxqs)[i];
411 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
412 mlx5_priv_rxq_ibv_release(priv, rxq_ctrl->ibv);
414 rte_intr_free_epoll_fd(intr_handle);
415 free(intr_handle->intr_vec);
416 intr_handle->nb_efd = 0;
417 intr_handle->intr_vec = NULL;
421 * MLX5 CQ notification .
424 * Pointer to receive queue structure.
426 * Sequence number per receive queue .
429 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
432 uint32_t doorbell_hi;
434 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
436 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
437 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
438 doorbell = (uint64_t)doorbell_hi << 32;
439 doorbell |= rxq->cqn;
440 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
442 rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
446 * DPDK callback for Rx queue interrupt enable.
449 * Pointer to Ethernet device structure.
454 * 0 on success, negative on failure.
457 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
459 struct priv *priv = mlx5_get_priv(dev);
460 struct mlx5_rxq_data *rxq_data;
461 struct mlx5_rxq_ctrl *rxq_ctrl;
465 rxq_data = (*priv->rxqs)[rx_queue_id];
470 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
472 struct mlx5_rxq_ibv *rxq_ibv;
474 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
479 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
480 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
485 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
490 * DPDK callback for Rx queue interrupt disable.
493 * Pointer to Ethernet device structure.
498 * 0 on success, negative on failure.
501 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
503 struct priv *priv = mlx5_get_priv(dev);
504 struct mlx5_rxq_data *rxq_data;
505 struct mlx5_rxq_ctrl *rxq_ctrl;
506 struct mlx5_rxq_ibv *rxq_ibv = NULL;
507 struct ibv_cq *ev_cq;
512 rxq_data = (*priv->rxqs)[rx_queue_id];
517 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
520 rxq_ibv = mlx5_priv_rxq_ibv_get(priv, rx_queue_id);
525 ret = ibv_get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
526 if (ret || ev_cq != rxq_ibv->cq) {
530 rxq_data->cq_arm_sn++;
531 ibv_ack_cq_events(rxq_ibv->cq, 1);
534 mlx5_priv_rxq_ibv_release(priv, rxq_ibv);
537 WARN("unable to disable interrupt on rx queue %d",
543 * Create the Rx queue Verbs object.
546 * Pointer to private structure.
548 * Queue index in DPDK Rx queue array
551 * The Verbs object initialised if it can be created.
554 mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
556 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
557 struct mlx5_rxq_ctrl *rxq_ctrl =
558 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
559 struct ibv_wq_attr mod;
562 struct ibv_cq_init_attr_ex ibv;
563 struct mlx5dv_cq_init_attr mlx5;
565 struct ibv_wq_init_attr wq;
566 struct ibv_cq_ex cq_attr;
568 unsigned int cqe_n = (1 << rxq_data->elts_n) - 1;
569 struct mlx5_rxq_ibv *tmpl;
570 struct mlx5dv_cq cq_info;
571 struct mlx5dv_rwq rwq;
574 struct mlx5dv_obj obj;
577 assert(!rxq_ctrl->ibv);
578 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
581 ERROR("%p: cannot allocate verbs resources",
585 tmpl->rxq_ctrl = rxq_ctrl;
586 /* Use the entire RX mempool as the memory region. */
587 tmpl->mr = priv_mr_get(priv, rxq_data->mp);
589 tmpl->mr = priv_mr_new(priv, rxq_data->mp);
591 ERROR("%p: MR creation failure", (void *)rxq_ctrl);
596 tmpl->channel = ibv_create_comp_channel(priv->ctx);
597 if (!tmpl->channel) {
598 ERROR("%p: Comp Channel creation failure",
603 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
605 .channel = tmpl->channel,
608 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
611 if (priv->cqe_comp && !rxq_data->hw_timestamp) {
612 attr.cq.mlx5.comp_mask |=
613 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
614 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
616 * For vectorized Rx, it must not be doubled in order to
617 * make cq_ci and rq_ci aligned.
619 if (rxq_check_vec_support(rxq_data) < 0)
620 attr.cq.ibv.cqe *= 2;
621 } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
622 DEBUG("Rx CQE compression is disabled for HW timestamp");
624 tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
626 if (tmpl->cq == NULL) {
627 ERROR("%p: CQ creation failure", (void *)rxq_ctrl);
630 DEBUG("priv->device_attr.max_qp_wr is %d",
631 priv->device_attr.orig_attr.max_qp_wr);
632 DEBUG("priv->device_attr.max_sge is %d",
633 priv->device_attr.orig_attr.max_sge);
634 attr.wq = (struct ibv_wq_init_attr){
635 .wq_context = NULL, /* Could be useful in the future. */
636 .wq_type = IBV_WQT_RQ,
637 /* Max number of outstanding WRs. */
638 .max_wr = (1 << rxq_data->elts_n) >> rxq_data->sges_n,
639 /* Max number of scatter/gather elements in a WR. */
640 .max_sge = 1 << rxq_data->sges_n,
644 IBV_WQ_FLAGS_CVLAN_STRIPPING |
646 .create_flags = (rxq_data->vlan_strip ?
647 IBV_WQ_FLAGS_CVLAN_STRIPPING :
650 /* By default, FCS (CRC) is stripped by hardware. */
651 if (rxq_data->crc_present) {
652 attr.wq.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
653 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
655 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
656 if (priv->hw_padding) {
657 attr.wq.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
658 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
661 tmpl->wq = ibv_create_wq(priv->ctx, &attr.wq);
662 if (tmpl->wq == NULL) {
663 ERROR("%p: WQ creation failure", (void *)rxq_ctrl);
667 * Make sure number of WRs*SGEs match expectations since a queue
668 * cannot allocate more than "desc" buffers.
670 if (((int)attr.wq.max_wr !=
671 ((1 << rxq_data->elts_n) >> rxq_data->sges_n)) ||
672 ((int)attr.wq.max_sge != (1 << rxq_data->sges_n))) {
673 ERROR("%p: requested %u*%u but got %u*%u WRs*SGEs",
675 ((1 << rxq_data->elts_n) >> rxq_data->sges_n),
676 (1 << rxq_data->sges_n),
677 attr.wq.max_wr, attr.wq.max_sge);
680 /* Change queue state to ready. */
681 mod = (struct ibv_wq_attr){
682 .attr_mask = IBV_WQ_ATTR_STATE,
683 .wq_state = IBV_WQS_RDY,
685 ret = ibv_modify_wq(tmpl->wq, &mod);
687 ERROR("%p: WQ state to IBV_WQS_RDY failed",
691 obj.cq.in = tmpl->cq;
692 obj.cq.out = &cq_info;
693 obj.rwq.in = tmpl->wq;
695 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
698 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
699 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
700 "it should be set to %u", RTE_CACHE_LINE_SIZE);
703 /* Fill the rings. */
704 rxq_data->wqes = (volatile struct mlx5_wqe_data_seg (*)[])
706 for (i = 0; (i != (unsigned int)(1 << rxq_data->elts_n)); ++i) {
707 struct rte_mbuf *buf = (*rxq_data->elts)[i];
708 volatile struct mlx5_wqe_data_seg *scat = &(*rxq_data->wqes)[i];
710 /* scat->addr must be able to store a pointer. */
711 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
712 *scat = (struct mlx5_wqe_data_seg){
713 .addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
715 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
716 .lkey = tmpl->mr->lkey,
719 rxq_data->rq_db = rwq.dbrec;
720 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
724 rxq_data->zip = (struct rxq_zip){
727 rxq_data->cq_db = cq_info.dbrec;
728 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
729 /* Update doorbell counter. */
730 rxq_data->rq_ci = (1 << rxq_data->elts_n) >> rxq_data->sges_n;
732 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
733 DEBUG("%p: rxq updated with %p", (void *)rxq_ctrl, (void *)&tmpl);
734 rte_atomic32_inc(&tmpl->refcnt);
735 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
736 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
737 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
741 claim_zero(ibv_destroy_wq(tmpl->wq));
743 claim_zero(ibv_destroy_cq(tmpl->cq));
745 claim_zero(ibv_destroy_comp_channel(tmpl->channel));
747 priv_mr_release(priv, tmpl->mr);
752 * Get an Rx queue Verbs object.
755 * Pointer to private structure.
757 * Queue index in DPDK Rx queue array
760 * The Verbs object if it exists.
763 mlx5_priv_rxq_ibv_get(struct priv *priv, uint16_t idx)
765 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
766 struct mlx5_rxq_ctrl *rxq_ctrl;
768 if (idx >= priv->rxqs_n)
772 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
774 priv_mr_get(priv, rxq_data->mp);
775 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
776 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
777 (void *)rxq_ctrl->ibv,
778 rte_atomic32_read(&rxq_ctrl->ibv->refcnt));
780 return rxq_ctrl->ibv;
784 * Release an Rx verbs queue object.
787 * Pointer to private structure.
789 * Verbs Rx queue object.
792 * 0 on success, errno value on failure.
795 mlx5_priv_rxq_ibv_release(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
803 ret = priv_mr_release(priv, rxq_ibv->mr);
806 DEBUG("%p: Verbs Rx queue %p: refcnt %d", (void *)priv,
807 (void *)rxq_ibv, rte_atomic32_read(&rxq_ibv->refcnt));
808 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
809 rxq_free_elts(rxq_ibv->rxq_ctrl);
810 claim_zero(ibv_destroy_wq(rxq_ibv->wq));
811 claim_zero(ibv_destroy_cq(rxq_ibv->cq));
812 if (rxq_ibv->channel)
813 claim_zero(ibv_destroy_comp_channel(rxq_ibv->channel));
814 LIST_REMOVE(rxq_ibv, next);
822 * Verify the Verbs Rx queue list is empty
825 * Pointer to private structure.
827 * @return the number of object not released.
830 mlx5_priv_rxq_ibv_verify(struct priv *priv)
833 struct mlx5_rxq_ibv *rxq_ibv;
835 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
836 DEBUG("%p: Verbs Rx queue %p still referenced", (void *)priv,
844 * Return true if a single reference exists on the object.
847 * Pointer to private structure.
849 * Verbs Rx queue object.
852 mlx5_priv_rxq_ibv_releasable(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv)
856 return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
860 * Create a DPDK Rx queue.
863 * Pointer to private structure.
867 * Number of descriptors to configure in queue.
869 * NUMA socket on which memory must be allocated.
872 * A DPDK queue object on success.
874 struct mlx5_rxq_ctrl*
875 mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
876 unsigned int socket, struct rte_mempool *mp)
878 struct rte_eth_dev *dev = priv->dev;
879 struct mlx5_rxq_ctrl *tmpl;
880 const uint16_t desc_n =
881 desc + priv->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
882 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
884 tmpl = rte_calloc_socket("RXQ", 1,
886 desc_n * sizeof(struct rte_mbuf *),
890 if (priv->dev->data->dev_conf.intr_conf.rxq)
892 /* Enable scattered packets support for this queue if necessary. */
893 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
894 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
895 (mb_len - RTE_PKTMBUF_HEADROOM)) {
896 tmpl->rxq.sges_n = 0;
897 } else if (dev->data->dev_conf.rxmode.enable_scatter) {
899 RTE_PKTMBUF_HEADROOM +
900 dev->data->dev_conf.rxmode.max_rx_pkt_len;
904 * Determine the number of SGEs needed for a full packet
905 * and round it to the next power of two.
907 sges_n = log2above((size / mb_len) + !!(size % mb_len));
908 tmpl->rxq.sges_n = sges_n;
909 /* Make sure rxq.sges_n did not overflow. */
910 size = mb_len * (1 << tmpl->rxq.sges_n);
911 size -= RTE_PKTMBUF_HEADROOM;
912 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
913 ERROR("%p: too many SGEs (%u) needed to handle"
914 " requested maximum packet size %u",
917 dev->data->dev_conf.rxmode.max_rx_pkt_len);
921 WARN("%p: the requested maximum Rx packet size (%u) is"
922 " larger than a single mbuf (%u) and scattered"
923 " mode has not been requested",
925 dev->data->dev_conf.rxmode.max_rx_pkt_len,
926 mb_len - RTE_PKTMBUF_HEADROOM);
928 DEBUG("%p: maximum number of segments per packet: %u",
929 (void *)dev, 1 << tmpl->rxq.sges_n);
930 if (desc % (1 << tmpl->rxq.sges_n)) {
931 ERROR("%p: number of RX queue descriptors (%u) is not a"
932 " multiple of SGEs per packet (%u)",
935 1 << tmpl->rxq.sges_n);
938 /* Toggle RX checksum offload if hardware supports it. */
940 tmpl->rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
941 if (priv->hw_csum_l2tun)
942 tmpl->rxq.csum_l2tun =
943 !!dev->data->dev_conf.rxmode.hw_ip_checksum;
944 tmpl->rxq.hw_timestamp =
945 !!dev->data->dev_conf.rxmode.hw_timestamp;
946 /* Configure VLAN stripping. */
947 tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
948 !!dev->data->dev_conf.rxmode.hw_vlan_strip);
949 /* By default, FCS (CRC) is stripped by hardware. */
950 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
951 tmpl->rxq.crc_present = 0;
952 } else if (priv->hw_fcs_strip) {
953 tmpl->rxq.crc_present = 1;
955 WARN("%p: CRC stripping has been disabled but will still"
956 " be performed by hardware, make sure MLNX_OFED and"
957 " firmware are up to date",
959 tmpl->rxq.crc_present = 0;
961 DEBUG("%p: CRC stripping is %s, %u bytes will be subtracted from"
962 " incoming frames to hide it",
964 tmpl->rxq.crc_present ? "disabled" : "enabled",
965 tmpl->rxq.crc_present << 2);
967 tmpl->rxq.rss_hash = priv->rxqs_n > 1;
968 tmpl->rxq.port_id = dev->data->port_id;
971 tmpl->rxq.stats.idx = idx;
972 tmpl->rxq.elts_n = log2above(desc);
974 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
975 rte_atomic32_inc(&tmpl->refcnt);
976 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
977 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
978 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
989 * Pointer to private structure.
994 * A pointer to the queue if it exists.
996 struct mlx5_rxq_ctrl*
997 mlx5_priv_rxq_get(struct priv *priv, uint16_t idx)
999 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1001 if ((*priv->rxqs)[idx]) {
1002 rxq_ctrl = container_of((*priv->rxqs)[idx],
1003 struct mlx5_rxq_ctrl,
1006 mlx5_priv_rxq_ibv_get(priv, idx);
1007 rte_atomic32_inc(&rxq_ctrl->refcnt);
1008 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1009 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1015 * Release a Rx queue.
1018 * Pointer to private structure.
1023 * 0 on success, errno value on failure.
1026 mlx5_priv_rxq_release(struct priv *priv, uint16_t idx)
1028 struct mlx5_rxq_ctrl *rxq_ctrl;
1030 if (!(*priv->rxqs)[idx])
1032 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1033 assert(rxq_ctrl->priv);
1034 if (rxq_ctrl->ibv) {
1037 ret = mlx5_priv_rxq_ibv_release(rxq_ctrl->priv, rxq_ctrl->ibv);
1039 rxq_ctrl->ibv = NULL;
1041 DEBUG("%p: Rx queue %p: refcnt %d", (void *)priv,
1042 (void *)rxq_ctrl, rte_atomic32_read(&rxq_ctrl->refcnt));
1043 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1044 LIST_REMOVE(rxq_ctrl, next);
1046 (*priv->rxqs)[idx] = NULL;
1053 * Verify if the queue can be released.
1056 * Pointer to private structure.
1061 * 1 if the queue can be released.
1064 mlx5_priv_rxq_releasable(struct priv *priv, uint16_t idx)
1066 struct mlx5_rxq_ctrl *rxq_ctrl;
1068 if (!(*priv->rxqs)[idx])
1070 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1071 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1075 * Verify the Rx Queue list is empty
1078 * Pointer to private structure.
1080 * @return the number of object not released.
1083 mlx5_priv_rxq_verify(struct priv *priv)
1085 struct mlx5_rxq_ctrl *rxq_ctrl;
1088 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1089 DEBUG("%p: Rx Queue %p still referenced", (void *)priv,
1097 * Create an indirection table.
1100 * Pointer to private structure.
1102 * Queues entering in the indirection table.
1104 * Number of queues in the array.
1107 * A new indirection table.
1109 struct mlx5_ind_table_ibv*
1110 mlx5_priv_ind_table_ibv_new(struct priv *priv, uint16_t queues[],
1113 struct mlx5_ind_table_ibv *ind_tbl;
1114 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1115 log2above(queues_n) :
1116 priv->ind_table_max_size;
1117 struct ibv_wq *wq[1 << wq_n];
1121 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1122 queues_n * sizeof(uint16_t), 0);
1125 for (i = 0; i != queues_n; ++i) {
1126 struct mlx5_rxq_ctrl *rxq =
1127 mlx5_priv_rxq_get(priv, queues[i]);
1131 wq[i] = rxq->ibv->wq;
1132 ind_tbl->queues[i] = queues[i];
1134 ind_tbl->queues_n = queues_n;
1135 /* Finalise indirection table. */
1136 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1138 ind_tbl->ind_table = ibv_create_rwq_ind_table(
1140 &(struct ibv_rwq_ind_table_init_attr){
1141 .log_ind_tbl_size = wq_n,
1145 if (!ind_tbl->ind_table)
1147 rte_atomic32_inc(&ind_tbl->refcnt);
1148 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1149 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1150 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1154 DEBUG("%p cannot create indirection table", (void *)priv);
1159 * Get an indirection table.
1162 * Pointer to private structure.
1164 * Queues entering in the indirection table.
1166 * Number of queues in the array.
1169 * An indirection table if found.
1171 struct mlx5_ind_table_ibv*
1172 mlx5_priv_ind_table_ibv_get(struct priv *priv, uint16_t queues[],
1175 struct mlx5_ind_table_ibv *ind_tbl;
1177 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1178 if ((ind_tbl->queues_n == queues_n) &&
1179 (memcmp(ind_tbl->queues, queues,
1180 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1187 rte_atomic32_inc(&ind_tbl->refcnt);
1188 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1189 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1190 for (i = 0; i != ind_tbl->queues_n; ++i)
1191 mlx5_priv_rxq_get(priv, ind_tbl->queues[i]);
1197 * Release an indirection table.
1200 * Pointer to private structure.
1202 * Indirection table to release.
1205 * 0 on success, errno value on failure.
1208 mlx5_priv_ind_table_ibv_release(struct priv *priv,
1209 struct mlx5_ind_table_ibv *ind_tbl)
1213 DEBUG("%p: Indirection table %p: refcnt %d", (void *)priv,
1214 (void *)ind_tbl, rte_atomic32_read(&ind_tbl->refcnt));
1215 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1216 claim_zero(ibv_destroy_rwq_ind_table(ind_tbl->ind_table));
1217 for (i = 0; i != ind_tbl->queues_n; ++i)
1218 claim_nonzero(mlx5_priv_rxq_release(priv, ind_tbl->queues[i]));
1219 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1220 LIST_REMOVE(ind_tbl, next);
1228 * Verify the Rx Queue list is empty
1231 * Pointer to private structure.
1233 * @return the number of object not released.
1236 mlx5_priv_ind_table_ibv_verify(struct priv *priv)
1238 struct mlx5_ind_table_ibv *ind_tbl;
1241 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1242 DEBUG("%p: Verbs indirection table %p still referenced",
1243 (void *)priv, (void *)ind_tbl);
1250 * Create an Rx Hash queue.
1253 * Pointer to private structure.
1255 * RSS key for the Rx hash queue.
1256 * @param rss_key_len
1258 * @param hash_fields
1259 * Verbs protocol hash field to make the RSS on.
1261 * Queues entering in hash queue.
1266 * An hash Rx queue on success.
1269 mlx5_priv_hrxq_new(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1270 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1272 struct mlx5_hrxq *hrxq;
1273 struct mlx5_ind_table_ibv *ind_tbl;
1276 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1278 ind_tbl = mlx5_priv_ind_table_ibv_new(priv, queues, queues_n);
1281 qp = ibv_create_qp_ex(
1283 &(struct ibv_qp_init_attr_ex){
1284 .qp_type = IBV_QPT_RAW_PACKET,
1286 IBV_QP_INIT_ATTR_PD |
1287 IBV_QP_INIT_ATTR_IND_TABLE |
1288 IBV_QP_INIT_ATTR_RX_HASH,
1289 .rx_hash_conf = (struct ibv_rx_hash_conf){
1290 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1291 .rx_hash_key_len = rss_key_len,
1292 .rx_hash_key = rss_key,
1293 .rx_hash_fields_mask = hash_fields,
1295 .rwq_ind_tbl = ind_tbl->ind_table,
1300 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1303 hrxq->ind_table = ind_tbl;
1305 hrxq->rss_key_len = rss_key_len;
1306 hrxq->hash_fields = hash_fields;
1307 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1308 rte_atomic32_inc(&hrxq->refcnt);
1309 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1310 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1311 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1314 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1316 claim_zero(ibv_destroy_qp(qp));
1321 * Get an Rx Hash queue.
1324 * Pointer to private structure.
1326 * RSS configuration for the Rx hash queue.
1328 * Queues entering in hash queue.
1333 * An hash Rx queue on success.
1336 mlx5_priv_hrxq_get(struct priv *priv, uint8_t *rss_key, uint8_t rss_key_len,
1337 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1339 struct mlx5_hrxq *hrxq;
1341 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1342 struct mlx5_ind_table_ibv *ind_tbl;
1344 if (hrxq->rss_key_len != rss_key_len)
1346 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1348 if (hrxq->hash_fields != hash_fields)
1350 ind_tbl = mlx5_priv_ind_table_ibv_get(priv, queues, queues_n);
1353 if (ind_tbl != hrxq->ind_table) {
1354 mlx5_priv_ind_table_ibv_release(priv, ind_tbl);
1357 rte_atomic32_inc(&hrxq->refcnt);
1358 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1359 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1366 * Release the hash Rx queue.
1369 * Pointer to private structure.
1371 * Pointer to Hash Rx queue to release.
1374 * 0 on success, errno value on failure.
1377 mlx5_priv_hrxq_release(struct priv *priv, struct mlx5_hrxq *hrxq)
1379 DEBUG("%p: Hash Rx queue %p: refcnt %d", (void *)priv,
1380 (void *)hrxq, rte_atomic32_read(&hrxq->refcnt));
1381 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1382 claim_zero(ibv_destroy_qp(hrxq->qp));
1383 mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table);
1384 LIST_REMOVE(hrxq, next);
1388 claim_nonzero(mlx5_priv_ind_table_ibv_release(priv, hrxq->ind_table));
1393 * Verify the Rx Queue list is empty
1396 * Pointer to private structure.
1398 * @return the number of object not released.
1401 mlx5_priv_hrxq_ibv_verify(struct priv *priv)
1403 struct mlx5_hrxq *hrxq;
1406 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1407 DEBUG("%p: Verbs Hash Rx queue %p still referenced",
1408 (void *)priv, (void *)hrxq);