4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Manage TX completions.
158 * When sending a burst, mlx5_tx_burst() posts several WRs.
159 * To improve performance, a completion event is only required once every
160 * MLX5_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
161 * for other WRs, but this information would not be used anyway.
164 * Pointer to TX queue structure.
167 txq_complete(struct txq *txq)
169 const unsigned int elts_n = txq->elts_n;
170 const unsigned int cqe_n = txq->cqe_n;
171 const unsigned int cqe_cnt = cqe_n - 1;
172 uint16_t elts_free = txq->elts_tail;
174 uint16_t cq_ci = txq->cq_ci;
175 unsigned int wqe_ci = (unsigned int)-1;
178 unsigned int idx = cq_ci & cqe_cnt;
179 volatile struct mlx5_cqe64 *cqe = &(*txq->cqes)[idx].cqe64;
181 if (check_cqe64(cqe, cqe_n, cq_ci) == 1)
184 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
185 if (!check_cqe64_seen(cqe))
186 ERROR("unexpected compressed CQE, TX stopped");
189 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
190 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
191 if (!check_cqe64_seen(cqe))
192 ERROR("unexpected error CQE, TX stopped");
196 wqe_ci = ntohs(cqe->wqe_counter);
199 if (unlikely(wqe_ci == (unsigned int)-1))
202 elts_tail = (wqe_ci + 1) & (elts_n - 1);
204 struct rte_mbuf *elt = (*txq->elts)[elts_free];
205 unsigned int elts_free_next =
206 (elts_free + 1) & (elts_n - 1);
207 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
211 memset(&(*txq->elts)[elts_free],
213 sizeof((*txq->elts)[elts_free]));
215 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
216 /* Only one segment needs to be freed. */
217 rte_pktmbuf_free_seg(elt);
218 elts_free = elts_free_next;
219 } while (elts_free != elts_tail);
221 txq->elts_tail = elts_tail;
222 /* Update the consumer index. */
224 *txq->cq_db = htonl(cq_ci);
228 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
229 * the cloned mbuf is allocated is returned instead.
235 * Memory pool where data is located for given mbuf.
237 static struct rte_mempool *
238 txq_mb2mp(struct rte_mbuf *buf)
240 if (unlikely(RTE_MBUF_INDIRECT(buf)))
241 return rte_mbuf_from_indirect(buf)->pool;
245 static inline uint32_t
246 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
247 __attribute__((always_inline));
250 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
251 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
252 * remove an entry first.
255 * Pointer to TX queue structure.
257 * Memory Pool for which a Memory Region lkey must be returned.
260 * mr->lkey on success, (uint32_t)-1 on failure.
262 static inline uint32_t
263 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
266 uint32_t lkey = (uint32_t)-1;
268 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
269 if (unlikely(txq->mp2mr[i].mp == NULL)) {
270 /* Unknown MP, add a new MR for it. */
273 if (txq->mp2mr[i].mp == mp) {
274 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
275 assert(htonl(txq->mp2mr[i].mr->lkey) ==
277 lkey = txq->mp2mr[i].lkey;
281 if (unlikely(lkey == (uint32_t)-1))
282 lkey = txq_mp2mr_reg(txq, mp, i);
287 * Write a regular WQE.
290 * Pointer to TX queue structure.
292 * Pointer to the WQE to fill.
294 * Buffer data address.
298 * Memory region lkey.
301 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
302 uintptr_t addr, uint32_t length, uint32_t lkey)
304 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
305 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
306 wqe->wqe.ctrl.data[3] = 0;
307 wqe->inl.eseg.rsvd0 = 0;
308 wqe->inl.eseg.rsvd1 = 0;
309 wqe->inl.eseg.mss = 0;
310 wqe->inl.eseg.rsvd2 = 0;
311 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
312 /* Copy the first 16 bytes into inline header. */
313 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
314 (uint8_t *)(uintptr_t)addr,
315 MLX5_ETH_INLINE_HEADER_SIZE);
316 addr += MLX5_ETH_INLINE_HEADER_SIZE;
317 length -= MLX5_ETH_INLINE_HEADER_SIZE;
318 /* Store remaining data in data segment. */
319 wqe->wqe.dseg.byte_count = htonl(length);
320 wqe->wqe.dseg.lkey = lkey;
321 wqe->wqe.dseg.addr = htonll(addr);
322 /* Increment consumer index. */
327 * Write a regular WQE with VLAN.
330 * Pointer to TX queue structure.
332 * Pointer to the WQE to fill.
334 * Buffer data address.
338 * Memory region lkey.
340 * VLAN field to insert in packet.
343 mlx5_wqe_write_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
344 uintptr_t addr, uint32_t length, uint32_t lkey,
347 uint32_t vlan = htonl(0x81000000 | vlan_tci);
349 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
350 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
351 wqe->wqe.ctrl.data[3] = 0;
352 wqe->inl.eseg.rsvd0 = 0;
353 wqe->inl.eseg.rsvd1 = 0;
354 wqe->inl.eseg.mss = 0;
355 wqe->inl.eseg.rsvd2 = 0;
356 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
358 * Copy 12 bytes of source & destination MAC address.
359 * Copy 4 bytes of VLAN.
360 * Copy 2 bytes of Ether type.
362 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
363 (uint8_t *)(uintptr_t)addr, 12);
364 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 12),
365 &vlan, sizeof(vlan));
366 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 16),
367 (uint8_t *)((uintptr_t)addr + 12), 2);
368 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
369 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
370 /* Store remaining data in data segment. */
371 wqe->wqe.dseg.byte_count = htonl(length);
372 wqe->wqe.dseg.lkey = lkey;
373 wqe->wqe.dseg.addr = htonll(addr);
374 /* Increment consumer index. */
379 * Ring TX queue doorbell.
382 * Pointer to TX queue structure.
385 mlx5_tx_dbrec(struct txq *txq)
387 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
389 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
390 htonl(txq->qp_num_8s),
395 *txq->qp_db = htonl(txq->wqe_ci);
396 /* Ensure ordering between DB record and BF copy. */
398 rte_mov16(dst, (uint8_t *)data);
399 txq->bf_offset ^= txq->bf_buf_size;
406 * Pointer to TX queue structure.
408 * CQE consumer index.
411 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
413 volatile struct mlx5_cqe64 *cqe;
415 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
420 * DPDK callback for TX.
423 * Generic pointer to TX queue structure.
425 * Packets to transmit.
427 * Number of packets in array.
430 * Number of packets successfully transmitted (<= pkts_n).
433 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
435 struct txq *txq = (struct txq *)dpdk_txq;
436 uint16_t elts_head = txq->elts_head;
437 const unsigned int elts_n = txq->elts_n;
440 volatile union mlx5_wqe *wqe;
441 struct rte_mbuf *buf;
443 if (unlikely(!pkts_n))
446 /* Prefetch first packet cacheline. */
447 tx_prefetch_cqe(txq, txq->cq_ci);
448 tx_prefetch_cqe(txq, txq->cq_ci + 1);
450 /* Start processing. */
452 max = (elts_n - (elts_head - txq->elts_tail));
456 assert(max <= elts_n);
457 /* Always leave one free entry in the ring. */
463 for (i = 0; (i != max); ++i) {
464 unsigned int elts_head_next = (elts_head + 1) & (elts_n - 1);
469 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
472 rte_prefetch0(pkts[i + 1]);
473 /* Retrieve buffer information. */
474 addr = rte_pktmbuf_mtod(buf, uintptr_t);
475 length = DATA_LEN(buf);
476 /* Update element. */
477 (*txq->elts)[elts_head] = buf;
478 /* Prefetch next buffer data. */
480 rte_prefetch0(rte_pktmbuf_mtod(pkts[i + 1],
482 /* Retrieve Memory Region key for this memory pool. */
483 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
484 if (buf->ol_flags & PKT_TX_VLAN_PKT)
485 mlx5_wqe_write_vlan(txq, wqe, addr, length, lkey,
488 mlx5_wqe_write(txq, wqe, addr, length, lkey);
489 /* Request completion if needed. */
490 if (unlikely(--txq->elts_comp == 0)) {
491 wqe->wqe.ctrl.data[2] = htonl(8);
492 txq->elts_comp = txq->elts_comp_cd_init;
494 wqe->wqe.ctrl.data[2] = 0;
496 /* Should we enable HW CKSUM offload */
498 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
499 wqe->wqe.eseg.cs_flags =
500 MLX5_ETH_WQE_L3_CSUM |
501 MLX5_ETH_WQE_L4_CSUM;
503 wqe->wqe.eseg.cs_flags = 0;
505 #ifdef MLX5_PMD_SOFT_COUNTERS
506 /* Increment sent bytes counter. */
507 txq->stats.obytes += length;
509 elts_head = elts_head_next;
512 /* Take a shortcut if nothing must be sent. */
513 if (unlikely(i == 0))
515 #ifdef MLX5_PMD_SOFT_COUNTERS
516 /* Increment sent packets counter. */
517 txq->stats.opackets += i;
519 /* Ring QP doorbell. */
521 txq->elts_head = elts_head;
526 * Translate RX completion flags to packet type.
531 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
534 * Packet type for struct rte_mbuf.
536 static inline uint32_t
537 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
540 uint8_t flags = cqe->l4_hdr_type_etc;
541 uint8_t info = cqe->rsvd0[0];
543 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
546 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
549 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
552 IBV_EXP_CQ_RX_IPV4_PACKET,
553 RTE_PTYPE_INNER_L3_IPV4) |
555 IBV_EXP_CQ_RX_IPV6_PACKET,
556 RTE_PTYPE_INNER_L3_IPV6);
560 MLX5_CQE_L3_HDR_TYPE_IPV6,
563 MLX5_CQE_L3_HDR_TYPE_IPV4,
569 * Get size of the next packet for a given CQE. For compressed CQEs, the
570 * consumer index is updated only once all packets of the current one have
574 * Pointer to RX queue.
579 * Packet size in bytes (0 if there is none), -1 in case of completion
583 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
586 struct rxq_zip *zip = &rxq->zip;
587 uint16_t cqe_n = cqe_cnt + 1;
590 /* Process compressed data in the CQE and mini arrays. */
592 volatile struct mlx5_mini_cqe8 (*mc)[8] =
593 (volatile struct mlx5_mini_cqe8 (*)[8])
594 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
596 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
597 if ((++zip->ai & 7) == 0) {
599 * Increment consumer index to skip the number of
600 * CQEs consumed. Hardware leaves holes in the CQ
601 * ring for software use.
606 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
607 uint16_t idx = rxq->cq_ci;
608 uint16_t end = zip->cq_ci;
611 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
615 rxq->cq_ci = zip->cq_ci;
618 /* No compressed data, get next CQE and verify if it is compressed. */
623 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
624 if (unlikely(ret == 1))
627 op_own = cqe->op_own;
628 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
629 volatile struct mlx5_mini_cqe8 (*mc)[8] =
630 (volatile struct mlx5_mini_cqe8 (*)[8])
631 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
634 /* Fix endianness. */
635 zip->cqe_cnt = ntohl(cqe->byte_cnt);
637 * Current mini array position is the one returned by
640 * If completion comprises several mini arrays, as a
641 * special case the second one is located 7 CQEs after
642 * the initial CQE instead of 8 for subsequent ones.
644 zip->ca = rxq->cq_ci & cqe_cnt;
645 zip->na = zip->ca + 7;
646 /* Compute the next non compressed CQE. */
648 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
649 /* Get packet size to return. */
650 len = ntohl((*mc)[0].byte_cnt);
653 len = ntohl(cqe->byte_cnt);
655 /* Error while receiving packet. */
656 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
663 * Translate RX completion flags to offload flags.
666 * Pointer to RX queue structure.
671 * Offload flags (ol_flags) for struct rte_mbuf.
673 static inline uint32_t
674 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
676 uint32_t ol_flags = 0;
677 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
678 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
679 uint8_t info = cqe->rsvd0[0];
681 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
682 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
684 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
685 PKT_RX_IP_CKSUM_BAD);
686 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
687 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
688 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
689 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
691 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
692 PKT_RX_L4_CKSUM_BAD);
694 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
695 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
698 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
700 TRANSPOSE(~cqe->l4_hdr_type_etc,
701 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
702 PKT_RX_IP_CKSUM_BAD) |
703 TRANSPOSE(~cqe->l4_hdr_type_etc,
704 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
705 PKT_RX_L4_CKSUM_BAD);
710 * DPDK callback for RX.
713 * Generic pointer to RX queue structure.
715 * Array to store received packets.
717 * Maximum number of packets in array.
720 * Number of packets successfully received (<= pkts_n).
723 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
725 struct rxq *rxq = dpdk_rxq;
726 unsigned int pkts_ret = 0;
728 unsigned int rq_ci = rxq->rq_ci;
729 const unsigned int elts_n = rxq->elts_n;
730 const unsigned int wqe_cnt = elts_n - 1;
731 const unsigned int cqe_cnt = rxq->cqe_n - 1;
733 for (i = 0; (i != pkts_n); ++i) {
734 unsigned int idx = rq_ci & wqe_cnt;
736 struct rte_mbuf *rep;
737 struct rte_mbuf *pkt;
738 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
739 volatile struct mlx5_cqe64 *cqe =
740 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
742 pkt = (*rxq->elts)[idx];
744 rep = rte_mbuf_raw_alloc(rxq->mp);
745 if (unlikely(rep == NULL)) {
746 ++rxq->stats.rx_nombuf;
749 SET_DATA_OFF(rep, RTE_PKTMBUF_HEADROOM);
751 PORT(rep) = rxq->port_id;
753 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
754 if (unlikely(len == 0)) {
755 rte_mbuf_refcnt_set(rep, 0);
756 __rte_mbuf_raw_free(rep);
759 if (unlikely(len == -1)) {
760 /* RX error, packet is likely too large. */
761 rte_mbuf_refcnt_set(rep, 0);
762 __rte_mbuf_raw_free(rep);
763 ++rxq->stats.idropped;
768 * Fill NIC descriptor with the new buffer. The lkey and size
769 * of the buffers are already known, only the buffer address
772 wqe->addr = htonll((uintptr_t)rep->buf_addr +
773 RTE_PKTMBUF_HEADROOM);
774 (*rxq->elts)[idx] = rep;
775 /* Update pkt information. */
776 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
779 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
780 pkt->ol_flags = rxq_cq_to_ol_flags(rxq, cqe);
782 if (cqe->l4_hdr_type_etc & MLX5_CQE_VLAN_STRIPPED) {
783 pkt->ol_flags |= PKT_RX_VLAN_PKT |
784 PKT_RX_VLAN_STRIPPED;
785 pkt->vlan_tci = ntohs(cqe->vlan_info);
787 if (rxq->crc_present)
788 len -= ETHER_CRC_LEN;
792 #ifdef MLX5_PMD_SOFT_COUNTERS
793 /* Increment bytes counter. */
794 rxq->stats.ibytes += len;
802 if (unlikely((i == 0) && (rq_ci == rxq->rq_ci)))
806 DEBUG("%p: reposting %u WRs", (void *)rxq, i);
808 /* Update the consumer index. */
811 *rxq->cq_db = htonl(rxq->cq_ci);
813 *rxq->rq_db = htonl(rxq->rq_ci);
814 #ifdef MLX5_PMD_SOFT_COUNTERS
815 /* Increment packets counter. */
816 rxq->stats.ipackets += pkts_ret;
822 * Dummy DPDK callback for TX.
824 * This function is used to temporarily replace the real callback during
825 * unsafe control operations on the queue, or in case of error.
828 * Generic pointer to TX queue structure.
830 * Packets to transmit.
832 * Number of packets in array.
835 * Number of packets successfully transmitted (<= pkts_n).
838 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
847 * Dummy DPDK callback for RX.
849 * This function is used to temporarily replace the real callback during
850 * unsafe control operations on the queue, or in case of error.
853 * Generic pointer to RX queue structure.
855 * Array to store received packets.
857 * Maximum number of packets in array.
860 * Number of packets successfully received (<= pkts_n).
863 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)