4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 ctrl = (volatile struct mlx5_wqe_ctrl *)
242 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
243 elts_tail = ctrl->ctrl3;
244 assert(elts_tail < (1 << txq->wqe_n));
246 while (elts_free != elts_tail) {
247 struct rte_mbuf *elt = (*txq->elts)[elts_free];
248 unsigned int elts_free_next =
249 (elts_free + 1) & (elts_n - 1);
250 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
254 memset(&(*txq->elts)[elts_free],
256 sizeof((*txq->elts)[elts_free]));
258 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
259 /* Only one segment needs to be freed. */
260 rte_pktmbuf_free_seg(elt);
261 elts_free = elts_free_next;
264 txq->elts_tail = elts_tail;
265 /* Update the consumer index. */
267 *txq->cq_db = htonl(cq_ci);
271 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
272 * the cloned mbuf is allocated is returned instead.
278 * Memory pool where data is located for given mbuf.
280 static struct rte_mempool *
281 txq_mb2mp(struct rte_mbuf *buf)
283 if (unlikely(RTE_MBUF_INDIRECT(buf)))
284 return rte_mbuf_from_indirect(buf)->pool;
289 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
290 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
291 * remove an entry first.
294 * Pointer to TX queue structure.
296 * Memory Pool for which a Memory Region lkey must be returned.
299 * mr->lkey on success, (uint32_t)-1 on failure.
301 static inline uint32_t
302 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
305 uint32_t lkey = (uint32_t)-1;
307 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
308 if (unlikely(txq->mp2mr[i].mp == NULL)) {
309 /* Unknown MP, add a new MR for it. */
312 if (txq->mp2mr[i].mp == mp) {
313 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
314 assert(htonl(txq->mp2mr[i].mr->lkey) ==
316 lkey = txq->mp2mr[i].lkey;
320 if (unlikely(lkey == (uint32_t)-1))
321 lkey = txq_mp2mr_reg(txq, mp, i);
326 * Ring TX queue doorbell.
329 * Pointer to TX queue structure.
331 * Pointer to the last WQE posted in the NIC.
334 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
336 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
337 volatile uint64_t *src = ((volatile uint64_t *)wqe);
340 *txq->qp_db = htonl(txq->wqe_ci);
341 /* Ensure ordering between DB record and BF copy. */
347 * DPDK callback for TX.
350 * Generic pointer to TX queue structure.
352 * Packets to transmit.
354 * Number of packets in array.
357 * Number of packets successfully transmitted (<= pkts_n).
360 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
362 struct txq *txq = (struct txq *)dpdk_txq;
363 uint16_t elts_head = txq->elts_head;
364 const unsigned int elts_n = 1 << txq->elts_n;
369 volatile struct mlx5_wqe_v *wqe = NULL;
370 unsigned int segs_n = 0;
371 struct rte_mbuf *buf = NULL;
374 if (unlikely(!pkts_n))
376 /* Prefetch first packet cacheline. */
377 rte_prefetch0(*pkts);
378 /* Start processing. */
380 max = (elts_n - (elts_head - txq->elts_tail));
384 volatile rte_v128u32_t *dseg = NULL;
389 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
391 uint8_t cs_flags = 0;
392 #ifdef MLX5_PMD_SOFT_COUNTERS
393 uint32_t total_length = 0;
398 segs_n = buf->nb_segs;
400 * Make sure there is enough room to store this packet and
401 * that one ring entry remains unused.
404 if (max < segs_n + 1)
410 wqe = (volatile struct mlx5_wqe_v *)
411 tx_mlx5_wqe(txq, txq->wqe_ci);
412 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
414 rte_prefetch0(*pkts);
415 addr = rte_pktmbuf_mtod(buf, uintptr_t);
416 length = DATA_LEN(buf);
417 ehdr = (((uint8_t *)addr)[1] << 8) |
418 ((uint8_t *)addr)[0];
419 #ifdef MLX5_PMD_SOFT_COUNTERS
420 total_length = length;
422 assert(length >= MLX5_WQE_DWORD_SIZE);
423 /* Update element. */
424 (*txq->elts)[elts_head] = buf;
425 elts_head = (elts_head + 1) & (elts_n - 1);
426 /* Prefetch next buffer data. */
428 volatile void *pkt_addr;
430 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
431 rte_prefetch0(pkt_addr);
433 /* Should we enable HW CKSUM offload */
435 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
436 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
438 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
440 * Start by copying the Ethernet header minus the first two
441 * bytes which will be appended at the end of the Ethernet
444 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
445 length -= MLX5_WQE_DWORD_SIZE;
446 addr += MLX5_WQE_DWORD_SIZE;
447 /* Replace the Ethernet type by the VLAN if necessary. */
448 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
449 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
451 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
453 &vlan, sizeof(vlan));
454 addr -= sizeof(vlan);
455 length += sizeof(vlan);
457 /* Inline if enough room. */
458 if (txq->max_inline != 0) {
459 uintptr_t end = (uintptr_t)
460 (((uintptr_t)txq->wqes) +
461 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
462 uint16_t max_inline =
463 txq->max_inline * RTE_CACHE_LINE_SIZE;
467 * raw starts two bytes before the boundary to
468 * continue the above copy of packet data.
470 raw += MLX5_WQE_DWORD_SIZE - 2;
471 room = end - (uintptr_t)raw;
472 if (room > max_inline) {
473 uintptr_t addr_end = (addr + max_inline) &
474 ~(RTE_CACHE_LINE_SIZE - 1);
475 uint16_t copy_b = ((addr_end - addr) > length) ?
479 rte_memcpy((void *)raw, (void *)addr, copy_b);
482 pkt_inline_sz += copy_b;
484 assert(addr <= addr_end);
487 * 2 DWORDs consumed by the WQE header + ETH segment +
488 * the size of the inline part of the packet.
490 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
492 dseg = (volatile rte_v128u32_t *)
494 (ds * MLX5_WQE_DWORD_SIZE));
495 if ((uintptr_t)dseg >= end)
496 dseg = (volatile rte_v128u32_t *)
499 } else if (!segs_n) {
502 /* dseg will be advance as part of next_seg */
503 dseg = (volatile rte_v128u32_t *)
505 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
510 * No inline has been done in the packet, only the
511 * Ethernet Header as been stored.
513 dseg = (volatile rte_v128u32_t *)
514 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
517 /* Add the remaining packet as a simple ds. */
518 naddr = htonll(addr);
519 *dseg = (rte_v128u32_t){
521 txq_mp2mr(txq, txq_mb2mp(buf)),
534 * Spill on next WQE when the current one does not have
535 * enough room left. Size of WQE must a be a multiple
536 * of data segment size.
538 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
539 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
540 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
541 ((1 << txq->wqe_n) - 1);
543 dseg = (volatile rte_v128u32_t *)
545 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
552 length = DATA_LEN(buf);
553 #ifdef MLX5_PMD_SOFT_COUNTERS
554 total_length += length;
556 /* Store segment information. */
557 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
558 *dseg = (rte_v128u32_t){
560 txq_mp2mr(txq, txq_mb2mp(buf)),
564 (*txq->elts)[elts_head] = buf;
565 elts_head = (elts_head + 1) & (elts_n - 1);
574 /* Initialize known and common part of the WQE structure. */
575 wqe->ctrl = (rte_v128u32_t){
576 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
577 htonl(txq->qp_num_8s | ds),
581 wqe->eseg = (rte_v128u32_t){
585 (ehdr << 16) | htons(pkt_inline_sz),
587 txq->wqe_ci += (ds + 3) / 4;
588 #ifdef MLX5_PMD_SOFT_COUNTERS
589 /* Increment sent bytes counter. */
590 txq->stats.obytes += total_length;
593 /* Take a shortcut if nothing must be sent. */
594 if (unlikely(i == 0))
596 /* Check whether completion threshold has been reached. */
597 comp = txq->elts_comp + i + j;
598 if (comp >= MLX5_TX_COMP_THRESH) {
599 volatile struct mlx5_wqe_ctrl *w =
600 (volatile struct mlx5_wqe_ctrl *)wqe;
602 /* Request completion on last WQE. */
604 /* Save elts_head in unused "immediate" field of WQE. */
605 w->ctrl3 = elts_head;
608 txq->elts_comp = comp;
610 #ifdef MLX5_PMD_SOFT_COUNTERS
611 /* Increment sent packets counter. */
612 txq->stats.opackets += i;
614 /* Ring QP doorbell. */
615 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
616 txq->elts_head = elts_head;
621 * Open a MPW session.
624 * Pointer to TX queue structure.
626 * Pointer to MPW session structure.
631 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
633 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
634 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
635 (volatile struct mlx5_wqe_data_seg (*)[])
636 tx_mlx5_wqe(txq, idx + 1);
638 mpw->state = MLX5_MPW_STATE_OPENED;
642 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
643 mpw->wqe->eseg.mss = htons(length);
644 mpw->wqe->eseg.inline_hdr_sz = 0;
645 mpw->wqe->eseg.rsvd0 = 0;
646 mpw->wqe->eseg.rsvd1 = 0;
647 mpw->wqe->eseg.rsvd2 = 0;
648 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
649 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
650 mpw->wqe->ctrl[2] = 0;
651 mpw->wqe->ctrl[3] = 0;
652 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
653 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
654 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
655 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
656 mpw->data.dseg[2] = &(*dseg)[0];
657 mpw->data.dseg[3] = &(*dseg)[1];
658 mpw->data.dseg[4] = &(*dseg)[2];
662 * Close a MPW session.
665 * Pointer to TX queue structure.
667 * Pointer to MPW session structure.
670 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
672 unsigned int num = mpw->pkts_n;
675 * Store size in multiple of 16 bytes. Control and Ethernet segments
678 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
679 mpw->state = MLX5_MPW_STATE_CLOSED;
684 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
685 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
689 * DPDK callback for TX with MPW support.
692 * Generic pointer to TX queue structure.
694 * Packets to transmit.
696 * Number of packets in array.
699 * Number of packets successfully transmitted (<= pkts_n).
702 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
704 struct txq *txq = (struct txq *)dpdk_txq;
705 uint16_t elts_head = txq->elts_head;
706 const unsigned int elts_n = 1 << txq->elts_n;
711 struct mlx5_mpw mpw = {
712 .state = MLX5_MPW_STATE_CLOSED,
715 if (unlikely(!pkts_n))
717 /* Prefetch first packet cacheline. */
718 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
719 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
720 /* Start processing. */
722 max = (elts_n - (elts_head - txq->elts_tail));
726 struct rte_mbuf *buf = *(pkts++);
727 unsigned int elts_head_next;
729 unsigned int segs_n = buf->nb_segs;
730 uint32_t cs_flags = 0;
733 * Make sure there is enough room to store this packet and
734 * that one ring entry remains unused.
737 if (max < segs_n + 1)
739 /* Do not bother with large packets MPW cannot handle. */
740 if (segs_n > MLX5_MPW_DSEG_MAX)
744 /* Should we enable HW CKSUM offload */
746 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
747 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
748 /* Retrieve packet information. */
749 length = PKT_LEN(buf);
751 /* Start new session if packet differs. */
752 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
753 ((mpw.len != length) ||
755 (mpw.wqe->eseg.cs_flags != cs_flags)))
756 mlx5_mpw_close(txq, &mpw);
757 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
758 mlx5_mpw_new(txq, &mpw, length);
759 mpw.wqe->eseg.cs_flags = cs_flags;
761 /* Multi-segment packets must be alone in their MPW. */
762 assert((segs_n == 1) || (mpw.pkts_n == 0));
763 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
767 volatile struct mlx5_wqe_data_seg *dseg;
770 elts_head_next = (elts_head + 1) & (elts_n - 1);
772 (*txq->elts)[elts_head] = buf;
773 dseg = mpw.data.dseg[mpw.pkts_n];
774 addr = rte_pktmbuf_mtod(buf, uintptr_t);
775 *dseg = (struct mlx5_wqe_data_seg){
776 .byte_count = htonl(DATA_LEN(buf)),
777 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
778 .addr = htonll(addr),
780 elts_head = elts_head_next;
781 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
782 length += DATA_LEN(buf);
788 assert(length == mpw.len);
789 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
790 mlx5_mpw_close(txq, &mpw);
791 elts_head = elts_head_next;
792 #ifdef MLX5_PMD_SOFT_COUNTERS
793 /* Increment sent bytes counter. */
794 txq->stats.obytes += length;
798 /* Take a shortcut if nothing must be sent. */
799 if (unlikely(i == 0))
801 /* Check whether completion threshold has been reached. */
802 /* "j" includes both packets and segments. */
803 comp = txq->elts_comp + j;
804 if (comp >= MLX5_TX_COMP_THRESH) {
805 volatile struct mlx5_wqe *wqe = mpw.wqe;
807 /* Request completion on last WQE. */
808 wqe->ctrl[2] = htonl(8);
809 /* Save elts_head in unused "immediate" field of WQE. */
810 wqe->ctrl[3] = elts_head;
813 txq->elts_comp = comp;
815 #ifdef MLX5_PMD_SOFT_COUNTERS
816 /* Increment sent packets counter. */
817 txq->stats.opackets += i;
819 /* Ring QP doorbell. */
820 if (mpw.state == MLX5_MPW_STATE_OPENED)
821 mlx5_mpw_close(txq, &mpw);
822 mlx5_tx_dbrec(txq, mpw.wqe);
823 txq->elts_head = elts_head;
828 * Open a MPW inline session.
831 * Pointer to TX queue structure.
833 * Pointer to MPW session structure.
838 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
840 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
841 struct mlx5_wqe_inl_small *inl;
843 mpw->state = MLX5_MPW_INL_STATE_OPENED;
847 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
848 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
851 mpw->wqe->ctrl[2] = 0;
852 mpw->wqe->ctrl[3] = 0;
853 mpw->wqe->eseg.mss = htons(length);
854 mpw->wqe->eseg.inline_hdr_sz = 0;
855 mpw->wqe->eseg.cs_flags = 0;
856 mpw->wqe->eseg.rsvd0 = 0;
857 mpw->wqe->eseg.rsvd1 = 0;
858 mpw->wqe->eseg.rsvd2 = 0;
859 inl = (struct mlx5_wqe_inl_small *)
860 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
861 mpw->data.raw = (uint8_t *)&inl->raw;
865 * Close a MPW inline session.
868 * Pointer to TX queue structure.
870 * Pointer to MPW session structure.
873 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
876 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
877 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
879 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
881 * Store size in multiple of 16 bytes. Control and Ethernet segments
884 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
885 mpw->state = MLX5_MPW_STATE_CLOSED;
886 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
887 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
891 * DPDK callback for TX with MPW inline support.
894 * Generic pointer to TX queue structure.
896 * Packets to transmit.
898 * Number of packets in array.
901 * Number of packets successfully transmitted (<= pkts_n).
904 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
907 struct txq *txq = (struct txq *)dpdk_txq;
908 uint16_t elts_head = txq->elts_head;
909 const unsigned int elts_n = 1 << txq->elts_n;
914 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
915 struct mlx5_mpw mpw = {
916 .state = MLX5_MPW_STATE_CLOSED,
919 if (unlikely(!pkts_n))
921 /* Prefetch first packet cacheline. */
922 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
923 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
924 /* Start processing. */
926 max = (elts_n - (elts_head - txq->elts_tail));
930 struct rte_mbuf *buf = *(pkts++);
931 unsigned int elts_head_next;
934 unsigned int segs_n = buf->nb_segs;
935 uint32_t cs_flags = 0;
938 * Make sure there is enough room to store this packet and
939 * that one ring entry remains unused.
942 if (max < segs_n + 1)
944 /* Do not bother with large packets MPW cannot handle. */
945 if (segs_n > MLX5_MPW_DSEG_MAX)
949 /* Should we enable HW CKSUM offload */
951 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
952 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
953 /* Retrieve packet information. */
954 length = PKT_LEN(buf);
955 /* Start new session if packet differs. */
956 if (mpw.state == MLX5_MPW_STATE_OPENED) {
957 if ((mpw.len != length) ||
959 (mpw.wqe->eseg.cs_flags != cs_flags))
960 mlx5_mpw_close(txq, &mpw);
961 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
962 if ((mpw.len != length) ||
964 (length > inline_room) ||
965 (mpw.wqe->eseg.cs_flags != cs_flags)) {
966 mlx5_mpw_inline_close(txq, &mpw);
968 txq->max_inline * RTE_CACHE_LINE_SIZE;
971 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
973 (length > inline_room)) {
974 mlx5_mpw_new(txq, &mpw, length);
975 mpw.wqe->eseg.cs_flags = cs_flags;
977 mlx5_mpw_inline_new(txq, &mpw, length);
978 mpw.wqe->eseg.cs_flags = cs_flags;
981 /* Multi-segment packets must be alone in their MPW. */
982 assert((segs_n == 1) || (mpw.pkts_n == 0));
983 if (mpw.state == MLX5_MPW_STATE_OPENED) {
984 assert(inline_room ==
985 txq->max_inline * RTE_CACHE_LINE_SIZE);
986 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
990 volatile struct mlx5_wqe_data_seg *dseg;
993 (elts_head + 1) & (elts_n - 1);
995 (*txq->elts)[elts_head] = buf;
996 dseg = mpw.data.dseg[mpw.pkts_n];
997 addr = rte_pktmbuf_mtod(buf, uintptr_t);
998 *dseg = (struct mlx5_wqe_data_seg){
999 .byte_count = htonl(DATA_LEN(buf)),
1000 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1001 .addr = htonll(addr),
1003 elts_head = elts_head_next;
1004 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1005 length += DATA_LEN(buf);
1011 assert(length == mpw.len);
1012 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1013 mlx5_mpw_close(txq, &mpw);
1017 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1018 assert(length <= inline_room);
1019 assert(length == DATA_LEN(buf));
1020 elts_head_next = (elts_head + 1) & (elts_n - 1);
1021 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1022 (*txq->elts)[elts_head] = buf;
1023 /* Maximum number of bytes before wrapping. */
1024 max = ((((uintptr_t)(txq->wqes)) +
1027 (uintptr_t)mpw.data.raw);
1029 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1032 mpw.data.raw = (volatile void *)txq->wqes;
1033 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1034 (void *)(addr + max),
1036 mpw.data.raw += length - max;
1038 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1041 mpw.data.raw += length;
1043 if ((uintptr_t)mpw.data.raw ==
1044 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1045 mpw.data.raw = (volatile void *)txq->wqes;
1048 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1049 mlx5_mpw_inline_close(txq, &mpw);
1051 txq->max_inline * RTE_CACHE_LINE_SIZE;
1053 inline_room -= length;
1056 mpw.total_len += length;
1057 elts_head = elts_head_next;
1058 #ifdef MLX5_PMD_SOFT_COUNTERS
1059 /* Increment sent bytes counter. */
1060 txq->stats.obytes += length;
1064 /* Take a shortcut if nothing must be sent. */
1065 if (unlikely(i == 0))
1067 /* Check whether completion threshold has been reached. */
1068 /* "j" includes both packets and segments. */
1069 comp = txq->elts_comp + j;
1070 if (comp >= MLX5_TX_COMP_THRESH) {
1071 volatile struct mlx5_wqe *wqe = mpw.wqe;
1073 /* Request completion on last WQE. */
1074 wqe->ctrl[2] = htonl(8);
1075 /* Save elts_head in unused "immediate" field of WQE. */
1076 wqe->ctrl[3] = elts_head;
1079 txq->elts_comp = comp;
1081 #ifdef MLX5_PMD_SOFT_COUNTERS
1082 /* Increment sent packets counter. */
1083 txq->stats.opackets += i;
1085 /* Ring QP doorbell. */
1086 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1087 mlx5_mpw_inline_close(txq, &mpw);
1088 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1089 mlx5_mpw_close(txq, &mpw);
1090 mlx5_tx_dbrec(txq, mpw.wqe);
1091 txq->elts_head = elts_head;
1096 * Translate RX completion flags to packet type.
1101 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1104 * Packet type for struct rte_mbuf.
1106 static inline uint32_t
1107 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1110 uint8_t flags = cqe->l4_hdr_type_etc;
1112 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1115 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1116 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
1118 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1119 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1121 MLX5_CQE_RX_IPV4_PACKET,
1122 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1124 MLX5_CQE_RX_IPV6_PACKET,
1125 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1129 MLX5_CQE_L3_HDR_TYPE_IPV6,
1130 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1132 MLX5_CQE_L3_HDR_TYPE_IPV4,
1133 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1138 * Get size of the next packet for a given CQE. For compressed CQEs, the
1139 * consumer index is updated only once all packets of the current one have
1143 * Pointer to RX queue.
1146 * @param[out] rss_hash
1147 * Packet RSS Hash result.
1150 * Packet size in bytes (0 if there is none), -1 in case of completion
1154 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1155 uint16_t cqe_cnt, uint32_t *rss_hash)
1157 struct rxq_zip *zip = &rxq->zip;
1158 uint16_t cqe_n = cqe_cnt + 1;
1161 /* Process compressed data in the CQE and mini arrays. */
1163 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1164 (volatile struct mlx5_mini_cqe8 (*)[8])
1165 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1167 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1168 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1169 if ((++zip->ai & 7) == 0) {
1171 * Increment consumer index to skip the number of
1172 * CQEs consumed. Hardware leaves holes in the CQ
1173 * ring for software use.
1178 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1179 uint16_t idx = rxq->cq_ci + 1;
1180 uint16_t end = zip->cq_ci;
1182 while (idx != end) {
1183 (*rxq->cqes)[idx & cqe_cnt].op_own =
1184 MLX5_CQE_INVALIDATE;
1187 rxq->cq_ci = zip->cq_ci;
1190 /* No compressed data, get next CQE and verify if it is compressed. */
1195 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1196 if (unlikely(ret == 1))
1199 op_own = cqe->op_own;
1200 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1201 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1202 (volatile struct mlx5_mini_cqe8 (*)[8])
1203 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1206 /* Fix endianness. */
1207 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1209 * Current mini array position is the one returned by
1212 * If completion comprises several mini arrays, as a
1213 * special case the second one is located 7 CQEs after
1214 * the initial CQE instead of 8 for subsequent ones.
1216 zip->ca = rxq->cq_ci & cqe_cnt;
1217 zip->na = zip->ca + 7;
1218 /* Compute the next non compressed CQE. */
1220 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1221 /* Get packet size to return. */
1222 len = ntohl((*mc)[0].byte_cnt);
1223 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1226 len = ntohl(cqe->byte_cnt);
1227 *rss_hash = ntohl(cqe->rx_hash_res);
1229 /* Error while receiving packet. */
1230 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1237 * Translate RX completion flags to offload flags.
1240 * Pointer to RX queue structure.
1245 * Offload flags (ol_flags) for struct rte_mbuf.
1247 static inline uint32_t
1248 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1250 uint32_t ol_flags = 0;
1251 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1252 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1254 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1255 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1256 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1258 PKT_RX_IP_CKSUM_GOOD);
1259 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1260 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1261 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1262 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1263 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1265 PKT_RX_L4_CKSUM_GOOD);
1266 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1268 TRANSPOSE(cqe->l4_hdr_type_etc,
1269 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1270 PKT_RX_IP_CKSUM_GOOD) |
1271 TRANSPOSE(cqe->l4_hdr_type_etc,
1272 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1273 PKT_RX_L4_CKSUM_GOOD);
1278 * DPDK callback for RX.
1281 * Generic pointer to RX queue structure.
1283 * Array to store received packets.
1285 * Maximum number of packets in array.
1288 * Number of packets successfully received (<= pkts_n).
1291 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1293 struct rxq *rxq = dpdk_rxq;
1294 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1295 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1296 const unsigned int sges_n = rxq->sges_n;
1297 struct rte_mbuf *pkt = NULL;
1298 struct rte_mbuf *seg = NULL;
1299 volatile struct mlx5_cqe *cqe =
1300 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1302 unsigned int rq_ci = rxq->rq_ci << sges_n;
1303 int len; /* keep its value across iterations. */
1306 unsigned int idx = rq_ci & wqe_cnt;
1307 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1308 struct rte_mbuf *rep = (*rxq->elts)[idx];
1309 uint32_t rss_hash_res = 0;
1317 rep = rte_mbuf_raw_alloc(rxq->mp);
1318 if (unlikely(rep == NULL)) {
1319 ++rxq->stats.rx_nombuf;
1322 * no buffers before we even started,
1323 * bail out silently.
1327 while (pkt != seg) {
1328 assert(pkt != (*rxq->elts)[idx]);
1330 rte_mbuf_refcnt_set(pkt, 0);
1331 __rte_mbuf_raw_free(pkt);
1337 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1338 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1341 rte_mbuf_refcnt_set(rep, 0);
1342 __rte_mbuf_raw_free(rep);
1345 if (unlikely(len == -1)) {
1346 /* RX error, packet is likely too large. */
1347 rte_mbuf_refcnt_set(rep, 0);
1348 __rte_mbuf_raw_free(rep);
1349 ++rxq->stats.idropped;
1353 assert(len >= (rxq->crc_present << 2));
1354 /* Update packet information. */
1355 pkt->packet_type = 0;
1357 if (rss_hash_res && rxq->rss_hash) {
1358 pkt->hash.rss = rss_hash_res;
1359 pkt->ol_flags = PKT_RX_RSS_HASH;
1362 ((cqe->sop_drop_qpn !=
1363 htonl(MLX5_FLOW_MARK_INVALID)) ||
1364 (cqe->sop_drop_qpn !=
1365 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1367 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1368 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1369 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1371 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1375 rxq_cq_to_pkt_type(cqe);
1377 rxq_cq_to_ol_flags(rxq, cqe);
1379 if (cqe->l4_hdr_type_etc &
1380 MLX5_CQE_VLAN_STRIPPED) {
1381 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1382 PKT_RX_VLAN_STRIPPED;
1383 pkt->vlan_tci = ntohs(cqe->vlan_info);
1385 if (rxq->crc_present)
1386 len -= ETHER_CRC_LEN;
1390 DATA_LEN(rep) = DATA_LEN(seg);
1391 PKT_LEN(rep) = PKT_LEN(seg);
1392 SET_DATA_OFF(rep, DATA_OFF(seg));
1393 NB_SEGS(rep) = NB_SEGS(seg);
1394 PORT(rep) = PORT(seg);
1396 (*rxq->elts)[idx] = rep;
1398 * Fill NIC descriptor with the new buffer. The lkey and size
1399 * of the buffers are already known, only the buffer address
1402 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1403 if (len > DATA_LEN(seg)) {
1404 len -= DATA_LEN(seg);
1409 DATA_LEN(seg) = len;
1410 #ifdef MLX5_PMD_SOFT_COUNTERS
1411 /* Increment bytes counter. */
1412 rxq->stats.ibytes += PKT_LEN(pkt);
1414 /* Return packet. */
1420 /* Align consumer index to the next stride. */
1425 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1427 /* Update the consumer index. */
1428 rxq->rq_ci = rq_ci >> sges_n;
1430 *rxq->cq_db = htonl(rxq->cq_ci);
1432 *rxq->rq_db = htonl(rxq->rq_ci);
1433 #ifdef MLX5_PMD_SOFT_COUNTERS
1434 /* Increment packets counter. */
1435 rxq->stats.ipackets += i;
1441 * Dummy DPDK callback for TX.
1443 * This function is used to temporarily replace the real callback during
1444 * unsafe control operations on the queue, or in case of error.
1447 * Generic pointer to TX queue structure.
1449 * Packets to transmit.
1451 * Number of packets in array.
1454 * Number of packets successfully transmitted (<= pkts_n).
1457 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1466 * Dummy DPDK callback for RX.
1468 * This function is used to temporarily replace the real callback during
1469 * unsafe control operations on the queue, or in case of error.
1472 * Generic pointer to RX queue structure.
1474 * Array to store received packets.
1476 * Maximum number of packets in array.
1479 * Number of packets successfully received (<= pkts_n).
1482 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)