1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
46 static __rte_always_inline void
47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
50 static __rte_always_inline void
51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
54 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
61 * Build a table to translate Rx completion flags to packet type.
63 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
66 mlx5_set_ptype_table(void)
69 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
71 /* Last entry must not be overwritten, reserved for errored packet. */
72 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
73 (*p)[i] = RTE_PTYPE_UNKNOWN;
75 * The index to the array should have:
76 * bit[1:0] = l3_hdr_type
77 * bit[4:2] = l4_hdr_type
80 * bit[7] = outer_l3_type
83 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
85 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
90 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
92 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
95 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
97 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
99 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
101 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
103 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
105 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
108 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 /* Repeat with outer_l3_type being set. Just in case. */
113 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 RTE_PTYPE_L4_NONFRAG;
115 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 RTE_PTYPE_L4_NONFRAG;
117 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
193 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L4_TCP;
196 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
199 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_TCP;
203 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
206 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_UDP;
209 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_UDP;
212 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_UDP;
218 * Build a table to translate packet to checksum type of Verbs.
221 mlx5_set_cksum_table(void)
227 * The index should have:
228 * bit[0] = PKT_TX_TCP_SEG
229 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
230 * bit[4] = PKT_TX_IP_CKSUM
231 * bit[8] = PKT_TX_OUTER_IP_CKSUM
234 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
237 /* Tunneled packet. */
238 if (i & (1 << 8)) /* Outer IP. */
239 v |= MLX5_ETH_WQE_L3_CSUM;
240 if (i & (1 << 4)) /* Inner IP. */
241 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
242 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
243 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
246 if (i & (1 << 4)) /* IP. */
247 v |= MLX5_ETH_WQE_L3_CSUM;
248 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
249 v |= MLX5_ETH_WQE_L4_CSUM;
251 mlx5_cksum_table[i] = v;
256 * Build a table to translate packet type of mbuf to SWP type of Verbs.
259 mlx5_set_swp_types_table(void)
265 * The index should have:
266 * bit[0:1] = PKT_TX_L4_MASK
267 * bit[4] = PKT_TX_IPV6
268 * bit[8] = PKT_TX_OUTER_IPV6
269 * bit[9] = PKT_TX_OUTER_UDP
271 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
274 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
276 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
278 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
279 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
280 v |= MLX5_ETH_WQE_L4_INNER_UDP;
281 mlx5_swp_types_table[i] = v;
286 * Return the size of tailroom of WQ.
289 * Pointer to TX queue structure.
291 * Pointer to tail of WQ.
297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
300 tailroom = (uintptr_t)(txq->wqes) +
301 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
307 * Copy data to tailroom of circular queue.
310 * Pointer to destination.
314 * Number of bytes to copy.
316 * Pointer to head of queue.
318 * Size of tailroom from dst.
321 * Pointer after copied data.
324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
325 void *base, size_t tailroom)
330 rte_memcpy(dst, src, tailroom);
331 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
333 ret = (uint8_t *)base + n - tailroom;
335 rte_memcpy(dst, src, n);
336 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
342 * Inline TSO headers into WQE.
345 * 0 on success, negative errno value on failure.
348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
351 uint16_t *pkt_inline_sz,
355 uint16_t *tso_header_sz)
357 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
358 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
360 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
361 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
365 *tso_segsz = buf->tso_segsz;
366 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
367 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
368 txq->stats.oerrors++;
372 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
373 /* First seg must contain all TSO headers. */
374 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
375 *tso_header_sz > DATA_LEN(buf)) {
376 txq->stats.oerrors++;
379 copy_b = *tso_header_sz - *pkt_inline_sz;
380 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
382 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
383 if (unlikely(*max_wqe < n_wqe))
386 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
389 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
390 *pkt_inline_sz += copy_b;
396 * DPDK callback to check the status of a tx descriptor.
401 * The index of the descriptor in the ring.
404 * The status of the tx descriptor.
407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
409 struct mlx5_txq_data *txq = tx_queue;
412 mlx5_tx_complete(txq);
413 used = txq->elts_head - txq->elts_tail;
415 return RTE_ETH_TX_DESC_FULL;
416 return RTE_ETH_TX_DESC_DONE;
420 * Internal function to compute the number of used descriptors in an RX queue
426 * The number of used rx descriptor.
429 rx_queue_count(struct mlx5_rxq_data *rxq)
431 struct rxq_zip *zip = &rxq->zip;
432 volatile struct mlx5_cqe *cqe;
433 const unsigned int cqe_n = (1 << rxq->cqe_n);
434 const unsigned int cqe_cnt = cqe_n - 1;
438 /* if we are processing a compressed cqe */
440 used = zip->cqe_cnt - zip->ca;
446 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
447 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
451 op_own = cqe->op_own;
452 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
453 n = rte_be_to_cpu_32(cqe->byte_cnt);
458 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
465 * DPDK callback to check the status of a rx descriptor.
470 * The index of the descriptor in the ring.
473 * The status of the tx descriptor.
476 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
478 struct mlx5_rxq_data *rxq = rx_queue;
479 struct mlx5_rxq_ctrl *rxq_ctrl =
480 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
481 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
483 if (dev->rx_pkt_burst != mlx5_rx_burst) {
487 if (offset >= (1 << rxq->elts_n)) {
491 if (offset < rx_queue_count(rxq))
492 return RTE_ETH_RX_DESC_DONE;
493 return RTE_ETH_RX_DESC_AVAIL;
497 * DPDK callback to get the number of used descriptors in a RX queue
500 * Pointer to the device structure.
506 * The number of used rx descriptor.
507 * -EINVAL if the queue is invalid
510 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
512 struct priv *priv = dev->data->dev_private;
513 struct mlx5_rxq_data *rxq;
515 if (dev->rx_pkt_burst != mlx5_rx_burst) {
519 rxq = (*priv->rxqs)[rx_queue_id];
524 return rx_queue_count(rxq);
528 * DPDK callback for TX.
531 * Generic pointer to TX queue structure.
533 * Packets to transmit.
535 * Number of packets in array.
538 * Number of packets successfully transmitted (<= pkts_n).
541 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
543 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
544 uint16_t elts_head = txq->elts_head;
545 const uint16_t elts_n = 1 << txq->elts_n;
546 const uint16_t elts_m = elts_n - 1;
553 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
554 unsigned int segs_n = 0;
555 const unsigned int max_inline = txq->max_inline;
558 if (unlikely(!pkts_n))
560 /* Prefetch first packet cacheline. */
561 rte_prefetch0(*pkts);
562 /* Start processing. */
563 mlx5_tx_complete(txq);
564 max_elts = (elts_n - (elts_head - txq->elts_tail));
565 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
566 if (unlikely(!max_wqe))
569 struct rte_mbuf *buf = *pkts; /* First_seg. */
571 volatile struct mlx5_wqe_v *wqe = NULL;
572 volatile rte_v128u32_t *dseg = NULL;
575 unsigned int sg = 0; /* counter of additional segs attached. */
577 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
578 uint16_t tso_header_sz = 0;
581 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
582 uint32_t swp_offsets = 0;
583 uint8_t swp_types = 0;
585 uint16_t tso_segsz = 0;
586 #ifdef MLX5_PMD_SOFT_COUNTERS
587 uint32_t total_length = 0;
591 segs_n = buf->nb_segs;
593 * Make sure there is enough room to store this packet and
594 * that one ring entry remains unused.
597 if (max_elts < segs_n)
601 if (unlikely(--max_wqe == 0))
603 wqe = (volatile struct mlx5_wqe_v *)
604 tx_mlx5_wqe(txq, txq->wqe_ci);
605 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
607 rte_prefetch0(*(pkts + 1));
608 addr = rte_pktmbuf_mtod(buf, uintptr_t);
609 length = DATA_LEN(buf);
610 ehdr = (((uint8_t *)addr)[1] << 8) |
611 ((uint8_t *)addr)[0];
612 #ifdef MLX5_PMD_SOFT_COUNTERS
613 total_length = length;
615 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
616 txq->stats.oerrors++;
619 /* Update element. */
620 (*txq->elts)[elts_head & elts_m] = buf;
621 /* Prefetch next buffer data. */
624 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
625 cs_flags = txq_ol_cksum_to_cs(buf);
626 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
627 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
628 /* Copy metadata from mbuf if valid */
629 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
631 /* Replace the Ethernet type by the VLAN if necessary. */
632 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
633 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
635 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
639 /* Copy Destination and source mac address. */
640 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
642 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
643 /* Copy missing two bytes to end the DSeg. */
644 memcpy((uint8_t *)raw + len + sizeof(vlan),
645 ((uint8_t *)addr) + len, 2);
649 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
650 MLX5_WQE_DWORD_SIZE);
651 length -= pkt_inline_sz;
652 addr += pkt_inline_sz;
654 raw += MLX5_WQE_DWORD_SIZE;
656 ret = inline_tso(txq, buf, &length,
657 &addr, &pkt_inline_sz,
659 &tso_segsz, &tso_header_sz);
660 if (ret == -EINVAL) {
662 } else if (ret == -EAGAIN) {
664 wqe->ctrl = (rte_v128u32_t){
665 rte_cpu_to_be_32(txq->wqe_ci << 8),
666 rte_cpu_to_be_32(txq->qp_num_8s | 1),
671 #ifdef MLX5_PMD_SOFT_COUNTERS
678 /* Inline if enough room. */
679 if (max_inline || tso) {
681 uintptr_t end = (uintptr_t)
682 (((uintptr_t)txq->wqes) +
683 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
684 unsigned int inline_room = max_inline *
685 RTE_CACHE_LINE_SIZE -
686 (pkt_inline_sz - 2) -
692 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
693 RTE_CACHE_LINE_SIZE);
694 copy_b = (addr_end > addr) ?
695 RTE_MIN((addr_end - addr), length) : 0;
696 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
698 * One Dseg remains in the current WQE. To
699 * keep the computation positive, it is
700 * removed after the bytes to Dseg conversion.
702 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
704 if (unlikely(max_wqe < n))
709 inl = rte_cpu_to_be_32(copy_b |
711 rte_memcpy((void *)raw,
712 (void *)&inl, sizeof(inl));
714 pkt_inline_sz += sizeof(inl);
716 rte_memcpy((void *)raw, (void *)addr, copy_b);
719 pkt_inline_sz += copy_b;
722 * 2 DWORDs consumed by the WQE header + ETH segment +
723 * the size of the inline part of the packet.
725 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
727 if (ds % (MLX5_WQE_SIZE /
728 MLX5_WQE_DWORD_SIZE) == 0) {
729 if (unlikely(--max_wqe == 0))
731 dseg = (volatile rte_v128u32_t *)
732 tx_mlx5_wqe(txq, txq->wqe_ci +
735 dseg = (volatile rte_v128u32_t *)
737 (ds * MLX5_WQE_DWORD_SIZE));
740 } else if (!segs_n) {
744 * Further inline the next segment only for
749 inline_room -= copy_b;
753 /* Move to the next segment. */
757 addr = rte_pktmbuf_mtod(buf, uintptr_t);
758 length = DATA_LEN(buf);
759 #ifdef MLX5_PMD_SOFT_COUNTERS
760 total_length += length;
762 (*txq->elts)[++elts_head & elts_m] = buf;
767 * No inline has been done in the packet, only the
768 * Ethernet Header as been stored.
770 dseg = (volatile rte_v128u32_t *)
771 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
774 /* Add the remaining packet as a simple ds. */
775 addr_64 = rte_cpu_to_be_64(addr);
776 *dseg = (rte_v128u32_t){
777 rte_cpu_to_be_32(length),
778 mlx5_tx_mb2mr(txq, buf),
791 * Spill on next WQE when the current one does not have
792 * enough room left. Size of WQE must a be a multiple
793 * of data segment size.
795 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
796 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
797 if (unlikely(--max_wqe == 0))
799 dseg = (volatile rte_v128u32_t *)
800 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
801 rte_prefetch0(tx_mlx5_wqe(txq,
802 txq->wqe_ci + ds / 4 + 1));
809 length = DATA_LEN(buf);
810 #ifdef MLX5_PMD_SOFT_COUNTERS
811 total_length += length;
813 /* Store segment information. */
814 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
815 *dseg = (rte_v128u32_t){
816 rte_cpu_to_be_32(length),
817 mlx5_tx_mb2mr(txq, buf),
821 (*txq->elts)[++elts_head & elts_m] = buf;
825 if (ds > MLX5_DSEG_MAX) {
826 txq->stats.oerrors++;
833 /* Initialize known and common part of the WQE structure. */
835 wqe->ctrl = (rte_v128u32_t){
836 rte_cpu_to_be_32((txq->wqe_ci << 8) |
838 rte_cpu_to_be_32(txq->qp_num_8s | ds),
842 wqe->eseg = (rte_v128u32_t){
844 cs_flags | (swp_types << 8) |
845 (rte_cpu_to_be_16(tso_segsz) << 16),
847 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
850 wqe->ctrl = (rte_v128u32_t){
851 rte_cpu_to_be_32((txq->wqe_ci << 8) |
853 rte_cpu_to_be_32(txq->qp_num_8s | ds),
857 wqe->eseg = (rte_v128u32_t){
859 cs_flags | (swp_types << 8),
861 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
865 txq->wqe_ci += (ds + 3) / 4;
866 /* Save the last successful WQE for completion request */
867 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
868 #ifdef MLX5_PMD_SOFT_COUNTERS
869 /* Increment sent bytes counter. */
870 txq->stats.obytes += total_length;
872 } while (i < pkts_n);
873 /* Take a shortcut if nothing must be sent. */
874 if (unlikely((i + k) == 0))
876 txq->elts_head += (i + j);
877 /* Check whether completion threshold has been reached. */
878 comp = txq->elts_comp + i + j + k;
879 if (comp >= MLX5_TX_COMP_THRESH) {
880 /* A CQE slot must always be available. */
881 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
882 /* Request completion on last WQE. */
883 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
884 /* Save elts_head in unused "immediate" field of WQE. */
885 last_wqe->ctrl3 = txq->elts_head;
888 txq->elts_comp = comp;
890 #ifdef MLX5_PMD_SOFT_COUNTERS
891 /* Increment sent packets counter. */
892 txq->stats.opackets += i;
894 /* Ring QP doorbell. */
895 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
900 * Open a MPW session.
903 * Pointer to TX queue structure.
905 * Pointer to MPW session structure.
910 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
912 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
913 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
914 (volatile struct mlx5_wqe_data_seg (*)[])
915 tx_mlx5_wqe(txq, idx + 1);
917 mpw->state = MLX5_MPW_STATE_OPENED;
921 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
922 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
923 mpw->wqe->eseg.inline_hdr_sz = 0;
924 mpw->wqe->eseg.rsvd0 = 0;
925 mpw->wqe->eseg.rsvd1 = 0;
926 mpw->wqe->eseg.flow_table_metadata = 0;
927 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
930 mpw->wqe->ctrl[2] = 0;
931 mpw->wqe->ctrl[3] = 0;
932 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
933 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
934 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
935 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
936 mpw->data.dseg[2] = &(*dseg)[0];
937 mpw->data.dseg[3] = &(*dseg)[1];
938 mpw->data.dseg[4] = &(*dseg)[2];
942 * Close a MPW session.
945 * Pointer to TX queue structure.
947 * Pointer to MPW session structure.
950 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
952 unsigned int num = mpw->pkts_n;
955 * Store size in multiple of 16 bytes. Control and Ethernet segments
958 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
959 mpw->state = MLX5_MPW_STATE_CLOSED;
964 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
965 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
969 * DPDK callback for TX with MPW support.
972 * Generic pointer to TX queue structure.
974 * Packets to transmit.
976 * Number of packets in array.
979 * Number of packets successfully transmitted (<= pkts_n).
982 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
984 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
985 uint16_t elts_head = txq->elts_head;
986 const uint16_t elts_n = 1 << txq->elts_n;
987 const uint16_t elts_m = elts_n - 1;
993 struct mlx5_mpw mpw = {
994 .state = MLX5_MPW_STATE_CLOSED,
997 if (unlikely(!pkts_n))
999 /* Prefetch first packet cacheline. */
1000 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1001 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1002 /* Start processing. */
1003 mlx5_tx_complete(txq);
1004 max_elts = (elts_n - (elts_head - txq->elts_tail));
1005 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1006 if (unlikely(!max_wqe))
1009 struct rte_mbuf *buf = *(pkts++);
1011 unsigned int segs_n = buf->nb_segs;
1013 rte_be32_t metadata;
1016 * Make sure there is enough room to store this packet and
1017 * that one ring entry remains unused.
1020 if (max_elts < segs_n)
1022 /* Do not bother with large packets MPW cannot handle. */
1023 if (segs_n > MLX5_MPW_DSEG_MAX) {
1024 txq->stats.oerrors++;
1029 cs_flags = txq_ol_cksum_to_cs(buf);
1030 /* Copy metadata from mbuf if valid */
1031 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1033 /* Retrieve packet information. */
1034 length = PKT_LEN(buf);
1036 /* Start new session if packet differs. */
1037 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1038 ((mpw.len != length) ||
1040 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1041 (mpw.wqe->eseg.cs_flags != cs_flags)))
1042 mlx5_mpw_close(txq, &mpw);
1043 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1045 * Multi-Packet WQE consumes at most two WQE.
1046 * mlx5_mpw_new() expects to be able to use such
1049 if (unlikely(max_wqe < 2))
1052 mlx5_mpw_new(txq, &mpw, length);
1053 mpw.wqe->eseg.cs_flags = cs_flags;
1054 mpw.wqe->eseg.flow_table_metadata = metadata;
1056 /* Multi-segment packets must be alone in their MPW. */
1057 assert((segs_n == 1) || (mpw.pkts_n == 0));
1058 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1062 volatile struct mlx5_wqe_data_seg *dseg;
1066 (*txq->elts)[elts_head++ & elts_m] = buf;
1067 dseg = mpw.data.dseg[mpw.pkts_n];
1068 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1069 *dseg = (struct mlx5_wqe_data_seg){
1070 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1071 .lkey = mlx5_tx_mb2mr(txq, buf),
1072 .addr = rte_cpu_to_be_64(addr),
1074 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1075 length += DATA_LEN(buf);
1081 assert(length == mpw.len);
1082 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1083 mlx5_mpw_close(txq, &mpw);
1084 #ifdef MLX5_PMD_SOFT_COUNTERS
1085 /* Increment sent bytes counter. */
1086 txq->stats.obytes += length;
1090 /* Take a shortcut if nothing must be sent. */
1091 if (unlikely(i == 0))
1093 /* Check whether completion threshold has been reached. */
1094 /* "j" includes both packets and segments. */
1095 comp = txq->elts_comp + j;
1096 if (comp >= MLX5_TX_COMP_THRESH) {
1097 volatile struct mlx5_wqe *wqe = mpw.wqe;
1099 /* A CQE slot must always be available. */
1100 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1101 /* Request completion on last WQE. */
1102 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1103 /* Save elts_head in unused "immediate" field of WQE. */
1104 wqe->ctrl[3] = elts_head;
1107 txq->elts_comp = comp;
1109 #ifdef MLX5_PMD_SOFT_COUNTERS
1110 /* Increment sent packets counter. */
1111 txq->stats.opackets += i;
1113 /* Ring QP doorbell. */
1114 if (mpw.state == MLX5_MPW_STATE_OPENED)
1115 mlx5_mpw_close(txq, &mpw);
1116 mlx5_tx_dbrec(txq, mpw.wqe);
1117 txq->elts_head = elts_head;
1122 * Open a MPW inline session.
1125 * Pointer to TX queue structure.
1127 * Pointer to MPW session structure.
1132 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1135 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1136 struct mlx5_wqe_inl_small *inl;
1138 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1142 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1143 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1144 (txq->wqe_ci << 8) |
1146 mpw->wqe->ctrl[2] = 0;
1147 mpw->wqe->ctrl[3] = 0;
1148 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1149 mpw->wqe->eseg.inline_hdr_sz = 0;
1150 mpw->wqe->eseg.cs_flags = 0;
1151 mpw->wqe->eseg.rsvd0 = 0;
1152 mpw->wqe->eseg.rsvd1 = 0;
1153 mpw->wqe->eseg.flow_table_metadata = 0;
1154 inl = (struct mlx5_wqe_inl_small *)
1155 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1156 mpw->data.raw = (uint8_t *)&inl->raw;
1160 * Close a MPW inline session.
1163 * Pointer to TX queue structure.
1165 * Pointer to MPW session structure.
1168 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1171 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1172 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1174 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1176 * Store size in multiple of 16 bytes. Control and Ethernet segments
1179 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1181 mpw->state = MLX5_MPW_STATE_CLOSED;
1182 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1183 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1187 * DPDK callback for TX with MPW inline support.
1190 * Generic pointer to TX queue structure.
1192 * Packets to transmit.
1194 * Number of packets in array.
1197 * Number of packets successfully transmitted (<= pkts_n).
1200 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1203 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1204 uint16_t elts_head = txq->elts_head;
1205 const uint16_t elts_n = 1 << txq->elts_n;
1206 const uint16_t elts_m = elts_n - 1;
1212 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1213 struct mlx5_mpw mpw = {
1214 .state = MLX5_MPW_STATE_CLOSED,
1217 * Compute the maximum number of WQE which can be consumed by inline
1220 * - 1 control segment,
1221 * - 1 Ethernet segment,
1222 * - N Dseg from the inline request.
1224 const unsigned int wqe_inl_n =
1225 ((2 * MLX5_WQE_DWORD_SIZE +
1226 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1227 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1229 if (unlikely(!pkts_n))
1231 /* Prefetch first packet cacheline. */
1232 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1233 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1234 /* Start processing. */
1235 mlx5_tx_complete(txq);
1236 max_elts = (elts_n - (elts_head - txq->elts_tail));
1238 struct rte_mbuf *buf = *(pkts++);
1241 unsigned int segs_n = buf->nb_segs;
1243 rte_be32_t metadata;
1246 * Make sure there is enough room to store this packet and
1247 * that one ring entry remains unused.
1250 if (max_elts < segs_n)
1252 /* Do not bother with large packets MPW cannot handle. */
1253 if (segs_n > MLX5_MPW_DSEG_MAX) {
1254 txq->stats.oerrors++;
1260 * Compute max_wqe in case less WQE were consumed in previous
1263 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1264 cs_flags = txq_ol_cksum_to_cs(buf);
1265 /* Copy metadata from mbuf if valid */
1266 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1268 /* Retrieve packet information. */
1269 length = PKT_LEN(buf);
1270 /* Start new session if packet differs. */
1271 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1272 if ((mpw.len != length) ||
1274 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1275 (mpw.wqe->eseg.cs_flags != cs_flags))
1276 mlx5_mpw_close(txq, &mpw);
1277 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1278 if ((mpw.len != length) ||
1280 (length > inline_room) ||
1281 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1282 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1283 mlx5_mpw_inline_close(txq, &mpw);
1285 txq->max_inline * RTE_CACHE_LINE_SIZE;
1288 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1289 if ((segs_n != 1) ||
1290 (length > inline_room)) {
1292 * Multi-Packet WQE consumes at most two WQE.
1293 * mlx5_mpw_new() expects to be able to use
1296 if (unlikely(max_wqe < 2))
1299 mlx5_mpw_new(txq, &mpw, length);
1300 mpw.wqe->eseg.cs_flags = cs_flags;
1301 mpw.wqe->eseg.flow_table_metadata = metadata;
1303 if (unlikely(max_wqe < wqe_inl_n))
1305 max_wqe -= wqe_inl_n;
1306 mlx5_mpw_inline_new(txq, &mpw, length);
1307 mpw.wqe->eseg.cs_flags = cs_flags;
1308 mpw.wqe->eseg.flow_table_metadata = metadata;
1311 /* Multi-segment packets must be alone in their MPW. */
1312 assert((segs_n == 1) || (mpw.pkts_n == 0));
1313 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1314 assert(inline_room ==
1315 txq->max_inline * RTE_CACHE_LINE_SIZE);
1316 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1320 volatile struct mlx5_wqe_data_seg *dseg;
1323 (*txq->elts)[elts_head++ & elts_m] = buf;
1324 dseg = mpw.data.dseg[mpw.pkts_n];
1325 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1326 *dseg = (struct mlx5_wqe_data_seg){
1328 rte_cpu_to_be_32(DATA_LEN(buf)),
1329 .lkey = mlx5_tx_mb2mr(txq, buf),
1330 .addr = rte_cpu_to_be_64(addr),
1332 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1333 length += DATA_LEN(buf);
1339 assert(length == mpw.len);
1340 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1341 mlx5_mpw_close(txq, &mpw);
1345 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1346 assert(length <= inline_room);
1347 assert(length == DATA_LEN(buf));
1348 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1349 (*txq->elts)[elts_head++ & elts_m] = buf;
1350 /* Maximum number of bytes before wrapping. */
1351 max = ((((uintptr_t)(txq->wqes)) +
1354 (uintptr_t)mpw.data.raw);
1356 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1359 mpw.data.raw = (volatile void *)txq->wqes;
1360 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1361 (void *)(addr + max),
1363 mpw.data.raw += length - max;
1365 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1371 (volatile void *)txq->wqes;
1373 mpw.data.raw += length;
1376 mpw.total_len += length;
1378 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1379 mlx5_mpw_inline_close(txq, &mpw);
1381 txq->max_inline * RTE_CACHE_LINE_SIZE;
1383 inline_room -= length;
1386 #ifdef MLX5_PMD_SOFT_COUNTERS
1387 /* Increment sent bytes counter. */
1388 txq->stats.obytes += length;
1392 /* Take a shortcut if nothing must be sent. */
1393 if (unlikely(i == 0))
1395 /* Check whether completion threshold has been reached. */
1396 /* "j" includes both packets and segments. */
1397 comp = txq->elts_comp + j;
1398 if (comp >= MLX5_TX_COMP_THRESH) {
1399 volatile struct mlx5_wqe *wqe = mpw.wqe;
1401 /* A CQE slot must always be available. */
1402 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1403 /* Request completion on last WQE. */
1404 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1405 /* Save elts_head in unused "immediate" field of WQE. */
1406 wqe->ctrl[3] = elts_head;
1409 txq->elts_comp = comp;
1411 #ifdef MLX5_PMD_SOFT_COUNTERS
1412 /* Increment sent packets counter. */
1413 txq->stats.opackets += i;
1415 /* Ring QP doorbell. */
1416 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1417 mlx5_mpw_inline_close(txq, &mpw);
1418 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1419 mlx5_mpw_close(txq, &mpw);
1420 mlx5_tx_dbrec(txq, mpw.wqe);
1421 txq->elts_head = elts_head;
1426 * Open an Enhanced MPW session.
1429 * Pointer to TX queue structure.
1431 * Pointer to MPW session structure.
1436 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1438 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1440 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1442 mpw->total_len = sizeof(struct mlx5_wqe);
1443 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1445 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1446 (txq->wqe_ci << 8) |
1447 MLX5_OPCODE_ENHANCED_MPSW);
1448 mpw->wqe->ctrl[2] = 0;
1449 mpw->wqe->ctrl[3] = 0;
1450 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1451 if (unlikely(padding)) {
1452 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1454 /* Pad the first 2 DWORDs with zero-length inline header. */
1455 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1456 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1457 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1458 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1459 /* Start from the next WQEBB. */
1460 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1462 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1467 * Close an Enhanced MPW session.
1470 * Pointer to TX queue structure.
1472 * Pointer to MPW session structure.
1475 * Number of consumed WQEs.
1477 static inline uint16_t
1478 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1482 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1485 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1486 MLX5_WQE_DS(mpw->total_len));
1487 mpw->state = MLX5_MPW_STATE_CLOSED;
1488 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1494 * TX with Enhanced MPW support.
1497 * Pointer to TX queue structure.
1499 * Packets to transmit.
1501 * Number of packets in array.
1504 * Number of packets successfully transmitted (<= pkts_n).
1506 static inline uint16_t
1507 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1510 uint16_t elts_head = txq->elts_head;
1511 const uint16_t elts_n = 1 << txq->elts_n;
1512 const uint16_t elts_m = elts_n - 1;
1517 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1518 unsigned int mpw_room = 0;
1519 unsigned int inl_pad = 0;
1522 struct mlx5_mpw mpw = {
1523 .state = MLX5_MPW_STATE_CLOSED,
1526 if (unlikely(!pkts_n))
1528 /* Start processing. */
1529 mlx5_tx_complete(txq);
1530 max_elts = (elts_n - (elts_head - txq->elts_tail));
1531 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1532 if (unlikely(!max_wqe))
1535 struct rte_mbuf *buf = *(pkts++);
1537 unsigned int do_inline = 0; /* Whether inline is possible. */
1540 rte_be32_t metadata;
1542 /* Multi-segmented packet is handled in slow-path outside. */
1543 assert(NB_SEGS(buf) == 1);
1544 /* Make sure there is enough room to store this packet. */
1545 if (max_elts - j == 0)
1547 cs_flags = txq_ol_cksum_to_cs(buf);
1548 /* Copy metadata from mbuf if valid */
1549 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1551 /* Retrieve packet information. */
1552 length = PKT_LEN(buf);
1553 /* Start new session if:
1554 * - multi-segment packet
1555 * - no space left even for a dseg
1556 * - next packet can be inlined with a new WQE
1559 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1560 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1562 (length <= txq->inline_max_packet_sz &&
1563 inl_pad + sizeof(inl_hdr) + length >
1565 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1566 (mpw.wqe->eseg.cs_flags != cs_flags))
1567 max_wqe -= mlx5_empw_close(txq, &mpw);
1569 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1570 /* In Enhanced MPW, inline as much as the budget is
1571 * allowed. The remaining space is to be filled with
1572 * dsegs. If the title WQEBB isn't padded, it will have
1575 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1576 (max_inline ? max_inline :
1577 pkts_n * MLX5_WQE_DWORD_SIZE) +
1579 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1581 /* Don't pad the title WQEBB to not waste WQ. */
1582 mlx5_empw_new(txq, &mpw, 0);
1583 mpw_room -= mpw.total_len;
1585 do_inline = length <= txq->inline_max_packet_sz &&
1586 sizeof(inl_hdr) + length <= mpw_room &&
1588 mpw.wqe->eseg.cs_flags = cs_flags;
1589 mpw.wqe->eseg.flow_table_metadata = metadata;
1591 /* Evaluate whether the next packet can be inlined.
1592 * Inlininig is possible when:
1593 * - length is less than configured value
1594 * - length fits for remaining space
1595 * - not required to fill the title WQEBB with dsegs
1598 length <= txq->inline_max_packet_sz &&
1599 inl_pad + sizeof(inl_hdr) + length <=
1601 (!txq->mpw_hdr_dseg ||
1602 mpw.total_len >= MLX5_WQE_SIZE);
1604 if (max_inline && do_inline) {
1605 /* Inline packet into WQE. */
1608 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1609 assert(length == DATA_LEN(buf));
1610 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1611 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1612 mpw.data.raw = (volatile void *)
1613 ((uintptr_t)mpw.data.raw + inl_pad);
1614 max = tx_mlx5_wq_tailroom(txq,
1615 (void *)(uintptr_t)mpw.data.raw);
1616 /* Copy inline header. */
1617 mpw.data.raw = (volatile void *)
1619 (void *)(uintptr_t)mpw.data.raw,
1622 (void *)(uintptr_t)txq->wqes,
1624 max = tx_mlx5_wq_tailroom(txq,
1625 (void *)(uintptr_t)mpw.data.raw);
1626 /* Copy packet data. */
1627 mpw.data.raw = (volatile void *)
1629 (void *)(uintptr_t)mpw.data.raw,
1632 (void *)(uintptr_t)txq->wqes,
1635 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1636 /* No need to get completion as the entire packet is
1637 * copied to WQ. Free the buf right away.
1639 rte_pktmbuf_free_seg(buf);
1640 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1641 /* Add pad in the next packet if any. */
1642 inl_pad = (((uintptr_t)mpw.data.raw +
1643 (MLX5_WQE_DWORD_SIZE - 1)) &
1644 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1645 (uintptr_t)mpw.data.raw;
1647 /* No inline. Load a dseg of packet pointer. */
1648 volatile rte_v128u32_t *dseg;
1650 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1651 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1652 assert(length == DATA_LEN(buf));
1653 if (!tx_mlx5_wq_tailroom(txq,
1654 (void *)((uintptr_t)mpw.data.raw
1656 dseg = (volatile void *)txq->wqes;
1658 dseg = (volatile void *)
1659 ((uintptr_t)mpw.data.raw +
1661 (*txq->elts)[elts_head++ & elts_m] = buf;
1662 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1664 *dseg = (rte_v128u32_t) {
1665 rte_cpu_to_be_32(length),
1666 mlx5_tx_mb2mr(txq, buf),
1670 mpw.data.raw = (volatile void *)(dseg + 1);
1671 mpw.total_len += (inl_pad + sizeof(*dseg));
1674 mpw_room -= (inl_pad + sizeof(*dseg));
1677 #ifdef MLX5_PMD_SOFT_COUNTERS
1678 /* Increment sent bytes counter. */
1679 txq->stats.obytes += length;
1682 } while (i < pkts_n);
1683 /* Take a shortcut if nothing must be sent. */
1684 if (unlikely(i == 0))
1686 /* Check whether completion threshold has been reached. */
1687 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1688 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1689 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1690 volatile struct mlx5_wqe *wqe = mpw.wqe;
1692 /* A CQE slot must always be available. */
1693 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1694 /* Request completion on last WQE. */
1695 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1696 /* Save elts_head in unused "immediate" field of WQE. */
1697 wqe->ctrl[3] = elts_head;
1699 txq->mpw_comp = txq->wqe_ci;
1701 txq->elts_comp += j;
1703 #ifdef MLX5_PMD_SOFT_COUNTERS
1704 /* Increment sent packets counter. */
1705 txq->stats.opackets += i;
1707 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1708 mlx5_empw_close(txq, &mpw);
1709 /* Ring QP doorbell. */
1710 mlx5_tx_dbrec(txq, mpw.wqe);
1711 txq->elts_head = elts_head;
1716 * DPDK callback for TX with Enhanced MPW support.
1719 * Generic pointer to TX queue structure.
1721 * Packets to transmit.
1723 * Number of packets in array.
1726 * Number of packets successfully transmitted (<= pkts_n).
1729 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1731 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1734 while (pkts_n > nb_tx) {
1738 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1740 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1745 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1747 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1757 * Translate RX completion flags to packet type.
1760 * Pointer to RX queue structure.
1764 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1767 * Packet type for struct rte_mbuf.
1769 static inline uint32_t
1770 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1773 uint8_t pinfo = cqe->pkt_info;
1774 uint16_t ptype = cqe->hdr_type_etc;
1777 * The index to the array should have:
1778 * bit[1:0] = l3_hdr_type
1779 * bit[4:2] = l4_hdr_type
1782 * bit[7] = outer_l3_type
1784 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1785 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1789 * Get size of the next packet for a given CQE. For compressed CQEs, the
1790 * consumer index is updated only once all packets of the current one have
1794 * Pointer to RX queue.
1798 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1802 * Packet size in bytes (0 if there is none), -1 in case of completion
1806 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1807 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1809 struct rxq_zip *zip = &rxq->zip;
1810 uint16_t cqe_n = cqe_cnt + 1;
1814 /* Process compressed data in the CQE and mini arrays. */
1816 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1817 (volatile struct mlx5_mini_cqe8 (*)[8])
1818 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1820 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1821 *mcqe = &(*mc)[zip->ai & 7];
1822 if ((++zip->ai & 7) == 0) {
1823 /* Invalidate consumed CQEs */
1826 while (idx != end) {
1827 (*rxq->cqes)[idx & cqe_cnt].op_own =
1828 MLX5_CQE_INVALIDATE;
1832 * Increment consumer index to skip the number of
1833 * CQEs consumed. Hardware leaves holes in the CQ
1834 * ring for software use.
1839 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1840 /* Invalidate the rest */
1844 while (idx != end) {
1845 (*rxq->cqes)[idx & cqe_cnt].op_own =
1846 MLX5_CQE_INVALIDATE;
1849 rxq->cq_ci = zip->cq_ci;
1852 /* No compressed data, get next CQE and verify if it is compressed. */
1857 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1858 if (unlikely(ret == 1))
1861 op_own = cqe->op_own;
1863 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1864 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1865 (volatile struct mlx5_mini_cqe8 (*)[8])
1866 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1869 /* Fix endianness. */
1870 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1872 * Current mini array position is the one returned by
1875 * If completion comprises several mini arrays, as a
1876 * special case the second one is located 7 CQEs after
1877 * the initial CQE instead of 8 for subsequent ones.
1879 zip->ca = rxq->cq_ci;
1880 zip->na = zip->ca + 7;
1881 /* Compute the next non compressed CQE. */
1883 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1884 /* Get packet size to return. */
1885 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1888 /* Prefetch all the entries to be invalidated */
1891 while (idx != end) {
1892 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1896 len = rte_be_to_cpu_32(cqe->byte_cnt);
1898 /* Error while receiving packet. */
1899 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1906 * Translate RX completion flags to offload flags.
1912 * Offload flags (ol_flags) for struct rte_mbuf.
1914 static inline uint32_t
1915 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1917 uint32_t ol_flags = 0;
1918 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1922 MLX5_CQE_RX_L3_HDR_VALID,
1923 PKT_RX_IP_CKSUM_GOOD) |
1925 MLX5_CQE_RX_L4_HDR_VALID,
1926 PKT_RX_L4_CKSUM_GOOD);
1931 * Fill in mbuf fields from RX completion flags.
1932 * Note that pkt->ol_flags should be initialized outside of this function.
1935 * Pointer to RX queue.
1940 * @param rss_hash_res
1941 * Packet RSS Hash result.
1944 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1945 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1947 /* Update packet information. */
1948 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1949 if (rss_hash_res && rxq->rss_hash) {
1950 pkt->hash.rss = rss_hash_res;
1951 pkt->ol_flags |= PKT_RX_RSS_HASH;
1953 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1954 pkt->ol_flags |= PKT_RX_FDIR;
1955 if (cqe->sop_drop_qpn !=
1956 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1957 uint32_t mark = cqe->sop_drop_qpn;
1959 pkt->ol_flags |= PKT_RX_FDIR_ID;
1960 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1964 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1965 if (rxq->vlan_strip &&
1966 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1967 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1968 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1970 if (rxq->hw_timestamp) {
1971 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1972 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1977 * DPDK callback for RX.
1980 * Generic pointer to RX queue structure.
1982 * Array to store received packets.
1984 * Maximum number of packets in array.
1987 * Number of packets successfully received (<= pkts_n).
1990 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1992 struct mlx5_rxq_data *rxq = dpdk_rxq;
1993 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1994 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1995 const unsigned int sges_n = rxq->sges_n;
1996 struct rte_mbuf *pkt = NULL;
1997 struct rte_mbuf *seg = NULL;
1998 volatile struct mlx5_cqe *cqe =
1999 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2001 unsigned int rq_ci = rxq->rq_ci << sges_n;
2002 int len = 0; /* keep its value across iterations. */
2005 unsigned int idx = rq_ci & wqe_cnt;
2006 volatile struct mlx5_wqe_data_seg *wqe =
2007 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2008 struct rte_mbuf *rep = (*rxq->elts)[idx];
2009 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2010 uint32_t rss_hash_res;
2018 rep = rte_mbuf_raw_alloc(rxq->mp);
2019 if (unlikely(rep == NULL)) {
2020 ++rxq->stats.rx_nombuf;
2023 * no buffers before we even started,
2024 * bail out silently.
2028 while (pkt != seg) {
2029 assert(pkt != (*rxq->elts)[idx]);
2033 rte_mbuf_raw_free(pkt);
2039 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2040 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2042 rte_mbuf_raw_free(rep);
2045 if (unlikely(len == -1)) {
2046 /* RX error, packet is likely too large. */
2047 rte_mbuf_raw_free(rep);
2048 ++rxq->stats.idropped;
2052 assert(len >= (rxq->crc_present << 2));
2054 /* If compressed, take hash result from mini-CQE. */
2055 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2057 mcqe->rx_hash_result);
2058 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2059 if (rxq->crc_present)
2060 len -= ETHER_CRC_LEN;
2063 DATA_LEN(rep) = DATA_LEN(seg);
2064 PKT_LEN(rep) = PKT_LEN(seg);
2065 SET_DATA_OFF(rep, DATA_OFF(seg));
2066 PORT(rep) = PORT(seg);
2067 (*rxq->elts)[idx] = rep;
2069 * Fill NIC descriptor with the new buffer. The lkey and size
2070 * of the buffers are already known, only the buffer address
2073 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2074 /* If there's only one MR, no need to replace LKey in WQE. */
2075 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2076 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2077 if (len > DATA_LEN(seg)) {
2078 len -= DATA_LEN(seg);
2083 DATA_LEN(seg) = len;
2084 #ifdef MLX5_PMD_SOFT_COUNTERS
2085 /* Increment bytes counter. */
2086 rxq->stats.ibytes += PKT_LEN(pkt);
2088 /* Return packet. */
2094 /* Align consumer index to the next stride. */
2099 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2101 /* Update the consumer index. */
2102 rxq->rq_ci = rq_ci >> sges_n;
2104 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2106 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2107 #ifdef MLX5_PMD_SOFT_COUNTERS
2108 /* Increment packets counter. */
2109 rxq->stats.ipackets += i;
2115 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2117 struct mlx5_mprq_buf *buf = opaque;
2119 if (rte_atomic16_read(&buf->refcnt) == 1) {
2120 rte_mempool_put(buf->mp, buf);
2121 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2122 rte_atomic16_set(&buf->refcnt, 1);
2123 rte_mempool_put(buf->mp, buf);
2128 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2130 mlx5_mprq_buf_free_cb(NULL, buf);
2134 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2136 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2137 volatile struct mlx5_wqe_data_seg *wqe =
2138 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2141 assert(rep != NULL);
2142 /* Replace MPRQ buf. */
2143 (*rxq->mprq_bufs)[rq_idx] = rep;
2145 addr = mlx5_mprq_buf_addr(rep);
2146 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2147 /* If there's only one MR, no need to replace LKey in WQE. */
2148 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2149 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2150 /* Stash a mbuf for next replacement. */
2151 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2152 rxq->mprq_repl = rep;
2154 rxq->mprq_repl = NULL;
2158 * DPDK callback for RX with Multi-Packet RQ support.
2161 * Generic pointer to RX queue structure.
2163 * Array to store received packets.
2165 * Maximum number of packets in array.
2168 * Number of packets successfully received (<= pkts_n).
2171 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2173 struct mlx5_rxq_data *rxq = dpdk_rxq;
2174 const unsigned int strd_n = 1 << rxq->strd_num_n;
2175 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2176 const unsigned int strd_shift =
2177 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2178 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2179 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2180 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2182 uint32_t rq_ci = rxq->rq_ci;
2183 uint16_t consumed_strd = rxq->consumed_strd;
2184 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2186 while (i < pkts_n) {
2187 struct rte_mbuf *pkt;
2195 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2196 uint32_t rss_hash_res = 0;
2198 if (consumed_strd == strd_n) {
2199 /* Replace WQE only if the buffer is still in use. */
2200 if (rte_atomic16_read(&buf->refcnt) > 1) {
2201 mprq_buf_replace(rxq, rq_ci & wq_mask);
2202 /* Release the old buffer. */
2203 mlx5_mprq_buf_free(buf);
2204 } else if (unlikely(rxq->mprq_repl == NULL)) {
2205 struct mlx5_mprq_buf *rep;
2208 * Currently, the MPRQ mempool is out of buffer
2209 * and doing memcpy regardless of the size of Rx
2210 * packet. Retry allocation to get back to
2213 if (!rte_mempool_get(rxq->mprq_mp,
2215 rxq->mprq_repl = rep;
2217 /* Advance to the next WQE. */
2220 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2222 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2223 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2226 if (unlikely(ret == -1)) {
2227 /* RX error, packet is likely too large. */
2228 ++rxq->stats.idropped;
2232 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2233 MLX5_MPRQ_STRIDE_NUM_SHIFT;
2235 consumed_strd += strd_cnt;
2236 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2239 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2240 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2242 /* mini-CQE for MPRQ doesn't have hash result. */
2243 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2245 assert(strd_idx < strd_n);
2246 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2248 * Currently configured to receive a packet per a stride. But if
2249 * MTU is adjusted through kernel interface, device could
2250 * consume multiple strides without raising an error. In this
2251 * case, the packet should be dropped because it is bigger than
2252 * the max_rx_pkt_len.
2254 if (unlikely(strd_cnt > 1)) {
2255 ++rxq->stats.idropped;
2258 pkt = rte_pktmbuf_alloc(rxq->mp);
2259 if (unlikely(pkt == NULL)) {
2260 ++rxq->stats.rx_nombuf;
2263 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2264 assert((int)len >= (rxq->crc_present << 2));
2265 if (rxq->crc_present)
2266 len -= ETHER_CRC_LEN;
2267 offset = strd_idx * strd_sz + strd_shift;
2268 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2269 /* Initialize the offload flag. */
2272 * Memcpy packets to the target mbuf if:
2273 * - The size of packet is smaller than mprq_max_memcpy_len.
2274 * - Out of buffer in the Mempool for Multi-Packet RQ.
2276 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2278 * When memcpy'ing packet due to out-of-buffer, the
2279 * packet must be smaller than the target mbuf.
2281 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2282 rte_pktmbuf_free_seg(pkt);
2283 ++rxq->stats.idropped;
2286 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2288 rte_iova_t buf_iova;
2289 struct rte_mbuf_ext_shared_info *shinfo;
2290 uint16_t buf_len = strd_cnt * strd_sz;
2292 /* Increment the refcnt of the whole chunk. */
2293 rte_atomic16_add_return(&buf->refcnt, 1);
2294 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2296 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2298 * MLX5 device doesn't use iova but it is necessary in a
2299 * case where the Rx packet is transmitted via a
2302 buf_iova = rte_mempool_virt2iova(buf) +
2303 RTE_PTR_DIFF(addr, buf);
2304 shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2305 &buf_len, mlx5_mprq_buf_free_cb, buf);
2307 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2308 * attaching the stride to mbuf and more offload flags
2309 * will be added below by calling rxq_cq_to_mbuf().
2310 * Other fields will be overwritten.
2312 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2314 rte_pktmbuf_reset_headroom(pkt);
2315 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2317 * Prevent potential overflow due to MTU change through
2320 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2321 rte_pktmbuf_free_seg(pkt);
2322 ++rxq->stats.idropped;
2326 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2328 DATA_LEN(pkt) = len;
2329 PORT(pkt) = rxq->port_id;
2330 #ifdef MLX5_PMD_SOFT_COUNTERS
2331 /* Increment bytes counter. */
2332 rxq->stats.ibytes += PKT_LEN(pkt);
2334 /* Return packet. */
2338 /* Update the consumer indexes. */
2339 rxq->consumed_strd = consumed_strd;
2341 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2342 if (rq_ci != rxq->rq_ci) {
2345 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2347 #ifdef MLX5_PMD_SOFT_COUNTERS
2348 /* Increment packets counter. */
2349 rxq->stats.ipackets += i;
2355 * Dummy DPDK callback for TX.
2357 * This function is used to temporarily replace the real callback during
2358 * unsafe control operations on the queue, or in case of error.
2361 * Generic pointer to TX queue structure.
2363 * Packets to transmit.
2365 * Number of packets in array.
2368 * Number of packets successfully transmitted (<= pkts_n).
2371 removed_tx_burst(void *dpdk_txq __rte_unused,
2372 struct rte_mbuf **pkts __rte_unused,
2373 uint16_t pkts_n __rte_unused)
2379 * Dummy DPDK callback for RX.
2381 * This function is used to temporarily replace the real callback during
2382 * unsafe control operations on the queue, or in case of error.
2385 * Generic pointer to RX queue structure.
2387 * Array to store received packets.
2389 * Maximum number of packets in array.
2392 * Number of packets successfully received (<= pkts_n).
2395 removed_rx_burst(void *dpdk_txq __rte_unused,
2396 struct rte_mbuf **pkts __rte_unused,
2397 uint16_t pkts_n __rte_unused)
2403 * Vectorized Rx/Tx routines are not compiled in when required vector
2404 * instructions are not supported on a target architecture. The following null
2405 * stubs are needed for linkage when those are not included outside of this file
2406 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2410 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2411 struct rte_mbuf **pkts __rte_unused,
2412 uint16_t pkts_n __rte_unused)
2418 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2419 struct rte_mbuf **pkts __rte_unused,
2420 uint16_t pkts_n __rte_unused)
2426 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2427 struct rte_mbuf **pkts __rte_unused,
2428 uint16_t pkts_n __rte_unused)
2434 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2440 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2446 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2452 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)