4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 txq->wqe_pi = ntohs(cqe->wqe_counter);
242 ctrl = (volatile struct mlx5_wqe_ctrl *)
243 tx_mlx5_wqe(txq, txq->wqe_pi);
244 elts_tail = ctrl->ctrl3;
245 assert(elts_tail < (1 << txq->wqe_n));
247 while (elts_free != elts_tail) {
248 struct rte_mbuf *elt = (*txq->elts)[elts_free];
249 unsigned int elts_free_next =
250 (elts_free + 1) & (elts_n - 1);
251 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
255 memset(&(*txq->elts)[elts_free],
257 sizeof((*txq->elts)[elts_free]));
259 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
260 /* Only one segment needs to be freed. */
261 rte_pktmbuf_free_seg(elt);
262 elts_free = elts_free_next;
265 txq->elts_tail = elts_tail;
266 /* Update the consumer index. */
268 *txq->cq_db = htonl(cq_ci);
272 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
273 * the cloned mbuf is allocated is returned instead.
279 * Memory pool where data is located for given mbuf.
281 static struct rte_mempool *
282 txq_mb2mp(struct rte_mbuf *buf)
284 if (unlikely(RTE_MBUF_INDIRECT(buf)))
285 return rte_mbuf_from_indirect(buf)->pool;
290 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
291 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
292 * remove an entry first.
295 * Pointer to TX queue structure.
297 * Memory Pool for which a Memory Region lkey must be returned.
300 * mr->lkey on success, (uint32_t)-1 on failure.
302 static inline uint32_t
303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
306 uint32_t lkey = (uint32_t)-1;
308 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
309 if (unlikely(txq->mp2mr[i].mp == NULL)) {
310 /* Unknown MP, add a new MR for it. */
313 if (txq->mp2mr[i].mp == mp) {
314 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
315 assert(htonl(txq->mp2mr[i].mr->lkey) ==
317 lkey = txq->mp2mr[i].lkey;
321 if (unlikely(lkey == (uint32_t)-1))
322 lkey = txq_mp2mr_reg(txq, mp, i);
327 * Ring TX queue doorbell.
330 * Pointer to TX queue structure.
332 * Pointer to the last WQE posted in the NIC.
335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
337 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
338 volatile uint64_t *src = ((volatile uint64_t *)wqe);
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
348 * DPDK callback to check the status of a tx descriptor.
353 * The index of the descriptor in the ring.
356 * The status of the tx descriptor.
359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
361 struct txq *txq = tx_queue;
362 const unsigned int elts_n = 1 << txq->elts_n;
363 const unsigned int elts_cnt = elts_n - 1;
367 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
369 return RTE_ETH_TX_DESC_FULL;
370 return RTE_ETH_TX_DESC_DONE;
374 * DPDK callback to check the status of a rx descriptor.
379 * The index of the descriptor in the ring.
382 * The status of the tx descriptor.
385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
387 struct rxq *rxq = rx_queue;
388 struct rxq_zip *zip = &rxq->zip;
389 volatile struct mlx5_cqe *cqe;
390 const unsigned int cqe_n = (1 << rxq->cqe_n);
391 const unsigned int cqe_cnt = cqe_n - 1;
395 /* if we are processing a compressed cqe */
397 used = zip->cqe_cnt - zip->ca;
403 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
404 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
408 op_own = cqe->op_own;
409 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
410 n = ntohl(cqe->byte_cnt);
415 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
417 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
419 return RTE_ETH_RX_DESC_DONE;
420 return RTE_ETH_RX_DESC_AVAIL;
424 * DPDK callback for TX.
427 * Generic pointer to TX queue structure.
429 * Packets to transmit.
431 * Number of packets in array.
434 * Number of packets successfully transmitted (<= pkts_n).
437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
439 struct txq *txq = (struct txq *)dpdk_txq;
440 uint16_t elts_head = txq->elts_head;
441 const unsigned int elts_n = 1 << txq->elts_n;
447 volatile struct mlx5_wqe_v *wqe = NULL;
448 unsigned int segs_n = 0;
449 struct rte_mbuf *buf = NULL;
452 if (unlikely(!pkts_n))
454 /* Prefetch first packet cacheline. */
455 rte_prefetch0(*pkts);
456 /* Start processing. */
458 max = (elts_n - (elts_head - txq->elts_tail));
461 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
462 if (unlikely(!max_wqe))
465 volatile rte_v128u32_t *dseg = NULL;
470 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
472 uint8_t cs_flags = 0;
473 #ifdef MLX5_PMD_SOFT_COUNTERS
474 uint32_t total_length = 0;
479 segs_n = buf->nb_segs;
481 * Make sure there is enough room to store this packet and
482 * that one ring entry remains unused.
485 if (max < segs_n + 1)
491 if (unlikely(--max_wqe == 0))
493 wqe = (volatile struct mlx5_wqe_v *)
494 tx_mlx5_wqe(txq, txq->wqe_ci);
495 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
497 rte_prefetch0(*pkts);
498 addr = rte_pktmbuf_mtod(buf, uintptr_t);
499 length = DATA_LEN(buf);
500 ehdr = (((uint8_t *)addr)[1] << 8) |
501 ((uint8_t *)addr)[0];
502 #ifdef MLX5_PMD_SOFT_COUNTERS
503 total_length = length;
505 assert(length >= MLX5_WQE_DWORD_SIZE);
506 /* Update element. */
507 (*txq->elts)[elts_head] = buf;
508 elts_head = (elts_head + 1) & (elts_n - 1);
509 /* Prefetch next buffer data. */
511 volatile void *pkt_addr;
513 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
514 rte_prefetch0(pkt_addr);
516 /* Should we enable HW CKSUM offload */
518 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
519 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
521 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
522 /* Replace the Ethernet type by the VLAN if necessary. */
523 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
524 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
525 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
529 /* Copy Destination and source mac address. */
530 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
532 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
533 /* Copy missing two bytes to end the DSeg. */
534 memcpy((uint8_t *)raw + len + sizeof(vlan),
535 ((uint8_t *)addr) + len, 2);
539 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
540 MLX5_WQE_DWORD_SIZE);
541 length -= pkt_inline_sz;
542 addr += pkt_inline_sz;
544 /* Inline if enough room. */
545 if (txq->max_inline) {
546 uintptr_t end = (uintptr_t)
547 (((uintptr_t)txq->wqes) +
548 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
549 unsigned int max_inline = txq->max_inline *
550 RTE_CACHE_LINE_SIZE -
552 uintptr_t addr_end = (addr + max_inline) &
553 ~(RTE_CACHE_LINE_SIZE - 1);
554 unsigned int copy_b = (addr_end > addr) ?
555 RTE_MIN((addr_end - addr), length) :
558 raw += MLX5_WQE_DWORD_SIZE;
559 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
561 * One Dseg remains in the current WQE. To
562 * keep the computation positive, it is
563 * removed after the bytes to Dseg conversion.
565 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
567 if (unlikely(max_wqe < n))
570 rte_memcpy((void *)raw, (void *)addr, copy_b);
573 pkt_inline_sz += copy_b;
576 * 2 DWORDs consumed by the WQE header + ETH segment +
577 * the size of the inline part of the packet.
579 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
581 if (ds % (MLX5_WQE_SIZE /
582 MLX5_WQE_DWORD_SIZE) == 0) {
583 if (unlikely(--max_wqe == 0))
585 dseg = (volatile rte_v128u32_t *)
586 tx_mlx5_wqe(txq, txq->wqe_ci +
589 dseg = (volatile rte_v128u32_t *)
591 (ds * MLX5_WQE_DWORD_SIZE));
594 } else if (!segs_n) {
597 /* dseg will be advance as part of next_seg */
598 dseg = (volatile rte_v128u32_t *)
600 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
605 * No inline has been done in the packet, only the
606 * Ethernet Header as been stored.
608 dseg = (volatile rte_v128u32_t *)
609 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
612 /* Add the remaining packet as a simple ds. */
613 naddr = htonll(addr);
614 *dseg = (rte_v128u32_t){
616 txq_mp2mr(txq, txq_mb2mp(buf)),
629 * Spill on next WQE when the current one does not have
630 * enough room left. Size of WQE must a be a multiple
631 * of data segment size.
633 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
634 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
635 if (unlikely(--max_wqe == 0))
637 dseg = (volatile rte_v128u32_t *)
638 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
639 rte_prefetch0(tx_mlx5_wqe(txq,
640 txq->wqe_ci + ds / 4 + 1));
647 length = DATA_LEN(buf);
648 #ifdef MLX5_PMD_SOFT_COUNTERS
649 total_length += length;
651 /* Store segment information. */
652 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
653 *dseg = (rte_v128u32_t){
655 txq_mp2mr(txq, txq_mb2mp(buf)),
659 (*txq->elts)[elts_head] = buf;
660 elts_head = (elts_head + 1) & (elts_n - 1);
669 /* Initialize known and common part of the WQE structure. */
670 wqe->ctrl = (rte_v128u32_t){
671 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
672 htonl(txq->qp_num_8s | ds),
676 wqe->eseg = (rte_v128u32_t){
680 (ehdr << 16) | htons(pkt_inline_sz),
682 txq->wqe_ci += (ds + 3) / 4;
683 #ifdef MLX5_PMD_SOFT_COUNTERS
684 /* Increment sent bytes counter. */
685 txq->stats.obytes += total_length;
688 /* Take a shortcut if nothing must be sent. */
689 if (unlikely(i == 0))
691 /* Check whether completion threshold has been reached. */
692 comp = txq->elts_comp + i + j;
693 if (comp >= MLX5_TX_COMP_THRESH) {
694 volatile struct mlx5_wqe_ctrl *w =
695 (volatile struct mlx5_wqe_ctrl *)wqe;
697 /* Request completion on last WQE. */
699 /* Save elts_head in unused "immediate" field of WQE. */
700 w->ctrl3 = elts_head;
703 txq->elts_comp = comp;
705 #ifdef MLX5_PMD_SOFT_COUNTERS
706 /* Increment sent packets counter. */
707 txq->stats.opackets += i;
709 /* Ring QP doorbell. */
710 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
711 txq->elts_head = elts_head;
716 * Open a MPW session.
719 * Pointer to TX queue structure.
721 * Pointer to MPW session structure.
726 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
728 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
729 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
730 (volatile struct mlx5_wqe_data_seg (*)[])
731 tx_mlx5_wqe(txq, idx + 1);
733 mpw->state = MLX5_MPW_STATE_OPENED;
737 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
738 mpw->wqe->eseg.mss = htons(length);
739 mpw->wqe->eseg.inline_hdr_sz = 0;
740 mpw->wqe->eseg.rsvd0 = 0;
741 mpw->wqe->eseg.rsvd1 = 0;
742 mpw->wqe->eseg.rsvd2 = 0;
743 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
744 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
745 mpw->wqe->ctrl[2] = 0;
746 mpw->wqe->ctrl[3] = 0;
747 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
748 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
749 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
750 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
751 mpw->data.dseg[2] = &(*dseg)[0];
752 mpw->data.dseg[3] = &(*dseg)[1];
753 mpw->data.dseg[4] = &(*dseg)[2];
757 * Close a MPW session.
760 * Pointer to TX queue structure.
762 * Pointer to MPW session structure.
765 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
767 unsigned int num = mpw->pkts_n;
770 * Store size in multiple of 16 bytes. Control and Ethernet segments
773 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
774 mpw->state = MLX5_MPW_STATE_CLOSED;
779 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
780 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
784 * DPDK callback for TX with MPW support.
787 * Generic pointer to TX queue structure.
789 * Packets to transmit.
791 * Number of packets in array.
794 * Number of packets successfully transmitted (<= pkts_n).
797 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
799 struct txq *txq = (struct txq *)dpdk_txq;
800 uint16_t elts_head = txq->elts_head;
801 const unsigned int elts_n = 1 << txq->elts_n;
807 struct mlx5_mpw mpw = {
808 .state = MLX5_MPW_STATE_CLOSED,
811 if (unlikely(!pkts_n))
813 /* Prefetch first packet cacheline. */
814 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
815 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
816 /* Start processing. */
818 max = (elts_n - (elts_head - txq->elts_tail));
821 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
822 if (unlikely(!max_wqe))
825 struct rte_mbuf *buf = *(pkts++);
826 unsigned int elts_head_next;
828 unsigned int segs_n = buf->nb_segs;
829 uint32_t cs_flags = 0;
832 * Make sure there is enough room to store this packet and
833 * that one ring entry remains unused.
836 if (max < segs_n + 1)
838 /* Do not bother with large packets MPW cannot handle. */
839 if (segs_n > MLX5_MPW_DSEG_MAX)
843 /* Should we enable HW CKSUM offload */
845 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
846 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
847 /* Retrieve packet information. */
848 length = PKT_LEN(buf);
850 /* Start new session if packet differs. */
851 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
852 ((mpw.len != length) ||
854 (mpw.wqe->eseg.cs_flags != cs_flags)))
855 mlx5_mpw_close(txq, &mpw);
856 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
858 * Multi-Packet WQE consumes at most two WQE.
859 * mlx5_mpw_new() expects to be able to use such
862 if (unlikely(max_wqe < 2))
865 mlx5_mpw_new(txq, &mpw, length);
866 mpw.wqe->eseg.cs_flags = cs_flags;
868 /* Multi-segment packets must be alone in their MPW. */
869 assert((segs_n == 1) || (mpw.pkts_n == 0));
870 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
874 volatile struct mlx5_wqe_data_seg *dseg;
877 elts_head_next = (elts_head + 1) & (elts_n - 1);
879 (*txq->elts)[elts_head] = buf;
880 dseg = mpw.data.dseg[mpw.pkts_n];
881 addr = rte_pktmbuf_mtod(buf, uintptr_t);
882 *dseg = (struct mlx5_wqe_data_seg){
883 .byte_count = htonl(DATA_LEN(buf)),
884 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
885 .addr = htonll(addr),
887 elts_head = elts_head_next;
888 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
889 length += DATA_LEN(buf);
895 assert(length == mpw.len);
896 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
897 mlx5_mpw_close(txq, &mpw);
898 elts_head = elts_head_next;
899 #ifdef MLX5_PMD_SOFT_COUNTERS
900 /* Increment sent bytes counter. */
901 txq->stats.obytes += length;
905 /* Take a shortcut if nothing must be sent. */
906 if (unlikely(i == 0))
908 /* Check whether completion threshold has been reached. */
909 /* "j" includes both packets and segments. */
910 comp = txq->elts_comp + j;
911 if (comp >= MLX5_TX_COMP_THRESH) {
912 volatile struct mlx5_wqe *wqe = mpw.wqe;
914 /* Request completion on last WQE. */
915 wqe->ctrl[2] = htonl(8);
916 /* Save elts_head in unused "immediate" field of WQE. */
917 wqe->ctrl[3] = elts_head;
920 txq->elts_comp = comp;
922 #ifdef MLX5_PMD_SOFT_COUNTERS
923 /* Increment sent packets counter. */
924 txq->stats.opackets += i;
926 /* Ring QP doorbell. */
927 if (mpw.state == MLX5_MPW_STATE_OPENED)
928 mlx5_mpw_close(txq, &mpw);
929 mlx5_tx_dbrec(txq, mpw.wqe);
930 txq->elts_head = elts_head;
935 * Open a MPW inline session.
938 * Pointer to TX queue structure.
940 * Pointer to MPW session structure.
945 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
947 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
948 struct mlx5_wqe_inl_small *inl;
950 mpw->state = MLX5_MPW_INL_STATE_OPENED;
954 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
955 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
958 mpw->wqe->ctrl[2] = 0;
959 mpw->wqe->ctrl[3] = 0;
960 mpw->wqe->eseg.mss = htons(length);
961 mpw->wqe->eseg.inline_hdr_sz = 0;
962 mpw->wqe->eseg.cs_flags = 0;
963 mpw->wqe->eseg.rsvd0 = 0;
964 mpw->wqe->eseg.rsvd1 = 0;
965 mpw->wqe->eseg.rsvd2 = 0;
966 inl = (struct mlx5_wqe_inl_small *)
967 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
968 mpw->data.raw = (uint8_t *)&inl->raw;
972 * Close a MPW inline session.
975 * Pointer to TX queue structure.
977 * Pointer to MPW session structure.
980 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
983 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
984 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
986 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
988 * Store size in multiple of 16 bytes. Control and Ethernet segments
991 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
992 mpw->state = MLX5_MPW_STATE_CLOSED;
993 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
994 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
998 * DPDK callback for TX with MPW inline support.
1001 * Generic pointer to TX queue structure.
1003 * Packets to transmit.
1005 * Number of packets in array.
1008 * Number of packets successfully transmitted (<= pkts_n).
1011 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1014 struct txq *txq = (struct txq *)dpdk_txq;
1015 uint16_t elts_head = txq->elts_head;
1016 const unsigned int elts_n = 1 << txq->elts_n;
1022 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1023 struct mlx5_mpw mpw = {
1024 .state = MLX5_MPW_STATE_CLOSED,
1027 * Compute the maximum number of WQE which can be consumed by inline
1030 * - 1 control segment,
1031 * - 1 Ethernet segment,
1032 * - N Dseg from the inline request.
1034 const unsigned int wqe_inl_n =
1035 ((2 * MLX5_WQE_DWORD_SIZE +
1036 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1037 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1039 if (unlikely(!pkts_n))
1041 /* Prefetch first packet cacheline. */
1042 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1043 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1044 /* Start processing. */
1046 max = (elts_n - (elts_head - txq->elts_tail));
1050 struct rte_mbuf *buf = *(pkts++);
1051 unsigned int elts_head_next;
1054 unsigned int segs_n = buf->nb_segs;
1055 uint32_t cs_flags = 0;
1058 * Make sure there is enough room to store this packet and
1059 * that one ring entry remains unused.
1062 if (max < segs_n + 1)
1064 /* Do not bother with large packets MPW cannot handle. */
1065 if (segs_n > MLX5_MPW_DSEG_MAX)
1070 * Compute max_wqe in case less WQE were consumed in previous
1073 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1074 /* Should we enable HW CKSUM offload */
1076 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1077 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1078 /* Retrieve packet information. */
1079 length = PKT_LEN(buf);
1080 /* Start new session if packet differs. */
1081 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1082 if ((mpw.len != length) ||
1084 (mpw.wqe->eseg.cs_flags != cs_flags))
1085 mlx5_mpw_close(txq, &mpw);
1086 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1087 if ((mpw.len != length) ||
1089 (length > inline_room) ||
1090 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1091 mlx5_mpw_inline_close(txq, &mpw);
1093 txq->max_inline * RTE_CACHE_LINE_SIZE;
1096 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1097 if ((segs_n != 1) ||
1098 (length > inline_room)) {
1100 * Multi-Packet WQE consumes at most two WQE.
1101 * mlx5_mpw_new() expects to be able to use
1104 if (unlikely(max_wqe < 2))
1107 mlx5_mpw_new(txq, &mpw, length);
1108 mpw.wqe->eseg.cs_flags = cs_flags;
1110 if (unlikely(max_wqe < wqe_inl_n))
1112 max_wqe -= wqe_inl_n;
1113 mlx5_mpw_inline_new(txq, &mpw, length);
1114 mpw.wqe->eseg.cs_flags = cs_flags;
1117 /* Multi-segment packets must be alone in their MPW. */
1118 assert((segs_n == 1) || (mpw.pkts_n == 0));
1119 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1120 assert(inline_room ==
1121 txq->max_inline * RTE_CACHE_LINE_SIZE);
1122 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1126 volatile struct mlx5_wqe_data_seg *dseg;
1129 (elts_head + 1) & (elts_n - 1);
1131 (*txq->elts)[elts_head] = buf;
1132 dseg = mpw.data.dseg[mpw.pkts_n];
1133 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1134 *dseg = (struct mlx5_wqe_data_seg){
1135 .byte_count = htonl(DATA_LEN(buf)),
1136 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1137 .addr = htonll(addr),
1139 elts_head = elts_head_next;
1140 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1141 length += DATA_LEN(buf);
1147 assert(length == mpw.len);
1148 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1149 mlx5_mpw_close(txq, &mpw);
1153 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1154 assert(length <= inline_room);
1155 assert(length == DATA_LEN(buf));
1156 elts_head_next = (elts_head + 1) & (elts_n - 1);
1157 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1158 (*txq->elts)[elts_head] = buf;
1159 /* Maximum number of bytes before wrapping. */
1160 max = ((((uintptr_t)(txq->wqes)) +
1163 (uintptr_t)mpw.data.raw);
1165 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1168 mpw.data.raw = (volatile void *)txq->wqes;
1169 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1170 (void *)(addr + max),
1172 mpw.data.raw += length - max;
1174 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1180 (volatile void *)txq->wqes;
1182 mpw.data.raw += length;
1185 mpw.total_len += length;
1187 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1188 mlx5_mpw_inline_close(txq, &mpw);
1190 txq->max_inline * RTE_CACHE_LINE_SIZE;
1192 inline_room -= length;
1195 elts_head = elts_head_next;
1196 #ifdef MLX5_PMD_SOFT_COUNTERS
1197 /* Increment sent bytes counter. */
1198 txq->stats.obytes += length;
1202 /* Take a shortcut if nothing must be sent. */
1203 if (unlikely(i == 0))
1205 /* Check whether completion threshold has been reached. */
1206 /* "j" includes both packets and segments. */
1207 comp = txq->elts_comp + j;
1208 if (comp >= MLX5_TX_COMP_THRESH) {
1209 volatile struct mlx5_wqe *wqe = mpw.wqe;
1211 /* Request completion on last WQE. */
1212 wqe->ctrl[2] = htonl(8);
1213 /* Save elts_head in unused "immediate" field of WQE. */
1214 wqe->ctrl[3] = elts_head;
1217 txq->elts_comp = comp;
1219 #ifdef MLX5_PMD_SOFT_COUNTERS
1220 /* Increment sent packets counter. */
1221 txq->stats.opackets += i;
1223 /* Ring QP doorbell. */
1224 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1225 mlx5_mpw_inline_close(txq, &mpw);
1226 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1227 mlx5_mpw_close(txq, &mpw);
1228 mlx5_tx_dbrec(txq, mpw.wqe);
1229 txq->elts_head = elts_head;
1234 * Translate RX completion flags to packet type.
1239 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1242 * Packet type for struct rte_mbuf.
1244 static inline uint32_t
1245 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1248 uint16_t flags = ntohs(cqe->hdr_type_etc);
1250 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1253 MLX5_CQE_RX_IPV4_PACKET,
1254 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1256 MLX5_CQE_RX_IPV6_PACKET,
1257 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1258 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1259 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1260 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1264 MLX5_CQE_L3_HDR_TYPE_IPV6,
1265 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1267 MLX5_CQE_L3_HDR_TYPE_IPV4,
1268 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1274 * Get size of the next packet for a given CQE. For compressed CQEs, the
1275 * consumer index is updated only once all packets of the current one have
1279 * Pointer to RX queue.
1282 * @param[out] rss_hash
1283 * Packet RSS Hash result.
1286 * Packet size in bytes (0 if there is none), -1 in case of completion
1290 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1291 uint16_t cqe_cnt, uint32_t *rss_hash)
1293 struct rxq_zip *zip = &rxq->zip;
1294 uint16_t cqe_n = cqe_cnt + 1;
1298 /* Process compressed data in the CQE and mini arrays. */
1300 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1301 (volatile struct mlx5_mini_cqe8 (*)[8])
1302 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1304 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1305 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1306 if ((++zip->ai & 7) == 0) {
1307 /* Invalidate consumed CQEs */
1310 while (idx != end) {
1311 (*rxq->cqes)[idx & cqe_cnt].op_own =
1312 MLX5_CQE_INVALIDATE;
1316 * Increment consumer index to skip the number of
1317 * CQEs consumed. Hardware leaves holes in the CQ
1318 * ring for software use.
1323 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1324 /* Invalidate the rest */
1328 while (idx != end) {
1329 (*rxq->cqes)[idx & cqe_cnt].op_own =
1330 MLX5_CQE_INVALIDATE;
1333 rxq->cq_ci = zip->cq_ci;
1336 /* No compressed data, get next CQE and verify if it is compressed. */
1341 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1342 if (unlikely(ret == 1))
1345 op_own = cqe->op_own;
1346 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1347 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1348 (volatile struct mlx5_mini_cqe8 (*)[8])
1349 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1352 /* Fix endianness. */
1353 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1355 * Current mini array position is the one returned by
1358 * If completion comprises several mini arrays, as a
1359 * special case the second one is located 7 CQEs after
1360 * the initial CQE instead of 8 for subsequent ones.
1362 zip->ca = rxq->cq_ci;
1363 zip->na = zip->ca + 7;
1364 /* Compute the next non compressed CQE. */
1366 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1367 /* Get packet size to return. */
1368 len = ntohl((*mc)[0].byte_cnt);
1369 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1371 /* Prefetch all the entries to be invalidated */
1374 while (idx != end) {
1375 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1379 len = ntohl(cqe->byte_cnt);
1380 *rss_hash = ntohl(cqe->rx_hash_res);
1382 /* Error while receiving packet. */
1383 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1390 * Translate RX completion flags to offload flags.
1393 * Pointer to RX queue structure.
1398 * Offload flags (ol_flags) for struct rte_mbuf.
1400 static inline uint32_t
1401 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1403 uint32_t ol_flags = 0;
1404 uint16_t flags = ntohs(cqe->hdr_type_etc);
1408 MLX5_CQE_RX_L3_HDR_VALID,
1409 PKT_RX_IP_CKSUM_GOOD) |
1411 MLX5_CQE_RX_L4_HDR_VALID,
1412 PKT_RX_L4_CKSUM_GOOD);
1413 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1416 MLX5_CQE_RX_L3_HDR_VALID,
1417 PKT_RX_IP_CKSUM_GOOD) |
1419 MLX5_CQE_RX_L4_HDR_VALID,
1420 PKT_RX_L4_CKSUM_GOOD);
1425 * DPDK callback for RX.
1428 * Generic pointer to RX queue structure.
1430 * Array to store received packets.
1432 * Maximum number of packets in array.
1435 * Number of packets successfully received (<= pkts_n).
1438 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1440 struct rxq *rxq = dpdk_rxq;
1441 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1442 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1443 const unsigned int sges_n = rxq->sges_n;
1444 struct rte_mbuf *pkt = NULL;
1445 struct rte_mbuf *seg = NULL;
1446 volatile struct mlx5_cqe *cqe =
1447 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1449 unsigned int rq_ci = rxq->rq_ci << sges_n;
1450 int len; /* keep its value across iterations. */
1453 unsigned int idx = rq_ci & wqe_cnt;
1454 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1455 struct rte_mbuf *rep = (*rxq->elts)[idx];
1456 uint32_t rss_hash_res = 0;
1464 rep = rte_mbuf_raw_alloc(rxq->mp);
1465 if (unlikely(rep == NULL)) {
1466 ++rxq->stats.rx_nombuf;
1469 * no buffers before we even started,
1470 * bail out silently.
1474 while (pkt != seg) {
1475 assert(pkt != (*rxq->elts)[idx]);
1477 rte_mbuf_refcnt_set(pkt, 0);
1478 __rte_mbuf_raw_free(pkt);
1484 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1485 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1488 rte_mbuf_refcnt_set(rep, 0);
1489 __rte_mbuf_raw_free(rep);
1492 if (unlikely(len == -1)) {
1493 /* RX error, packet is likely too large. */
1494 rte_mbuf_refcnt_set(rep, 0);
1495 __rte_mbuf_raw_free(rep);
1496 ++rxq->stats.idropped;
1500 assert(len >= (rxq->crc_present << 2));
1501 /* Update packet information. */
1502 pkt->packet_type = 0;
1504 if (rss_hash_res && rxq->rss_hash) {
1505 pkt->hash.rss = rss_hash_res;
1506 pkt->ol_flags = PKT_RX_RSS_HASH;
1509 ((cqe->sop_drop_qpn !=
1510 htonl(MLX5_FLOW_MARK_INVALID)) &&
1511 (cqe->sop_drop_qpn !=
1512 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1514 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1515 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1516 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1518 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1522 rxq_cq_to_pkt_type(cqe);
1524 rxq_cq_to_ol_flags(rxq, cqe);
1526 if (ntohs(cqe->hdr_type_etc) &
1527 MLX5_CQE_VLAN_STRIPPED) {
1528 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1529 PKT_RX_VLAN_STRIPPED;
1530 pkt->vlan_tci = ntohs(cqe->vlan_info);
1532 if (rxq->crc_present)
1533 len -= ETHER_CRC_LEN;
1537 DATA_LEN(rep) = DATA_LEN(seg);
1538 PKT_LEN(rep) = PKT_LEN(seg);
1539 SET_DATA_OFF(rep, DATA_OFF(seg));
1540 NB_SEGS(rep) = NB_SEGS(seg);
1541 PORT(rep) = PORT(seg);
1543 (*rxq->elts)[idx] = rep;
1545 * Fill NIC descriptor with the new buffer. The lkey and size
1546 * of the buffers are already known, only the buffer address
1549 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1550 if (len > DATA_LEN(seg)) {
1551 len -= DATA_LEN(seg);
1556 DATA_LEN(seg) = len;
1557 #ifdef MLX5_PMD_SOFT_COUNTERS
1558 /* Increment bytes counter. */
1559 rxq->stats.ibytes += PKT_LEN(pkt);
1561 /* Return packet. */
1567 /* Align consumer index to the next stride. */
1572 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1574 /* Update the consumer index. */
1575 rxq->rq_ci = rq_ci >> sges_n;
1577 *rxq->cq_db = htonl(rxq->cq_ci);
1579 *rxq->rq_db = htonl(rxq->rq_ci);
1580 #ifdef MLX5_PMD_SOFT_COUNTERS
1581 /* Increment packets counter. */
1582 rxq->stats.ipackets += i;
1588 * Dummy DPDK callback for TX.
1590 * This function is used to temporarily replace the real callback during
1591 * unsafe control operations on the queue, or in case of error.
1594 * Generic pointer to TX queue structure.
1596 * Packets to transmit.
1598 * Number of packets in array.
1601 * Number of packets successfully transmitted (<= pkts_n).
1604 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1613 * Dummy DPDK callback for RX.
1615 * This function is used to temporarily replace the real callback during
1616 * unsafe control operations on the queue, or in case of error.
1619 * Generic pointer to RX queue structure.
1621 * Array to store received packets.
1623 * Maximum number of packets in array.
1626 * Number of packets successfully received (<= pkts_n).
1629 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)