4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Manage TX completions.
158 * When sending a burst, mlx5_tx_burst() posts several WRs.
161 * Pointer to TX queue structure.
164 txq_complete(struct txq *txq)
166 const unsigned int elts_n = txq->elts_n;
167 const unsigned int cqe_n = txq->cqe_n;
168 const unsigned int cqe_cnt = cqe_n - 1;
169 uint16_t elts_free = txq->elts_tail;
171 uint16_t cq_ci = txq->cq_ci;
172 volatile struct mlx5_cqe64 *cqe = NULL;
173 volatile union mlx5_wqe *wqe;
176 volatile struct mlx5_cqe64 *tmp;
178 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
179 if (check_cqe64(tmp, cqe_n, cq_ci))
183 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
184 if (!check_cqe64_seen(cqe))
185 ERROR("unexpected compressed CQE, TX stopped");
188 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
189 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
190 if (!check_cqe64_seen(cqe))
191 ERROR("unexpected error CQE, TX stopped");
197 if (unlikely(cqe == NULL))
199 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];
200 elts_tail = wqe->wqe.ctrl.data[3];
201 assert(elts_tail < txq->wqe_n);
203 while (elts_free != elts_tail) {
204 struct rte_mbuf *elt = (*txq->elts)[elts_free];
205 unsigned int elts_free_next =
206 (elts_free + 1) & (elts_n - 1);
207 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
211 memset(&(*txq->elts)[elts_free],
213 sizeof((*txq->elts)[elts_free]));
215 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
216 /* Only one segment needs to be freed. */
217 rte_pktmbuf_free_seg(elt);
218 elts_free = elts_free_next;
221 txq->elts_tail = elts_tail;
222 /* Update the consumer index. */
224 *txq->cq_db = htonl(cq_ci);
228 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
229 * the cloned mbuf is allocated is returned instead.
235 * Memory pool where data is located for given mbuf.
237 static struct rte_mempool *
238 txq_mb2mp(struct rte_mbuf *buf)
240 if (unlikely(RTE_MBUF_INDIRECT(buf)))
241 return rte_mbuf_from_indirect(buf)->pool;
245 static inline uint32_t
246 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
247 __attribute__((always_inline));
250 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
251 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
252 * remove an entry first.
255 * Pointer to TX queue structure.
257 * Memory Pool for which a Memory Region lkey must be returned.
260 * mr->lkey on success, (uint32_t)-1 on failure.
262 static inline uint32_t
263 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
266 uint32_t lkey = (uint32_t)-1;
268 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
269 if (unlikely(txq->mp2mr[i].mp == NULL)) {
270 /* Unknown MP, add a new MR for it. */
273 if (txq->mp2mr[i].mp == mp) {
274 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
275 assert(htonl(txq->mp2mr[i].mr->lkey) ==
277 lkey = txq->mp2mr[i].lkey;
281 if (unlikely(lkey == (uint32_t)-1))
282 lkey = txq_mp2mr_reg(txq, mp, i);
287 * Write a regular WQE.
290 * Pointer to TX queue structure.
292 * Pointer to the WQE to fill.
294 * Buffer data address.
298 * Memory region lkey.
301 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
302 uintptr_t addr, uint32_t length, uint32_t lkey)
304 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
305 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
306 wqe->wqe.ctrl.data[3] = 0;
307 wqe->inl.eseg.rsvd0 = 0;
308 wqe->inl.eseg.rsvd1 = 0;
309 wqe->inl.eseg.mss = 0;
310 wqe->inl.eseg.rsvd2 = 0;
311 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
312 /* Copy the first 16 bytes into inline header. */
313 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
314 (uint8_t *)(uintptr_t)addr,
315 MLX5_ETH_INLINE_HEADER_SIZE);
316 addr += MLX5_ETH_INLINE_HEADER_SIZE;
317 length -= MLX5_ETH_INLINE_HEADER_SIZE;
318 /* Store remaining data in data segment. */
319 wqe->wqe.dseg.byte_count = htonl(length);
320 wqe->wqe.dseg.lkey = lkey;
321 wqe->wqe.dseg.addr = htonll(addr);
322 /* Increment consumer index. */
327 * Write a regular WQE with VLAN.
330 * Pointer to TX queue structure.
332 * Pointer to the WQE to fill.
334 * Buffer data address.
338 * Memory region lkey.
340 * VLAN field to insert in packet.
343 mlx5_wqe_write_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
344 uintptr_t addr, uint32_t length, uint32_t lkey,
347 uint32_t vlan = htonl(0x81000000 | vlan_tci);
349 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
350 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
351 wqe->wqe.ctrl.data[3] = 0;
352 wqe->inl.eseg.rsvd0 = 0;
353 wqe->inl.eseg.rsvd1 = 0;
354 wqe->inl.eseg.mss = 0;
355 wqe->inl.eseg.rsvd2 = 0;
356 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
358 * Copy 12 bytes of source & destination MAC address.
359 * Copy 4 bytes of VLAN.
360 * Copy 2 bytes of Ether type.
362 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
363 (uint8_t *)(uintptr_t)addr, 12);
364 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 12),
365 &vlan, sizeof(vlan));
366 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 16),
367 (uint8_t *)((uintptr_t)addr + 12), 2);
368 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
369 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
370 /* Store remaining data in data segment. */
371 wqe->wqe.dseg.byte_count = htonl(length);
372 wqe->wqe.dseg.lkey = lkey;
373 wqe->wqe.dseg.addr = htonll(addr);
374 /* Increment consumer index. */
379 * Write a inline WQE.
382 * Pointer to TX queue structure.
384 * Pointer to the WQE to fill.
386 * Buffer data address.
390 * Memory region lkey.
393 mlx5_wqe_write_inline(struct txq *txq, volatile union mlx5_wqe *wqe,
394 uintptr_t addr, uint32_t length)
397 uint16_t wqe_cnt = txq->wqe_n - 1;
398 uint16_t wqe_ci = txq->wqe_ci + 1;
400 /* Copy the first 16 bytes into inline header. */
401 rte_memcpy((void *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
402 (void *)(uintptr_t)addr,
403 MLX5_ETH_INLINE_HEADER_SIZE);
404 addr += MLX5_ETH_INLINE_HEADER_SIZE;
405 length -= MLX5_ETH_INLINE_HEADER_SIZE;
406 size = 3 + ((4 + length + 15) / 16);
407 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
408 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
409 (void *)addr, MLX5_WQE64_INL_DATA);
410 addr += MLX5_WQE64_INL_DATA;
411 length -= MLX5_WQE64_INL_DATA;
413 volatile union mlx5_wqe *wqe_next =
414 &(*txq->wqes)[wqe_ci & wqe_cnt];
415 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
419 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
422 length -= copy_bytes;
426 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
427 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
428 wqe->inl.ctrl.data[3] = 0;
429 wqe->inl.eseg.rsvd0 = 0;
430 wqe->inl.eseg.rsvd1 = 0;
431 wqe->inl.eseg.mss = 0;
432 wqe->inl.eseg.rsvd2 = 0;
433 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
434 /* Increment consumer index. */
435 txq->wqe_ci = wqe_ci;
439 * Write a inline WQE with VLAN.
442 * Pointer to TX queue structure.
444 * Pointer to the WQE to fill.
446 * Buffer data address.
450 * Memory region lkey.
452 * VLAN field to insert in packet.
455 mlx5_wqe_write_inline_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
456 uintptr_t addr, uint32_t length, uint16_t vlan_tci)
459 uint32_t wqe_cnt = txq->wqe_n - 1;
460 uint16_t wqe_ci = txq->wqe_ci + 1;
461 uint32_t vlan = htonl(0x81000000 | vlan_tci);
464 * Copy 12 bytes of source & destination MAC address.
465 * Copy 4 bytes of VLAN.
466 * Copy 2 bytes of Ether type.
468 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
469 (uint8_t *)addr, 12);
470 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 12,
471 &vlan, sizeof(vlan));
472 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 16,
473 ((uint8_t *)addr + 12), 2);
474 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
475 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
476 size = (sizeof(wqe->inl.ctrl.ctrl) +
477 sizeof(wqe->inl.eseg) +
478 sizeof(wqe->inl.byte_cnt) +
480 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
481 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
482 (void *)addr, MLX5_WQE64_INL_DATA);
483 addr += MLX5_WQE64_INL_DATA;
484 length -= MLX5_WQE64_INL_DATA;
486 volatile union mlx5_wqe *wqe_next =
487 &(*txq->wqes)[wqe_ci & wqe_cnt];
488 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
492 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
495 length -= copy_bytes;
499 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
500 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
501 wqe->inl.ctrl.data[3] = 0;
502 wqe->inl.eseg.rsvd0 = 0;
503 wqe->inl.eseg.rsvd1 = 0;
504 wqe->inl.eseg.mss = 0;
505 wqe->inl.eseg.rsvd2 = 0;
506 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
507 /* Increment consumer index. */
508 txq->wqe_ci = wqe_ci;
512 * Ring TX queue doorbell.
515 * Pointer to TX queue structure.
518 mlx5_tx_dbrec(struct txq *txq)
520 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
522 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
523 htonl(txq->qp_num_8s),
528 *txq->qp_db = htonl(txq->wqe_ci);
529 /* Ensure ordering between DB record and BF copy. */
531 rte_mov16(dst, (uint8_t *)data);
532 txq->bf_offset ^= txq->bf_buf_size;
539 * Pointer to TX queue structure.
541 * CQE consumer index.
544 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
546 volatile struct mlx5_cqe64 *cqe;
548 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
556 * Pointer to TX queue structure.
558 * WQE consumer index.
561 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
563 volatile union mlx5_wqe *wqe;
565 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
570 * DPDK callback for TX.
573 * Generic pointer to TX queue structure.
575 * Packets to transmit.
577 * Number of packets in array.
580 * Number of packets successfully transmitted (<= pkts_n).
583 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
585 struct txq *txq = (struct txq *)dpdk_txq;
586 uint16_t elts_head = txq->elts_head;
587 const unsigned int elts_n = txq->elts_n;
591 volatile union mlx5_wqe *wqe;
593 if (unlikely(!pkts_n))
595 /* Prefetch first packet cacheline. */
596 tx_prefetch_cqe(txq, txq->cq_ci);
597 tx_prefetch_cqe(txq, txq->cq_ci + 1);
598 rte_prefetch0(*pkts);
599 /* Start processing. */
601 max = (elts_n - (elts_head - txq->elts_tail));
605 struct rte_mbuf *buf;
606 unsigned int elts_head_next;
612 * Make sure there is enough room to store this packet and
613 * that one ring entry remains unused.
620 elts_head_next = (elts_head + 1) & (elts_n - 1);
621 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
624 rte_prefetch0(*pkts);
625 /* Retrieve buffer information. */
626 addr = rte_pktmbuf_mtod(buf, uintptr_t);
627 length = DATA_LEN(buf);
628 /* Update element. */
629 (*txq->elts)[elts_head] = buf;
630 /* Prefetch next buffer data. */
632 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
634 /* Retrieve Memory Region key for this memory pool. */
635 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
636 if (buf->ol_flags & PKT_TX_VLAN_PKT)
637 mlx5_wqe_write_vlan(txq, wqe, addr, length, lkey,
640 mlx5_wqe_write(txq, wqe, addr, length, lkey);
641 wqe->wqe.ctrl.data[2] = 0;
642 /* Should we enable HW CKSUM offload */
644 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
645 wqe->wqe.eseg.cs_flags =
646 MLX5_ETH_WQE_L3_CSUM |
647 MLX5_ETH_WQE_L4_CSUM;
649 wqe->wqe.eseg.cs_flags = 0;
651 #ifdef MLX5_PMD_SOFT_COUNTERS
652 /* Increment sent bytes counter. */
653 txq->stats.obytes += length;
655 elts_head = elts_head_next;
658 /* Take a shortcut if nothing must be sent. */
659 if (unlikely(i == 0))
661 /* Check whether completion threshold has been reached. */
662 comp = txq->elts_comp + i;
663 if (comp >= MLX5_TX_COMP_THRESH) {
664 /* Request completion on last WQE. */
665 wqe->wqe.ctrl.data[2] = htonl(8);
666 /* Save elts_head in unused "immediate" field of WQE. */
667 wqe->wqe.ctrl.data[3] = elts_head;
670 txq->elts_comp = comp;
672 #ifdef MLX5_PMD_SOFT_COUNTERS
673 /* Increment sent packets counter. */
674 txq->stats.opackets += i;
676 /* Ring QP doorbell. */
678 txq->elts_head = elts_head;
683 * DPDK callback for TX with inline support.
686 * Generic pointer to TX queue structure.
688 * Packets to transmit.
690 * Number of packets in array.
693 * Number of packets successfully transmitted (<= pkts_n).
696 mlx5_tx_burst_inline(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
698 struct txq *txq = (struct txq *)dpdk_txq;
699 uint16_t elts_head = txq->elts_head;
700 const unsigned int elts_n = txq->elts_n;
704 volatile union mlx5_wqe *wqe;
705 unsigned int max_inline = txq->max_inline;
707 if (unlikely(!pkts_n))
709 /* Prefetch first packet cacheline. */
710 tx_prefetch_cqe(txq, txq->cq_ci);
711 tx_prefetch_cqe(txq, txq->cq_ci + 1);
712 rte_prefetch0(*pkts);
713 /* Start processing. */
715 max = (elts_n - (elts_head - txq->elts_tail));
719 struct rte_mbuf *buf;
720 unsigned int elts_head_next;
726 * Make sure there is enough room to store this packet and
727 * that one ring entry remains unused.
734 elts_head_next = (elts_head + 1) & (elts_n - 1);
735 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
736 tx_prefetch_wqe(txq, txq->wqe_ci);
737 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
739 rte_prefetch0(*pkts);
740 /* Should we enable HW CKSUM offload */
742 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
743 wqe->inl.eseg.cs_flags =
744 MLX5_ETH_WQE_L3_CSUM |
745 MLX5_ETH_WQE_L4_CSUM;
747 wqe->inl.eseg.cs_flags = 0;
749 /* Retrieve buffer information. */
750 addr = rte_pktmbuf_mtod(buf, uintptr_t);
751 length = DATA_LEN(buf);
752 /* Update element. */
753 (*txq->elts)[elts_head] = buf;
754 /* Prefetch next buffer data. */
756 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
758 if (length <= max_inline) {
759 if (buf->ol_flags & PKT_TX_VLAN_PKT)
760 mlx5_wqe_write_inline_vlan(txq, wqe,
764 mlx5_wqe_write_inline(txq, wqe, addr, length);
766 /* Retrieve Memory Region key for this memory pool. */
767 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
768 if (buf->ol_flags & PKT_TX_VLAN_PKT)
769 mlx5_wqe_write_vlan(txq, wqe, addr, length,
770 lkey, buf->vlan_tci);
772 mlx5_wqe_write(txq, wqe, addr, length, lkey);
774 wqe->inl.ctrl.data[2] = 0;
775 elts_head = elts_head_next;
776 #ifdef MLX5_PMD_SOFT_COUNTERS
777 /* Increment sent bytes counter. */
778 txq->stats.obytes += length;
782 /* Take a shortcut if nothing must be sent. */
783 if (unlikely(i == 0))
785 /* Check whether completion threshold has been reached. */
786 comp = txq->elts_comp + i;
787 if (comp >= MLX5_TX_COMP_THRESH) {
788 /* Request completion on last WQE. */
789 wqe->inl.ctrl.data[2] = htonl(8);
790 /* Save elts_head in unused "immediate" field of WQE. */
791 wqe->inl.ctrl.data[3] = elts_head;
794 txq->elts_comp = comp;
796 #ifdef MLX5_PMD_SOFT_COUNTERS
797 /* Increment sent packets counter. */
798 txq->stats.opackets += i;
800 /* Ring QP doorbell. */
802 txq->elts_head = elts_head;
807 * Open a MPW session.
810 * Pointer to TX queue structure.
812 * Pointer to MPW session structure.
817 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
819 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
820 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
821 (volatile struct mlx5_wqe_data_seg (*)[])
822 (uintptr_t)&(*txq->wqes)[(idx + 1) & (txq->wqe_n - 1)];
824 mpw->state = MLX5_MPW_STATE_OPENED;
828 mpw->wqe = &(*txq->wqes)[idx];
829 mpw->wqe->mpw.eseg.mss = htons(length);
830 mpw->wqe->mpw.eseg.inline_hdr_sz = 0;
831 mpw->wqe->mpw.eseg.rsvd0 = 0;
832 mpw->wqe->mpw.eseg.rsvd1 = 0;
833 mpw->wqe->mpw.eseg.rsvd2 = 0;
834 mpw->wqe->mpw.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
836 MLX5_OPCODE_LSO_MPW);
837 mpw->wqe->mpw.ctrl.data[2] = 0;
838 mpw->wqe->mpw.ctrl.data[3] = 0;
839 mpw->data.dseg[0] = &mpw->wqe->mpw.dseg[0];
840 mpw->data.dseg[1] = &mpw->wqe->mpw.dseg[1];
841 mpw->data.dseg[2] = &(*dseg)[0];
842 mpw->data.dseg[3] = &(*dseg)[1];
843 mpw->data.dseg[4] = &(*dseg)[2];
847 * Close a MPW session.
850 * Pointer to TX queue structure.
852 * Pointer to MPW session structure.
855 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
857 unsigned int num = mpw->pkts_n;
860 * Store size in multiple of 16 bytes. Control and Ethernet segments
863 mpw->wqe->mpw.ctrl.data[1] = htonl(txq->qp_num_8s | (2 + num));
864 mpw->state = MLX5_MPW_STATE_CLOSED;
869 tx_prefetch_wqe(txq, txq->wqe_ci);
870 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
874 * DPDK callback for TX with MPW support.
877 * Generic pointer to TX queue structure.
879 * Packets to transmit.
881 * Number of packets in array.
884 * Number of packets successfully transmitted (<= pkts_n).
887 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
889 struct txq *txq = (struct txq *)dpdk_txq;
890 uint16_t elts_head = txq->elts_head;
891 const unsigned int elts_n = txq->elts_n;
895 struct mlx5_mpw mpw = {
896 .state = MLX5_MPW_STATE_CLOSED,
899 if (unlikely(!pkts_n))
901 /* Prefetch first packet cacheline. */
902 tx_prefetch_cqe(txq, txq->cq_ci);
903 tx_prefetch_wqe(txq, txq->wqe_ci);
904 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
905 /* Start processing. */
907 max = (elts_n - (elts_head - txq->elts_tail));
911 struct rte_mbuf *buf;
912 volatile struct mlx5_wqe_data_seg *dseg;
913 unsigned int elts_head_next;
916 uint32_t cs_flags = 0;
919 * Make sure there is enough room to store this packet and
920 * that one ring entry remains unused.
927 elts_head_next = (elts_head + 1) & (elts_n - 1);
928 /* Should we enable HW CKSUM offload */
930 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
931 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
932 /* Retrieve buffer information. */
933 addr = rte_pktmbuf_mtod(buf, uintptr_t);
934 length = DATA_LEN(buf);
935 /* Update element. */
936 (*txq->elts)[elts_head] = buf;
937 /* Start new session if packet differs. */
938 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
939 ((mpw.len != length) ||
940 (mpw.wqe->mpw.eseg.cs_flags != cs_flags)))
941 mlx5_mpw_close(txq, &mpw);
942 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
943 mlx5_mpw_new(txq, &mpw, length);
944 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
946 dseg = mpw.data.dseg[mpw.pkts_n];
947 *dseg = (struct mlx5_wqe_data_seg){
948 .byte_count = htonl(length),
949 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
950 .addr = htonll(addr),
953 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
954 mlx5_mpw_close(txq, &mpw);
955 elts_head = elts_head_next;
956 #ifdef MLX5_PMD_SOFT_COUNTERS
957 /* Increment sent bytes counter. */
958 txq->stats.obytes += length;
962 /* Take a shortcut if nothing must be sent. */
963 if (unlikely(i == 0))
965 /* Check whether completion threshold has been reached. */
966 comp = txq->elts_comp + i;
967 if (comp >= MLX5_TX_COMP_THRESH) {
968 volatile union mlx5_wqe *wqe = mpw.wqe;
970 /* Request completion on last WQE. */
971 wqe->mpw.ctrl.data[2] = htonl(8);
972 /* Save elts_head in unused "immediate" field of WQE. */
973 wqe->mpw.ctrl.data[3] = elts_head;
976 txq->elts_comp = comp;
978 #ifdef MLX5_PMD_SOFT_COUNTERS
979 /* Increment sent packets counter. */
980 txq->stats.opackets += i;
982 /* Ring QP doorbell. */
983 if (mpw.state == MLX5_MPW_STATE_OPENED)
984 mlx5_mpw_close(txq, &mpw);
986 txq->elts_head = elts_head;
991 * Open a MPW inline session.
994 * Pointer to TX queue structure.
996 * Pointer to MPW session structure.
1001 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1003 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
1005 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1009 mpw->wqe = &(*txq->wqes)[idx];
1010 mpw->wqe->mpw_inl.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1011 (txq->wqe_ci << 8) |
1012 MLX5_OPCODE_LSO_MPW);
1013 mpw->wqe->mpw_inl.ctrl.data[2] = 0;
1014 mpw->wqe->mpw_inl.ctrl.data[3] = 0;
1015 mpw->wqe->mpw_inl.eseg.mss = htons(length);
1016 mpw->wqe->mpw_inl.eseg.inline_hdr_sz = 0;
1017 mpw->wqe->mpw_inl.eseg.cs_flags = 0;
1018 mpw->wqe->mpw_inl.eseg.rsvd0 = 0;
1019 mpw->wqe->mpw_inl.eseg.rsvd1 = 0;
1020 mpw->wqe->mpw_inl.eseg.rsvd2 = 0;
1021 mpw->data.raw = &mpw->wqe->mpw_inl.data[0];
1025 * Close a MPW inline session.
1028 * Pointer to TX queue structure.
1030 * Pointer to MPW session structure.
1033 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1037 size = sizeof(*mpw->wqe) - MLX5_MWQE64_INL_DATA + mpw->total_len;
1039 * Store size in multiple of 16 bytes. Control and Ethernet segments
1042 mpw->wqe->mpw_inl.ctrl.data[1] =
1043 htonl(txq->qp_num_8s | ((size + 15) / 16));
1044 mpw->state = MLX5_MPW_STATE_CLOSED;
1045 mpw->wqe->mpw_inl.byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1046 txq->wqe_ci += (size + (sizeof(*mpw->wqe) - 1)) / sizeof(*mpw->wqe);
1050 * DPDK callback for TX with MPW inline support.
1053 * Generic pointer to TX queue structure.
1055 * Packets to transmit.
1057 * Number of packets in array.
1060 * Number of packets successfully transmitted (<= pkts_n).
1063 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1066 struct txq *txq = (struct txq *)dpdk_txq;
1067 uint16_t elts_head = txq->elts_head;
1068 const unsigned int elts_n = txq->elts_n;
1072 unsigned int inline_room = txq->max_inline;
1073 struct mlx5_mpw mpw = {
1074 .state = MLX5_MPW_STATE_CLOSED,
1077 if (unlikely(!pkts_n))
1079 /* Prefetch first packet cacheline. */
1080 tx_prefetch_cqe(txq, txq->cq_ci);
1081 tx_prefetch_wqe(txq, txq->wqe_ci);
1082 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
1083 /* Start processing. */
1085 max = (elts_n - (elts_head - txq->elts_tail));
1089 struct rte_mbuf *buf;
1090 unsigned int elts_head_next;
1093 uint32_t cs_flags = 0;
1096 * Make sure there is enough room to store this packet and
1097 * that one ring entry remains unused.
1104 elts_head_next = (elts_head + 1) & (elts_n - 1);
1105 /* Should we enable HW CKSUM offload */
1107 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1108 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1109 /* Retrieve buffer information. */
1110 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1111 length = DATA_LEN(buf);
1112 /* Update element. */
1113 (*txq->elts)[elts_head] = buf;
1114 /* Start new session if packet differs. */
1115 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1116 if ((mpw.len != length) ||
1117 (mpw.wqe->mpw.eseg.cs_flags != cs_flags))
1118 mlx5_mpw_close(txq, &mpw);
1119 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1120 if ((mpw.len != length) ||
1121 (length > inline_room) ||
1122 (mpw.wqe->mpw_inl.eseg.cs_flags != cs_flags)) {
1123 mlx5_mpw_inline_close(txq, &mpw);
1124 inline_room = txq->max_inline;
1127 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1128 if (length > inline_room) {
1129 mlx5_mpw_new(txq, &mpw, length);
1130 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1132 mlx5_mpw_inline_new(txq, &mpw, length);
1133 mpw.wqe->mpw_inl.eseg.cs_flags = cs_flags;
1136 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1137 volatile struct mlx5_wqe_data_seg *dseg;
1139 assert(inline_room == txq->max_inline);
1140 dseg = mpw.data.dseg[mpw.pkts_n];
1141 *dseg = (struct mlx5_wqe_data_seg){
1142 .byte_count = htonl(length),
1143 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1144 .addr = htonll(addr),
1147 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1148 mlx5_mpw_close(txq, &mpw);
1152 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1153 assert(length <= inline_room);
1154 /* Maximum number of bytes before wrapping. */
1155 max = ((uintptr_t)&(*txq->wqes)[txq->wqe_n] -
1156 (uintptr_t)mpw.data.raw);
1158 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1162 (volatile void *)&(*txq->wqes)[0];
1163 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1164 (void *)(addr + max),
1166 mpw.data.raw += length - max;
1168 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1171 mpw.data.raw += length;
1173 if ((uintptr_t)mpw.data.raw ==
1174 (uintptr_t)&(*txq->wqes)[txq->wqe_n])
1176 (volatile void *)&(*txq->wqes)[0];
1178 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1179 mlx5_mpw_inline_close(txq, &mpw);
1180 inline_room = txq->max_inline;
1182 inline_room -= length;
1185 mpw.total_len += length;
1186 elts_head = elts_head_next;
1187 #ifdef MLX5_PMD_SOFT_COUNTERS
1188 /* Increment sent bytes counter. */
1189 txq->stats.obytes += length;
1193 /* Take a shortcut if nothing must be sent. */
1194 if (unlikely(i == 0))
1196 /* Check whether completion threshold has been reached. */
1197 comp = txq->elts_comp + i;
1198 if (comp >= MLX5_TX_COMP_THRESH) {
1199 volatile union mlx5_wqe *wqe = mpw.wqe;
1201 /* Request completion on last WQE. */
1202 wqe->mpw_inl.ctrl.data[2] = htonl(8);
1203 /* Save elts_head in unused "immediate" field of WQE. */
1204 wqe->mpw_inl.ctrl.data[3] = elts_head;
1207 txq->elts_comp = comp;
1209 #ifdef MLX5_PMD_SOFT_COUNTERS
1210 /* Increment sent packets counter. */
1211 txq->stats.opackets += i;
1213 /* Ring QP doorbell. */
1214 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1215 mlx5_mpw_inline_close(txq, &mpw);
1216 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1217 mlx5_mpw_close(txq, &mpw);
1219 txq->elts_head = elts_head;
1224 * Translate RX completion flags to packet type.
1229 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1232 * Packet type for struct rte_mbuf.
1234 static inline uint32_t
1235 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1238 uint8_t flags = cqe->l4_hdr_type_etc;
1239 uint8_t info = cqe->rsvd0[0];
1241 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1244 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1245 RTE_PTYPE_L3_IPV4) |
1247 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1248 RTE_PTYPE_L3_IPV6) |
1250 IBV_EXP_CQ_RX_IPV4_PACKET,
1251 RTE_PTYPE_INNER_L3_IPV4) |
1253 IBV_EXP_CQ_RX_IPV6_PACKET,
1254 RTE_PTYPE_INNER_L3_IPV6);
1258 MLX5_CQE_L3_HDR_TYPE_IPV6,
1259 RTE_PTYPE_L3_IPV6) |
1261 MLX5_CQE_L3_HDR_TYPE_IPV4,
1267 * Get size of the next packet for a given CQE. For compressed CQEs, the
1268 * consumer index is updated only once all packets of the current one have
1272 * Pointer to RX queue.
1277 * Packet size in bytes (0 if there is none), -1 in case of completion
1281 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1284 struct rxq_zip *zip = &rxq->zip;
1285 uint16_t cqe_n = cqe_cnt + 1;
1288 /* Process compressed data in the CQE and mini arrays. */
1290 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1291 (volatile struct mlx5_mini_cqe8 (*)[8])
1292 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1294 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1295 if ((++zip->ai & 7) == 0) {
1297 * Increment consumer index to skip the number of
1298 * CQEs consumed. Hardware leaves holes in the CQ
1299 * ring for software use.
1304 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1305 uint16_t idx = rxq->cq_ci;
1306 uint16_t end = zip->cq_ci;
1308 while (idx != end) {
1309 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1310 MLX5_CQE_INVALIDATE;
1313 rxq->cq_ci = zip->cq_ci;
1316 /* No compressed data, get next CQE and verify if it is compressed. */
1321 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1322 if (unlikely(ret == 1))
1325 op_own = cqe->op_own;
1326 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1327 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1328 (volatile struct mlx5_mini_cqe8 (*)[8])
1329 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1332 /* Fix endianness. */
1333 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1335 * Current mini array position is the one returned by
1338 * If completion comprises several mini arrays, as a
1339 * special case the second one is located 7 CQEs after
1340 * the initial CQE instead of 8 for subsequent ones.
1342 zip->ca = rxq->cq_ci & cqe_cnt;
1343 zip->na = zip->ca + 7;
1344 /* Compute the next non compressed CQE. */
1346 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1347 /* Get packet size to return. */
1348 len = ntohl((*mc)[0].byte_cnt);
1351 len = ntohl(cqe->byte_cnt);
1353 /* Error while receiving packet. */
1354 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1361 * Translate RX completion flags to offload flags.
1364 * Pointer to RX queue structure.
1369 * Offload flags (ol_flags) for struct rte_mbuf.
1371 static inline uint32_t
1372 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1374 uint32_t ol_flags = 0;
1375 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1376 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1377 uint8_t info = cqe->rsvd0[0];
1379 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1380 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1382 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1383 PKT_RX_IP_CKSUM_BAD);
1384 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1385 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1386 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1387 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1389 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1390 PKT_RX_L4_CKSUM_BAD);
1392 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1393 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1396 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1398 TRANSPOSE(~cqe->l4_hdr_type_etc,
1399 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1400 PKT_RX_IP_CKSUM_BAD) |
1401 TRANSPOSE(~cqe->l4_hdr_type_etc,
1402 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1403 PKT_RX_L4_CKSUM_BAD);
1408 * DPDK callback for RX.
1411 * Generic pointer to RX queue structure.
1413 * Array to store received packets.
1415 * Maximum number of packets in array.
1418 * Number of packets successfully received (<= pkts_n).
1421 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1423 struct rxq *rxq = dpdk_rxq;
1424 unsigned int pkts_ret = 0;
1426 unsigned int rq_ci = rxq->rq_ci;
1427 const unsigned int elts_n = rxq->elts_n;
1428 const unsigned int wqe_cnt = elts_n - 1;
1429 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1431 for (i = 0; (i != pkts_n); ++i) {
1432 unsigned int idx = rq_ci & wqe_cnt;
1434 struct rte_mbuf *rep;
1435 struct rte_mbuf *pkt;
1436 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1437 volatile struct mlx5_cqe64 *cqe =
1438 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1440 pkt = (*rxq->elts)[idx];
1442 rep = rte_mbuf_raw_alloc(rxq->mp);
1443 if (unlikely(rep == NULL)) {
1444 ++rxq->stats.rx_nombuf;
1447 SET_DATA_OFF(rep, RTE_PKTMBUF_HEADROOM);
1449 PORT(rep) = rxq->port_id;
1451 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1452 if (unlikely(len == 0)) {
1453 rte_mbuf_refcnt_set(rep, 0);
1454 __rte_mbuf_raw_free(rep);
1457 if (unlikely(len == -1)) {
1458 /* RX error, packet is likely too large. */
1459 rte_mbuf_refcnt_set(rep, 0);
1460 __rte_mbuf_raw_free(rep);
1461 ++rxq->stats.idropped;
1466 * Fill NIC descriptor with the new buffer. The lkey and size
1467 * of the buffers are already known, only the buffer address
1470 wqe->addr = htonll((uintptr_t)rep->buf_addr +
1471 RTE_PKTMBUF_HEADROOM);
1472 (*rxq->elts)[idx] = rep;
1473 /* Update pkt information. */
1474 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1477 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1478 pkt->ol_flags = rxq_cq_to_ol_flags(rxq, cqe);
1480 if (cqe->l4_hdr_type_etc & MLX5_CQE_VLAN_STRIPPED) {
1481 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1482 PKT_RX_VLAN_STRIPPED;
1483 pkt->vlan_tci = ntohs(cqe->vlan_info);
1485 if (rxq->crc_present)
1486 len -= ETHER_CRC_LEN;
1489 DATA_LEN(pkt) = len;
1490 #ifdef MLX5_PMD_SOFT_COUNTERS
1491 /* Increment bytes counter. */
1492 rxq->stats.ibytes += len;
1494 /* Return packet. */
1500 if (unlikely((i == 0) && (rq_ci == rxq->rq_ci)))
1504 DEBUG("%p: reposting %u WRs", (void *)rxq, i);
1506 /* Update the consumer index. */
1509 *rxq->cq_db = htonl(rxq->cq_ci);
1511 *rxq->rq_db = htonl(rxq->rq_ci);
1512 #ifdef MLX5_PMD_SOFT_COUNTERS
1513 /* Increment packets counter. */
1514 rxq->stats.ipackets += pkts_ret;
1520 * Dummy DPDK callback for TX.
1522 * This function is used to temporarily replace the real callback during
1523 * unsafe control operations on the queue, or in case of error.
1526 * Generic pointer to TX queue structure.
1528 * Packets to transmit.
1530 * Number of packets in array.
1533 * Number of packets successfully transmitted (<= pkts_n).
1536 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1545 * Dummy DPDK callback for RX.
1547 * This function is used to temporarily replace the real callback during
1548 * unsafe control operations on the queue, or in case of error.
1551 * Generic pointer to RX queue structure.
1553 * Array to store received packets.
1555 * Maximum number of packets in array.
1558 * Number of packets successfully received (<= pkts_n).
1561 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)