1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
40 #include "mlx5_glue.h"
42 /* Support tunnel matching. */
43 #define MLX5_FLOW_TUNNEL 5
45 struct mlx5_rxq_stats {
46 #ifdef MLX5_PMD_SOFT_COUNTERS
47 uint64_t ipackets; /**< Total of successfully received packets. */
48 uint64_t ibytes; /**< Total of successfully received bytes. */
50 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
51 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
54 struct mlx5_txq_stats {
55 #ifdef MLX5_PMD_SOFT_COUNTERS
56 uint64_t opackets; /**< Total of successfully sent packets. */
57 uint64_t obytes; /**< Total of successfully sent bytes. */
59 uint64_t oerrors; /**< Total number of failed transmitted packets. */
64 /* Compressed CQE context. */
66 uint16_t ai; /* Array index. */
67 uint16_t ca; /* Current array index. */
68 uint16_t na; /* Next array index. */
69 uint16_t cq_ci; /* The next CQE. */
70 uint32_t cqe_cnt; /* Number of CQEs. */
73 /* Multi-Packet RQ buffer header. */
74 struct mlx5_mprq_buf {
75 struct rte_mempool *mp;
76 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
77 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
78 struct rte_mbuf_ext_shared_info shinfos[];
80 * Shared information per stride.
81 * More memory will be allocated for the first stride head-room and for
84 } __rte_cache_aligned;
86 /* Get pointer to the first stride. */
87 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
88 sizeof(struct mlx5_mprq_buf) + \
90 sizeof(struct rte_mbuf_ext_shared_info) + \
91 RTE_PKTMBUF_HEADROOM))
93 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
94 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
96 enum mlx5_rxq_err_state {
97 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
98 MLX5_RXQ_ERR_STATE_NEED_RESET,
99 MLX5_RXQ_ERR_STATE_NEED_READY,
102 /* RX queue descriptor. */
103 struct mlx5_rxq_data {
104 unsigned int csum:1; /* Enable checksum offloading. */
105 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
106 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
107 unsigned int crc_present:1; /* CRC must be subtracted. */
108 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
109 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
110 unsigned int elts_n:4; /* Log 2 of Mbufs. */
111 unsigned int rss_hash:1; /* RSS hash result is enabled. */
112 unsigned int mark:1; /* Marked flow available on the queue. */
113 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
114 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
115 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
116 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
117 unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
118 unsigned int :3; /* Remaining bits. */
119 volatile uint32_t *rq_db;
120 volatile uint32_t *cq_db;
123 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
126 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
128 struct rxq_zip zip; /* Compressed context. */
129 uint16_t decompressed;
130 /* Number of ready mbufs decompressed from the CQ. */
132 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
133 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
135 volatile struct mlx5_cqe(*cqes)[];
138 struct rte_mbuf *(*elts)[];
139 struct mlx5_mprq_buf *(*mprq_bufs)[];
141 struct rte_mempool *mp;
142 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
143 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
144 uint16_t idx; /* Queue index. */
145 struct mlx5_rxq_stats stats;
146 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
147 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
148 void *cq_uar; /* CQ user access region. */
149 uint32_t cqn; /* CQ number. */
150 uint8_t cq_arm_sn; /* CQ arm seq number. */
152 rte_spinlock_t *uar_lock_cq;
153 /* CQ (UAR) access lock required for 32bit implementations */
155 uint32_t tunnel; /* Tunnel information. */
156 } __rte_cache_aligned;
158 enum mlx5_rxq_obj_type {
159 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
160 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
163 /* Verbs/DevX Rx queue elements. */
164 struct mlx5_rxq_obj {
165 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
166 rte_atomic32_t refcnt; /* Reference counter. */
167 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
168 struct ibv_cq *cq; /* Completion Queue. */
169 enum mlx5_rxq_obj_type type;
172 struct ibv_wq *wq; /* Work Queue. */
173 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
175 struct ibv_comp_channel *channel;
178 /* RX queue control descriptor. */
179 struct mlx5_rxq_ctrl {
180 struct mlx5_rxq_data rxq; /* Data path structure. */
181 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
182 rte_atomic32_t refcnt; /* Reference counter. */
183 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
184 struct mlx5_priv *priv; /* Back pointer to private data. */
185 unsigned int socket; /* CPU socket ID for allocations. */
186 unsigned int irq:1; /* Whether IRQ is enabled. */
187 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
188 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
189 uint32_t wqn; /* WQ number. */
190 uint16_t dump_file_n; /* Number of dump files. */
191 uint32_t dbr_umem_id; /* Storing door-bell information, */
192 uint64_t dbr_offset; /* needed when freeing door-bell. */
193 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
196 enum mlx5_ind_tbl_type {
197 MLX5_IND_TBL_TYPE_IBV,
198 MLX5_IND_TBL_TYPE_DEVX,
201 /* Indirection table. */
202 struct mlx5_ind_table_obj {
203 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
204 rte_atomic32_t refcnt; /* Reference counter. */
205 enum mlx5_ind_tbl_type type;
208 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
209 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
211 uint32_t queues_n; /**< Number of queues in the list. */
212 uint16_t queues[]; /**< Queue list. */
217 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
218 rte_atomic32_t refcnt; /* Reference counter. */
219 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
222 struct ibv_qp *qp; /* Verbs queue pair. */
223 struct mlx5_devx_obj *tir; /* DevX TIR object. */
225 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
226 void *action; /* DV QP action pointer. */
228 uint64_t hash_fields; /* Verbs Hash fields. */
229 uint32_t rss_key_len; /* Hash key length in bytes. */
230 uint8_t rss_key[]; /* Hash key. */
233 /* TX queue send local data. */
235 struct mlx5_txq_local {
236 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
237 struct rte_mbuf *mbuf; /* first mbuf to process. */
238 uint16_t pkts_copy; /* packets copied to elts. */
239 uint16_t pkts_sent; /* packets sent. */
240 uint16_t elts_free; /* available elts remain. */
241 uint16_t wqe_free; /* available wqe remain. */
242 uint16_t mbuf_off; /* data offset in current mbuf. */
243 uint16_t mbuf_nseg; /* number of remaining mbuf. */
246 /* TX queue descriptor. */
248 struct mlx5_txq_data {
249 uint16_t elts_head; /* Current counter in (*elts)[]. */
250 uint16_t elts_tail; /* Counter of first element awaiting completion. */
251 uint16_t elts_comp; /* elts index since last completion request. */
252 uint16_t elts_s; /* Number of mbuf elements. */
253 uint16_t elts_m; /* Mask for mbuf elements indices. */
254 /* Fields related to elts mbuf storage. */
255 uint16_t wqe_ci; /* Consumer index for work queue. */
256 uint16_t wqe_pi; /* Producer index for work queue. */
257 uint16_t wqe_s; /* Number of WQ elements. */
258 uint16_t wqe_m; /* Mask Number for WQ elements. */
259 uint16_t wqe_comp; /* WQE index since last completion request. */
260 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
261 /* WQ related fields. */
262 uint16_t cq_ci; /* Consumer index for completion queue. */
264 uint16_t cq_pi; /* Counter of issued CQE "always" requests. */
266 uint16_t cqe_s; /* Number of CQ elements. */
267 uint16_t cqe_m; /* Mask for CQ indices. */
268 /* CQ related fields. */
269 uint16_t elts_n:4; /* elts[] length (in log2). */
270 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
271 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
272 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
273 uint16_t tunnel_en:1;
274 /* When set TX offload for tunneled packets are supported. */
275 uint16_t swp_en:1; /* Whether SW parser is enabled. */
276 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
277 uint16_t inlen_send; /* Ordinary send data inline size. */
278 uint16_t inlen_empw; /* eMPW max packet size to inline. */
279 uint16_t inlen_mode; /* Minimal data length to inline. */
280 uint32_t qp_num_8s; /* QP number shifted by 8. */
281 uint64_t offloads; /* Offloads for Tx Queue. */
282 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
283 struct mlx5_wqe *wqes; /* Work queue. */
284 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
285 volatile struct mlx5_cqe *cqes; /* Completion queue. */
286 volatile uint32_t *qp_db; /* Work queue doorbell. */
287 volatile uint32_t *cq_db; /* Completion queue doorbell. */
288 uint16_t port_id; /* Port ID of device. */
289 uint16_t idx; /* Queue index. */
290 struct mlx5_txq_stats stats; /* TX queue counters. */
292 rte_spinlock_t *uar_lock;
293 /* UAR access lock required for 32bit implementations */
295 struct rte_mbuf *elts[0];
296 /* Storage for queued packets, must be the last field. */
297 } __rte_cache_aligned;
299 /* Verbs Rx queue elements. */
300 struct mlx5_txq_ibv {
301 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
302 rte_atomic32_t refcnt; /* Reference counter. */
303 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
304 struct ibv_cq *cq; /* Completion Queue. */
305 struct ibv_qp *qp; /* Queue Pair. */
308 /* TX queue control descriptor. */
309 struct mlx5_txq_ctrl {
310 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
311 rte_atomic32_t refcnt; /* Reference counter. */
312 unsigned int socket; /* CPU socket ID for allocations. */
313 unsigned int max_inline_data; /* Max inline data. */
314 unsigned int max_tso_header; /* Max TSO header size. */
315 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
316 struct mlx5_priv *priv; /* Back pointer to private data. */
317 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
318 void *bf_reg; /* BlueFlame register from Verbs. */
319 uint16_t dump_file_n; /* Number of dump files. */
320 struct mlx5_txq_data txq; /* Data path structure. */
321 /* Must be the last field in the structure, contains elts[]. */
324 #define MLX5_TX_BFREG(txq) \
325 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
329 extern uint8_t rss_hash_default_key[];
331 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
332 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
333 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
334 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
335 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
336 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
337 unsigned int socket, const struct rte_eth_rxconf *conf,
338 struct rte_mempool *mp);
339 void mlx5_rx_queue_release(void *dpdk_rxq);
340 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
341 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
342 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
343 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
344 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
345 enum mlx5_rxq_obj_type type);
346 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
347 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
348 uint16_t desc, unsigned int socket,
349 const struct rte_eth_rxconf *conf,
350 struct rte_mempool *mp);
351 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
352 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
353 int mlx5_rxq_verify(struct rte_eth_dev *dev);
354 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
355 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
356 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
357 const uint8_t *rss_key, uint32_t rss_key_len,
358 uint64_t hash_fields,
359 const uint16_t *queues, uint32_t queues_n,
360 int tunnel __rte_unused, int lro);
361 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
362 const uint8_t *rss_key, uint32_t rss_key_len,
363 uint64_t hash_fields,
364 const uint16_t *queues, uint32_t queues_n);
365 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
366 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
367 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
368 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
369 uint64_t mlx5_get_rx_port_offloads(struct rte_eth_dev *dev);
370 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
371 int mlx5_lro_on(struct rte_eth_dev *dev);
375 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
376 unsigned int socket, const struct rte_eth_txconf *conf);
377 void mlx5_tx_queue_release(void *dpdk_txq);
378 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
379 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
380 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
381 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
382 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
383 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
384 uint16_t desc, unsigned int socket,
385 const struct rte_eth_txconf *conf);
386 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
387 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
388 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
389 int mlx5_txq_verify(struct rte_eth_dev *dev);
390 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
391 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
395 extern uint32_t mlx5_ptype_table[];
396 extern uint8_t mlx5_cksum_table[];
397 extern uint8_t mlx5_swp_types_table[];
399 void mlx5_set_ptype_table(void);
400 void mlx5_set_cksum_table(void);
401 void mlx5_set_swp_types_table(void);
402 __rte_noinline uint16_t mlx5_tx_error_cqe_handle
403 (struct mlx5_txq_data *restrict txq,
404 volatile struct mlx5_err_cqe *err_cqe);
405 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
406 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
407 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq,
408 uint8_t mbuf_prepare);
409 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
410 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
411 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
413 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
415 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
417 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
418 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
419 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
420 void mlx5_dump_debug_information(const char *path, const char *title,
421 const void *buf, unsigned int len);
422 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
423 const struct mlx5_mp_arg_queue_state_modify *sm);
425 /* Vectorized version of mlx5_rxtx.c */
426 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
427 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
428 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
433 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
434 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
435 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
436 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
437 struct rte_mempool *mp);
438 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
440 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
444 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
445 * 64bit architectures.
448 * value to write in CPU endian format.
450 * Address to write to.
452 * Address of the lock to use for that UAR access.
454 static __rte_always_inline void
455 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
456 rte_spinlock_t *lock __rte_unused)
459 *(uint64_t *)addr = val;
460 #else /* !RTE_ARCH_64 */
461 rte_spinlock_lock(lock);
462 *(uint32_t *)addr = val;
464 *((uint32_t *)addr + 1) = val >> 32;
465 rte_spinlock_unlock(lock);
470 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
471 * 64bit architectures while guaranteeing the order of execution with the
472 * code being executed.
475 * value to write in CPU endian format.
477 * Address to write to.
479 * Address of the lock to use for that UAR access.
481 static __rte_always_inline void
482 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
485 __mlx5_uar_write64_relaxed(val, addr, lock);
488 /* Assist macros, used instead of directly calling the functions they wrap. */
490 #define mlx5_uar_write64_relaxed(val, dst, lock) \
491 __mlx5_uar_write64_relaxed(val, dst, NULL)
492 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
494 #define mlx5_uar_write64_relaxed(val, dst, lock) \
495 __mlx5_uar_write64_relaxed(val, dst, lock)
496 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
500 enum mlx5_cqe_status {
501 MLX5_CQE_STATUS_SW_OWN,
502 MLX5_CQE_STATUS_HW_OWN,
507 * Check whether CQE is valid.
512 * Size of completion queue.
519 static __rte_always_inline enum mlx5_cqe_status
520 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
523 const uint16_t idx = ci & cqes_n;
524 const uint8_t op_own = cqe->op_own;
525 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
526 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
528 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
529 return MLX5_CQE_STATUS_HW_OWN;
531 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
532 op_code == MLX5_CQE_REQ_ERR))
533 return MLX5_CQE_STATUS_ERR;
534 return MLX5_CQE_STATUS_SW_OWN;
538 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
539 * cloned mbuf is allocated is returned instead.
545 * Memory pool where data is located for given mbuf.
547 static inline struct rte_mempool *
548 mlx5_mb2mp(struct rte_mbuf *buf)
550 if (unlikely(RTE_MBUF_CLONED(buf)))
551 return rte_mbuf_from_indirect(buf)->pool;
556 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
557 * as mempool is pre-configured and static.
560 * Pointer to Rx queue structure.
565 * Searched LKey on success, UINT32_MAX on no match.
567 static __rte_always_inline uint32_t
568 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
570 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
573 /* Linear search on MR cache array. */
574 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
575 MLX5_MR_CACHE_N, addr);
576 if (likely(lkey != UINT32_MAX))
578 /* Take slower bottom-half (Binary Search) on miss. */
579 return mlx5_rx_addr2mr_bh(rxq, addr);
582 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
585 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
588 * Pointer to Tx queue structure.
593 * Searched LKey on success, UINT32_MAX on no match.
595 static __rte_always_inline uint32_t
596 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
598 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
599 uintptr_t addr = (uintptr_t)mb->buf_addr;
602 /* Check generation bit to see if there's any change on existing MRs. */
603 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
604 mlx5_mr_flush_local_cache(mr_ctrl);
605 /* Linear search on MR cache array. */
606 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
607 MLX5_MR_CACHE_N, addr);
608 if (likely(lkey != UINT32_MAX))
610 /* Take slower bottom-half on miss. */
611 return mlx5_tx_mb2mr_bh(txq, mb);
615 * Ring TX queue doorbell and flush the update if requested.
618 * Pointer to TX queue structure.
620 * Pointer to the last WQE posted in the NIC.
622 * Request for write memory barrier after BlueFlame update.
624 static __rte_always_inline void
625 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
628 uint64_t *dst = MLX5_TX_BFREG(txq);
629 volatile uint64_t *src = ((volatile uint64_t *)wqe);
632 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
633 /* Ensure ordering between DB record and BF copy. */
635 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
641 * Ring TX queue doorbell and flush the update by write memory barrier.
644 * Pointer to TX queue structure.
646 * Pointer to the last WQE posted in the NIC.
648 static __rte_always_inline void
649 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
651 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
654 #endif /* RTE_PMD_MLX5_RXTX_H_ */