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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 struct mlx5_rxq_stats {
69 unsigned int idx; /**< Mapping index. */
70 #ifdef MLX5_PMD_SOFT_COUNTERS
71 uint64_t ipackets; /**< Total of successfully received packets. */
72 uint64_t ibytes; /**< Total of successfully received bytes. */
74 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
75 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
78 struct mlx5_txq_stats {
79 unsigned int idx; /**< Mapping index. */
80 #ifdef MLX5_PMD_SOFT_COUNTERS
81 uint64_t opackets; /**< Total of successfully sent packets. */
82 uint64_t obytes; /**< Total of successfully sent bytes. */
84 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
87 /* Flow director queue structure. */
89 struct ibv_qp *qp; /* Associated RX QP. */
90 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
91 struct ibv_exp_wq *wq; /* Work queue. */
92 struct ibv_cq *cq; /* Completion queue. */
97 /* Compressed CQE context. */
99 uint16_t ai; /* Array index. */
100 uint16_t ca; /* Current array index. */
101 uint16_t na; /* Next array index. */
102 uint16_t cq_ci; /* The next CQE. */
103 uint32_t cqe_cnt; /* Number of CQEs. */
106 /* RX queue descriptor. */
108 unsigned int csum:1; /* Enable checksum offloading. */
109 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int port_id:8;
116 unsigned int rss_hash:1; /* RSS hash result is enabled. */
117 unsigned int mark:1; /* Marked flow available on the queue. */
118 unsigned int :8; /* Remaining bits. */
119 volatile uint32_t *rq_db;
120 volatile uint32_t *cq_db;
123 volatile struct mlx5_wqe_data_seg(*wqes)[];
124 volatile struct mlx5_cqe(*cqes)[];
125 struct rxq_zip zip; /* Compressed context. */
126 struct rte_mbuf *(*elts)[];
127 struct rte_mempool *mp;
128 struct mlx5_rxq_stats stats;
129 } __rte_cache_aligned;
131 /* RX queue control descriptor. */
133 struct priv *priv; /* Back pointer to private data. */
134 struct ibv_cq *cq; /* Completion Queue. */
135 struct ibv_exp_wq *wq; /* Work Queue. */
136 struct ibv_exp_res_domain *rd; /* Resource Domain. */
137 struct fdir_queue *fdir_queue; /* Flow director queue. */
138 struct ibv_mr *mr; /* Memory Region (for mp). */
139 struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
140 struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
141 struct ibv_comp_channel *channel;
142 unsigned int socket; /* CPU socket ID for allocations. */
143 struct rxq rxq; /* Data path structure. */
146 /* Hash RX queue types. */
157 /* Flow structure with Ethernet specification. It is packed to prevent padding
158 * between attr and spec as this layout is expected by libibverbs. */
159 struct flow_attr_spec_eth {
160 struct ibv_exp_flow_attr attr;
161 struct ibv_exp_flow_spec_eth spec;
162 } __attribute__((packed));
164 /* Define a struct flow_attr_spec_eth object as an array of at least
165 * "size" bytes. Room after the first index is normally used to store
166 * extra flow specifications. */
167 #define FLOW_ATTR_SPEC_ETH(name, size) \
168 struct flow_attr_spec_eth name \
169 [((size) / sizeof(struct flow_attr_spec_eth)) + \
170 !!((size) % sizeof(struct flow_attr_spec_eth))]
172 /* Initialization data for hash RX queue. */
173 struct hash_rxq_init {
174 uint64_t hash_fields; /* Fields that participate in the hash. */
175 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
176 unsigned int flow_priority; /* Flow priority to use. */
179 enum ibv_exp_flow_spec_type type;
182 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
183 struct ibv_exp_flow_spec_ipv4 ipv4;
184 struct ibv_exp_flow_spec_ipv6 ipv6;
185 struct ibv_exp_flow_spec_eth eth;
186 } flow_spec; /* Flow specification template. */
187 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
190 /* Initialization data for indirection table. */
191 struct ind_table_init {
192 unsigned int max_size; /* Maximum number of WQs. */
193 /* Hash RX queues using this table. */
194 unsigned int hash_types;
195 unsigned int hash_types_n;
198 /* Initialization data for special flows. */
199 struct special_flow_init {
200 uint8_t dst_mac_val[6];
201 uint8_t dst_mac_mask[6];
202 unsigned int hash_types;
203 unsigned int per_vlan:1;
206 enum hash_rxq_flow_type {
207 HASH_RXQ_FLOW_TYPE_PROMISC,
208 HASH_RXQ_FLOW_TYPE_ALLMULTI,
209 HASH_RXQ_FLOW_TYPE_BROADCAST,
210 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
211 HASH_RXQ_FLOW_TYPE_MAC,
215 static inline const char *
216 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
219 case HASH_RXQ_FLOW_TYPE_PROMISC:
220 return "promiscuous";
221 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
222 return "allmulticast";
223 case HASH_RXQ_FLOW_TYPE_BROADCAST:
225 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
226 return "IPv6 multicast";
227 case HASH_RXQ_FLOW_TYPE_MAC:
235 struct priv *priv; /* Back pointer to private data. */
236 struct ibv_qp *qp; /* Hash RX QP. */
237 enum hash_rxq_type type; /* Hash RX queue type. */
238 /* MAC flow steering rules, one per VLAN ID. */
239 struct ibv_exp_flow *mac_flow
240 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
241 struct ibv_exp_flow *special_flow
242 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
245 /* TX queue descriptor. */
248 uint16_t elts_head; /* Current index in (*elts)[]. */
249 uint16_t elts_tail; /* First element awaiting completion. */
250 uint16_t elts_comp; /* Counter since last completion request. */
251 uint16_t mpw_comp; /* WQ index since last completion request. */
252 uint16_t cq_ci; /* Consumer index for completion queue. */
253 uint16_t cq_pi; /* Producer index for completion queue. */
254 uint16_t wqe_ci; /* Consumer index for work queue. */
255 uint16_t wqe_pi; /* Producer index for work queue. */
256 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
257 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
258 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
259 uint16_t inline_en:1; /* When set inline is enabled. */
260 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
261 uint16_t tunnel_en:1;
262 /* When set TX offload for tunneled packets are supported. */
263 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
264 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
265 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
266 uint32_t qp_num_8s; /* QP number shifted by 8. */
267 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
268 volatile void *wqes; /* Work queue (use volatile to write into). */
269 volatile uint32_t *qp_db; /* Work queue doorbell. */
270 volatile uint32_t *cq_db; /* Completion queue doorbell. */
271 volatile void *bf_reg; /* Blueflame register. */
273 const struct rte_mempool *mp; /* Cached Memory Pool. */
274 struct ibv_mr *mr; /* Memory Region (for mp). */
275 uint32_t lkey; /* htonl(mr->lkey) */
276 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
277 struct rte_mbuf *(*elts)[]; /* TX elements. */
278 struct mlx5_txq_stats stats; /* TX queue counters. */
279 } __rte_cache_aligned;
281 /* TX queue control descriptor. */
283 struct priv *priv; /* Back pointer to private data. */
284 struct ibv_cq *cq; /* Completion Queue. */
285 struct ibv_qp *qp; /* Queue Pair. */
286 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
287 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
288 struct ibv_exp_res_domain *rd; /* Resource Domain. */
289 unsigned int socket; /* CPU socket ID for allocations. */
290 struct txq txq; /* Data path structure. */
295 extern const struct hash_rxq_init hash_rxq_init[];
296 extern const unsigned int hash_rxq_init_n;
298 extern uint8_t rss_hash_default_key[];
299 extern const size_t rss_hash_default_key_len;
301 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
302 size_t, enum hash_rxq_type);
303 int priv_create_hash_rxqs(struct priv *);
304 void priv_destroy_hash_rxqs(struct priv *);
305 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
306 int priv_rehash_flows(struct priv *);
307 int priv_intr_efd_enable(struct priv *priv);
308 void priv_intr_efd_disable(struct priv *priv);
309 int priv_create_intr_vec(struct priv *priv);
310 void priv_destroy_intr_vec(struct priv *priv);
311 void rxq_cleanup(struct rxq_ctrl *);
312 int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
313 int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
314 unsigned int, const struct rte_eth_rxconf *,
315 struct rte_mempool *);
316 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
317 const struct rte_eth_rxconf *, struct rte_mempool *);
318 void mlx5_rx_queue_release(void *);
319 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
323 void txq_cleanup(struct txq_ctrl *);
324 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
325 unsigned int, const struct rte_eth_txconf *);
326 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
327 const struct rte_eth_txconf *);
328 void mlx5_tx_queue_release(void *);
329 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
333 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
334 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
335 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
336 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
337 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
338 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
339 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
340 int mlx5_rx_descriptor_status(void *, uint16_t);
341 int mlx5_tx_descriptor_status(void *, uint16_t);
342 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
343 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
347 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
348 void txq_mp2mr_iter(struct rte_mempool *, void *);
349 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
351 #endif /* RTE_PMD_MLX5_RXTX_H_ */