1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
30 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 struct mlx5_rxq_stats {
38 unsigned int idx; /**< Mapping index. */
39 #ifdef MLX5_PMD_SOFT_COUNTERS
40 uint64_t ipackets; /**< Total of successfully received packets. */
41 uint64_t ibytes; /**< Total of successfully received bytes. */
43 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
44 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
47 struct mlx5_txq_stats {
48 unsigned int idx; /**< Mapping index. */
49 #ifdef MLX5_PMD_SOFT_COUNTERS
50 uint64_t opackets; /**< Total of successfully sent packets. */
51 uint64_t obytes; /**< Total of successfully sent bytes. */
53 uint64_t oerrors; /**< Total number of failed transmitted packets. */
58 /* Compressed CQE context. */
60 uint16_t ai; /* Array index. */
61 uint16_t ca; /* Current array index. */
62 uint16_t na; /* Next array index. */
63 uint16_t cq_ci; /* The next CQE. */
64 uint32_t cqe_cnt; /* Number of CQEs. */
67 /* Multi-Packet RQ buffer header. */
68 struct mlx5_mprq_buf {
69 struct rte_mempool *mp;
70 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
71 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
72 } __rte_cache_aligned;
74 /* Get pointer to the first stride. */
75 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
77 /* RX queue descriptor. */
78 struct mlx5_rxq_data {
79 unsigned int csum:1; /* Enable checksum offloading. */
80 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
81 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
82 unsigned int crc_present:1; /* CRC must be subtracted. */
83 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
84 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
85 unsigned int elts_n:4; /* Log 2 of Mbufs. */
86 unsigned int rss_hash:1; /* RSS hash result is enabled. */
87 unsigned int mark:1; /* Marked flow available on the queue. */
88 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
89 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
90 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
91 unsigned int :6; /* Remaining bits. */
92 volatile uint32_t *rq_db;
93 volatile uint32_t *cq_db;
96 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
99 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
100 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
102 volatile struct mlx5_cqe(*cqes)[];
103 struct rxq_zip zip; /* Compressed context. */
106 struct rte_mbuf *(*elts)[];
107 struct mlx5_mprq_buf *(*mprq_bufs)[];
109 struct rte_mempool *mp;
110 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
111 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
112 struct mlx5_rxq_stats stats;
113 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
114 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
115 void *cq_uar; /* CQ user access region. */
116 uint32_t cqn; /* CQ number. */
117 uint8_t cq_arm_sn; /* CQ arm seq number. */
118 uint32_t tunnel; /* Tunnel information. */
119 } __rte_cache_aligned;
121 /* Verbs Rx queue elements. */
122 struct mlx5_rxq_ibv {
123 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
124 rte_atomic32_t refcnt; /* Reference counter. */
125 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
126 struct ibv_cq *cq; /* Completion Queue. */
127 struct ibv_wq *wq; /* Work Queue. */
128 struct ibv_comp_channel *channel;
131 /* RX queue control descriptor. */
132 struct mlx5_rxq_ctrl {
133 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
134 rte_atomic32_t refcnt; /* Reference counter. */
135 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
136 struct priv *priv; /* Back pointer to private data. */
137 struct mlx5_rxq_data rxq; /* Data path structure. */
138 unsigned int socket; /* CPU socket ID for allocations. */
139 unsigned int irq:1; /* Whether IRQ is enabled. */
140 uint16_t idx; /* Queue index. */
141 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
144 /* Indirection table. */
145 struct mlx5_ind_table_ibv {
146 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
147 rte_atomic32_t refcnt; /* Reference counter. */
148 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
149 uint32_t queues_n; /**< Number of queues in the list. */
150 uint16_t queues[]; /**< Queue list. */
155 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
156 rte_atomic32_t refcnt; /* Reference counter. */
157 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
158 struct ibv_qp *qp; /* Verbs queue pair. */
159 uint64_t hash_fields; /* Verbs Hash fields. */
160 uint32_t tunnel; /* Tunnel type. */
161 uint32_t rss_level; /* RSS on tunnel level. */
162 uint32_t rss_key_len; /* Hash key length in bytes. */
163 uint8_t rss_key[]; /* Hash key. */
166 /* TX queue descriptor. */
168 struct mlx5_txq_data {
169 uint16_t elts_head; /* Current counter in (*elts)[]. */
170 uint16_t elts_tail; /* Counter of first element awaiting completion. */
171 uint16_t elts_comp; /* Counter since last completion request. */
172 uint16_t mpw_comp; /* WQ index since last completion request. */
173 uint16_t cq_ci; /* Consumer index for completion queue. */
175 uint16_t cq_pi; /* Producer index for completion queue. */
177 uint16_t wqe_ci; /* Consumer index for work queue. */
178 uint16_t wqe_pi; /* Producer index for work queue. */
179 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
180 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
181 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
182 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
183 uint16_t tunnel_en:1;
184 /* When set TX offload for tunneled packets are supported. */
185 uint16_t swp_en:1; /* Whether SW parser is enabled. */
186 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
187 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
188 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
189 uint32_t qp_num_8s; /* QP number shifted by 8. */
190 uint64_t offloads; /* Offloads for Tx Queue. */
191 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
192 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
193 volatile void *wqes; /* Work queue (use volatile to write into). */
194 volatile uint32_t *qp_db; /* Work queue doorbell. */
195 volatile uint32_t *cq_db; /* Completion queue doorbell. */
196 volatile void *bf_reg; /* Blueflame register remapped. */
197 struct rte_mbuf *(*elts)[]; /* TX elements. */
198 struct mlx5_txq_stats stats; /* TX queue counters. */
199 } __rte_cache_aligned;
201 /* Verbs Rx queue elements. */
202 struct mlx5_txq_ibv {
203 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
204 rte_atomic32_t refcnt; /* Reference counter. */
205 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
206 struct ibv_cq *cq; /* Completion Queue. */
207 struct ibv_qp *qp; /* Queue Pair. */
210 /* TX queue control descriptor. */
211 struct mlx5_txq_ctrl {
212 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
213 rte_atomic32_t refcnt; /* Reference counter. */
214 unsigned int socket; /* CPU socket ID for allocations. */
215 unsigned int max_inline_data; /* Max inline data. */
216 unsigned int max_tso_header; /* Max TSO header size. */
217 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
218 struct priv *priv; /* Back pointer to private data. */
219 struct mlx5_txq_data txq; /* Data path structure. */
220 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
221 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
222 uint16_t idx; /* Queue index. */
227 extern uint8_t rss_hash_default_key[];
228 extern const size_t rss_hash_default_key_len;
230 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
231 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
232 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
233 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
234 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
235 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
236 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
237 unsigned int socket, const struct rte_eth_rxconf *conf,
238 struct rte_mempool *mp);
239 void mlx5_rx_queue_release(void *dpdk_rxq);
240 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
241 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
242 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
243 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
244 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
245 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
246 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
247 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
248 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
249 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
250 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
251 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
252 uint16_t desc, unsigned int socket,
253 const struct rte_eth_rxconf *conf,
254 struct rte_mempool *mp);
255 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
256 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
257 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
258 int mlx5_rxq_verify(struct rte_eth_dev *dev);
259 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
260 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
261 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
262 const uint16_t *queues,
264 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
265 const uint16_t *queues,
267 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
268 struct mlx5_ind_table_ibv *ind_tbl);
269 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
270 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
271 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
272 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
273 const uint8_t *rss_key, uint32_t rss_key_len,
274 uint64_t hash_fields,
275 const uint16_t *queues, uint32_t queues_n,
276 uint32_t tunnel, uint32_t rss_level);
277 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
278 const uint8_t *rss_key, uint32_t rss_key_len,
279 uint64_t hash_fields,
280 const uint16_t *queues, uint32_t queues_n,
281 uint32_t tunnel, uint32_t rss_level);
282 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
283 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
284 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
285 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
286 uint64_t mlx5_get_rx_port_offloads(void);
287 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
291 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
292 unsigned int socket, const struct rte_eth_txconf *conf);
293 void mlx5_tx_queue_release(void *dpdk_txq);
294 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
295 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
296 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
297 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
298 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
299 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
300 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
301 uint16_t desc, unsigned int socket,
302 const struct rte_eth_txconf *conf);
303 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
304 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
305 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
306 int mlx5_txq_verify(struct rte_eth_dev *dev);
307 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
308 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
312 extern uint32_t mlx5_ptype_table[];
313 extern uint8_t mlx5_cksum_table[];
314 extern uint8_t mlx5_swp_types_table[];
316 void mlx5_set_ptype_table(void);
317 void mlx5_set_cksum_table(void);
318 void mlx5_set_swp_types_table(void);
319 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
321 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
323 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
325 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
327 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
328 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
329 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
330 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
332 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
334 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
336 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
337 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
339 /* Vectorized version of mlx5_rxtx.c */
340 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
341 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
342 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
343 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
344 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
346 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
348 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
353 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
354 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
355 uint32_t mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr);
359 * Verify or set magic value in CQE.
368 check_cqe_seen(volatile struct mlx5_cqe *cqe)
370 static const uint8_t magic[] = "seen";
371 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
375 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
376 if (!ret || (*buf)[i] != magic[i]) {
378 (*buf)[i] = magic[i];
385 * Check whether CQE is valid.
390 * Size of completion queue.
395 * 0 on success, 1 on failure.
397 static __rte_always_inline int
398 check_cqe(volatile struct mlx5_cqe *cqe,
399 unsigned int cqes_n, const uint16_t ci)
401 uint16_t idx = ci & cqes_n;
402 uint8_t op_own = cqe->op_own;
403 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
404 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
406 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
407 return 1; /* No CQE. */
409 if ((op_code == MLX5_CQE_RESP_ERR) ||
410 (op_code == MLX5_CQE_REQ_ERR)) {
411 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
412 uint8_t syndrome = err_cqe->syndrome;
414 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
415 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
417 if (!check_cqe_seen(cqe)) {
419 "unexpected CQE error %u (0x%02x) syndrome"
421 op_code, op_code, syndrome);
422 rte_hexdump(stderr, "MLX5 Error CQE:",
423 (const void *)((uintptr_t)err_cqe),
427 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
428 (op_code != MLX5_CQE_REQ)) {
429 if (!check_cqe_seen(cqe)) {
430 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
432 rte_hexdump(stderr, "MLX5 CQE:",
433 (const void *)((uintptr_t)cqe),
443 * Return the address of the WQE.
446 * Pointer to TX queue structure.
448 * WQE consumer index.
453 static inline uintptr_t *
454 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
456 ci &= ((1 << txq->wqe_n) - 1);
457 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
461 * Manage TX completions.
463 * When sending a burst, mlx5_tx_burst() posts several WRs.
466 * Pointer to TX queue structure.
468 static __rte_always_inline void
469 mlx5_tx_complete(struct mlx5_txq_data *txq)
471 const uint16_t elts_n = 1 << txq->elts_n;
472 const uint16_t elts_m = elts_n - 1;
473 const unsigned int cqe_n = 1 << txq->cqe_n;
474 const unsigned int cqe_cnt = cqe_n - 1;
475 uint16_t elts_free = txq->elts_tail;
477 uint16_t cq_ci = txq->cq_ci;
478 volatile struct mlx5_cqe *cqe = NULL;
479 volatile struct mlx5_wqe_ctrl *ctrl;
480 struct rte_mbuf *m, *free[elts_n];
481 struct rte_mempool *pool = NULL;
482 unsigned int blk_n = 0;
484 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
485 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
488 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
489 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
490 if (!check_cqe_seen(cqe)) {
491 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
492 rte_hexdump(stderr, "MLX5 TXQ:",
493 (const void *)((uintptr_t)txq->wqes),
501 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
502 ctrl = (volatile struct mlx5_wqe_ctrl *)
503 tx_mlx5_wqe(txq, txq->wqe_pi);
504 elts_tail = ctrl->ctrl3;
505 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
507 while (elts_free != elts_tail) {
508 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
509 if (likely(m != NULL)) {
510 if (likely(m->pool == pool)) {
513 if (likely(pool != NULL))
514 rte_mempool_put_bulk(pool,
524 rte_mempool_put_bulk(pool, (void *)free, blk_n);
526 elts_free = txq->elts_tail;
528 while (elts_free != elts_tail) {
529 memset(&(*txq->elts)[elts_free & elts_m],
531 sizeof((*txq->elts)[elts_free & elts_m]));
536 txq->elts_tail = elts_tail;
537 /* Update the consumer index. */
538 rte_compiler_barrier();
539 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
543 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
544 * as mempool is pre-configured and static.
547 * Pointer to Rx queue structure.
552 * Searched LKey on success, UINT32_MAX on no match.
554 static __rte_always_inline uint32_t
555 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
557 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
560 /* Linear search on MR cache array. */
561 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
562 MLX5_MR_CACHE_N, addr);
563 if (likely(lkey != UINT32_MAX))
565 /* Take slower bottom-half (Binary Search) on miss. */
566 return mlx5_rx_addr2mr_bh(rxq, addr);
569 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
572 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
575 * Pointer to Tx queue structure.
580 * Searched LKey on success, UINT32_MAX on no match.
582 static __rte_always_inline uint32_t
583 mlx5_tx_addr2mr(struct mlx5_txq_data *txq, uintptr_t addr)
585 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
588 /* Check generation bit to see if there's any change on existing MRs. */
589 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
590 mlx5_mr_flush_local_cache(mr_ctrl);
591 /* Linear search on MR cache array. */
592 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
593 MLX5_MR_CACHE_N, addr);
594 if (likely(lkey != UINT32_MAX))
596 /* Take slower bottom-half (binary search) on miss. */
597 return mlx5_tx_addr2mr_bh(txq, addr);
600 #define mlx5_tx_mb2mr(rxq, mb) mlx5_tx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
603 * Ring TX queue doorbell and flush the update if requested.
606 * Pointer to TX queue structure.
608 * Pointer to the last WQE posted in the NIC.
610 * Request for write memory barrier after BlueFlame update.
612 static __rte_always_inline void
613 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
616 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
617 volatile uint64_t *src = ((volatile uint64_t *)wqe);
620 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
621 /* Ensure ordering between DB record and BF copy. */
629 * Ring TX queue doorbell and flush the update by write memory barrier.
632 * Pointer to TX queue structure.
634 * Pointer to the last WQE posted in the NIC.
636 static __rte_always_inline void
637 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
639 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
643 * Convert mbuf to Verb SWP.
646 * Pointer to the Tx queue.
648 * Pointer to the mbuf.
650 * TSO offloads enabled.
652 * VLAN offloads enabled
654 * Pointer to the SWP header offsets.
656 * Pointer to the SWP header types.
658 static __rte_always_inline void
659 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
660 uint8_t *offsets, uint8_t *swp_types)
662 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
663 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
664 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
665 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
666 const uint64_t inner_ip =
667 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
668 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
673 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
674 tunnel != PKT_TX_TUNNEL_IP)))
677 * The index should have:
678 * bit[0:1] = PKT_TX_L4_MASK
679 * bit[4] = PKT_TX_IPV6
680 * bit[8] = PKT_TX_OUTER_IPV6
681 * bit[9] = PKT_TX_OUTER_UDP
683 idx = (buf->ol_flags & ol_flags_mask) >> 52;
684 if (tunnel == PKT_TX_TUNNEL_UDP)
686 *swp_types = mlx5_swp_types_table[idx];
688 * Set offsets for SW parser. Since ConnectX-5, SW parser just
689 * complements HW parser. SW parser starts to engage only if HW parser
690 * can't reach a header. For the older devices, HW parser will not kick
691 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
692 * should be set regardless of HW offload.
694 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
695 offsets[1] = off >> 1; /* Outer L3 offset. */
696 off += buf->outer_l3_len;
697 if (tunnel == PKT_TX_TUNNEL_UDP)
698 offsets[0] = off >> 1; /* Outer L4 offset. */
701 offsets[3] = off >> 1; /* Inner L3 offset. */
702 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
703 csum_flags == PKT_TX_UDP_CKSUM) {
705 offsets[2] = off >> 1; /* Inner L4 offset. */
711 * Convert the Checksum offloads to Verbs.
714 * Pointer to the mbuf.
717 * Converted checksum flags.
719 static __rte_always_inline uint8_t
720 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
723 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
724 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
725 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
728 * The index should have:
729 * bit[0] = PKT_TX_TCP_SEG
730 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
731 * bit[4] = PKT_TX_IP_CKSUM
732 * bit[8] = PKT_TX_OUTER_IP_CKSUM
735 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
736 return mlx5_cksum_table[idx];
740 * Count the number of contiguous single segment packets.
743 * Pointer to array of packets.
748 * Number of contiguous single segment packets.
750 static __rte_always_inline unsigned int
751 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
757 /* Count the number of contiguous single segment packets. */
758 for (pos = 0; pos < pkts_n; ++pos)
759 if (NB_SEGS(pkts[pos]) > 1)
765 * Count the number of contiguous multi-segment packets.
768 * Pointer to array of packets.
773 * Number of contiguous multi-segment packets.
775 static __rte_always_inline unsigned int
776 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
782 /* Count the number of contiguous multi-segment packets. */
783 for (pos = 0; pos < pkts_n; ++pos)
784 if (NB_SEGS(pkts[pos]) == 1)
789 #endif /* RTE_PMD_MLX5_RXTX_H_ */