1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
33 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
41 /* Support tunnel matching. */
42 #define MLX5_FLOW_TUNNEL 5
44 struct mlx5_rxq_stats {
45 #ifdef MLX5_PMD_SOFT_COUNTERS
46 uint64_t ipackets; /**< Total of successfully received packets. */
47 uint64_t ibytes; /**< Total of successfully received bytes. */
49 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
50 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
53 struct mlx5_txq_stats {
54 #ifdef MLX5_PMD_SOFT_COUNTERS
55 uint64_t opackets; /**< Total of successfully sent packets. */
56 uint64_t obytes; /**< Total of successfully sent bytes. */
58 uint64_t oerrors; /**< Total number of failed transmitted packets. */
63 /* Compressed CQE context. */
65 uint16_t ai; /* Array index. */
66 uint16_t ca; /* Current array index. */
67 uint16_t na; /* Next array index. */
68 uint16_t cq_ci; /* The next CQE. */
69 uint32_t cqe_cnt; /* Number of CQEs. */
72 /* Multi-Packet RQ buffer header. */
73 struct mlx5_mprq_buf {
74 struct rte_mempool *mp;
75 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
76 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
77 } __rte_cache_aligned;
79 /* Get pointer to the first stride. */
80 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
82 enum mlx5_rxq_err_state {
83 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
84 MLX5_RXQ_ERR_STATE_NEED_RESET,
85 MLX5_RXQ_ERR_STATE_NEED_READY,
88 /* RX queue descriptor. */
89 struct mlx5_rxq_data {
90 unsigned int csum:1; /* Enable checksum offloading. */
91 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
92 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
93 unsigned int crc_present:1; /* CRC must be subtracted. */
94 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
95 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
96 unsigned int elts_n:4; /* Log 2 of Mbufs. */
97 unsigned int rss_hash:1; /* RSS hash result is enabled. */
98 unsigned int mark:1; /* Marked flow available on the queue. */
99 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
100 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
101 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
102 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
103 unsigned int :4; /* Remaining bits. */
104 volatile uint32_t *rq_db;
105 volatile uint32_t *cq_db;
108 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
111 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
113 struct rxq_zip zip; /* Compressed context. */
114 uint16_t decompressed;
115 /* Number of ready mbufs decompressed from the CQ. */
117 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
118 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
120 volatile struct mlx5_cqe(*cqes)[];
123 struct rte_mbuf *(*elts)[];
124 struct mlx5_mprq_buf *(*mprq_bufs)[];
126 struct rte_mempool *mp;
127 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
128 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
129 uint16_t idx; /* Queue index. */
130 struct mlx5_rxq_stats stats;
131 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
132 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
133 void *cq_uar; /* CQ user access region. */
134 uint32_t cqn; /* CQ number. */
135 uint8_t cq_arm_sn; /* CQ arm seq number. */
137 rte_spinlock_t *uar_lock_cq;
138 /* CQ (UAR) access lock required for 32bit implementations */
140 uint32_t tunnel; /* Tunnel information. */
141 } __rte_cache_aligned;
143 /* Verbs Rx queue elements. */
144 struct mlx5_rxq_ibv {
145 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
146 rte_atomic32_t refcnt; /* Reference counter. */
147 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
148 struct ibv_cq *cq; /* Completion Queue. */
149 struct ibv_wq *wq; /* Work Queue. */
150 struct ibv_comp_channel *channel;
153 /* RX queue control descriptor. */
154 struct mlx5_rxq_ctrl {
155 struct mlx5_rxq_data rxq; /* Data path structure. */
156 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
157 rte_atomic32_t refcnt; /* Reference counter. */
158 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
159 struct mlx5_priv *priv; /* Back pointer to private data. */
160 unsigned int socket; /* CPU socket ID for allocations. */
161 unsigned int irq:1; /* Whether IRQ is enabled. */
162 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
163 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
164 uint32_t wqn; /* WQ number. */
165 uint16_t dump_file_n; /* Number of dump files. */
168 /* Indirection table. */
169 struct mlx5_ind_table_ibv {
170 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
171 rte_atomic32_t refcnt; /* Reference counter. */
172 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
173 uint32_t queues_n; /**< Number of queues in the list. */
174 uint16_t queues[]; /**< Queue list. */
179 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
180 rte_atomic32_t refcnt; /* Reference counter. */
181 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
182 struct ibv_qp *qp; /* Verbs queue pair. */
183 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
184 void *action; /* DV QP action pointer. */
186 uint64_t hash_fields; /* Verbs Hash fields. */
187 uint32_t rss_key_len; /* Hash key length in bytes. */
188 uint8_t rss_key[]; /* Hash key. */
191 /* TX queue send local data. */
193 struct mlx5_txq_local {
194 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
195 struct rte_mbuf *mbuf; /* first mbuf to process. */
196 uint16_t pkts_copy; /* packets copied to elts. */
197 uint16_t pkts_sent; /* packets sent. */
198 uint16_t elts_free; /* available elts remain. */
199 uint16_t wqe_free; /* available wqe remain. */
200 uint16_t mbuf_off; /* data offset in current mbuf. */
201 uint16_t mbuf_nseg; /* number of remaining mbuf. */
204 /* TX queue descriptor. */
206 struct mlx5_txq_data {
207 uint16_t elts_head; /* Current counter in (*elts)[]. */
208 uint16_t elts_tail; /* Counter of first element awaiting completion. */
209 uint16_t elts_comp; /* elts index since last completion request. */
210 uint16_t elts_s; /* Number of mbuf elements. */
211 uint16_t elts_m; /* Mask for mbuf elements indices. */
212 /* Fields related to elts mbuf storage. */
213 uint16_t wqe_ci; /* Consumer index for work queue. */
214 uint16_t wqe_pi; /* Producer index for work queue. */
215 uint16_t wqe_s; /* Number of WQ elements. */
216 uint16_t wqe_m; /* Mask Number for WQ elements. */
217 uint16_t wqe_comp; /* WQE index since last completion request. */
218 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
219 /* WQ related fields. */
220 uint16_t cq_ci; /* Consumer index for completion queue. */
222 uint16_t cq_pi; /* Counter of issued CQE "always" requests. */
224 uint16_t cqe_s; /* Number of CQ elements. */
225 uint16_t cqe_m; /* Mask for CQ indices. */
226 /* CQ related fields. */
227 uint16_t elts_n:4; /* elts[] length (in log2). */
228 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
229 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
230 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
231 uint16_t tunnel_en:1;
232 /* When set TX offload for tunneled packets are supported. */
233 uint16_t swp_en:1; /* Whether SW parser is enabled. */
234 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
235 uint16_t inlen_send; /* Ordinary send data inline size. */
236 uint16_t inlen_empw; /* eMPW max packet size to inline. */
237 uint16_t inlen_mode; /* Minimal data length to inline. */
238 uint32_t qp_num_8s; /* QP number shifted by 8. */
239 uint64_t offloads; /* Offloads for Tx Queue. */
240 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
241 struct mlx5_wqe *wqes; /* Work queue. */
242 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
243 volatile struct mlx5_cqe *cqes; /* Completion queue. */
244 volatile uint32_t *qp_db; /* Work queue doorbell. */
245 volatile uint32_t *cq_db; /* Completion queue doorbell. */
246 uint16_t port_id; /* Port ID of device. */
247 uint16_t idx; /* Queue index. */
248 struct mlx5_txq_stats stats; /* TX queue counters. */
250 rte_spinlock_t *uar_lock;
251 /* UAR access lock required for 32bit implementations */
253 struct rte_mbuf *elts[0];
254 /* Storage for queued packets, must be the last field. */
255 } __rte_cache_aligned;
257 /* Verbs Rx queue elements. */
258 struct mlx5_txq_ibv {
259 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
260 rte_atomic32_t refcnt; /* Reference counter. */
261 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
262 struct ibv_cq *cq; /* Completion Queue. */
263 struct ibv_qp *qp; /* Queue Pair. */
266 /* TX queue control descriptor. */
267 struct mlx5_txq_ctrl {
268 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
269 rte_atomic32_t refcnt; /* Reference counter. */
270 unsigned int socket; /* CPU socket ID for allocations. */
271 unsigned int max_inline_data; /* Max inline data. */
272 unsigned int max_tso_header; /* Max TSO header size. */
273 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
274 struct mlx5_priv *priv; /* Back pointer to private data. */
275 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
276 void *bf_reg; /* BlueFlame register from Verbs. */
277 uint16_t dump_file_n; /* Number of dump files. */
278 struct mlx5_txq_data txq; /* Data path structure. */
279 /* Must be the last field in the structure, contains elts[]. */
282 #define MLX5_TX_BFREG(txq) \
283 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
287 extern uint8_t rss_hash_default_key[];
289 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
290 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
291 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
292 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
293 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
294 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
295 unsigned int socket, const struct rte_eth_rxconf *conf,
296 struct rte_mempool *mp);
297 void mlx5_rx_queue_release(void *dpdk_rxq);
298 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
299 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
300 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
301 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
302 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
303 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
304 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
305 uint16_t desc, unsigned int socket,
306 const struct rte_eth_rxconf *conf,
307 struct rte_mempool *mp);
308 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
309 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
310 int mlx5_rxq_verify(struct rte_eth_dev *dev);
311 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
312 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
313 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
314 const uint8_t *rss_key, uint32_t rss_key_len,
315 uint64_t hash_fields,
316 const uint16_t *queues, uint32_t queues_n,
317 int tunnel __rte_unused);
318 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
319 const uint8_t *rss_key, uint32_t rss_key_len,
320 uint64_t hash_fields,
321 const uint16_t *queues, uint32_t queues_n);
322 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
323 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
324 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
325 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
326 uint64_t mlx5_get_rx_port_offloads(void);
327 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
331 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
332 unsigned int socket, const struct rte_eth_txconf *conf);
333 void mlx5_tx_queue_release(void *dpdk_txq);
334 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
335 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
336 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
337 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
338 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
339 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
340 uint16_t desc, unsigned int socket,
341 const struct rte_eth_txconf *conf);
342 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
343 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
344 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
345 int mlx5_txq_verify(struct rte_eth_dev *dev);
346 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
347 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
351 extern uint32_t mlx5_ptype_table[];
352 extern uint8_t mlx5_cksum_table[];
353 extern uint8_t mlx5_swp_types_table[];
355 void mlx5_set_ptype_table(void);
356 void mlx5_set_cksum_table(void);
357 void mlx5_set_swp_types_table(void);
358 __rte_noinline uint16_t mlx5_tx_error_cqe_handle
359 (struct mlx5_txq_data *restrict txq,
360 volatile struct mlx5_err_cqe *err_cqe);
361 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
362 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
363 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq,
364 uint8_t mbuf_prepare);
365 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
366 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
367 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
369 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
371 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
373 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
374 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
375 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
376 void mlx5_dump_debug_information(const char *path, const char *title,
377 const void *buf, unsigned int len);
378 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
379 const struct mlx5_mp_arg_queue_state_modify *sm);
381 /* Vectorized version of mlx5_rxtx.c */
382 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
383 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
384 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
389 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
390 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
391 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
392 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
393 struct rte_mempool *mp);
394 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
396 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
400 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
401 * 64bit architectures.
404 * value to write in CPU endian format.
406 * Address to write to.
408 * Address of the lock to use for that UAR access.
410 static __rte_always_inline void
411 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
412 rte_spinlock_t *lock __rte_unused)
415 *(uint64_t *)addr = val;
416 #else /* !RTE_ARCH_64 */
417 rte_spinlock_lock(lock);
418 *(uint32_t *)addr = val;
420 *((uint32_t *)addr + 1) = val >> 32;
421 rte_spinlock_unlock(lock);
426 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
427 * 64bit architectures while guaranteeing the order of execution with the
428 * code being executed.
431 * value to write in CPU endian format.
433 * Address to write to.
435 * Address of the lock to use for that UAR access.
437 static __rte_always_inline void
438 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
441 __mlx5_uar_write64_relaxed(val, addr, lock);
444 /* Assist macros, used instead of directly calling the functions they wrap. */
446 #define mlx5_uar_write64_relaxed(val, dst, lock) \
447 __mlx5_uar_write64_relaxed(val, dst, NULL)
448 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
450 #define mlx5_uar_write64_relaxed(val, dst, lock) \
451 __mlx5_uar_write64_relaxed(val, dst, lock)
452 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
456 enum mlx5_cqe_status {
457 MLX5_CQE_STATUS_SW_OWN,
458 MLX5_CQE_STATUS_HW_OWN,
463 * Check whether CQE is valid.
468 * Size of completion queue.
475 static __rte_always_inline enum mlx5_cqe_status
476 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
479 const uint16_t idx = ci & cqes_n;
480 const uint8_t op_own = cqe->op_own;
481 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
482 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
484 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
485 return MLX5_CQE_STATUS_HW_OWN;
487 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
488 op_code == MLX5_CQE_REQ_ERR))
489 return MLX5_CQE_STATUS_ERR;
490 return MLX5_CQE_STATUS_SW_OWN;
494 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
495 * cloned mbuf is allocated is returned instead.
501 * Memory pool where data is located for given mbuf.
503 static inline struct rte_mempool *
504 mlx5_mb2mp(struct rte_mbuf *buf)
506 if (unlikely(RTE_MBUF_CLONED(buf)))
507 return rte_mbuf_from_indirect(buf)->pool;
512 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
513 * as mempool is pre-configured and static.
516 * Pointer to Rx queue structure.
521 * Searched LKey on success, UINT32_MAX on no match.
523 static __rte_always_inline uint32_t
524 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
526 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
529 /* Linear search on MR cache array. */
530 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
531 MLX5_MR_CACHE_N, addr);
532 if (likely(lkey != UINT32_MAX))
534 /* Take slower bottom-half (Binary Search) on miss. */
535 return mlx5_rx_addr2mr_bh(rxq, addr);
538 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
541 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
544 * Pointer to Tx queue structure.
549 * Searched LKey on success, UINT32_MAX on no match.
551 static __rte_always_inline uint32_t
552 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
554 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
555 uintptr_t addr = (uintptr_t)mb->buf_addr;
558 /* Check generation bit to see if there's any change on existing MRs. */
559 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
560 mlx5_mr_flush_local_cache(mr_ctrl);
561 /* Linear search on MR cache array. */
562 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
563 MLX5_MR_CACHE_N, addr);
564 if (likely(lkey != UINT32_MAX))
566 /* Take slower bottom-half on miss. */
567 return mlx5_tx_mb2mr_bh(txq, mb);
571 * Ring TX queue doorbell and flush the update if requested.
574 * Pointer to TX queue structure.
576 * Pointer to the last WQE posted in the NIC.
578 * Request for write memory barrier after BlueFlame update.
580 static __rte_always_inline void
581 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
584 uint64_t *dst = MLX5_TX_BFREG(txq);
585 volatile uint64_t *src = ((volatile uint64_t *)wqe);
588 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
589 /* Ensure ordering between DB record and BF copy. */
591 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
597 * Ring TX queue doorbell and flush the update by write memory barrier.
600 * Pointer to TX queue structure.
602 * Pointer to the last WQE posted in the NIC.
604 static __rte_always_inline void
605 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
607 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
610 #endif /* RTE_PMD_MLX5_RXTX_H_ */