1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
16 #include <rte_mempool.h>
17 #include <rte_prefetch.h>
20 #include "mlx5_utils.h"
21 #include "mlx5_rxtx.h"
22 #include "mlx5_rxtx_vec.h"
23 #include "mlx5_autoconf.h"
24 #include "mlx5_defs.h"
27 #pragma GCC diagnostic ignored "-Wcast-qual"
30 * Fill in buffer descriptors in a multi-packet send descriptor.
33 * Pointer to TX queue structure.
35 * Pointer to buffer descriptor to be written.
37 * Pointer to array of packets to be sent.
39 * Number of packets to be filled.
42 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
43 struct rte_mbuf **pkts, unsigned int n)
47 const uint8x16_t dseg_shuf_m = {
48 3, 2, 1, 0, /* length, bswap32 */
49 4, 5, 6, 7, /* lkey */
50 15, 14, 13, 12, /* addr, bswap64 */
53 #ifdef MLX5_PMD_SOFT_COUNTERS
57 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
59 struct rte_mbuf *pkt = pkts[pos];
61 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
62 desc = vreinterpretq_u8_u32((uint32x4_t) {
64 mlx5_tx_mb2mr(txq, pkt),
67 desc = vqtbl1q_u8(desc, dseg_shuf_m);
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 tx_byte += DATA_LEN(pkt);
73 #ifdef MLX5_PMD_SOFT_COUNTERS
74 txq->stats.obytes += tx_byte;
79 * Send multi-segmented packets until it encounters a single segment packet in
83 * Pointer to TX queue structure.
85 * Pointer to array of packets to be sent.
87 * Number of packets to be sent.
90 * Number of packets successfully transmitted (<= pkts_n).
93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
96 uint16_t elts_head = txq->elts_head;
97 const uint16_t elts_n = 1 << txq->elts_n;
98 const uint16_t elts_m = elts_n - 1;
99 const uint16_t wq_n = 1 << txq->wqe_n;
100 const uint16_t wq_mask = wq_n - 1;
101 const unsigned int nb_dword_per_wqebb =
102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
103 const unsigned int nb_dword_in_hdr =
104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
106 volatile struct mlx5_wqe *wqe = NULL;
108 assert(elts_n > pkts_n);
109 mlx5_tx_complete(txq);
110 if (unlikely(!pkts_n))
112 for (n = 0; n < pkts_n; ++n) {
113 struct rte_mbuf *buf = pkts[n];
114 unsigned int segs_n = buf->nb_segs;
115 unsigned int ds = nb_dword_in_hdr;
116 unsigned int len = PKT_LEN(buf);
117 uint16_t wqe_ci = txq->wqe_ci;
118 const uint8x16_t ctrl_shuf_m = {
119 3, 2, 1, 0, /* bswap32 */
120 7, 6, 5, 4, /* bswap32 */
121 11, 10, 9, 8, /* bswap32 */
132 max_elts = elts_n - (elts_head - txq->elts_tail);
133 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
135 * A MPW session consumes 2 WQEs at most to
136 * include MLX5_MPW_DSEG_MAX pointers.
139 max_elts < segs_n || max_wqe < 2)
141 wqe = &((volatile struct mlx5_wqe64 *)
142 txq->wqes)[wqe_ci & wq_mask].hdr;
143 cs_flags = txq_ol_cksum_to_cs(buf);
144 /* Title WQEBB pointer. */
145 t_wqe = (uint8x16_t *)wqe;
146 dseg = (uint8_t *)(wqe + 1);
148 if (!(ds++ % nb_dword_per_wqebb)) {
150 &((volatile struct mlx5_wqe64 *)
151 txq->wqes)[++wqe_ci & wq_mask];
153 txq_wr_dseg_v(txq, dseg, &buf, 1);
154 dseg += MLX5_WQE_DWORD_SIZE;
155 (*txq->elts)[elts_head++ & elts_m] = buf;
159 /* Fill CTRL in the header. */
160 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
161 MLX5_OPC_MOD_MPW << 24 |
162 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
163 txq->qp_num_8s | ds, 0, 0});
164 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
165 vst1q_u8((void *)t_wqe, ctrl);
166 /* Fill ESEG in the header. */
167 vst1q_u16((void *)(t_wqe + 1),
168 ((uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len),
170 txq->wqe_ci = wqe_ci;
174 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
175 txq->elts_head = elts_head;
176 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
177 /* A CQE slot must always be available. */
178 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
179 wqe->ctrl[2] = rte_cpu_to_be_32(8);
180 wqe->ctrl[3] = txq->elts_head;
183 #ifdef MLX5_PMD_SOFT_COUNTERS
184 txq->stats.opackets += n;
186 mlx5_tx_dbrec(txq, wqe);
191 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
192 * it returns to make it processed by txq_scatter_v(). All the packets in
193 * the pkts list should be single segment packets having same offload flags.
194 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload().
197 * Pointer to TX queue structure.
199 * Pointer to array of packets to be sent.
201 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
203 * Checksum offload flags to be written in the descriptor.
206 * Number of packets successfully transmitted (<= pkts_n).
208 static inline uint16_t
209 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
212 struct rte_mbuf **elts;
213 uint16_t elts_head = txq->elts_head;
214 const uint16_t elts_n = 1 << txq->elts_n;
215 const uint16_t elts_m = elts_n - 1;
216 const unsigned int nb_dword_per_wqebb =
217 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
218 const unsigned int nb_dword_in_hdr =
219 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
224 uint32_t comp_req = 0;
225 const uint16_t wq_n = 1 << txq->wqe_n;
226 const uint16_t wq_mask = wq_n - 1;
227 uint16_t wq_idx = txq->wqe_ci & wq_mask;
228 volatile struct mlx5_wqe64 *wq =
229 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
230 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
231 const uint8x16_t ctrl_shuf_m = {
232 3, 2, 1, 0, /* bswap32 */
233 7, 6, 5, 4, /* bswap32 */
234 11, 10, 9, 8, /* bswap32 */
241 /* Make sure all packets can fit into a single WQE. */
242 assert(elts_n > pkts_n);
243 mlx5_tx_complete(txq);
244 max_elts = (elts_n - (elts_head - txq->elts_tail));
245 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
246 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
247 if (unlikely(!pkts_n))
249 elts = &(*txq->elts)[elts_head & elts_m];
250 /* Loop for available tailroom first. */
251 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
252 for (pos = 0; pos < (n & -2); pos += 2)
253 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
255 elts[pos] = pkts[pos];
256 /* Check if it crosses the end of the queue. */
257 if (unlikely(n < pkts_n)) {
258 elts = &(*txq->elts)[0];
259 for (pos = 0; pos < pkts_n - n; ++pos)
260 elts[pos] = pkts[n + pos];
262 txq->elts_head += pkts_n;
263 /* Save title WQEBB pointer. */
264 t_wqe = (uint8x16_t *)wqe;
265 dseg = (uint8_t *)(wqe + 1);
266 /* Calculate the number of entries to the end. */
268 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
271 txq_wr_dseg_v(txq, dseg, pkts, n);
272 /* Check if it crosses the end of the queue. */
274 dseg = (uint8_t *)txq->wqes;
275 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
277 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
278 txq->elts_comp += pkts_n;
280 /* A CQE slot must always be available. */
281 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
282 /* Request a completion. */
286 /* Fill CTRL in the header. */
287 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
288 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
289 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
290 txq->qp_num_8s | (pkts_n + 2),
293 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
294 vst1q_u8((void *)t_wqe, ctrl);
295 /* Fill ESEG in the header. */
296 vst1q_u8((void *)(t_wqe + 1),
297 ((uint8x16_t) { 0, 0, 0, 0,
301 #ifdef MLX5_PMD_SOFT_COUNTERS
302 txq->stats.opackets += pkts_n;
304 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
306 /* Ring QP doorbell. */
307 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
312 * Store free buffers to RX SW ring.
315 * Pointer to RX queue structure.
317 * Pointer to array of packets to be stored.
319 * Number of packets to be stored.
322 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
324 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
325 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
329 for (pos = 0; pos < p; pos += 2) {
332 mbp = vld1q_u64((void *)&elts[pos]);
333 vst1q_u64((void *)&pkts[pos], mbp);
336 pkts[pos] = elts[pos];
340 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
341 * extracted from the title completion descriptor.
344 * Pointer to RX queue structure.
346 * Pointer to completion array having a compressed completion at first.
348 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
349 * the title completion descriptor to be copied to the rest of mbufs.
352 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
353 struct rte_mbuf **elts)
355 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
356 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
359 unsigned int inv = 0;
360 /* Mask to shuffle from extracted mini CQE to mbuf. */
361 const uint8x16_t mcqe_shuf_m1 = {
362 -1, -1, -1, -1, /* skip packet_type */
363 7, 6, -1, -1, /* pkt_len, bswap16 */
364 7, 6, /* data_len, bswap16 */
365 -1, -1, /* skip vlan_tci */
366 3, 2, 1, 0 /* hash.rss, bswap32 */
368 const uint8x16_t mcqe_shuf_m2 = {
369 -1, -1, -1, -1, /* skip packet_type */
370 15, 14, -1, -1, /* pkt_len, bswap16 */
371 15, 14, /* data_len, bswap16 */
372 -1, -1, /* skip vlan_tci */
373 11, 10, 9, 8 /* hash.rss, bswap32 */
375 /* Restore the compressed count. Must be 16 bits. */
376 const uint16_t mcqe_n = t_pkt->data_len +
377 (rxq->crc_present * ETHER_CRC_LEN);
378 const uint64x2_t rearm =
379 vld1q_u64((void *)&t_pkt->rearm_data);
380 const uint32x4_t rxdf_mask = {
381 0xffffffff, /* packet_type */
382 0, /* skip pkt_len */
383 0xffff0000, /* vlan_tci, skip data_len */
384 0, /* skip hash.rss */
386 const uint8x16_t rxdf =
387 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
388 vreinterpretq_u8_u32(rxdf_mask));
389 const uint16x8_t crc_adj = {
391 rxq->crc_present * ETHER_CRC_LEN, 0,
392 rxq->crc_present * ETHER_CRC_LEN, 0,
395 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
396 #ifdef MLX5_PMD_SOFT_COUNTERS
397 uint32_t rcvd_byte = 0;
399 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
400 const uint8x8_t len_shuf_m = {
402 15, 14, /* 2nd mCQE */
403 23, 22, /* 3rd mCQE */
404 31, 30 /* 4th mCQE */
408 * A. load mCQEs into a 128bit register.
409 * B. store rearm data to mbuf.
410 * C. combine data from mCQEs with rx_descriptor_fields1.
411 * D. store rx_descriptor_fields1.
412 * E. store flow tag (rte_flow mark).
414 for (pos = 0; pos < mcqe_n; ) {
415 uint8_t *p = (void *)&mcq[pos % 8];
416 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
417 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
418 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
419 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
421 #ifdef MLX5_PMD_SOFT_COUNTERS
422 uint16x4_t invalid_mask =
423 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
424 -1UL << ((mcqe_n - pos) *
425 sizeof(uint16_t) * 8) : 0);
428 if (!(pos & 0x7) && pos + 8 < mcqe_n)
429 rte_prefetch0((void *)(cq + pos + 8));
431 /* A.1 load mCQEs into a 128bit register. */
432 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
433 /* B.1 store rearm data to mbuf. */
434 "st1 {%[rearm].2d}, [%[e0]] \n\t"
435 "add %[e0], %[e0], #16 \n\t"
436 "st1 {%[rearm].2d}, [%[e1]] \n\t"
437 "add %[e1], %[e1], #16 \n\t"
438 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
439 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
440 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
441 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
442 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
443 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
444 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
445 /* D.1 store rx_descriptor_fields1. */
446 "st1 {v18.2d}, [%[e0]] \n\t"
447 "st1 {v19.2d}, [%[e1]] \n\t"
448 /* B.1 store rearm data to mbuf. */
449 "st1 {%[rearm].2d}, [%[e2]] \n\t"
450 "add %[e2], %[e2], #16 \n\t"
451 "st1 {%[rearm].2d}, [%[e3]] \n\t"
452 "add %[e3], %[e3], #16 \n\t"
453 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
454 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
455 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
456 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
457 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
458 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
459 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
460 /* D.1 store rx_descriptor_fields1. */
461 "st1 {v18.2d}, [%[e2]] \n\t"
462 "st1 {v19.2d}, [%[e3]] \n\t"
463 #ifdef MLX5_PMD_SOFT_COUNTERS
464 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
466 :[byte_cnt]"=&w"(byte_cnt)
470 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
471 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
472 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
473 [crc_adj]"w"(crc_adj),
474 [len_shuf_m]"w"(len_shuf_m)
475 :"memory", "v16", "v17", "v18", "v19");
476 #ifdef MLX5_PMD_SOFT_COUNTERS
477 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
478 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
481 /* E.1 store flow tag (rte_flow mark). */
482 elts[pos]->hash.fdir.hi = flow_tag;
483 elts[pos + 1]->hash.fdir.hi = flow_tag;
484 elts[pos + 2]->hash.fdir.hi = flow_tag;
485 elts[pos + 3]->hash.fdir.hi = flow_tag;
487 pos += MLX5_VPMD_DESCS_PER_LOOP;
488 /* Move to next CQE and invalidate consumed CQEs. */
489 if (!(pos & 0x7) && pos < mcqe_n) {
490 mcq = (void *)&(cq + pos)->pkt_info;
491 for (i = 0; i < 8; ++i)
492 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
495 /* Invalidate the rest of CQEs. */
496 for (; inv < mcqe_n; ++inv)
497 cq[inv].op_own = MLX5_CQE_INVALIDATE;
498 #ifdef MLX5_PMD_SOFT_COUNTERS
499 rxq->stats.ipackets += mcqe_n;
500 rxq->stats.ibytes += rcvd_byte;
502 rxq->cq_ci += mcqe_n;
506 * Calculate packet type and offload flag for mbuf and store it.
509 * Pointer to RX queue structure.
511 * Array of four 4bytes packet type info extracted from the original
512 * completion descriptor.
514 * Array of four 4bytes flow ID extracted from the original completion
517 * Opcode vector having responder error status. Each field is 4B.
519 * Pointer to array of packets to be filled.
522 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
523 uint32x4_t ptype_info, uint32x4_t flow_tag,
524 uint16x4_t op_err, struct rte_mbuf **pkts)
527 uint32x4_t pinfo, cv_flags;
528 uint32x4_t ol_flags =
529 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
530 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
531 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
532 const uint8x16_t cv_flag_sel = {
534 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
535 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
537 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
539 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
540 0, 0, 0, 0, 0, 0, 0, 0, 0
542 const uint32x4_t cv_mask =
543 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
544 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
545 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
546 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
547 uint64x2_t rearm0, rearm1, rearm2, rearm3;
548 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
551 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
552 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
553 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
554 uint32x4_t invalid_mask;
556 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
557 invalid_mask = vceqzq_u32(flow_tag);
558 ol_flags = vorrq_u32(ol_flags,
559 vbicq_u32(fdir_flags, invalid_mask));
560 /* Mask out invalid entries. */
561 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
562 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
563 ol_flags = vorrq_u32(ol_flags,
564 vbicq_u32(fdir_id_flags,
565 vceqq_u32(flow_tag, ft_def)));
568 * ptype_info has the following:
572 * bit[11:10] = l3_hdr_type
573 * bit[14:12] = l4_hdr_type
576 * bit[17] = outer_l3_type
578 ptype = vshrn_n_u32(ptype_info, 10);
579 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
580 ptype = vorr_u16(ptype, op_err);
581 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6);
582 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4);
583 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2);
584 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0);
585 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
586 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
587 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
588 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
589 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
590 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
591 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
592 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
593 /* Fill flags for checksum and VLAN. */
594 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
595 pinfo = vreinterpretq_u32_u8(
596 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
597 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
598 cv_flags = vshlq_n_u32(pinfo, 9);
599 cv_flags = vorrq_u32(pinfo, cv_flags);
600 /* Move back flags to start from byte[0]. */
601 cv_flags = vshrq_n_u32(cv_flags, 8);
602 /* Mask out garbage bits. */
603 cv_flags = vandq_u32(cv_flags, cv_mask);
604 /* Merge to ol_flags. */
605 ol_flags = vorrq_u32(ol_flags, cv_flags);
606 /* Merge mbuf_init and ol_flags, and store. */
607 rearm0 = vcombine_u64(mbuf_init,
608 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
610 rearm1 = vcombine_u64(mbuf_init,
611 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
612 ol_flags)), r32_mask));
613 rearm2 = vcombine_u64(mbuf_init,
614 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
616 rearm3 = vcombine_u64(mbuf_init,
617 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
618 ol_flags)), r32_mask));
619 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
620 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
621 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
622 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
626 * Receive burst of packets. An errored completion also consumes a mbuf, but the
627 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
628 * before returning to application.
631 * Pointer to RX queue structure.
633 * Array to store received packets.
635 * Maximum number of packets in array.
637 * Pointer to a flag. Set non-zero value if pkts array has at least one error
641 * Number of packets received including errors (<= pkts_n).
643 static inline uint16_t
644 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
647 const uint16_t q_n = 1 << rxq->cqe_n;
648 const uint16_t q_mask = q_n - 1;
649 volatile struct mlx5_cqe *cq;
650 struct rte_mbuf **elts;
654 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
655 uint16_t nocmp_n = 0;
656 uint16_t rcvd_pkt = 0;
657 unsigned int cq_idx = rxq->cq_ci & q_mask;
658 unsigned int elts_idx;
659 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
660 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
661 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
662 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
663 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
664 #ifdef MLX5_PMD_SOFT_COUNTERS
665 uint32_t rcvd_byte = 0;
667 /* Mask to generate 16B length vector. */
668 const uint8x8_t len_shuf_m = {
669 52, 53, /* 4th CQE */
670 36, 37, /* 3rd CQE */
671 20, 21, /* 2nd CQE */
674 /* Mask to extract 16B data from a 64B CQE. */
675 const uint8x16_t cqe_shuf_m = {
676 28, 29, /* hdr_type_etc */
679 47, 46, /* byte_cnt, bswap16 */
680 31, 30, /* vlan_info, bswap16 */
681 15, 14, 13, 12, /* rx_hash_res, bswap32 */
682 57, 58, 59, /* flow_tag */
685 /* Mask to generate 16B data for mbuf. */
686 const uint8x16_t mb_shuf_m = {
687 4, 5, -1, -1, /* pkt_len */
690 8, 9, 10, 11, /* hash.rss */
691 12, 13, 14, -1 /* hash.fdir.hi */
693 /* Mask to generate 16B owner vector. */
694 const uint8x8_t owner_shuf_m = {
695 63, -1, /* 4th CQE */
696 47, -1, /* 3rd CQE */
697 31, -1, /* 2nd CQE */
700 /* Mask to generate a vector having packet_type/ol_flags. */
701 const uint8x16_t ptype_shuf_m = {
702 48, 49, 50, -1, /* 4th CQE */
703 32, 33, 34, -1, /* 3rd CQE */
704 16, 17, 18, -1, /* 2nd CQE */
705 0, 1, 2, -1 /* 1st CQE */
707 /* Mask to generate a vector having flow tags. */
708 const uint8x16_t ftag_shuf_m = {
709 60, 61, 62, -1, /* 4th CQE */
710 44, 45, 46, -1, /* 3rd CQE */
711 28, 29, 30, -1, /* 2nd CQE */
712 12, 13, 14, -1 /* 1st CQE */
714 const uint16x8_t crc_adj = {
715 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0
717 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
719 assert(rxq->sges_n == 0);
720 assert(rxq->cqe_n == rxq->elts_n);
721 cq = &(*rxq->cqes)[cq_idx];
722 rte_prefetch_non_temporal(cq);
723 rte_prefetch_non_temporal(cq + 1);
724 rte_prefetch_non_temporal(cq + 2);
725 rte_prefetch_non_temporal(cq + 3);
726 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
729 * rq_ci >= cq_ci >= rq_pi
730 * Definition of indexes:
731 * rq_ci - cq_ci := # of buffers owned by HW (posted).
732 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
733 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
735 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
736 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n))
737 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
738 /* See if there're unreturned mbufs from compressed CQE. */
739 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
741 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
742 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
743 rxq->rq_pi += rcvd_pkt;
746 elts_idx = rxq->rq_pi & q_mask;
747 elts = &(*rxq->elts)[elts_idx];
748 /* Not to overflow pkts array. */
749 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
750 /* Not to cross queue end. */
751 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
754 /* At this point, there shouldn't be any remained packets. */
755 assert(rxq->rq_pi == rxq->cq_ci);
757 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
758 * there's no instruction to count trailing zeros. __builtin_clzl() is
761 * A. copy 4 mbuf pointers from elts ring to returing pkts.
762 * B. load 64B CQE and extract necessary fields
763 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
764 * following structure:
766 * uint16_t hdr_type_etc;
770 * uint16_t vlan_info;
771 * uint32_t rx_has_res;
772 * uint8_t flow_tag[3];
777 * E. find compressed CQE.
781 pos += MLX5_VPMD_DESCS_PER_LOOP) {
783 uint16x4_t opcode, owner_mask, invalid_mask;
784 uint16x4_t comp_mask;
787 uint32x4_t ptype_info, flow_tag;
788 register uint64x2_t c0, c1, c2, c3;
789 uint8_t *p0, *p1, *p2, *p3;
790 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
791 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
792 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
793 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
794 void *elts_p = (void *)&elts[pos];
795 void *pkts_p = (void *)&pkts[pos];
797 /* A.0 do not cross the end of CQ. */
798 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
799 -1UL >> ((pkts_n - pos) *
800 sizeof(uint16_t) * 8) : 0);
801 p0 = (void *)&cq[pos].pkt_info;
802 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
803 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
804 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
805 /* B.0 (CQE 3) load a block having op_own. */
806 c3 = vld1q_u64((uint64_t *)(p3 + 48));
807 /* B.0 (CQE 2) load a block having op_own. */
808 c2 = vld1q_u64((uint64_t *)(p2 + 48));
809 /* B.0 (CQE 1) load a block having op_own. */
810 c1 = vld1q_u64((uint64_t *)(p1 + 48));
811 /* B.0 (CQE 0) load a block having op_own. */
812 c0 = vld1q_u64((uint64_t *)(p0 + 48));
813 /* Synchronize for loading the rest of blocks. */
815 /* Prefetch next 4 CQEs. */
816 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
817 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
818 rte_prefetch_non_temporal(&cq[next]);
819 rte_prefetch_non_temporal(&cq[next + 1]);
820 rte_prefetch_non_temporal(&cq[next + 2]);
821 rte_prefetch_non_temporal(&cq[next + 3]);
824 /* B.1 (CQE 3) load the rest of blocks. */
825 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
826 /* B.2 (CQE 3) move the block having op_own. */
827 "mov v19.16b, %[c3].16b \n\t"
828 /* B.3 (CQE 3) extract 16B fields. */
829 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
830 /* B.1 (CQE 2) load the rest of blocks. */
831 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
832 /* B.4 (CQE 3) adjust CRC length. */
833 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
834 /* C.1 (CQE 3) generate final structure for mbuf. */
835 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
836 /* B.2 (CQE 2) move the block having op_own. */
837 "mov v19.16b, %[c2].16b \n\t"
838 /* B.3 (CQE 2) extract 16B fields. */
839 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
840 /* B.1 (CQE 1) load the rest of blocks. */
841 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
842 /* B.4 (CQE 2) adjust CRC length. */
843 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
844 /* C.1 (CQE 2) generate final structure for mbuf. */
845 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
846 /* B.2 (CQE 1) move the block having op_own. */
847 "mov v19.16b, %[c1].16b \n\t"
848 /* B.3 (CQE 1) extract 16B fields. */
849 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
850 /* B.1 (CQE 0) load the rest of blocks. */
851 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
852 /* B.4 (CQE 1) adjust CRC length. */
853 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
854 /* C.1 (CQE 1) generate final structure for mbuf. */
855 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
856 /* B.2 (CQE 0) move the block having op_own. */
857 "mov v19.16b, %[c0].16b \n\t"
858 /* A.1 load mbuf pointers. */
859 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
860 /* B.3 (CQE 0) extract 16B fields. */
861 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
862 /* B.4 (CQE 0) adjust CRC length. */
863 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
864 /* D.1 extract op_own byte. */
865 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
866 /* C.2 (CQE 3) adjust flow mark. */
867 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
868 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
869 "st1 {v15.2d}, [%[e3]] \n\t"
870 /* C.2 (CQE 2) adjust flow mark. */
871 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
872 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
873 "st1 {v14.2d}, [%[e2]] \n\t"
874 /* C.1 (CQE 0) generate final structure for mbuf. */
875 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
876 /* C.2 (CQE 1) adjust flow mark. */
877 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
878 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
879 "st1 {v13.2d}, [%[e1]] \n\t"
880 #ifdef MLX5_PMD_SOFT_COUNTERS
881 /* Extract byte_cnt. */
882 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
884 /* Extract ptype_info. */
885 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
886 /* Extract flow_tag. */
887 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
888 /* A.2 copy mbuf pointers. */
889 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
890 /* C.2 (CQE 0) adjust flow mark. */
891 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
892 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
893 "st1 {v12.2d}, [%[e0]] \n\t"
894 :[op_own]"=&w"(op_own),
895 [byte_cnt]"=&w"(byte_cnt),
896 [ptype_info]"=&w"(ptype_info),
897 [flow_tag]"=&w"(flow_tag)
898 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
899 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
900 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
903 [cqe_shuf_m]"w"(cqe_shuf_m),
904 [mb_shuf_m]"w"(mb_shuf_m),
905 [owner_shuf_m]"w"(owner_shuf_m),
906 [len_shuf_m]"w"(len_shuf_m),
907 [ptype_shuf_m]"w"(ptype_shuf_m),
908 [ftag_shuf_m]"w"(ftag_shuf_m),
909 [crc_adj]"w"(crc_adj),
910 [flow_mark_adj]"w"(flow_mark_adj)
912 "v12", "v13", "v14", "v15",
913 "v16", "v17", "v18", "v19",
914 "v20", "v21", "v22", "v23",
916 /* D.2 flip owner bit to mark CQEs from last round. */
917 owner_mask = vand_u16(op_own, owner_check);
918 owner_mask = vceq_u16(owner_mask, ownership);
919 /* D.3 get mask for invalidated CQEs. */
920 opcode = vand_u16(op_own, opcode_check);
921 invalid_mask = vceq_u16(opcode_check, opcode);
922 /* E.1 find compressed CQE format. */
923 comp_mask = vand_u16(op_own, format_check);
924 comp_mask = vceq_u16(comp_mask, format_check);
925 /* D.4 mask out beyond boundary. */
926 invalid_mask = vorr_u16(invalid_mask, mask);
927 /* D.5 merge invalid_mask with invalid owner. */
928 invalid_mask = vorr_u16(invalid_mask, owner_mask);
929 /* E.2 mask out invalid entries. */
930 comp_mask = vbic_u16(comp_mask, invalid_mask);
931 /* E.3 get the first compressed CQE. */
932 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
934 (sizeof(uint16_t) * 8);
935 /* D.6 mask out entries after the compressed CQE. */
936 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
937 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
939 invalid_mask = vorr_u16(invalid_mask, mask);
940 /* D.7 count non-compressed valid CQEs. */
941 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
942 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
944 /* D.2 get the final invalid mask. */
945 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
946 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
947 invalid_mask = vorr_u16(invalid_mask, mask);
948 /* D.3 check error in opcode. */
949 opcode = vceq_u16(resp_err_check, opcode);
950 opcode = vbic_u16(opcode, invalid_mask);
951 /* D.4 mark if any error is set */
952 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
953 /* C.4 fill in mbuf - rearm_data and packet_type. */
954 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
956 if (rxq->hw_timestamp) {
957 elts[pos]->timestamp =
959 container_of(p0, struct mlx5_cqe,
960 pkt_info)->timestamp);
961 elts[pos + 1]->timestamp =
963 container_of(p1, struct mlx5_cqe,
964 pkt_info)->timestamp);
965 elts[pos + 2]->timestamp =
967 container_of(p2, struct mlx5_cqe,
968 pkt_info)->timestamp);
969 elts[pos + 3]->timestamp =
971 container_of(p3, struct mlx5_cqe,
972 pkt_info)->timestamp);
974 #ifdef MLX5_PMD_SOFT_COUNTERS
975 /* Add up received bytes count. */
976 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
977 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
980 * Break the loop unless more valid CQE is expected, or if
981 * there's a compressed CQE.
983 if (n != MLX5_VPMD_DESCS_PER_LOOP)
986 /* If no new CQE seen, return without updating cq_db. */
987 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
989 /* Update the consumer indexes for non-compressed CQEs. */
990 assert(nocmp_n <= pkts_n);
991 rxq->cq_ci += nocmp_n;
992 rxq->rq_pi += nocmp_n;
994 #ifdef MLX5_PMD_SOFT_COUNTERS
995 rxq->stats.ipackets += nocmp_n;
996 rxq->stats.ibytes += rcvd_byte;
998 /* Decompress the last CQE if compressed. */
999 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1000 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1001 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1002 /* Return more packets if needed. */
1003 if (nocmp_n < pkts_n) {
1004 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1006 n = RTE_MIN(n, pkts_n - nocmp_n);
1007 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1012 rte_compiler_barrier();
1013 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1017 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */