4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-Wpedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 * Allocate TX queue elements.
73 * Pointer to TX queue structure.
75 * Number of elements to allocate.
78 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
82 for (i = 0; (i != elts_n); ++i)
83 (*txq_ctrl->txq.elts)[i] = NULL;
84 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
85 volatile struct mlx5_wqe64 *wqe =
86 (volatile struct mlx5_wqe64 *)
87 txq_ctrl->txq.wqes + i;
89 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
91 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
92 txq_ctrl->txq.elts_head = 0;
93 txq_ctrl->txq.elts_tail = 0;
94 txq_ctrl->txq.elts_comp = 0;
98 * Free TX queue elements.
101 * Pointer to TX queue structure.
104 txq_free_elts(struct txq_ctrl *txq_ctrl)
106 unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
107 unsigned int elts_head = txq_ctrl->txq.elts_head;
108 unsigned int elts_tail = txq_ctrl->txq.elts_tail;
109 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
111 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
112 txq_ctrl->txq.elts_head = 0;
113 txq_ctrl->txq.elts_tail = 0;
114 txq_ctrl->txq.elts_comp = 0;
116 while (elts_tail != elts_head) {
117 struct rte_mbuf *elt = (*elts)[elts_tail];
120 rte_pktmbuf_free(elt);
123 memset(&(*elts)[elts_tail],
125 sizeof((*elts)[elts_tail]));
127 if (++elts_tail == elts_n)
133 * Clean up a TX queue.
135 * Destroy objects, free allocated memory and reset the structure for reuse.
138 * Pointer to TX queue structure.
141 txq_cleanup(struct txq_ctrl *txq_ctrl)
143 struct ibv_exp_release_intf_params params;
146 DEBUG("cleaning up %p", (void *)txq_ctrl);
147 txq_free_elts(txq_ctrl);
148 if (txq_ctrl->if_qp != NULL) {
149 assert(txq_ctrl->priv != NULL);
150 assert(txq_ctrl->priv->ctx != NULL);
151 assert(txq_ctrl->qp != NULL);
152 params = (struct ibv_exp_release_intf_params){
155 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
159 if (txq_ctrl->if_cq != NULL) {
160 assert(txq_ctrl->priv != NULL);
161 assert(txq_ctrl->priv->ctx != NULL);
162 assert(txq_ctrl->cq != NULL);
163 params = (struct ibv_exp_release_intf_params){
166 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
170 if (txq_ctrl->qp != NULL)
171 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
172 if (txq_ctrl->cq != NULL)
173 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
174 if (txq_ctrl->rd != NULL) {
175 struct ibv_exp_destroy_res_domain_attr attr = {
179 assert(txq_ctrl->priv != NULL);
180 assert(txq_ctrl->priv->ctx != NULL);
181 claim_zero(ibv_exp_destroy_res_domain(txq_ctrl->priv->ctx,
185 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
186 if (txq_ctrl->txq.mp2mr[i].mp == NULL)
188 assert(txq_ctrl->txq.mp2mr[i].mr != NULL);
189 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
191 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
195 * Initialize TX queue.
198 * Pointer to TX queue control template.
200 * Pointer to TX queue control.
203 * 0 on success, errno value on failure.
206 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
208 struct mlx5_qp *qp = to_mqp(tmpl->qp);
209 struct ibv_cq *ibcq = tmpl->cq;
210 struct mlx5_cq *cq = to_mxxx(cq, cq);
212 if (cq->cqe_sz != RTE_CACHE_LINE_SIZE) {
213 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
214 "it should be set to %u", RTE_CACHE_LINE_SIZE);
217 tmpl->txq.cqe_n = log2above(ibcq->cqe);
218 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
219 tmpl->txq.wqes = qp->gen_data.sqstart;
220 tmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);
221 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
222 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
223 tmpl->txq.cq_db = cq->dbrec;
225 (volatile struct mlx5_cqe (*)[])
226 (uintptr_t)cq->active_buf->buf;
228 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
229 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
234 * Configure a TX queue.
237 * Pointer to Ethernet device structure.
239 * Pointer to TX queue structure.
241 * Number of descriptors to configure in queue.
243 * NUMA socket on which memory must be allocated.
245 * Thresholds parameters.
248 * 0 on success, errno value on failure.
251 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
252 uint16_t desc, unsigned int socket,
253 const struct rte_eth_txconf *conf)
255 struct priv *priv = mlx5_get_priv(dev);
256 struct txq_ctrl tmpl = {
261 struct ibv_exp_query_intf_params params;
262 struct ibv_exp_qp_init_attr init;
263 struct ibv_exp_res_domain_init_attr rd;
264 struct ibv_exp_cq_init_attr cq;
265 struct ibv_exp_qp_attr mod;
266 struct ibv_exp_cq_attr cq_attr;
268 enum ibv_exp_query_intf_status status;
271 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
273 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
276 (void)conf; /* Thresholds configuration (ignored). */
277 assert(desc > MLX5_TX_COMP_THRESH);
278 tmpl.txq.elts_n = log2above(desc);
279 /* MRs will be registered in mp2mr[] later. */
280 attr.rd = (struct ibv_exp_res_domain_init_attr){
281 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
282 IBV_EXP_RES_DOMAIN_MSG_MODEL),
283 .thread_model = IBV_EXP_THREAD_SINGLE,
284 .msg_model = IBV_EXP_MSG_HIGH_BW,
286 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
287 if (tmpl.rd == NULL) {
289 ERROR("%p: RD creation failure: %s",
290 (void *)dev, strerror(ret));
293 attr.cq = (struct ibv_exp_cq_init_attr){
294 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
295 .res_domain = tmpl.rd,
297 tmpl.cq = ibv_exp_create_cq(priv->ctx,
298 (((desc / MLX5_TX_COMP_THRESH) - 1) ?
299 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1),
300 NULL, NULL, 0, &attr.cq);
301 if (tmpl.cq == NULL) {
303 ERROR("%p: CQ creation failure: %s",
304 (void *)dev, strerror(ret));
307 DEBUG("priv->device_attr.max_qp_wr is %d",
308 priv->device_attr.max_qp_wr);
309 DEBUG("priv->device_attr.max_sge is %d",
310 priv->device_attr.max_sge);
311 attr.init = (struct ibv_exp_qp_init_attr){
312 /* CQ to be associated with the send queue. */
314 /* CQ to be associated with the receive queue. */
317 /* Max number of outstanding WRs. */
318 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
319 priv->device_attr.max_qp_wr :
322 * Max number of scatter/gather elements in a WR,
323 * must be 1 to prevent libmlx5 from trying to affect
324 * too much memory. TX gather is not impacted by the
325 * priv->device_attr.max_sge limit and will still work
330 .qp_type = IBV_QPT_RAW_PACKET,
331 /* Do *NOT* enable this, completions events are managed per
335 .res_domain = tmpl.rd,
336 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
337 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
339 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
340 tmpl.txq.max_inline =
341 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
342 RTE_CACHE_LINE_SIZE);
343 attr.init.cap.max_inline_data =
344 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
346 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
347 if (tmpl.qp == NULL) {
348 ret = (errno ? errno : EINVAL);
349 ERROR("%p: QP creation failure: %s",
350 (void *)dev, strerror(ret));
353 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
354 " max_inline_data=%u",
355 attr.init.cap.max_send_wr,
356 attr.init.cap.max_send_sge,
357 attr.init.cap.max_inline_data);
358 attr.mod = (struct ibv_exp_qp_attr){
359 /* Move the QP to this state. */
360 .qp_state = IBV_QPS_INIT,
361 /* Primary port number. */
362 .port_num = priv->port
364 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
365 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
367 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
368 (void *)dev, strerror(ret));
371 ret = txq_setup(&tmpl, txq_ctrl);
373 ERROR("%p: cannot initialize TX queue structure: %s",
374 (void *)dev, strerror(ret));
377 txq_alloc_elts(&tmpl, desc);
378 attr.mod = (struct ibv_exp_qp_attr){
379 .qp_state = IBV_QPS_RTR
381 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
383 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
384 (void *)dev, strerror(ret));
387 attr.mod.qp_state = IBV_QPS_RTS;
388 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
390 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
391 (void *)dev, strerror(ret));
394 attr.params = (struct ibv_exp_query_intf_params){
395 .intf_scope = IBV_EXP_INTF_GLOBAL,
396 .intf = IBV_EXP_INTF_CQ,
399 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
400 if (tmpl.if_cq == NULL) {
402 ERROR("%p: CQ interface family query failed with status %d",
403 (void *)dev, status);
406 attr.params = (struct ibv_exp_query_intf_params){
407 .intf_scope = IBV_EXP_INTF_GLOBAL,
408 .intf = IBV_EXP_INTF_QP_BURST,
411 /* Enable multi-packet send if supported. */
413 ((priv->mps && !priv->sriov) ?
414 IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR :
417 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
418 if (tmpl.if_qp == NULL) {
420 ERROR("%p: QP interface family query failed with status %d",
421 (void *)dev, status);
424 /* Clean up txq in case we're reinitializing it. */
425 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
426 txq_cleanup(txq_ctrl);
428 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
429 /* Pre-register known mempools. */
430 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
440 * DPDK callback to configure a TX queue.
443 * Pointer to Ethernet device structure.
447 * Number of descriptors to configure in queue.
449 * NUMA socket on which memory must be allocated.
451 * Thresholds parameters.
454 * 0 on success, negative errno value on failure.
457 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
458 unsigned int socket, const struct rte_eth_txconf *conf)
460 struct priv *priv = dev->data->dev_private;
461 struct txq *txq = (*priv->txqs)[idx];
462 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
465 if (mlx5_is_secondary())
466 return -E_RTE_SECONDARY;
469 if (desc <= MLX5_TX_COMP_THRESH) {
470 WARN("%p: number of descriptors requested for TX queue %u"
471 " must be higher than MLX5_TX_COMP_THRESH, using"
473 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
474 desc = MLX5_TX_COMP_THRESH + 1;
476 if (!rte_is_power_of_2(desc)) {
477 desc = 1 << log2above(desc);
478 WARN("%p: increased number of descriptors in TX queue %u"
479 " to the next power of two (%d)",
480 (void *)dev, idx, desc);
482 DEBUG("%p: configuring queue %u for %u descriptors",
483 (void *)dev, idx, desc);
484 if (idx >= priv->txqs_n) {
485 ERROR("%p: queue index out of range (%u >= %u)",
486 (void *)dev, idx, priv->txqs_n);
491 DEBUG("%p: reusing already allocated queue index %u (%p)",
492 (void *)dev, idx, (void *)txq);
497 (*priv->txqs)[idx] = NULL;
498 txq_cleanup(txq_ctrl);
501 rte_calloc_socket("TXQ", 1,
503 desc * sizeof(struct rte_mbuf *),
505 if (txq_ctrl == NULL) {
506 ERROR("%p: unable to allocate queue index %u",
512 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
516 txq_ctrl->txq.stats.idx = idx;
517 DEBUG("%p: adding TX queue %p to list",
518 (void *)dev, (void *)txq_ctrl);
519 (*priv->txqs)[idx] = &txq_ctrl->txq;
520 /* Update send callback. */
521 priv_select_tx_function(priv);
528 * DPDK callback to release a TX queue.
531 * Generic TX queue pointer.
534 mlx5_tx_queue_release(void *dpdk_txq)
536 struct txq *txq = (struct txq *)dpdk_txq;
537 struct txq_ctrl *txq_ctrl;
541 if (mlx5_is_secondary())
546 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
547 priv = txq_ctrl->priv;
549 for (i = 0; (i != priv->txqs_n); ++i)
550 if ((*priv->txqs)[i] == txq) {
551 DEBUG("%p: removing TX queue %p from list",
552 (void *)priv->dev, (void *)txq_ctrl);
553 (*priv->txqs)[i] = NULL;
556 txq_cleanup(txq_ctrl);
562 * DPDK callback for TX in secondary processes.
564 * This function configures all queues from primary process information
565 * if necessary before reverting to the normal TX burst callback.
568 * Generic pointer to TX queue structure.
570 * Packets to transmit.
572 * Number of packets in array.
575 * Number of packets successfully transmitted (<= pkts_n).
578 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
581 struct txq *txq = dpdk_txq;
582 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
583 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
584 struct priv *primary_priv;
590 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
591 /* Look for queue index in both private structures. */
592 for (index = 0; index != priv->txqs_n; ++index)
593 if (((*primary_priv->txqs)[index] == txq) ||
594 ((*priv->txqs)[index] == txq))
596 if (index == priv->txqs_n)
598 txq = (*priv->txqs)[index];
599 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);